Data center resource real-time scheduling method based on multi-dimensional resource sensitivity perception

Abstract

The invention provides a data center resource real-time scheduling method based on multi-dimensional resource sensitivity perception, which comprises the following steps that: a data center concurrently executes a plurality of target application programs, and quantifies the sensitivity of each target application program to at least two different hardware resource types; the data center selects a hardware resource type with the highest sensitivity as a sensitive hardware resource type of the target application program; and the data center schedules the target application program to preferentially run on the hardware resources belonging to the sensitive hardware resource type to obtain a running result of the target application program. Therefore, the resource sensitivity of one application can be systematically analyzed in multiple dimensions. In this way, the scheduler can make the most efficient resource allocation decision.

Description

Technical Field

[0001] This invention relates to the fields of data center resource management and computer system performance optimization, and particularly to a method, apparatus, electronic device, computer-readable storage medium, and computer program product for real-time scheduling of data center resources based on multi-dimensional resource sensitivity perception. Background Technology

[0002] Data centers are a crucial infrastructure for cloud computing, but they often struggle to simultaneously address the issues of low system resource utilization and inconsistent quality of service (QoS) for hybrid applications. To fully utilize the abundant resources of data centers (such as processor cores, on-chip cache, and memory bandwidth), various types of applications often run concurrently. These applications share system resources, and this resource sharing introduces significant uncertainty into application performance, making it difficult to guarantee the QoS of hybrid applications.

[0003] Data center workloads are diverse, broadly categorized into Latency Critical (LC) and Best Efforts (BE) applications. LC applications (such as web queries and social networking services) prioritize tail latency as a performance metric, while BE applications (such as big data mining applications) prioritize IPC (Internal Processing Rate). In data centers, tail latency for LC applications directly impacts user experience and carries higher priority, while BE applications, often batch processing-based, have relatively lower priority. However, the workload of LC applications typically fluctuates over time, often failing to fully utilize existing resources. To improve resource utilization, data centers typically employ application co-location, placing multiple applications on a single physical or virtual machine. To mitigate interference between applications, resource allocation strategies are required.

[0004] Existing resource scheduling frameworks often lack the ability to diagnose specific application bottlenecks when allocating resources. They either employ a uniform resource adjustment strategy or randomly select resources for allocation, failing to differentiate the varying sensitivities of different applications to processor cores, cache, and memory bandwidth. This "resource-agnostic" scheduling approach frequently leads to inefficient allocation, or even misallocation of resources to non-bottleneck components, resulting in waste and failing to effectively improve application performance.

[0005] Existing technologies, such as "Resource Scheduling Methods, Application Identification Methods, and Related Equipment for Cloud Computing Systems," introduce an ARQ strategy for allocating cores and last-level caches and propose system entropy to quantify interference in the system. However, they do not selectively schedule certain types of resources based on the application's sensitivity to different types of resources. In contrast, this invention proposes a resource allocation strategy based on the application's sensitivity to resources for both latency-sensitive and best-effort applications. It analyzes the sensitivity of both types of applications to multiple resources, thereby allocating resources accordingly. This can further improve the quality of service for latency-sensitive applications and the throughput of best-effort applications, thus improving the overall performance of the data center.

[0006] The existing technology, "A method and system for cache partitioning to ensure the quality of service for multiple latency-critical programs," focuses on a relatively isolated sub-problem. Its technical scope is strictly limited to the partitioning and management of LLC (Limited Area Code), without involving the coordinated allocation of processor cores and memory bandwidth. In modern data centers where multi-dimensional resource contention is a major performance bottleneck, its breadth of problem-solving is limited. This fundamental difference in scope directly leads to the difference in the core methods and intelligence levels of the two: This invention dynamically analyzes the real-time sensitivity of each application to different resources (such as MPKI, parallelizability ratio, and memory idle time), and performs proactive resource scheduling with the goal of maximizing utility. This is an online, data-driven, and proactive decision-making process. In contrast, the solution of the patent relies on a more static and reactive rule engine. Its core method is to first classify and initialize applications based on offline performance indicators (HPKI / MPKI), and then passively adjust the cache at runtime based on the slack indicator, a posterior performance feedback. Its intelligence is reflected in the execution of simple rules rather than the optimization of the overall system utility, lacking multi-level, multi-resource dynamic intelligent decision-making capabilities. Summary of the Invention

[0007] This invention aims to address the problems of blind and inefficient scheduling caused by the inability to accurately diagnose application resource bottlenecks in existing technologies. This invention provides a real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness, capable of systematically and multi-dimensionally analyzing the resource sensitivity of an application. It designs specific performance indicators and analysis methods that best reflect the utilization of each key hardware resource (processor core, final-level cache LLC, memory bandwidth). In this way, the scheduler can clearly know "which application's performance is primarily limited by "which resource," thereby making the most efficient resource allocation decisions—that is, precisely allocating resources to where they will generate the greatest benefit.

[0008] To address the shortcomings of existing technologies, such as Figure 6As shown, this invention proposes a real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness, including:

[0009] The quantification process involves the data center executing multiple target applications concurrently in real time, and for each target application, quantifying its sensitivity to at least two different hardware resource types.

[0010] In the selection process, the data center selects the most sensitive hardware resource type as the sensitive hardware resource type for the target application.

[0011] The scheduling step involves the data center scheduling the target application to run on hardware resources belonging to the sensitive hardware resource type, thereby obtaining the running result of the target application.

[0012] The types of hardware resources involved in the quantization step include: processor cores, final-level cache LLC, and memory bandwidth.

[0013] The aforementioned real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness includes the following quantification step:

[0014] When quantifying the sensitivity of the target application to processor cores, the parallelization ratio of the target application is periodically detected. The target application has been running for a period of time Then enters the time-consuming phase. The measurement phase; in this measurement phase, the parallelization ratio of the target application is detected by the following formula. This refers to the sensitivity of the target application to the processor core;

[0015] in, For this target application in The speedup achieved by running on multiple cores compared to running on a single core;

[0016] exist Measure single-core IPC value over a time period. Internal measurement One core IPC value, using The ratio of the IPC value per core to the IPC value per single core is used as the speedup ratio. .

[0017] The aforementioned real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness includes the following quantification step:

[0018] When quantifying the sensitivity of the target application to the last-level cache LLC, monitor the curve of the number of cache misses (MPKI) during the runtime of the target application as a function of the LLC allocation capacity;

[0019] The curve is obtained by dynamically limiting the target application to a specific range of cache paths and measuring its cache misses and instruction executions at intervals t. The slope of the curve for the target application is then used as the sensitivity of the target application to the final cache LLC.

[0020] The aforementioned real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness includes the following quantification step:

[0021] When quantifying the target application's sensitivity to memory bandwidth, a hardware performance monitoring unit (PMU) is used to obtain in real-time the percentage of CPU cycles that are idle due to waiting for memory access during the execution of each target application. This is due to the target application's sensitivity to memory bandwidth.

[0022] like Figure 7 As shown, this invention also proposes a real-time data center resource scheduling device B based on multi-dimensional resource sensitivity awareness, which includes:

[0023] The quantization module enables the data center to execute multiple target applications concurrently in real time. For each target application, the module quantifies its sensitivity to at least two different hardware resource types.

[0024] In the module selection, the data center selects the most sensitive hardware resource type as the sensitive hardware resource type for the target application.

[0025] The scheduling module, located in the data center, schedules the target application to run on hardware resources belonging to the sensitive hardware resource type, and obtains the running result of the target application.

[0026] The types of hardware resources in the quantization module include: processor cores, final-level cache LLC, and memory bandwidth.

[0027] The aforementioned real-time data center resource scheduling device based on multi-dimensional resource sensitivity awareness, wherein the quantization module includes:

[0028] When quantifying the sensitivity of the target application to processor cores, the parallelization ratio of the target application is periodically detected. The target application has been running for a period of time Then enters the time-consuming phase. The measurement phase; in this measurement phase, the parallelization ratio of the target application is detected by the following formula. This refers to the sensitivity of the target application to the processor core;

[0029] in, For this target application in The speedup achieved by running on multiple cores compared to running on a single core;

[0030] exist Measure single-core IPC value over a time period. Internal measurement One core IPC value, using The ratio of the IPC value per core to the IPC value per single core is used as the speedup ratio. .

[0031] The aforementioned real-time data center resource scheduling device based on multi-dimensional resource sensitivity awareness, wherein the quantization module includes:

[0032] When quantifying the sensitivity of the target application to the last-level cache LLC, monitor the curve of the number of cache misses (MPKI) during the runtime of the target application as a function of the LLC allocation capacity;

[0033] The curve is obtained by dynamically limiting the target application to a specific range of cache paths and measuring its cache misses and instruction executions at intervals t. The slope of the curve for the target application is then used as the sensitivity of the target application to the last-level cache LLC.

[0034] This quantization module includes:

[0035] When quantifying the target application's sensitivity to memory bandwidth, a hardware performance monitoring unit (PMU) is used to obtain in real-time the percentage of CPU cycles that are idle due to waiting for memory access during the execution of each target application. This is due to the target application's sensitivity to memory bandwidth.

[0036] The present invention also proposes an electronic device, including the aforementioned real-time data center resource scheduling device based on multi-dimensional resource sensitivity perception. The electronic device may be connected to an information display device, which is used to display the running results using user-set display parameters, attributes, or through an artificial intelligence model.

[0037] The present invention also proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness.

[0038] The present invention also proposes a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of the real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness. Attached Figure Description

[0039] Figure 1 A graph showing the ratio of real-time parallelizability to runtime for PARSEC applications.

[0040] Figure 2 A flowchart for real-time measurement of parallelizable scales;

[0041] Figure 3 A graph showing the percentage of memory stall cycles and the 99th percentile tail latency for LC applications under different memory bandwidth allocation levels;

[0042] Figure 4 This is a detailed diagram illustrating the allocation of Pharos and ARQ in the same application scenario of this invention;

[0043] Figure 5 A diagram showing the MPKI curve measurement method;

[0044] Figure 6 This is a flowchart of the method of the present invention;

[0045] Figure 7 This is a block diagram of the device of the present invention;

[0046] Figure 8 This is a schematic diagram of the structure of the first electronic device of the present invention;

[0047] Figure 9 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0048] Figure 10 This is a schematic diagram of the structure of the second electronic device of the present invention.

[0049] Figure label:

[0050] A - First electronic device;

[0051] B-A real-time data center resource scheduling device based on multi-dimensional resource sensitivity perception;

[0052] C-Data acquisition equipment;

[0053] D-Information display device;

[0054] 1000 - Second electronic device;

[0055] Ⅰ-Computational Unit;

[0056] II-ROM;

[0057] III-RAM;

[0058] N-bus;

[0059] V-Interface;

[0060] VI - Input Unit;

[0061] VII - Output Unit;

[0062] VIII - Storage medium;

[0063] IX - Communication Unit. Detailed Implementation

[0064] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0065] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0067] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory, and by calling data stored in memory.

[0068] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.

[0069] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0070] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0071] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0072] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0073] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0074] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0075] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0076] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0078] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] This invention discloses a resource scheduling method and system for data centers, aiming to solve the problem of low scheduling efficiency caused by the inability to accurately diagnose application resource bottlenecks. The method establishes independent sensitivity profiling models for different types of hardware resources (processor cores, LLC cache, and memory bandwidth): it uses real-time parallelizable proportional analysis of core sensitivity, MPKI curve analysis of LLC sensitivity, and memory stagnation cycle proportional analysis of memory bandwidth sensitivity. During scheduling, the system first performs multi-dimensional sensitivity profiling on the target application, quantifying its dependence on various resources, and then selects the most sensitive resource type for allocation. This invention, through accurate bottleneck diagnosis, allocates the most suitable resources to the most demanding applications, significantly improving the effectiveness of resource scheduling and the overall performance of the system.

[0080] To achieve the above-mentioned technical effects, the present invention proposes the following steps:

[0081] a) For a target application, analyze its sensitivity to at least two different types of hardware resources, wherein for each type of hardware resource, a corresponding performance metric is used to quantify the sensitivity.

[0082] The target application can be an image classification program, a machine translation program (natural language processing applications such as Moses), a search or indexing application (such as Xapian), or a large-scale numerical computation program (such as Blackscholes and Swaptions). It is important to emphasize that the method proposed in this invention is universal and not limited to the above applications. It can be used in cloud server environments as well as resource management scenarios on local computers or embedded devices.

[0083] b) Based on the quantification results of the various sensitivities, determine the type of hardware resource that the target application is more sensitive to;

[0084] c) When resources need to be allocated to the target application, priority is given to allocating the hardware resource types that the application is more sensitive to. For example, when an application is sensitive to memory bandwidth, the "priority allocated resources" are not limited to a specific physical core, but refer to the available memory bandwidth resources in the system itself. For example, the system can improve performance by increasing the available bandwidth for the application, reducing bandwidth interference from competing processes, or selecting an execution environment with better bandwidth channels. In specific implementation, the experimental method of this application is to change the proportion of bandwidth available to the application by adjusting the MBA (Memory Bandwidth Allocation) level. When an application is identified as bandwidth-sensitive, a higher available bandwidth can be allocated to it.

[0085] The sensitivity analysis of the processor cores is achieved by calculating the real-time parallelizability ratio of the application online. The method for determining the sensitivity of an application to processor core resources is as follows: the real-time parallelizability ratio of each application is sorted, and if an application's real-time parallelizability ratio is in the top x% of all applications (x can be a value between 10 and 50 depending on the specific application scenario), then the application is considered to be processor core sensitive.

[0086] Sensitivity profiling of the on-chip last-level cache (LLC) is achieved by online measurement and analysis of the rate of change of the cache miss rate (MPKI) curve for the application under different LLC capacity allocations. The method for confirming the application's sensitivity to on-chip last-level cache resources is as follows: Each application is ranked according to its MPKI decline rate under the current on-chip last-level cache capacity. If an application's decline rate is in the top x% of all applications (x can be a value between 10 and 50, depending on the specific application scenario), then the application is considered to be sensitive to the on-chip last-level cache.

[0087] Sensitivity analysis of memory bandwidth involves monitoring the proportion of cycles in the total number of cycles during which the processor stalls due to waiting for memory access. This is achieved through [method / mechanism]. The method for determining an application's sensitivity to memory bandwidth resources is as follows: for each application... Sort by application, if a certain application If an application is ranked in the top x% of all applications (x can be any value between 10 and 50 depending on the specific application scenario), then the application is considered to be memory bandwidth sensitive.

[0088] The runtime measures the current number of instructions per cycle and compares it with the periodically measured number of instructions per cycle per core to obtain the speedup of the application under a specific number of processor cores. Then, it calculates the real-time parallelization ratio based on the parallelization ratio calculation formula.

[0089] The runtime limit is set to 1 available core. The number of executed instructions and the number of cycles are measured over a period of time, and the ratio is used to obtain the number of instructions per cycle per core.

[0090] Adjust the available on-chip last-level cache capacity for the application, obtain the number of on-chip last-level cache misses and the number of executed instructions, calculate their ratio to obtain the MPKI value, and then obtain the curve of MPKI changing with the size of the on-chip last-level cache.

[0091] Based on the application's real-time parallelizability ratio, the rate of change of the MPKI curve, and the percentage of memory access stall cycles ( This process determines the application's sensitivity to three types of resources: processor cores, on-chip final level cache (LLC), and memory bandwidth. If an application's sensitivity to a certain resource ranks in the top x% of all applications (x can be a value between 10 and 50, depending on the specific application scenario), then that resource is added to the application's sensitive resource candidate list. Finally, a sensitive resource is randomly selected from the sensitive resource candidate list for allocation. Each application has its own sensitive resource candidate list, which records which specific resource the application is sensitive to. If the sensitive resource candidate list is empty, a resource is randomly selected for allocation.

[0092] The reason for adopting a random selection strategy is that sensitivity assessment is the result of ranking and comparing within each type of resource. Ranking may be subject to errors due to various factors (such as measurement errors and real-time changes in program behavior). Therefore, introducing a random mechanism helps improve the robustness of the resource allocation strategy, avoiding system bias due to assessment bias, thereby maintaining the overall balance and adaptability of resource scheduling. To make the above features and effects of this invention clearer and easier to understand, specific embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of this invention. The disclosed embodiments are merely illustrative. The scope of protection of this invention is not limited to the disclosed embodiments; this invention is defined by the appended claims.

[0093] The core of this invention lies in the mechanism embodied by the two functions profileResourceSensitivity and selectResourceType shown in Algorithm 1.

[0094] 1. Analyzing processor core sensitivity

[0095] The system uses the Karp-Flatt metric to measure the real-time parallelizability of online computing applications. As shown in expression 1. Where, For a certain application in The speedup achieved by running on multiple cores compared to running on a single core is... The value can be determined based on the number of cores it occupies during the actual scheduling process.

[0096] The Karp-flatt theory refers to an index that measures the "effective serialization ratio" of a program, given the parallelism (i.e., how many cores are used) and the measured actual speedup.

[0097] The proportion of real-time parallelizability of an application The higher the number, the greater the performance improvement from adding processor cores, meaning the more sensitive the processor is to core resources. For example... Figure 1 As shown, the parallelizability of the application changes dynamically over time, indicating that its sensitivity to the core changes dynamically over time, thus making online measurement crucial.

[0098] Real-time parallelizable scaling measurement methods, such as Figure 2 As shown. Because measuring the real-time parallelization ratio of an application at runtime introduces additional time overhead and interferes with the application under test, it is necessary to perform this measurement periodically, i.e., allow the application to run normally for a period of time first. Then enter the time-consuming phase. The measurement phase. During normal operation, the IPC (instructions per cycle) value for multi-core parallel operation is calculated; during the measurement phase, the single-core IPC value is calculated. If... If the value is too large, the measurement will be time-consuming, potentially affecting the normal execution of the application; if it is too small, the obtained F value will be unstable. The speedup ratio is calculated by measuring the IPC value of a single core during a specific time period and then using this measured IPC value. = IPC during multi-core operation / IPC during single-core operation. The parallelization ratio is calculated using formula (1) based on the current number of cores. Due to the long measurement interval, the multi-core IPC measured during operation is more stable. Measuring single-core IPC does not involve core changes, and the observed IPC value is stable, so the calculated F value is also stable.

[0099] 2. Analyzing LLC Sensitivity

[0100] This system's LLC sensitivity analysis is based on online, lightweight profiling of application behavior. It quantifies sensitivity by focusing on the curve of cache misses per thousand instructions (MPKI) as a function of LLC allocation capacity. This method is superior to traditional miss rate (MR) curves because MPKI not only reflects program locality but also includes instruction access density information, thus more directly relating to the application's actual performance (such as IPC or latency).

[0101] The MPKI curve is obtained based on Intel's Cache Allocation Technology (CAT), such as... Figure 5 As shown, the number of LLC paths used in the measurement phase is dynamically changing. Therefore, by dynamically limiting the target application to a specific range of cache paths and measuring its cache misses and instruction executions within a short time interval t, the MPKI curve as a function of cache capacity can be efficiently plotted. Here, "limiting" means allowing the application to run for a short period at the target LLC path count to measure the corresponding performance metrics.

[0102] Using this curve, the scheduler Pharos proposed in this invention can identify applications most sensitive to LLC resources under the current resource configuration. The larger the absolute value of the slope of the MPKI curve under a certain LLC configuration, the more sensitive the application is to LLC capacity. This invention approximates the descent slope of the MPKI curve at the current configuration point by calculating the difference between the MPKI value of an application under the current LLC capacity allocation and the MPKI value after increasing the capacity by one unit, thereby quantifying its sensitivity to LLC capacity. During scheduling, limited LLC resources are allocated to applications that can obtain the greatest marginal performance improvement, thus improving the overall system throughput and significantly reducing system entropy while ensuring the service quality of latency-sensitive applications.

[0103] 3. Analyze memory bandwidth sensitivity

[0104] The system uses a hardware performance monitoring unit (PMU) to obtain real-time data. The metric is the percentage of CPU cycles that are idle while waiting for memory access.

[0105] We selected the percentage of memory standby periods ( This metric is chosen because its trend with varying Memory Bandwidth Allocation (MBA) levels closely matches LC tail latency: as MBA limits tighten, The tail latency increases monotonically in sync with this. Therefore, by sorting applications by the percentage of memory stagnation periods, their memory bandwidth sensitivity level can be directly and effectively determined, allowing Pharos to accurately identify applications that should be prioritized for bandwidth allocation.

[0106] like Figure 3 As shown, this metric is highly correlated with the application's tail latency and can directly reflect the degree to which the application is limited by memory bandwidth.

[0107] 4. Decision-making and allocation

[0108] After identifying the benefiting application, the system calls the `selectResourceType` function to compare the application's sensitivity ranking across three dimensions: cores, LLC, and memory bandwidth. Resources ranking in the top x% (where x can be a value between 10 and 50 depending on the specific application scenario) are selected as candidate resources (added to the sensitive resource candidate list). Then, one type of resource is randomly selected from these candidate resources for allocation. The reason for using a random selection strategy is that sensitivity assessment is the result of ranking and comparing resources within each resource category. This ranking may be subject to errors due to various factors (such as measurement errors and real-time changes in program behavior). Therefore, introducing a random mechanism helps improve the robustness of the resource allocation strategy, avoiding system bias due to assessment bias, and thus maintaining the overall balance and adaptability of resource scheduling.

[0109] Figure 4 An implementation example is provided: when the performance of the Xapian application degraded, this invention analyzed the bottleneck and found that it was due to insufficient core count. Therefore, more cores were allocated to it, successfully restoring performance. In contrast, the ARQ method described in the patent "Resource Scheduling Method, Application Identification Method and Related Equipment for Cloud Computing Systems" incorrectly allocated LLC, which was not only ineffective but also interfered with other applications.

[0110] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0111] like Figure 7 As shown, this invention also proposes a real-time data center resource scheduling device B based on multi-dimensional resource sensitivity awareness, which includes:

[0112] The quantization module enables the data center to execute multiple target applications concurrently in real time. For each target application, the module quantifies its sensitivity to at least two different hardware resource types.

[0113] In the module selection, the data center selects the most sensitive hardware resource type as the sensitive hardware resource type for the target application.

[0114] The scheduling module, located in the data center, schedules the target application to run on hardware resources belonging to the sensitive hardware resource type, and obtains the running result of the target application.

[0115] The types of hardware resources in the quantization module include: processor cores, final-level cache LLC, and memory bandwidth.

[0116] The aforementioned real-time data center resource scheduling device based on multi-dimensional resource sensitivity awareness, wherein the quantization module includes:

[0117] When quantifying the sensitivity of the target application to processor cores, the parallelization ratio of the target application is periodically detected. The target application has been running for a period of time Then enters the time-consuming phase. The measurement phase; in this measurement phase, the parallelization ratio of the target application is detected by the following formula. This refers to the sensitivity of the target application to the processor core;

[0118] in, For this target application in The speedup achieved by running on multiple cores compared to running on a single core;

[0119] exist Measure single-core IPC value over a time period. Internal measurement One core IPC value, using The ratio of the IPC value per core to the IPC value per single core is used as the speedup ratio. .

[0120] The aforementioned real-time data center resource scheduling device based on multi-dimensional resource sensitivity awareness, wherein the quantization module includes:

[0121] When quantifying the sensitivity of the target application to the last-level cache LLC, monitor the curve of the number of cache misses (MPKI) during the runtime of the target application as a function of the LLC allocation capacity;

[0122] The curve is obtained by dynamically limiting the target application to a specific range of cache paths and measuring its cache misses and instruction executions at intervals t. The slope of the curve for the target application is then used as the sensitivity of the target application to the last-level cache LLC.

[0123] This quantization module includes:

[0124] When quantifying the target application's sensitivity to memory bandwidth, a hardware performance monitoring unit (PMU) is used to obtain in real-time the percentage of CPU cycles that are idle due to waiting for memory access during the execution of each target application. This is due to the target application's sensitivity to memory bandwidth.

[0125] like Figure 8 As shown, in another embodiment of the present invention, a first electronic device A is also proposed, which includes the aforementioned data center resource real-time scheduling device B based on multi-dimensional resource sensitivity perception.

[0126] like Figure 9 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D via wired or wireless information transmission schemes. The data acquisition device C is used to collect target applications, such as image classification programs, machine translation programs (natural language processing applications such as Moses), and search or indexing references (such as Xapian). The information display device D is used to display the running results obtained by the analysis of this invention, such as image classification results, text translation results, and search results.

[0127] The information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can present the user with the specified key information based on user-defined display parameters and / or attributes, such as the data range and font, color, and scrolling options. Users can access this information more quickly without needing to navigate to secondary pages or scroll through pages, saving them time and effort. Alternatively, the information display mechanism can be an artificial intelligence (AI) display model that learns the user's key information interests based on past usage habits, such as viewing time, click count, and edit count, and automatically presents rich and necessary key information.

[0128] The present invention also provides a computer program product, which includes a computer program that can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness provided by the above methods.

[0129] In another embodiment, the present invention also proposes a storage medium VIII for storing a computer program that executes the aforementioned real-time data center resource scheduling method based on multi-dimensional resource sensitivity awareness. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0130] Figure 10 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0131] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.

[0132] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0133] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S3. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).

[0134] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for real-time scheduling of data center resources based on multi-dimensional resource sensitivity awareness, the method comprising: receiving a request for a resource; determining a resource sensitivity profile for the request; and scheduling the request based on the resource sensitivity profile. The method comprises the following steps: a quantification step, in which the data center quantifies the sensitivity of each target application to at least two different types of hardware resources in real time and concurrently; a selection step, in which the data center selects the type of hardware resource with the highest sensitivity as the sensitive hardware resource type of the target application; a scheduling step, in which the data center schedules the target application to run on the hardware resource belonging to the sensitive hardware resource type, and obtains the running result of the target application. In the quantification step, the types of hardware resources include processor cores, last-level caches LLC, and memory bandwidth.

2. The method for real-time scheduling of data center resources based on multi-dimensional resource sensitivity awareness as claimed in claim 1, wherein, The quantification step comprises the following steps: detecting a parallelization ratio of the target application periodically , the target application runs for a while the post-entry time consumption ; in the measurement phase, the parallelization ratio of the target application is detected by , as the sensitivity of the target application to the processor core; wherein, the target application runs on a speedup ratio resulting from running the target application on In period measures a single core IPC value, at time measures core IPC value, using ratio of the multi core IPC value and the single core IPC value as the speedup ratio ; The sensitivity of the target application to the processor core resource is determined by ranking the real-time parallelization ratio of each target application. If the real-time parallelization ratio of the application is in the top x% of all applications, and x ranges from 10 to 50, the application is considered to be sensitive to the processor core.

3. The method for real-time scheduling of data center resources based on multi-dimensional resource sensitivity awareness as claimed in claim 1, wherein, The quantification step comprises the following steps: When quantifying the sensitivity of the target application to the LLC, the curve of the number of cache misses MPKI of the target application when running with the LLC allocation capacity is monitored; The curve is obtained by dynamically limiting the target application to a specific range of cache ways and measuring the number of cache misses and instruction executions within an interval time t. The slope of the curve of the target application is calculated as the sensitivity of the target application to the LLC. The sensitivity of the target application to the on-chip LLC resource is determined by ranking the MPKI slope of each target application under the current on-chip LLC capacity. If the slope of the application is in the top x% of all target applications, and x ranges from 10 to 50, the application is considered to be sensitive to the on-chip LLC.

4. The method for real-time scheduling of data center resources based on multi-dimensional resource sensitivity awareness as claimed in claim 1, wherein, The quantification step comprises the following steps: When quantifying the sensitivity of the target application to memory bandwidth, the proportion of cycles that the CPU stalls for memory accesses is obtained in real time using the hardware performance monitoring unit PMU when each of the target application is executed as the sensitivity of the target application to memory bandwidth; The method for determining the sensitivity of a target application to memory bandwidth resources is as follows: for each target application... Sort according to the target application's... If a target application is ranked in the top x% of all target applications, with x ranging from 10 to 50, then the target application is considered to be memory bandwidth sensitive.

5. A multi-dimensional resource sensitivity aware based data center resource real-time scheduling apparatus, characterized in that, The method comprises the following steps: a quantification module, in which the data center quantifies the sensitivity of each target application to at least two different types of hardware resources in real time and concurrently; a selection module, in which the data center selects the type of hardware resource with the highest sensitivity as the sensitive hardware resource type of the target application; a scheduling module, in which the data center schedules the target application to run on the hardware resource belonging to the sensitive hardware resource type, and obtains the running result of the target application. In the quantification module, the types of hardware resources include processor cores, last-level caches LLC, and memory bandwidth.

6. The data center resource real-time scheduling apparatus based on multi-dimensional resource sensitivity perception of claim 5, wherein, The quantification module comprises the following steps: sensitivity of the target application to the processor core , the target application is run for a period of time post-entry time consumption of the measurement phase; in the measurement phase the parallelization ratio of the target application is detected by as the sensitivity of the target application to the processor core wherein, the target application runs on a speedup ratio resulting from running the target application on In period measures a single core IPC value, at time measures core IPC value, uses core IPC value and the ratio of the single core IPC value as the speedup ratio ; The sensitivity of the target application to the processor core resource is determined by ranking the real-time parallelization ratio of each target application. If the real-time parallelization ratio of the application is in the top x% of all applications, and x ranges from 10 to 50, the application is considered to be sensitive to the processor core.

7. The data center resource real-time scheduling apparatus based on multi-dimensional resource sensitivity perception of claim 5, wherein, The quantification module comprises the following steps: When quantifying the sensitivity of the target application to the LLC, the curve of the number of cache misses MPKI of the target application when running with the LLC allocation capacity is monitored; The curve is obtained by dynamically limiting the target application program in a specific cache path quantity range, and measuring the cache miss number and instruction execution number within an interval time t; and the slope of the curve of the target application program is taken as the sensitivity of the target application program to the last level cache LLC; The sensitivity confirmation method of the application program to the on-chip last level cache resource is: sorting the MPKI slope of each target application program under the current on-chip last level cache capacity, if the slope of the application is located in the top x% of all applications, and the value range of x is 10 to 50, it is considered that the target application program is sensitive to the on-chip last level cache; The quantification module comprises: When quantifying the sensitivity of the target application to memory bandwidth, the proportion of cycles that the CPU stalls for memory accesses is obtained in real time using the hardware performance monitoring unit PMU when each of the target application is executed as the sensitivity of the target application to memory bandwidth; The method for confirming the sensitivity of target application programs to memory bandwidth resources is: for each target application program is sorted, if the target application program is located in the top x% of all target application programs, and x is in the range of 10 to 50, it is considered that the target application program is sensitive to memory bandwidth.

8. An electronic device, comprising: The electronic device comprises the data center resource real-time scheduling device based on multi-dimensional resource sensitivity perception as claimed in claims 5-7, or is connected with an information display device, and the information display device is used for displaying the running result by a user-set display parameter, attribute or through an artificial intelligence model. 9.A computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the steps of the data center resource real-time scheduling method based on multi-dimensional resource sensitivity perception as claimed in any one of claims 1-4.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the data center resource real-time scheduling method based on multi-dimensional resource sensitivity perception as claimed in any one of claims 1-4.

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