Chip program burning adapter and chip program burning method and system

Abstract

The invention provides a chip program burning adapter and a chip program burning method and system, and relates to the technical field of chip program burning. The chip program burning adapter comprises a universal burning base, a field programmable gate array (FPGA) chip and a flash memory chip; a plurality of slots are formed in the universal burning base, and the universal burning base is in plug-in connection with pins of at least one chip to be burnt through the slots; a plurality of slots of the universal burning base are respectively connected with corresponding interfaces on the FPGA chip; the FPGA chip comprises an online programming interface, a storage interface and a program burning interface, the online programming interface is used for being connected with an upper computer, the storage interface is used for being connected with the flash memory chip, and the program burning interface is used for being connected with a burner. The adapter disclosed by the invention has relatively high universality, and different chips to be burnt can be adapted without designing one adapter for each chip.

Description

Technical Field

[0001] This application relates to the field of chip programming technology, and more specifically, to a chip programming adapter, a chip programming method and system. Background Technology

[0002] Complex electronic systems often integrate a large number of various control boards. These boards serve as the core carriers for realizing system functions, and the types of chips integrated on them can reach hundreds or even thousands. For example, in terms of packaging, they include various types such as Dual In-line Package (DIP), Small Outline Package (SOP), Thin Shrink Small Outline Package (TSSOP), Quad Flat No-leads Package (QFN), and Ball Grid Array Package (BGA). Moreover, the number of pins varies significantly among different types of chips, ranging from a few pins to thousands of pins.

[0003] During the development, debugging, manufacturing, and maintenance of complex systems, it is necessary to program the chips on the circuit board, that is, to write the preset firmware program and logic configuration file into the chip to realize the chip's intended function. At present, the common technical solution adopted in the industry is "one chip corresponds to one programming adapter". Since there is no unified standard for the pin definitions of different chips (for example, there are significant differences in the assignment of programming pin functions), engineers need to prepare hundreds of different programming adapters when facing programming requirements for multiple types of chips.

[0004] In practice, it is necessary to frequently change the adapter to match the chip to be programmed, which not only increases the operating cost, but also easily leads to programming failure due to incorrect adapter selection or improper installation, which seriously affects the development and debugging progress and the operating efficiency of the production line. Summary of the Invention

[0005] This application addresses the shortcomings of the prior art by providing a chip programming adapter, a chip programming method, and a system to solve the problems existing in the prior art.

[0006] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a chip programming adapter, including: a universal programming dock, a field-programmable gate array (FPGA) chip, and a flash memory chip; The universal programming socket is provided with multiple slots, and the universal programming socket is connected to the pins of at least one chip to be programmed through the multiple slots; the multiple slots of the universal programming socket are respectively connected to the corresponding interfaces on the FPGA chip. The FPGA chip includes an online programming interface, a storage interface, and a program programming interface. The online programming interface is used to connect to a host computer, the storage interface is used to connect to the flash memory chip, and the program programming interface is used to connect to a programmer.

[0007] In one embodiment, the universal programming base is provided with a clamping cover having an elastic limiting device.

[0008] In one embodiment, the spacing between the plurality of slots on the universal programming dock is the same.

[0009] Secondly, embodiments of this application provide a chip programming method, applied to a Field Programmable Gate Array (FPGA) chip in a chip programming adapter described in any of the above embodiments, the method comprising: Receive interface configuration information sent by the host computer through the online programming interface; Based on the interface configuration information, the interface configuration program in the flash memory is updated through the storage interface; the interface configuration program is used to indicate the correspondence between the interface of the FPGA chip and the pins of the chip to be programmed. The programming interface receives the programming program sent by the programmer for the target pin of the chip to be programmed. According to the interface configuration program, the programming program is programmed into the chip through the target pin of the chip to be programmed.

[0010] In one embodiment, before configuring the programming program according to the interface and programming the programming program into the chip to be programmed through the target pin of the chip to be programmed, the method further includes: Reboot the FPGA chip to retrieve the interface configuration program stored in the flash memory.

[0011] In one embodiment, the step of programming the programming program into the chip through the target pin of the chip to be programmed according to the interface configuration program includes: Based on the interface configuration program, the target pin of the chip to be programmed is determined according to the programming program; The programming program is programmed into the chip through the target pin of the chip to be programmed.

[0012] In one embodiment, before receiving the programming program for the target pin of the chip to be programmed sent by the programmer through the programming interface, the method further includes: The interface configuration program is validated; The step of receiving the programming program for the target pin of the chip to be programmed, sent by the programmer through the programming interface, includes: If the interface configuration program passes the verification, the programmer sends the programming program for the target pin of the chip to be programmed through the programming interface.

[0013] In one embodiment, the method further includes: If the interface configuration program fails verification, an alarm message is sent to the host computer so that the host computer can resend the interface configuration information to the FPGA chip.

[0014] In one embodiment, if the interface configuration program verification fails, sending an alarm message to the host computer so that the host computer resends the interface configuration information to the FPGA chip includes: Determine whether the number of times the interface configuration program fails verification is less than a preset threshold. If the number of times the interface configuration program fails to pass verification is less than the preset threshold, an alarm message is sent to the host computer so that the host computer resends the interface configuration information to the FPGA chip.

[0015] Thirdly, embodiments of this application provide a chip programming system, including: the chip programming adapter, programmer, and host computer described in any of the above embodiments; The online programming interface of the FPGA chip in the chip programming adapter is connected to the host computer, the programming interface of the FPGA chip is connected to the programmer, and the control interface of the programmer is connected to the host computer.

[0016] The beneficial effects of this application are as follows: This application provides a chip programming adapter, including a universal programming socket, a field-programmable gate array (FPGA) chip, and a flash memory chip; the universal programming socket is provided with multiple slots, and the universal programming socket is connected to the pins of at least one chip to be programmed through the multiple slots; the multiple slots of the universal programming socket are respectively connected to corresponding interfaces on the FPGA chip; the FPGA chip includes: an online programming interface, a storage interface, and a programming interface, wherein the online programming interface is used to connect to a host computer, the storage interface is used to connect to the flash memory chip, and the programming interface is used to connect to a programmer.

[0017] The adapter in this application has high versatility. It only requires one FPGA chip and one flash memory chip to program different types of chips. There is no need to design an adapter for each type of chip, which reduces the chip programming cost and improves the development and debugging progress and the efficiency of the production line. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the chip programming adapter provided in the embodiments of this application; Figure 2 This is a schematic diagram illustrating the insertion of different chips into the same socket, as provided in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of the universal programming socket provided in the embodiments of this application; Figure 4 This is one of the flowcharts illustrating the chip programming method provided in this application embodiment; Figure 5 A schematic diagram of the interface of the host computer configuration software provided in the embodiments of this application; Figure 6 A second schematic flowchart illustrating the chip programming method provided in this application embodiment; Figure 7 The third schematic flowchart of the chip programming method provided in this application embodiment; Figure 8 The fourth schematic flowchart of the chip programming method provided in the embodiments of this application; Figure 9 This is a schematic diagram of the chip programming system provided in the embodiments of this application; Figure 10 This is a schematic diagram of the chip programming device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0023] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can be a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other. The embodiments provided in this application are illustrated below with reference to the accompanying drawings through multiple examples.

[0026] Figure 1 This is a schematic diagram of the chip programming adapter provided in the embodiments of this application, as shown below. Figure 1 As shown, the programming adapter includes a universal programming dock, a field-programmable gate array (FPGA) chip, and a flash memory chip.

[0027] The universal programming socket has multiple slots, which are used to connect to the pins of at least one chip to be programmed. The multiple slots of the universal programming socket are respectively connected to the corresponding interfaces on the FPGA chip.

[0028] Specifically, the universal programming socket is the basic hardware for achieving "one socket for multiple uses". Its design follows the principle of "full coverage of similar packages". The multiple slots on the socket are spaced uniformly, and the total number of slots is adapted to the maximum number of pins of chips of the same package. For example, for DIP type packaged chips, it is known that the maximum number of pins of existing DIP packaged chips is 64P. Therefore, the number of slots of the universal programming socket is set to 64, forming a DIP-64 socket.

[0029] like Figure 2 As shown, when the chip to be programmed is a DIP packaged chip with different pin counts, such as DIP-8 or DIP-16, simply align pin 1 of the chip with pin 1 of the socket and insert it. A connection can then be established with the FPGA chip through the 64 slots of the socket, without needing to replace the socket. Similarly, for SOP and TSSOP packaged chips, the number of socket slots is adapted to the maximum number of pins for that type of package (usually no more than 100); for QFN packaged chips, the number of socket slots is adapted to their maximum number of pins (usually no more than 200); and for QFP and TQFP packaged chips, the number of socket slots is adapted to their maximum number of pins (usually no more than 400).

[0030] A clamping cover with an elastic limiting device is installed on the universal programming socket. When the chip to be programmed is inserted into the socket, the elastic pressure of the clamping cover will firmly fix the chip on the socket, ensuring that each pin of the chip can make stable contact with the socket slot and avoiding programming failure due to contact problems.

[0031] The FPGA chip, as the core control unit, is responsible for port mapping, data interaction, and flow control. Its hardware interface and functional design are as follows: Interface Configuration: The FPGA chip is equipped with an in-circuit programming interface, a storage interface, and a program programming interface. The in-circuit programming interface connects to the host computer using a standard communication protocol, supporting high-speed reception of interface configuration information sent by the host computer. This information includes the programming interface type (such as JTAG, SWD, ISP, SPI, I2C, etc.) and the corresponding programming pin number. The storage interface connects to the flash memory chip via the SPI protocol, enabling high-speed storage and retrieval of the programming program and configuration information. The program programming interface matches the corresponding interface of the programmer, completing the transmission of interface configuration information and the reception of the programming program.

[0032] I / O Interface Expansion: To address the differences in pin counts among different packaged chips, FPGA chips employ flexible I / O interface configuration schemes. For conventional packaged chips such as DIP and SOP, the number of I / O interfaces on a single FPGA chip (typically hundreds to thousands) can fully cover its maximum pin count, requiring no expansion. For BGA packaged chips with a pin count exceeding the coverage of a single FPGA chip's I / O interfaces, multiple FPGA chips are cascaded, and I / O interface expansion is achieved through synchronous communication protocols between FPGAs, ensuring coverage of all pins on the BGA packaged chip and meeting programming requirements.

[0033] Flash memory chips, as storage units, are used to store the programming program and corresponding interface configuration information. Their storage area division and functional design are as follows: Partitioned storage: Based on the different interface types of the FPGA chip and the corresponding package type of the chip to be programmed, the flash memory chip is divided into multiple independent storage areas. For example, there is a storage area corresponding to the JTAG interface, a storage area corresponding to the SWD interface, etc., and each storage area is further subdivided into program storage sub-areas for different package types of chips. After the FPGA chip completes the parsing of the interface configuration information, the programming program can be accurately stored in the corresponding storage area, avoiding program storage chaos and facilitating subsequent fast retrieval.

[0034] Data Backup: The flash memory chip also features data backup functionality, performing real-time backups of the stored programming program and interface configuration information. If stored data is corrupted or lost, it can be recovered from the backup, ensuring an uninterrupted programming process and improving device reliability.

[0035] In one embodiment, Figure 3 This is a schematic diagram of the structure of the universal programming dock provided in the embodiments of this application, as shown below. Figure 3 As shown, the spacing between the multiple slots on the universal programming dock is the same, ensuring that chips with different pin counts and the same package type can be stably plugged in without adjusting the dock's hardware structure. Figure 3 The dotted line in the lower left corner indicates the position of the placed chip.

[0036] In summary, the adapter of this application has high versatility. It only requires one FPGA chip and one flash memory chip to program different types of chips, eliminating the need to design an adapter for each type of chip. This reduces chip programming costs and improves development and debugging progress as well as production line efficiency.

[0037] Figure 4 This is one of the flowcharts illustrating the chip programming method provided in this application embodiment, such as... Figure 4As shown, this application also provides a chip programming method, applied to a Field Programmable Gate Array (FPGA) chip in the chip programming adapter provided in any of the above embodiments, the method comprising: S101. Receive interface configuration information sent by the host computer through the online programming interface.

[0038] The host computer is equipped with dedicated configuration software that exhaustively covers mainstream standard programming interfaces such as JTAG, SWD, ISP, SPI, and I2C, and provides an independent configuration interface for each interface. Before programming, the user first determines the programming interface type and corresponding pin numbers of the chip based on the chip's datasheet. Then, in the host computer's configuration software, the user selects the corresponding programming interface configuration interface and enters the programming pin numbers into the designated boxes. After inputting the information, the user clicks the "Connect" button to connect the host computer to the chip programming adapter, and then clicks the "Send" button. The host computer generates interface configuration information based on the input information and sends this information to the FPGA chip through the FPGA chip's online programming interface. Simultaneously, the host computer's serial port information display window shows a real-time "Configuration information being sent" status message.

[0039] For example Figure 5 As shown, the user opens the host computer configuration software, selects "JTAG" in the interface type selection bar, and enters the JTAG interface configuration interface. Based on the chip's datasheet, the user inputs the corresponding programming pin numbers for each signal (e.g., enter "10" in the "TMS Pin Number" input box, "11" in the "TCK Pin Number" input box, "12" in the "TDI Pin Number" input box, and "13" in the "TDO Pin Number" input box). After inputting the information, click the "Generate Configuration" button. The host computer automatically generates interface configuration information containing "Interface Type: JTAG; TMS Pin Number: 10; TCK Pin Number: 11; TDI Pin Number: 12; TDO Pin Number: 13," which is encapsulated in JSON format.

[0040] Subsequently, the user clicks the "Connect" button to complete the connection between the host computer and the chip programming adapter, and then clicks the "Send" button. The host computer sends the interface configuration information to the FPGA chip via a USB data cable (connecting the host computer's USB interface to the FPGA chip's online programming interface). After receiving the data, the FPGA chip's online programming interface first performs data frame verification (checking whether the frame header and frame tail are complete). If the verification passes, it is temporarily stored in an internal register, and at the same time, an ACK signal indicating "configuration information received successfully" is sent back to the host computer. This feedback information is displayed in real time in the host computer's serial port information display window.

[0041] Apart from the "JTAG" type programming interface, other types of programming interfaces are designed as described above. Although there are many types of chips and the pin definitions cannot be unified, the programming interface types are specified by IEEE or industry / enterprise standards, and the types are relatively fixed. You can exhaustively list them during the design process and configure them accordingly during use.

[0042] S102. Based on the interface configuration information, update the interface configuration program in the flash memory through the storage interface.

[0043] After receiving the interface configuration information, the FPGA chip converts the information into an executable interface configuration program through its own storage interface and writes it into the flash memory. The written program is then verified to ensure that there is no loss or error in the program.

[0044] This interface configuration program clarifies the one-to-one correspondence between each I / O port of the FPGA chip and the pins of the chip to be programmed, and also includes the adaptation logic of the interface communication protocol, providing the instruction basis for the subsequent transmission of the programming program.

[0045] S103: Receive the programming program sent by the programmer for the target pin of the chip to be programmed through the programming interface.

[0046] The FPGA chip establishes a communication connection with an external programmer through a programming interface. The programmer sends the compiled programming program (including the chip's control logic and functional algorithms) for the target pins of the chip to be programmed to the FPGA chip through the programming interface, according to the chip's model and functional requirements. The FPGA chip performs a preliminary integrity check on the received programming program to ensure that the program data packet is intact.

[0047] S104. According to the interface configuration program, the programming program is programmed into the chip through the target pin of the chip to be programmed.

[0048] The FPGA chip transmits the received programming program frame by frame to the target pin of the chip to be programmed, based on the interface configuration program loaded in the flash memory and the correspondence between the I / O ports and the target pins of the chip to be programmed as defined in the program, and completes the program writing operation according to the timing requirements of the interface communication protocol.

[0049] During the programming process, the FPGA chip feeds back the programming progress and status to the host computer in real time. After the programming program is completely written, the program verification process of the chip to be programmed is triggered to confirm that the program has been successfully programmed into the chip's internal storage area, thus completing the entire programming task.

[0050] If the chip to be programmed is replaced with another chip of the same package (DIP package) but with different pin definitions, you only need to reconfigure the pin mapping information of the corresponding interface on the host machine in step S101, and repeat the above steps to complete the programming. There is no need to replace the programming adapter.

[0051] Specifically, Figure 6 This is a second schematic flowchart of the chip programming method provided in the embodiments of this application, as shown below. Figure 6 As shown, before performing step S104, the method of this application further includes: S201. Restart the FPGA chip to obtain the interface configuration program stored in the flash memory.

[0052] The FPGA chip automatically triggers an internal reset signal to execute a restart process. During the restart, the FPGA chip initializes its internal logic circuits, clears temporary register data, and then reads the interface configuration program stored in the flash memory through the storage interface and loads the program into the FPGA's internal registers.

[0053] Step S104 includes: S202. Based on the interface configuration program, determine the target pin of the chip to be programmed according to the programming program.

[0054] The mapping table in the FPGA chip parsing interface configuration program is used to extract key mapping rules related to program burning. For example, it is determined that the FPGA chip's IO20 interface corresponds to the TCK pin of the chip to be burned, the FPGA chip's IO22 interface corresponds to the TMS pin of the chip to be burned, the FPGA chip's IO24 interface corresponds to the TDI pin of the chip to be burned, and the FPGA chip's IO26 interface corresponds to the TDO pin of the chip to be burned.

[0055] Then, based on the pin information in the programming program, the target pin of the chip to be programmed is determined. At the same time, the FPGA chip reads the timing parameters of the communication protocol, such as the TCK clock frequency (set to 10MHz), the TMS signal level switching timing, and the TDI data transmission width (8 bits), to ensure that the subsequent programming program transmission matches the pin response timing of the chip to be programmed, and avoids data transmission errors due to timing deviations.

[0056] S203. The programming program is programmed into the chip through the target pin of the chip to be programmed.

[0057] In summary, this embodiment provides a chip programming method that uses FPGA port mapping and flash memory partitioning for storage. The same process can be adapted to chips with different pin definitions in the same package, eliminating the need to design a separate programming process for each type of chip.

[0058] Figure 7This is the third flowchart illustrating the chip programming method provided in this application embodiment, as shown below. Figure 7 As shown, before executing step S103, which involves receiving the programming program for the target pin of the chip to be programmed from the programmer via the programming interface, the method of this application further includes: S301. Verify the interface configuration program.

[0059] The FPGA chip reads the interface configuration program from flash memory storage area 1 and performs dual verification, including: Integrity verification: The FPGA chip reads the storage address range of the interface configuration program in the flash memory (0x0000-0x1FFF by default), extracts the CRC32 checksum from the program header (this checksum is generated and attached synchronously by the host computer when the configuration information is sent from S101), and at the same time, the FPGA chip recalculates the CRC32 value of the currently loaded interface configuration program data and compares the calculation result with the checksum from the program header. If the two match, the data integrity verification passes; if they do not match, the verification fails.

[0060] Validity verification: Verify the mapping relationship between FPGA I / O ports and the pins of the chip to be programmed in the program to ensure that the mapped FPGA I / O ports are valid and usable ports.

[0061] If both verifications pass, proceed to the next step of the programming process; if either verification fails, the verification failure handling mechanism is triggered.

[0062] S103 describes receiving the programming program sent by the programmer to the target pin of the chip to be programmed via the programming interface, including: S302. If the interface configuration program verification passes, the programmer sends the programming program for the target pin of the chip to be programmed through the programming interface.

[0063] In one embodiment, the method of this application further includes: S303. If the interface configuration program fails to verify, an alarm message is sent to the host computer so that the host computer can resend the interface configuration information to the FPGA chip.

[0064] Specifically, Figure 8 This is the fourth flowchart illustrating the chip programming method provided in this application embodiment, as shown below. Figure 8 As shown, S303 includes: S401. Determine whether the number of times the interface configuration program fails to verify is less than the preset threshold.

[0065] The FPGA chip has an internal verification failure counter, which is initially set to 0. When a verification fails, the counter value is incremented by 1 (e.g., from 0 to 1), and it is determined whether the counter value is less than a preset threshold number (in this embodiment, the preset threshold number is 3).

[0066] S402. If the number of times the interface configuration program fails to pass verification is less than the preset threshold, an alarm message is sent to the host computer so that the host computer resends the interface configuration information to the FPGA chip.

[0067] If the counter value (e.g., 1) is less than the threshold (3 times), the FPGA chip sends an alarm message to the host computer through the online programming interface. The message content is, for example, "Interface configuration program verification failed (reason: integrity verification mismatch), please resend the configuration information". The host computer serial port information display window displays the alarm message in red flashing font, and at the same time automatically regenerates and resends the interface configuration information, and returns to step S101.

[0068] If the counter value reaches the threshold (e.g., three consecutive verification failures), the FPGA chip sends a fault message to the host computer: "Verification failure count reaches threshold, programming process paused." The host computer triggers an audible and visual alarm (buzzer sounds + indicator light flashes) and displays a troubleshooting prompt on the interface: "It is recommended to check the chip pin definitions." The user needs to troubleshoot the problem and then manually restart the programming process.

[0069] In summary, this application provides a chip programming method with the following advantages: 1. By mapping FPGA ports and partitioning flash memory, the same process can be adapted to chips with different pin definitions in the same package, without the need to design a separate programming process for each chip.

[0070] 2. The host computer provides visual configuration, eliminating the need for manual debugging of FPGA ports and lowering the barrier to entry for engineers.

[0071] 3. The program is stored in flash memory, so there is no need to receive the program again when programming the same type of chip, thus shortening the programming cycle.

[0072] Figure 9 This is a schematic diagram of the chip programming system provided in the embodiments of this application, as shown below. Figure 9 As shown, this application also provides a chip programming system, including the chip programming adapter, programmer, and host computer provided in any of the above embodiments.

[0073] The in-circuit programming interface of the FPGA chip in the chip programming adapter is connected to the host computer, the programming interface of the FPGA chip is connected to the programmer, and the control interface of the programmer is connected to the host computer.

[0074] The following will continue to explain the apparatus and storage medium for implementing the chip programming method provided in any of the above embodiments of this application. The specific implementation process and the resulting technical effects are the same as those in the corresponding method embodiments. For the sake of brevity, the parts not mentioned in the following embodiments can be referred to the corresponding content in the method embodiments.

[0075] Figure 10 This is a schematic diagram of the chip programming apparatus provided in the embodiments of this application, as shown below. Figure 10 As shown, this application also provides a chip programming apparatus, applied to a Field Programmable Gate Array (FPGA) chip in the chip programming adapter of any of the above embodiments, the apparatus comprising: The first receiving module 10 is used to receive interface configuration information sent by the host computer through an online programming interface.

[0076] The update module 20 is used to update the interface configuration program in the flash memory through the storage interface according to the interface configuration information; the interface configuration program is used to indicate the correspondence between the interface of the FPGA chip and the pins of the chip to be programmed.

[0077] The second receiving module 30 is used to receive the programming program sent by the programmer for the target pin of the chip to be programmed through the programming interface.

[0078] The programming module 40 is used to program the programming program into the chip to be programmed through the target pin of the chip to be programmed according to the interface configuration program.

[0079] Optionally, the apparatus of this application further includes an acquisition module for restarting the FPGA chip to acquire the interface configuration program stored in the flash memory.

[0080] Optionally, the programming module 40 is further configured to determine the target pin of the chip to be programmed corresponding to the programming program according to the interface configuration program; and to program the programming program into the chip to be programmed through the target pin of the chip to be programmed.

[0081] Optionally, the apparatus of this application further includes a verification module for verifying the interface configuration program. The second receiving module 30 is further configured to, if the interface configuration program passes the verification, receive, through the program programming interface, a programming program for the target pin of the chip to be programmed sent by the programmer.

[0082] Optionally, the apparatus of this application further includes a sending module, used to send an alarm message to the host computer if the interface configuration program verification fails, so that the host computer resends the interface configuration information to the FPGA chip.

[0083] Optionally, the sending module is further configured to determine whether the number of times the interface configuration program fails to verify is less than a preset threshold number; If the number of times the interface configuration program fails to pass verification is less than the preset threshold, an alarm message is sent to the host computer so that the host computer resends the interface configuration information to the FPGA chip.

[0084] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0085] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0086] This application also provides a readable storage medium storing program instructions, which, when executed by a processor, implement the chip programming method described in any of the above embodiments.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0088] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0090] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip program burning adapter, characterized in that, The chip program burning adapter comprises a universal burning base, a field programmable gate array (FPGA) chip and a flash memory chip. The universal burning base is provided with a plurality of slots, and the universal burning base is connected with pins of at least one chip to be burned through the plurality of slots. The plurality of slots of the universal burning base are respectively connected with corresponding interfaces of the FPGA chip. The FPGA chip comprises an online programming interface, a storage interface and a program burning interface, wherein the online programming interface is used for connecting a host computer, the storage interface is used for connecting the flash memory chip, and the program burning interface is used for connecting a burner. The universal burning base is provided with a compression cover with an elastic limiting device.

2. The chip program burn adapter of claim 1, wherein, The spacing between the plurality of slots of the universal burning base is the same.

3. The chip program burn adapter of claim 1, wherein, The FPGA chip is applied to the chip program burning adapter of any one of claims 1-3, and the method comprises the following steps of:

4. A chip program burning method, characterized in that, receiving interface configuration information sent by the host computer through the online programming interface; updating an interface configuration program in the flash memory according to the interface configuration information through the storage interface; the interface configuration program is used for indicating a corresponding relationship between interfaces of the FPGA chip and pins of the chip to be burned; receiving a burning program for a target pin of the chip to be burned sent by the burner through the program burning interface; burning the burning program into the chip to be burned through the target pin of the chip to be burned according to the interface configuration program. Before the burning program is burned into the chip to be burned through the target pin of the chip to be burned according to the interface configuration program, the method further comprises the following step of:

5. The method of claim 4, wherein, restarting the FPGA chip to obtain the interface configuration program stored in the flash memory. The burning program is burned into the chip to be burned through the target pin of the chip to be burned according to the interface configuration program, comprising the following steps of:

6. The method of claim 5, wherein, determining that the burning program corresponds to the target pin of the chip to be burned according to the interface configuration program; burning the burning program into the chip to be burned through the target pin of the chip to be burned. Before the burning program for the target pin of the chip to be burned sent by the burner is received through the program burning interface, the method further comprises the following steps of:

7. The method of claim 4, wherein, verifying the interface configuration program; the burning program for the target pin of the chip to be burned sent by the burner is received through the program burning interface, comprising the following step of: if the verification of the interface configuration program is passed, the burning program for the target pin of the chip to be burned sent by the burner is received through the program burning interface. The method further comprises the following steps of:

8. The method of claim 7, wherein, if the verification of the interface configuration program is not passed, alarm information is sent to the host computer, so that the host computer sends interface configuration information to the FPGA chip again. if the verification of the interface configuration program is not passed, alarm information is sent to the host computer, so that the host computer sends interface configuration information to the FPGA chip again, comprising the following steps of:

9. The method of claim 7, wherein, determining whether the number of times that the verification of the interface configuration program is not passed is less than a preset number threshold. ​ If the number of times of the interface configuration program check failure is less than the preset number threshold, alarm information is sent to the host computer, so that the host computer re-sends interface configuration information to the FPGA chip.

10. A chip program burning system, characterized in that, The application relates to a chip program burning adapter, a burner and a host computer. The online programming interface of the field programmable gate array (FPGA) chip in the chip program burning adapter is connected with the host computer, the program burning interface of the FPGA chip is connected with the burner, and the control interface of the burner is connected with the host computer. ​

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