Secret computing security management of systems in multi-chiplet, multi-accelerator package

Abstract

The invention relates to confidential computing security management of a system in a multi-chiplet and multi-accelerator package. Systems, apparatus, articles of manufacture, and methods are disclosed for secure computing security management of a multi-chiplet, multi-accelerator system in package. An example multi-die system in package (SiP) includes a first die including circuitry. Further, the example multi-die SiP includes a second die to authenticate the circuitry to permit secure communications within the SiP.

Description

Background Technology

[0001] The electronics industry has moved towards more compact designs of integrated circuits. Electronics manufacturers have developed compact circuit designs such as System-on-Chip (SoC) or System-in-Package (SiP). SoC and SiP encompass most or all of the components in an electrical system. SoC typically integrates components onto a single semiconductor die, while SiP typically includes multiple integrated circuits integrated onto a substrate within a carrier package. The integrated circuits used in SiP consist of semiconductor dies and are sometimes referred to as tiles or chiplets. Attached Figure Description

[0002] Figure 1 This is a block diagram of an example system that provides secure computing identification, authentication, and trust security for multiple accelerator circuits in a System-in-a-Package (SiP).

[0003] Figure 2 This diagram is used for reporting measurements. Figure 1 A block diagram illustrating example communication between a first example chiplet and a root of trust (RoT) device's confidential computing (DCC) circuitry.

[0004] Figure 3 The diagram is used in Figure 1 A block diagram illustrating an example communication between the Trusted Execution Environment (TEE) Security Management (TSM) circuitry of the core tile and the Chipset Device Security Management (CDSM) circuitry of the first chiplet, to establish a secure communication session.

[0005] Figure 4 The diagram is used in Figure 1 An additional example block diagram illustrating the communication between the TSM circuitry of the core tile and the CDSM circuitry of the first chiplet to establish a secure communication session.

[0006] Figure 5 yes Figure 1 Block diagrams of example implementations of the CDSM circuit and the RoTDCC circuit.

[0007] Figure 6 This is a flowchart illustrating example machine-readable instructions and / or example operations, which can be implemented, illustrated, and / or executed by example programmable circuit modules. Figure 1 The TSM circuit.

[0008] Figure 7 This is a flowchart illustrating example machine-readable instructions and / or example operations, which can be implemented, illustrated, and / or executed by example programmable circuit modules. Figure 1 CDSM circuit.

[0009] Figure 8 This is a flowchart illustrating example machine-readable instructions and / or example operations, which can be implemented, illustrated, and / or executed by example programmable circuit modules. Figure 1 The Rot DCC circuit.

[0010] Figure 9 This is a block diagram of a system-in-package (SiP) that includes an example fleet management system (FMS) circuit.

[0011] Figure 10 The description depends on the FMS circuit relative to Figure 9 A graphical illustration showing the availability of examples of FMS circuits where SiP is implemented.

[0012] Figure 11 It includes Figure 9 A block diagram of an example system for the FMS circuit.

[0013] Figure 12 yes Figure 9 A block diagram of an example implementation of the FMS circuit.

[0014] Figure 13 It is implemented in example memory and input / output chiplets of SiP. Figure 9 Example SiP block diagram of FMS circuit.

[0015] Figure 14 It is included in the example accelerator chiplet of SiP. Figure 9 Example SiP block diagram of FMS circuit.

[0016] Figure 15 It is included in the implementation outside the example SiP. Figure 9 A block diagram of an example system for the FMS circuit.

[0017] Figure 16 It is a block diagram of an example system including an example SiP, where Figure 9 The FMS circuit is implemented as a dedicated chip.

[0018] Figure 17 It is a diagram. Figure 9 A block diagram illustrating example communication between the FMS circuitry and the network in the example platform, wherein the example SiP includes example infrastructure processor unit (IPU) circuitry integrated within the SiP.

[0019] Figure 18 It is a diagram. Figure 9 A block diagram illustrating example communication between the FMS circuitry and the network in the example platform, where the example SiP includes an example network interface card (NIC) circuitry integrated externally to the SiP.

[0020] Figure 19 yes Figure 9 A block diagram of an example implementation of the FMS circuit.

[0021] Figure 20 This is a flowchart illustrating example machine-readable instructions and / or example operations, which can be implemented, illustrated, and / or executed by example programmable circuit modules. Figure 9 The FMS circuitry is used to identify the remote cluster manager and load it onto the board along with the remote cluster manager.

[0022] Figure 21 This is a flowchart illustrating example machine-readable instructions and / or example operations, which can be implemented, illustrated, and / or executed by example programmable circuit modules. Figure 9 The FMS circuit is used to perform cluster management.

[0023] Figure 22 This is a block diagram of an example processing platform including programmable circuit modules configured to execute, executor, and / or perform example machine-readable instructions and / or execute... Figure 6 , 7 Example operations of 8, 20 and / or 21 to achieve Figures 1-5 TSM circuit, Figures 1-5 CDSM circuit, Figures 1-5 ROT DCC circuit and / or Figures 9-19 The FMS circuit.

[0024] Figure 23 yes Figure 22 A block diagram of an example implementation of a programmable circuit module.

[0025] Figure 24 yes Figure 22 A block diagram of another example implementation of a programmable circuit module.

[0026] Figure 25 This is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) used to distribute software, instructions, and / or firmware (e.g., corresponding to...). Figure 6 , 7 Example machine-readable instructions (8, 20 and / or 21) are distributed to client devices associated with end users and / or consumers (e.g., for licensing, selling and / or using), retailers (e.g., for selling, reselling, licensing and / or sub-licensing) and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or other end users such as direct purchase customers).

[0027] Generally, the same reference numerals will be used throughout the accompanying drawings and written description to refer to the same or similar parts. The drawings are not necessarily drawn to scale. Detailed Implementation

[0028] A System-on-Package (SiP) typically comprises multiple integrated circuits (ICs) (e.g., dies, tiles, chiplets) integrated together within the same carrier package. In some examples, tiles, chiplets, and / or dies are modular ICs, and two or more such modular ICs can be combined to form a System-on-Chip (SoC) or SiP. In some examples, chiplets are located within a package having one or more other chiplets. For example, on-mount packages are used to stack ICs, place ICs side-by-side, and / or embed ICs in or on a substrate of the SiP. On-mount packages include coupling one or more leads of a first IC package to one or more leads of a second IC package to vertically combine the first and second ICs relative to a substrate on which one of the first or second ICs is disposed. For example, the leads of the first and second ICs can be implemented using solder pads interconnected via a ball grid array (BGA) or other surface mount technology (SMT).

[0029] A System-on-Package (SiP) can include multiple chiplets within the same package, each chiplet comprising multiple accelerator circuits, and each accelerator circuit operating as a Root Complex Integrated Endpoint Device (RCiEP). For example, an RCIEP is a device defined by the Peripheral Component Interconnect (PCIe) standard as an integrated device (e.g., integrated within a semiconductor package) that connects a central processing unit (CPU) and memory subsystem to a PCIe switching architecture comprising one or more PCIe or PCI devices. Thus, from a software perspective, the accelerator circuits in a multi-chiplet-based SiP behave like PCIe devices, but are connected to the CPU and / or other processor circuitry modules via one or more physical connections conforming to Universal Chiplet Interconnect (UCIe). In some examples, the physical connections between chiplets and dies (e.g., chiplet-to-chiplet interconnects, die-to-die interconnects, etc.) conform to other standards or specifications, such as the Wire Harness (BoW) specification, the Accelerator Cache Coherent Interconnect (CCIX) specification, the Advanced Interface Bus (AIB) standard, the 112 Gbps (112G) specification, or the Open High Bandwidth Interconnect (OpenHBI) specification, etc.

[0030] Furthermore, chiplets in a multi-chiplet SiP can be interconnected using compute fast link (CXL) protocols, such as CXL for cache-coherent access to system memory (CXL.cache or CXL.$), CXL for device memory (CXL.Mem), or CXL for PCIe-based I / O devices (CXL.IO / PCIe). Example accelerator circuits include artificial intelligence (AI) accelerator circuits, graphics processing unit (GPU) accelerator circuits, quick assist technology (QAT) accelerator circuits, network interface card (NIC) accelerator circuits, virtual radio access network (vRAN) accelerator circuits, turbo intellectual property (IP) (TIP) accelerator circuits (e.g., for fifth-generation (5G) network coding in vRAN), infrastructure processing unit (IPU) accelerator circuits, and so on.

[0031] For example, a QAT accelerator circuit is a circuit module that can perform cryptographic functions (e.g., encryption, decryption, etc.), compression, and / or decompression more efficiently than a general-purpose processor core. In some examples, QAT accelerator circuits are used for encryption and / or decryption of network traffic in Virtual Private Networks (VPNs), load balancers, Content Delivery Networks (CDNs), and web servers. Other examples of accelerator circuits are possible, such as inference engine accelerator circuits, Tensor Processing Unit (TPU) accelerator circuits, Neural Processing Unit (NPU) accelerator circuits, AI Core Processor (AKP) accelerator circuits, 5G and / or sixth-generation (6G) network accelerator circuits, and input / output (I / O) accelerator circuits.

[0032] To ensure confidential computation between trusted software and accelerator circuits, the trusted software should verify the authenticity and / or identity of the accelerator circuits. Confidential computation standards define security protocols (e.g., Security Protocol and Data Model (SPDM), Trusted Execution Environment (TEE) Device Interface Security Protocol (TDISP), etc.) to extend trust from a trusted virtual machine (VM) (e.g., provided by Trust Domain Extension (TDX)) to one or more endpoint devices. However, confidential computation standards do not specify how to extend trust from a trusted VM to accelerator circuits and / or I / O devices in multi-chip and / or tile-based SiPs, where the accelerator circuits and / or I / O devices reside on different chipsets within the same package and operate as RCIEPs. In such cases, confidential data (e.g., data defining AI models and / or data associated with AI models) may be unprotected in the SiP. Furthermore, improved cryptographic techniques (such as post-quantum cryptography (PQC)) may require confidential computation.

[0033] To enable secure computing (e.g., TDX connectivity) in a multi-chiplet, multi-accelerator-based device, a trusted VM (e.g., also known as a trust domain (TD)) must securely identify and authenticate the accelerator circuitry on the chiplets and establish a secure communication channel with trusted entities on the chiplets before allowing one or more of the accelerator circuitry to enter the trusted VM's trust boundary. Advantageously, the examples disclosed herein include identification and authentication security architectures for widespread and high-performance secure computing in multi-chiplet, multi-accelerator circuitry SiPs. The methods, apparatuses, and articles of art disclosed herein include scalable and cost-effective chiplet identification and authentication security architectures that are scalable to third-party chiplets and conform to industry standards. In some disclosed examples, the trusted VM examines chiplets with consistent identification and one or more accelerator circuitry on each chiplet, and authenticates the identification of the chiplets and / or accelerator circuitry via an on-package security mechanism as described below. Therefore, the examples disclosed herein include in-package security systems.

[0034] Figure 1 This is a block diagram of an example system 100 that provides secure computing identification, authentication, and trust security for multiple accelerator circuits in a system-in-a-package (SiP). For example, Figure 1 System 100 (e.g., an identification, authentication, and key establishment system) describes example components, example communications, and example security states of a SiP or SoC comprising multiple de-assembled chiplets, each chiplet controlling multiple accelerator circuits. In some examples, SiP refers to a system in a package. Furthermore, the examples disclosed herein can be integrated into any integrated accelerator circuitry, whether (1) on a single, separate tile, (2) on an integrated memory and I / O tile, or (3) within a compute building block (CBB).

[0035] A CBB is one or more logic circuits whose operation on the accelerator circuit can be general-purpose and / or specific to the accelerator circuit. For example, a general-purpose CBB can be a memory, a memory management unit, a controller, and / or a scheduler. Furthermore, for example, in accelerator circuitry implementing a vision processor unit (VPU) accelerator circuit, a specific CBB can be a convolutional neural network, a recurrent neural network, and / or a digital signal processor (DSP). Additionally or alternatively, in accelerator circuitry implementing a GPU, a specific CBB can be a thread scheduler, a graphics technology interface, and / or any other CBB intended to improve the processing speed and overall performance of computer graphics and / or image processing. In some examples, in accelerator circuitry implementing a field-programmable gate array (FPGA), a specific CBB can be an arithmetic logic unit (ALU) and / or any other CBB intended to improve the processing speed and overall performance of general-purpose computing.

[0036] exist Figure 1 In the illustrated example, system 100 includes an example core tile 102, one or more example chiplets 104, and an example root of trust (RoT) chiplet 106. Figure 1 In the example, core tile 102 includes example Trusted Execution Environment (TEE) Security Management (TSM) circuitry 108 and one or more example cores 110. For example, one or more cores 110 include first example core 1101 to Mth example core 110. M .

[0037] exist Figure 1 In the illustrated example, each instance of one or more cores 110 is implemented by core processor circuitry. For example, each instance of one or more cores 110 implements a trusted VM or TD (e.g., TD-1 to TD-M). In some examples, instead of a VM, at least one of the one or more cores 110 may implement a container, or other virtualized execution environment, which may be used in any of the examples described herein. Figure 1 In the example, core tile 102 also includes a first example interface circuit 112. For example, the first interface circuit 112 implements a virtual machine monitor (VMM), such as a hypervisor. Figure 1 In the example, the first interface circuit 112 can be implemented by software, hardware and / or firmware.

[0038] exist Figure 1 In the illustrated example, one or more chiplets 104 include first example chiplets 1041 to Nth example chiplets 104. N Furthermore, each of the one or more chiplets 104 includes an example chiplet device security management (CDSM) circuitry 114, one or more accelerator circuits 116, and a second example interface circuitry 118. Figure 1 In the examples, one or more accelerator circuits 116 include first example accelerator circuits 1161 to Pth example accelerator circuits 116. P .exist Figure 1 In the example, one or more of the accelerator circuits 116 are implemented by AI accelerator circuits, GPU accelerator circuits, QAT accelerator circuits, NIC accelerator circuits, vRAN accelerator circuits, TIP accelerator circuits, IPU accelerator circuits, TPU accelerator circuits, NPU accelerator circuits, AKP accelerator circuits, 5G network accelerator circuits, 6G network accelerator circuits, and / or I / O accelerator circuits, etc.

[0039] exist Figure 1In the illustrated example, the RoT chiplet 106 includes an example Root of Trust (RoT) device secure computing (DCC) circuitry 120. In some examples, the RoT DCC circuitry 120 is referred to as a SiP secure circuit. Figure 1 In the examples, RoT chiplet 106 can be any chiplet housing RoT DCC circuitry 120. For example, RoT chiplet 106 can be an integrated memory and I / O chiplet of system 100. In some examples, RoT chiplet 106 can be core tile 102. Figure 1 In the example, the RoTDCC circuit 120 communicates with one or more chipsets 104 via at least one device-to-device (D2D) sideband channel. For example, at least one D2D sideband channel is authenticated and protected with confidentiality.

[0040] exist Figure 1 In the illustrated example, the CDSM circuit 114 is implemented by at least one programmable processor circuit and / or at least one logic circuit. Figure 1 In the example, CDSM circuit 114 is a security engine that acts as a device security manager (DSM) or DSM circuit for the chiplets on which CDSM circuit 114 is implemented. For example, each of one or more chiplets 104 includes an instance of CDSM circuit 114 acting as a centralized security entity on behalf of one or more accelerator circuits 116.

[0041] exist Figure 1 In the illustrated example, the TSM circuit 108 is implemented by one or more processor cores. Figure 1 In the example, TSM circuit 108 is an authentication security entity that establishes (e.g., explicitly establishes) a trust and secure communication session between one or more cores 110 and one or more accelerator circuits operating as RCIEP, regardless of the tiles and / or chips on which the one or more accelerator circuits reside. Additionally, TSM circuit 108 is an authentication security entity that establishes (e.g., explicitly establishes) a trust and secure communication session between one or more cores 110 and one or more accelerator circuits, regardless of the physical communication channel (e.g., CXL.Cache, CXL.IO / PCIe, UCIe, etc.) through which core tile 102 communicates with one or more accelerator circuits 116.

[0042] exist Figure 1 In the illustrated example, the RoT DCC circuit 120 operates as a single logical RoT within system 100. RoT is hardware (HW), software (SW), and / or firmware (FW) that provides one or more security functions for establishing security on the device. Figure 1In the example, the RoT DCC circuit 120 creates an identifier (ID) for each of one or more chiplets 104 and a corresponding accelerator circuit in one or more accelerator circuits 116. Furthermore, the RoT DCC circuit 120 manages the lifecycle of the identifier.

[0043] exist Figure 1 In the illustrated example, the identification of one or more chiplets 104 and one or more accelerator circuits 116 of the corresponding chiplets within one or more chiplets 104 is implemented by an example Root Trusted (RoT) Device Secret Computing (DCC) certificate 122 (e.g., at least one identifier certificate). For example, the RoTDCC certificate 122 is a Trusted Computing Organization (TCG) Device Identifier Synthesis Engine (DICE) certificate. The DICE certificate provides hardware-based identification (e.g., a unique cryptographic identifier). Figure 1 In the example, the RoT DCC circuit 120 creates a public key-private key pair for each of the RoT DCC certificates 122 and adds these key pairs to the key hierarchy of system 100 (e.g., the DICE key hierarchy).

[0044] exist Figure 1 In the illustrated example, the RoT DCC circuit 120 also executes an authentication security protocol (e.g., SPDM) to allow the TSM circuit 108 to authenticate one or more accelerator circuits and vice versa. In this way, the result of the security protocol executed by the RoT DCC circuit 120 is a secure communication session that is unique to each chiplet and each accelerator circuit within a chiplet. Therefore, multiple accelerator circuits that may reside on multiple chiplets can establish and use confidential communication sessions with the TSM circuit 108. Thus, even if the system 100 includes third-party untrusted chiplets or other third-party untrusted circuits, communication between the TSM circuit 108 and the accelerator circuits remains protected. Furthermore, interactions between components of the system 100 that occur for service access control purposes on the CXL.Cache data lane and / or the CXL.IO / PCIe data lane remain secure.

[0045] exist Figure 1 In the illustrated example, the first interface circuit 112 implements an example Data Object Exchange (DOE) mailbox requester 124. Furthermore, the second interface circuit 118 implements an example DOE mailbox responder 126 and an example Vendor-Specific Dedicated Extension Capability (DVSEC) register 128. Figure 1 In the example, DOE mailbox requester 124 and DOE mailbox responder 126 are mailboxes used for communication between TSM circuit 108 and one or more chiplets 104.

[0046] existFigure 1 In the illustrated example, DVSEC register 128 implements the capabilities for implementing TDX connectivity. For example, DVSEC register 128 includes a capability register, a control register, TEE mode enable / disable for each virtual function (VF) supported by a corresponding chip in one or more chiplets 104, a measurement register for a corresponding chip in one or more chiplets 104, and a mailbox register. Figure 2 In the example, for trusted device mode (e.g., TEE device interface), at least one VF can be enabled.

[0047] In the example operation, the example TSM SPDM logic circuit 130 of TSM circuit 108 represents one or more cores 110 establishing an example SPDM session 132 with at least one of the one or more accelerator circuits 116 of the first chiplet 1041. Figure 2 In the example, CDSM circuit 114 acts as a proxy (e.g., forward communication) between TSM SPDM logic circuit 130 and RoTDCC circuit 120 to perform an example SPDM handshake 134. For example, the communication proxies between TSM SPDM logic circuit 130 and RoTDCC circuit 120 is related to the identification and authentication of CDSM circuit 114.

[0048] For example, TSM SPDM logic circuit 130 identifies to RoT DCC circuit 120 at least one of one or more accelerator circuits 116 that TSM circuit 108 is attempting to establish a secure communication session with. Figure 1 In the example, RoTDCC circuit 120 verifies that at least one of the one or more accelerator circuits 116 that TSM circuit 108 is attempting to establish a secure communication session with matches the identifier in RoT DCC certificate 122. Based on the verification by RoT DCC circuit 120 that at least one of the one or more accelerator circuits 116 matches the identifier in RoTDCC certificate 122, RoT DCC circuit 120 provides a certificate (e.g., RoT DCC certificate) with an embedded public key to TSM SPDM logic circuit 130 (e.g., TSM circuit 108). Furthermore, after performing SPDM handshake 134, TSM SPDM logic circuit 130 receives RoTDCC certificate 122 from CDSM circuit 114 and example measurements 136 from one or more accelerator circuits 116 of first chip 1041.

[0049] In some examples, TSM SPDM logic circuit 130 can retrieve measurement 136 from CDSM circuit 114 after SPDM handshake 134. For example, TSM SPDM logic circuit 130 can request measurement 136 from CDSM circuit 114 using SPDM commands. In example operation, after completing SPDM handshake 134, RoT DCC circuit 120 performs a key exchange or key establishment procedure with CDSM circuit 114 to derive example session key 138 for SPDM session 132.

[0050] In the example operation, after the key transfer in SPDM session 132, TSM SPDM logic circuit 130 can obtain measurement 136 from one or more accelerator circuits 116. Additional details about the measurement are in Figure 2 As described in the text. For example, Figure 2 This diagram is used for reporting measurements. Figure 2 The block diagram illustrates example communication 200 between a first example chip 1041 and the RoT DCC circuit 120. As described above, the RoT DCC circuit 120 creates and authorizes RoT DCC certificates 122 on behalf of one or more chips 104 and corresponding accelerator circuits in one or more accelerator circuits 116 of the one or more chips 104. For example, as needed, the RoT DCC circuit 120 securely generates unique identifiers for one or more chips 104, securely stores and manages the identifiers along with the public and private key pairs for each identifier, and manages (e.g., revocation and / or refresh) the identifiers.

[0051] exist Figure 2 In the illustrated example, CDSM circuit 114 authenticates its firmware. For example, CDSM circuit 114 accesses its firmware image from its read-only memory (ROM). Figure 3 In the example, CDSM circuit 114 generates a first example hash 202 of the firmware image of CDSM circuit 114. Furthermore, one or more accelerator circuits 116 authenticate the firmware of one or more accelerator circuits 116. For example, one or more accelerator circuits 116 access one or more corresponding firmware images of one or more accelerator circuits 116 from the ROM of one or more accelerator circuits 116. Additionally, one or more accelerator circuits 116 generate one or more second example hashes 204 of one or more corresponding firmware images of one or more accelerator circuits 116.

[0052] exist Figure 1In the illustrated example, one or more example registers 206 of the first chiplet 1041 store a first hash 202, one or more second hashes 204, and the security version number (SVN) of the CDSM circuit 114 and one or more accelerator circuits 116. Figure 3 In the example, measurement reports from the accelerator circuitry of various chiplets allow the RoT DCC circuitry 120 to maintain the latest measurements and / or security versions of the accelerator circuitry of system 100. In this way, the RoT DCC circuitry 120 can use a first hash 202, one or more second hashes 204, and / or SVN as part of a key establishment protocol (e.g., SPDM).

[0053] Figure 3 The diagram is used in Figure 3 A block diagram of an example communication 300 establishing a secure communication session between the TSM circuit 108 of the core tile 102 and the CDSM circuit 114 of the first chiplet 1041. Figure 1 In the example, CDSM circuit 114 and RoT DCC circuit 120 are mutually authenticated (e.g., by configuration) and share a protected sideband channel. Furthermore, RoT DCC circuit 120 has previously obtained firmware measurements and security version numbers (SVNs) from one or more accelerator circuits 116.

[0054] exist Figure 3 In the illustrated example, the RoT DCC circuit 120 has previously created unique identifiers and unique per-chip public / private key pairs for the CDSM circuit 114. For example, the RoT DCC circuit 120 generates identifiers (IDs) as RoT DCC certificates 122 for the first chip 1041, the CDSM circuit 114, and one or more accelerator circuits 116. Furthermore, the RoT DCC circuit 120 derives public / private key pairs for the CDSM circuit 114 and one or more accelerator circuits 116. Figure 3 In the example, the RoTDCC circuit 120 signs the public key and private key pair to (e.g., Figure 1 The system's root authentication key (or platform root authentication key) is used in System 100. For example, the platform root authentication key is derived according to the TCG DICE standard. Similar key levels are implemented in TDX, Software Protection Extensions (SGX), and CPU RoT visas.

[0055] exist Figure 3 In the illustrated example, TSM circuit 108, representing one or more cores 110, initiates an SPDM handshake with CDSM circuit 114 (e.g., SPDM handshake 134). For example, TSM circuit 108 initiates an SPDM handshake with CDSM circuit 114 via DOE mailbox requester 124 and DOE mailbox responder 126.Figure 3 In the example, the first example SPDM logic circuit 302 of the TSM circuit 108 (e.g., Figure 3 The TSM SPDM logic circuit 130 transmits a request from at least one of one or more cores 110 to the CDSM circuit 114 to form a secure communication session. Figure 3 In the example, CDSM circuit 114 reads the incoming message from TSM circuit 108 and detects that the incoming message is an SPDM message. In addition, CDSM circuit 114 places a specific (e.g., proprietary) header on the SPDM message and transfers the SPDM message to RoT DCC circuit 120.

[0056] exist Figure 4 In the illustrated example, RoTDCC circuit 120 acts as the final endpoint of the SPDM handshake and handles the SPDM exchange between TSM circuit 108 and CDSM circuit 114. For example, RoTDCC circuit 120 prepares an SPDM response and sends it to CDSM circuit 114. Based on the received SPDM response, CDSM circuit 114 sends an SPDM response to TSM circuit 108 via DOE mailbox responder 126 and DOE mailbox requester 124. In this way, CDSM circuit 114 acts as a "proxy" for the SPDM handshake, thereby providing an example SPDM tunnel 304 between the first SPDM logic circuit 302 and the second example SPDM logic circuit 306 of RoTDCC circuit 120.

[0057] exist Figure 1 In the illustrated example, upon completion of the SPDM handshake, TSM circuit 108 and RoT DCC circuit 120 perform a key exchange or key establishment operation. For example, RoT DCC circuit 120 derives a session key 138 for a secure communication session between TSM circuit 108 and CDSM circuit 114. Figure 4 In the example, the RoT DCC circuit 120 delivers session key 138 to the CDSM circuit 114. For example, the RoT DCC circuit 120 transfers session key 138 to the first example TDISP logic circuit 308 of the CDSM circuit 114. Additionally, the RoT DCC circuit 120 removes session key 138 from the RoT DCC circuit 120.

[0058] exist Figure 4In the illustrated example, the RoT DCC circuit 120 also maintains the session context of the secure communication session. For example, the session context (also referred to as a session record) is a record of the SPDM session (e.g., a secure communication session) between the TSM circuit 108 and at least one of the one or more accelerator circuits 116 (e.g., via the CDSM circuit 114). In this way, the RoT DCC circuit 120 maintains a record of the secure communication session between the TSM circuit 108 and one or more chiplets 104.

[0059] In this way, both TSM circuit 108 and RoTDCC circuit 120 have unique keys for confidential and integrity-protected communication. From this point, communication between TSM circuit 108 and CDSM circuit 114 is protected by session key 138, which now terminates at CDSM circuit 114. For example, the first TDISP logic circuit 308 and the second example TDISP logic circuit 310 of TSM circuit 108 utilize session key 138 for TDISP protocol encryption. In this way, an SPDM-protected communication session exists between TSM circuit 108 and CDSM circuit 114. As described above, the SPDM handshake is an exchange between the two parties, thereby generating a mutually trusted key for subsequent encrypted TDISP exchanges. Furthermore, after the SPDM handshake, RoTDCC circuit 120 continues to monitor the SPDM session and intervenes in the SPDM session in response to abnormal events.

[0060] Figure 4 The diagram is used in Figure 4 An additional example communication 400 block diagram showing the establishment of a secure communication session between the TSM circuit 108 of the core tile 102 and the CDSM circuit 114 of the first chiplet 1041. Figure 5 In the example, CDSM circuit 114 reads the SPDM message from DOE mailbox responder 126, and the firmware of CDSM circuit 114 performs processing actions, including transmitting the SPDM message to RoT DCC circuit 120 as described above. Furthermore, as described above, communication between CDSM circuit 114 and RoT DCC circuit 120 occurs via a secure sideband interface such as a UCIe industry standard protocol. In some examples, CDSM circuit 114 communicates with RoT DCC circuit 120 via a secure sideband channel using vendor-specific protocols such as events and mailboxes.

[0061] exist Figure 1 In the illustrated example, the first SPDM logic circuit 302 sends session key 138 (e.g., the SPDM session key) to the second TDISP logic circuit 310. Figure 5In the example, the second TDISP logic circuit 310 processes one or more TDISP requests to the first chiplet 1041 and encrypts the one or more TDISP requests with session key 138 to protect them. Furthermore, the second TDISP logic circuit 310 forwards the one or more encrypted TDISP requests to the DOE mailbox requester 124, which in turn transmits the one or more encrypted TDISP requests to the DOE mailbox responder 126.

[0062] exist Figure 5 In the illustrated example, within SPDM session 132, CDSM circuit 114 uses session key 138 to decrypt one or more encrypted TDISP requests. Additionally, first TDISP logic circuit 308 processes one or more TDISP requests. Based on processing one or more TDISP requests, first TDISP logic circuit 308 provides one or more TDISP responses to second TDISP logic circuit 310 via DOE mailbox responder 126 and DOE mailbox requester 124.

[0063] Figure 5 yes Figure 5 Block diagrams of example implementations of CDSM circuit 114 and RoTDCC circuit 120. Figure 5 In the example, CDSM circuit 114 includes an example PCIe configuration space register 502, an example TDISP circuit 504 (e.g., one or more state machine circuits) for each TDI and / or VF supported by one or more accelerator circuits 116, and an example TDISP state memory 506. For example, TDISP state memory 506 includes one or more keys, encryption states, and other data, and is retained when the accelerator circuit is reset.

[0064] exist Figure 5 In the illustrated example, the RoT DCC circuit 120 includes an example process main band (MB) message 508 for SPDM passthrough and an example CDSM to RoTDCC header 510 (e.g., to facilitate SPDM tunneling 304). Furthermore, the RoTDCC circuit 120 includes an example SPDM key context (e.g., session key 138) and an example TDISP protocol 514. Figure 5 In the example, the RoT DCC circuit 120 also includes one or more example cryptographic circuits 516 (e.g., PQC circuits).

[0065] exist Figure 1-5In the illustrated example, the RoT DCC circuit 120 can read and / or write to the DOE mailbox responder 126. Additionally, the RoT DCC circuit 120 can write to the DVSEC register 128. Figure 1-5 In the example, RoTDCC circuit 120 can check the base address register of CDSM circuit 114. Furthermore, RoTDCC circuit 120 can lock one or more TDI registers of TDISP circuit 504 via example locking logic circuit 518 of first chip 1041. Figure 1-5 In the example, the RoT DCC circuit 120 can also detect when the TDISP state memory 506 has been written after being locked via the example write detection logic circuit 520 of the first chip 1041. Figure 1-5 The example RoT DCC circuit 120 can also read and / or write to the TDISP state memory 506.

[0066] Figure 1-5 The TSM circuit 108, CDSM circuit 114, and / or RoT DCC circuit 120 can be exemplified (e.g., instantiated, generated, materialized, implemented, etc.) by a programmable circuit module (such as a central processing unit (CPU) that executes the first instruction). Additionally or alternatively, Figure 3 The TSM circuit 108, CDSM circuit 114, and / or RoT DCC circuit 120 can be exemplified (e.g., created, generated, materialized, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA) that can be constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that... Figure 6 Some or all of the circuit modules in the circuit module can therefore be exemplified at the same or different times. For example, Figure 22 Some or all of the circuit modules in the circuit module can be instantiated in hardware simultaneously and / or serially in hardware in one or more threads. Furthermore, in some examples, Figure 23 Some or all of the circuit modules in the circuit module can be implemented by a microprocessor circuit module that executes instructions and / or an FPGA circuit module that performs operations to implement one or more virtual machines and / or containers.

[0067] In some examples, Figure 6 The first SPDM logic circuit 302 is exemplified by a programmable circuit module that executes SPDM instructions and / or is configured to perform actions such as those described by... Figure 24Operations such as those represented by one or more flowcharts. In some examples, TSM circuit 108 includes components for implementing the first security protocol. For example, the components for implementation may be implemented by first SPDM logic circuit 302. In some examples, first SPDM logic circuit 302 may be exemplified by a programmable circuit module, such as... Figure 6 Example programmable circuit module 2212. For example, the first SPDM logic circuit 302 can be derived from... Figure 22 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figure 23 The instructions implemented in boxes 602, 604, and 606.

[0068] In some examples, the first SPDM logic circuit 302 may be exemplified by a hardware logic circuit module, which may be an ASIC, XPU, or [other device] configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 6 The FPGA circuit module 2400 is used for implementation. Additionally or alternatively, the first SPDM logic circuit 302 may be exemplified by any other combination of hardware, software, and / or firmware. For example, the first SPDM logic circuit 302 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally suitable.

[0069] In some examples, the second TDISP logic circuit 310 is executed by a programmable circuit module that executes TDISP instructions and / or is configured to perform actions such as those described by... Figure 24 Operations such as those represented by one or more flowcharts. In some examples, TSM circuit 108 includes components for implementing the second security protocol. For example, the components for implementation may be implemented by a second TDISP logic circuit 310. In some examples, the second TDISP logic circuit 310 may be exemplified by a programmable circuit module, such as... Figure 7 Example programmable circuit module 2212. For example, the second TDISP logic circuit 310 can be derived from... Figure 22 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figure 23The instructions implemented in box 608.

[0070] In some examples, the second TDISP logic circuit 310 may be exemplified by a hardware logic circuit module, which may be an ASIC, XPU, or other hardware logic circuit configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 7 The second TDISP logic circuit 310 is implemented by the FPGA circuit module 2400. Additionally or alternatively, the second TDISP logic circuit 310 may be exemplified by any other combination of hardware, software, and / or firmware. For example, the second TDISP logic circuit 310 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally suitable.

[0071] In some examples, the SPDM tunnel 304 is executed by a programmable circuit module that executes SPDM instructions and / or is configured to perform actions such as those described by... Figure 24 Operations such as those represented by one or more flowcharts. In some examples, CDSM circuit 114 includes components for implementing the first security protocol. For example, the components for implementation may be implemented by SPDM tunnel 304. In some examples, SPDM tunnel 304 may be exemplified by a programmable circuit module, such as... Figure 7 Example programmable circuit module 2212. For example, SPDM tunnel 304 can be made by... Figure 22 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figure 23 The instructions implemented in boxes 702, 704, 706, 708, 710, 712, 714, 716, and 718.

[0072] In some examples, the SPDM tunnel 304 can be exemplified by a hardware logic circuit module, which may be an ASIC, XPU, or [other device] configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 7The SPDM tunnel 304 is implemented by the FPGA circuit module 2400. Additionally or alternatively, the SPDM tunnel 304 may be exemplified by any other combination of hardware, software, and / or firmware. For example, the SPDM tunnel 304 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware; however, other configurations are equally suitable.

[0073] In some examples, the first TDISP logic circuit 308 is executed by a programmable circuit module that executes TDISP instructions and / or is configured to perform actions such as those described by... Figure 24 Operations such as those represented by one or more flowcharts. In some examples, CDSM circuit 114 includes components for implementing the second security protocol. For example, the components for implementation may be implemented by first TDISP logic circuit 308. In some examples, first TDISP logic circuit 308 may be exemplified by a programmable circuit module, such as... Figure 8 Example programmable circuit module 2212. For example, the first TDISP logic circuit 308 can be derived from... Figure 22 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figure 23 The instructions implemented in box 720.

[0074] In some examples, the first TDISP logic circuit 308 may be exemplified by a hardware logic circuit module, which may be an ASIC, XPU, or [other device] configured and / or constructed to perform operations corresponding to machine-readable instructions. Figure 8 The FPGA circuit module 2400 is used for implementation. Additionally or alternatively, the first TDISP logic circuit 308 may be exemplified by any other combination of hardware, software, and / or firmware. For example, the first TDISP logic circuit 308 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparator, operational amplifier, logic circuit, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally suitable.

[0075] In some examples, the second SPDM logic circuit 306 is executed by a programmable circuit module that executes SPDM instructions and / or is configured to perform actions such as those described by... Figure 24 Operations such as those represented by one or more flowcharts. In some examples, the RoT DCC circuit 120 includes components for implementing the first security protocol. For example, the components for implementation may be implemented by a second SPDM logic circuit 306. In some examples, the second SPDM logic circuit 306 may be exemplified by a programmable circuit module, such as... Figures 1-5 Example programmable circuit module 2212. For example, the second SPDM logic circuit 306 can be derived from... Figures 1-5 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figures 1-5 The instructions implemented in boxes 802, 804, 806, 808, 810, 812, 814, 816, 818, and 820.

[0076] In some examples, the second SPDM logic circuit 306 may be exemplified by a hardware logic circuit module, which may be an ASIC, XPU, or [other device] configured and / or constructed to perform operations corresponding to machine-readable instructions. Figures 1-5 The second SPDM logic circuit 306 is implemented by the FPGA circuit module 2400. Additionally or alternatively, the second SPDM logic circuit 306 may be exemplified by any other combination of hardware, software, and / or firmware. For example, the second SPDM logic circuit 306 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGA, ASIC, XPU, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally suitable.

[0077] Although Figure 6 The diagram illustrates an example of implementing the TSM circuit 108, CDSM circuit 114, and RoTDCC circuit 120, but... Figure 7 One or more of the elements, processes, and / or devices illustrated in the diagram may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, Figure 8The example TSM circuit 108, example CDSM circuit 114, and / or example RoT DCC circuit 120 can be implemented individually in hardware, or in combination with software and / or firmware. Therefore, for example, any of the example TSM circuit 108, example CDSM circuit 114, and / or example RoT DCC circuit 120 can be implemented by a programmable circuit module in combination with machine-readable instructions (e.g., firmware or software), a processor circuit module, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (one or more GPUs), one or more digital signal processors (one or more DSPs), one or more ASICs, one or more programmable logic devices (one or more PLDs), and / or one or more field-programmable logic devices (one or more FPLDs, such as FPGAs). Furthermore, the example TSM circuit 108, example CDSM circuit 114, and / or example RoT DCC circuit 120 can include, as a complement to... Figures 1-5 The elements, processes and devices illustrated herein may be supplemented or replaced by one or more elements, processes and / or devices, and / or may include any or more of the elements, processes and devices illustrated herein.

[0078] Figures 1-5 , Figure 22 and Figure 23 The diagram shows how programmable circuit modules can be implemented and / or exemplified. Figure 24 Example machine-readable instructions and / or representations of example TSM circuit 108, example CDSM circuit 114, and example RoTDCC circuit 120 can be executed by a programmable circuit module to implement and / or exemplify Figure 6 Flowcharts of example operations (one or more) of example TSM circuit 108, example CDSM circuit 114, and example RoTDCC circuit 120. Machine-readable instructions may be used by combining, for example, the following... Figure 1 The programmable circuit module 2212, as shown in the example programmable circuit module platform 2200 discussed in the discussion, executes one or more executable programs or one or more portions of one or more executable programs, and / or may be used for execution by the programmable circuit module 2212, as described below. Figure 6 and / or Figure 6 The examples discussed are programmable circuit modules (e.g., FPGAs) that perform one or more functions or portions of functions. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed and / or executed in a real-world manner. As used herein, “automation” means without human intervention.

[0079] Figure 7 This is a flowchart illustrating example machine-readable instructions and / or example operations 600, which can be implemented, executed, and / or executed by an example programmable circuit module to achieve... Figure 1 The TSM circuit 108. Machine-readable instructions and / or operations 600 begin at block 602, where the TSM circuit 108 causes the first interface circuit 112 of the core tile 102 to send a request to the CDSM circuit 114 of the first chiplet 1041 to initiate a secure communication session. For example, the request is an SPDM handshake request.

[0080] exist Figure 7 In the illustrated example, at block 604, TSM circuit 108 performs a handshake with RoT DCC circuit 120 according to a first security protocol (e.g., SPDM) to establish a secure communication session. Figure 7 In the example, at block 606, upon handshake completion, TSM circuit 108 accesses the session key of the secure communication session from first interface circuit 112. For example, the session key is derived from RoTDCC circuit 120. At block 608, TSM circuit 108 uses the session key to protect (e.g., encrypt, decrypt, etc.) communication with CDSM circuit 114 according to a second security protocol (e.g., TDISP).

[0081] Figure 7 This is a flowchart illustrating example machine-readable instructions and / or example operations 700, which can be implemented, executed, and / or executed by an example programmable circuit module to achieve... Figure 7 The CDSM circuit 114. Machine-readable instructions and / or operations 700 begin at block 702, where the CDSM circuit 114 of the first chiplet 1041 of the SiP (e.g., system 100) mutually authenticates with the RoT DCC circuit 120 of the SiP. At block 704, the CDSM circuit 114 causes a second interface circuit 118 of the first chiplet 1041 to send firmware measurements and security version numbers of at least one accelerator circuit of the first chiplet 1041 to the RoT DCC circuit 120.

[0082] exist Figure 7 In the illustrated example, at block 706, CDSM circuit 114 accesses a message from SiP's TSM circuit 108 via second interface circuit 118. At block 708, CDSM circuit 114 detects that the message includes a request to initiate a secure communication session with CDSM circuit 114 according to a first security protocol (e.g., SPDM). Figure 8In the example, in box 710, CDSM circuit 114 adds a header to the request. For example, CDSM circuit 114 adds a proprietary header to the request.

[0083] exist Figure 1 In the illustrated example, at block 712, CDSM circuit 114 causes second interface circuit 118 to forward the request to RoT DCC circuit 120. Figure 8 In the example, at block 714, based on the response to the request received from the RoT DCC circuit 120, the CDSM circuit 114 causes the second interface circuit 118 to send a response to the TSM circuit 108. At block 716, the CDSM circuit 114 accesses the session key of the secure communication session, which is generated by the RoT DCC circuit 120. Figure 8 In the example, at block 718, CDSM circuit 114 causes second interface circuit 118 to send a session key to TSM circuit 108. At block 720, CDSM circuit 114 uses the session key to protect communication with TSM circuit 108 according to a second security protocol (e.g., TDISP).

[0084] Figure 8 This is a flowchart illustrating example machine-readable instructions and / or example operations 800, which can be implemented, executed, and / or executed by an example programmable circuit module to achieve... Figure 8 The RoTDCC circuit 120. Machine-readable instructions and / or operations 800 begin at block 802, where the RoTDCC circuit 120 mutually authenticates with the CDSM circuit 114 of the first chiplet 1041 of the SiP (e.g., system 100). At block 804, the RoTDCC circuit 120 creates a unique identifier (e.g., RoTDCC certificate 122) for each of the first chiplet 1041 (e.g., CDSM circuit 114) and one or more accelerator circuits 116 of the first chiplet 1041.

[0085] exist Figure 8 In the illustrated example, at block 806, the RoT DCC circuit 120 creates a corresponding public-private key pair for each of the first chiplet 1041 and one or more accelerator circuits 116. For example, the RoT DCC circuit 120 uses the public-private key pairs for authentication of one or more accelerator circuits and / or key management. At block 808, the RoT DCC circuit 120 registers the corresponding public-private key pair into the platform root certificate key of the SiP (e.g., system 100). Figure 9 In the example, in box 810, the RoT DCC circuit 120 accesses firmware measurements and security version numbers of at least one accelerator circuit of the first chip 1041 from the CDSM circuit 114.

[0086] exist Figure 9 In the illustrated example, at block 812, based on a received request to establish a secure communication session with CDSM circuitry 114, RoT DCC circuitry 120 processes the request to generate a response, which is generated by TSM circuitry 108 of the SiP (e.g., system 100). At block 814, RoT DCC circuitry 120 causes interface circuitry (e.g., UCIe interface circuitry) of RoT chiplet 106 to send a response to CDSM circuitry 114. Figure 9 In the example, in box 816, the RoTDCC circuit 120 generates a session key for a secure communication session between the TSM circuit 108 and the CDSM circuit 114.

[0087] exist Figure 9 In the illustrated example, at block 818, the RoT DCC circuit 120 causes the interface circuitry of the RoT chiplet 106 to deliver the session key to the CDSM circuitry 114. Furthermore, at block 820, the RoT DCC circuit 120 removes the session key from the RoTDCC circuit 120. As described above, the RoTDCC circuit 120 (sometimes referred to as the SiP security circuitry) authenticates at least one accelerator circuit to the TSM circuitry 108 (e.g., the core processor circuitry) to provide in-package security within the SiP.

[0088] As described above, the examples disclosed herein include an identification and authentication security architecture for deploying secure computing (e.g., TDX connectivity) across multiple chiplets and / or tiles, wherein each chiplet and / or tile includes multiple accelerator circuits (e.g., AI processors, I / O devices, etc.) and the multiple chiplets and / or tiles are housed within a single package, wherein each accelerator circuit is used to operate as an RCIEP device. The examples disclosed herein define an architectural construct that centralizes the identification establishment and management of all chiplets in a SiP. Such centralization includes creating chiplet and / or tile identifiers, updating identifiers as security profiles change, and securely transmitting identifiers for trust and key establishment.

[0089] Furthermore, the examples disclosed herein define an architectural construct for assigning responsibility for the security state management of chiplets and accelerator circuits to device entities based on their role-specific functionalities. For example, the disclosed methods, apparatus, and artifacts allow for optimal product solutions for security analysis, implementation, and verification. The examples disclosed herein also define an architectural construct for providing a TD visa system for de-aggregated and multi-chiplet accelerator devices. For example, TDX, SGX, and / or Advanced Microdevice Security Encryption Virtualization (AMD-SEV) visas can be used for TD visas. The examples disclosed herein also define an architectural construct for providing secure inter-chiplet communication across UCIe-defined interfaces. For example, secure inter-chiplet communication can occur on primary or sideband channels.

[0090] In addition to providing secure computing between trusted software and accelerator circuitry in SiPs and / or SoCs, the examples disclosed herein also include cluster management in multi-die, multi-chiplet, and / or multi-watt platforms. Deploying and managing SiPs and / or SoCs at the network edge is complex. For example, SiPs deployed at the edge are distributed, unmanned, and physically insecure heterogeneous platforms (e.g., edge devices may be housed in lockers that are relatively insecure compared to data centers).

[0091] As mentioned above, SiP and / or SoC can include multiple dies (also known as dielets or tiles), each of which can be swapped in and / or swapped out like modular components. Furthermore, the platform can be designed according to modular standards such as OCP and can have multiple ledges for each component of the platform. Despite the multi-die nature of SiP and / or SoC, users of SiP and / or SoC expect cluster management to perform as consistently as in a single-die environment. However, there are no reliably consistent de-aggregated SiP and / or SoC infrastructure architecture components that can be used to deliver differentiated edge services.

[0092] For example, edge service providers have been using combinations of different elements of a platform to manage edge devices and deliver edge services. These approaches include using an operating system (OS) and / or host-based applications or external sideband management controllers, such as a substrate management controller (BMC), a light-off processor (LOP), etc. OpenBMC and OCP aim to define unified technologies and interoperability, but are both oriented towards a centralized, system control interface that is necessary. In this way, the models provided by OpenBMC and OCP allow for a declarative system approach to silicon-based dedicated system control.

[0093] However, host-based and sideband-based cluster management technologies are severely limited by their inability to scale to address the modularity of SiPs and / or SoCs (e.g., composed of multiple dies) and platforms (e.g., composed of multiple expansion slots). Furthermore, host-based device cluster management technologies are severely limited by their inability to manage critical pre-booted edge devices, including secure identifier-based provisioning, dynamic attitude-based SoC and / or platform key management, OS-independent recovery, remote debugging, etc. Moreover, sideband-based components are constrained and non-standardized (e.g., diverse in capabilities). For example, sideband-based components are insecure and cannot be relied upon for any trusted device cluster management functions.

[0094] Furthermore, vendors of sideband-based components are limited by technology and cost. For example, sideband-based components are implemented outside the SoC, and thus lack access to valuable SiP trusted and / or SoC trusted services. Additionally, the modular nature of SiP and / or SoC increases the cost of implementing sideband-based components for cluster management. Therefore, edge cluster management remains fragmented and vendor-specific, hindering widespread scalable deployment.

[0095] Examples disclosed herein include standardized, scalable, and secure cluster management, provisioning, and visibility deployed across the edge. For example, the example cluster management in SiPs and / or SoCs disclosed herein is low-cost, scalable, automated (e.g., hands-free), and secure, allowing remote visibility and secure access via out-of-band (OOB) channels. Furthermore, the example cluster management disclosed herein provides availability and survivability (e.g., even when the SoC is not powered). Examples disclosed herein include cluster management systems (FMS) that provide consistent capabilities across heterogeneous systems. For example, the example FMS disclosed herein includes the ability for a provisioning-free device deployed in the field to “call home” for secure provisioning, as described below.

[0096] Figure 9 This is a block diagram of a system-in-package (SiP) 900 that includes an example cluster management system (FMS) circuitry 902. Figure 9 In the example, SiP 900 is an edge processor unit (EPU) and includes an example FMS circuit 902, an example core chiplet 904, an example accelerator chiplet 906, an example networking chiplet 908, and an example memory and input / output (I / O) chiplet 910. Additionally, in Figure 9In the examples, SiP 900 is implemented on example platform 912. In some examples, SiP 900 includes example Baseboard Management Controller (BMC) circuitry 914. In some examples, SiP 900 includes instances of more than one FMS circuitry 902, depending on customer deployment and Stockkeeping Unit (SKU) requirements.

[0097] exist Figure 9 In the illustrated example, core chiplet 904 includes one or more core processor circuits that perform general processing on SiP 900. Furthermore, accelerator chiplet 906 includes one or more accelerator circuits similar to those implemented with the one or more accelerator circuits 116 described above. In some examples, accelerator chiplet 906 also includes one or more memory control circuits and / or one or more interface circuits. Figure 9 In the example, the networking chip 908 includes one or more network interface circuits (such as a network interface card (NIC)) and provides network accessibility to the SiP 900.

[0098] exist Figure 9 In the illustrated example, the memory and I / O chiplet 910 includes one or more memory control circuitry to provide access to the memory of the SiP900 and / or platform 912, and includes one or more interface circuitry for communicating with the I / O devices of the platform 912. In some examples, the memory and I / O chiplet 910 also includes one or more accelerator circuitry. Figure 9 In the example, the BMC circuit 914 is embedded in the motherboard of the platform 912 and allows the administrator to remotely monitor and manage the platform 912, even when the platform 912 is off and / or unresponsive.

[0099] exist Figure 9 In the illustrated example, the FMS circuit 902 is a dedicated and isolated component of the SiP 900, operating adjacent to but independent of host resources (e.g., other components of the SiP 900), and is responsible for the loading and recovery of the edge system (e.g., the SiP 900). For example, the FMS circuit 902 provides isolated control and authorization for the management of the SiP 900, while also providing guarantees of the SiP 900's recoverability. The FMS circuit 902 can autonomously recover the SiP 900 using a declarative configuration model with the help of an external cluster manager (e.g., a cluster management service).

[0100] exist Figure 9In the illustrated example, the FMS circuit 902 is designed as a multi-chiplet SiP and / or SoC (such as SiP 900) implementation across a highly decentralized architecture. The architecture of the FMS circuit 902 provides the flexibility to integrate the FMS circuit 902 with one or more chiplets within or within the SiP 900 as a single chiplet, depending on cluster management requirements and desired characteristics. Figure 9 In the example, the FMS circuit 902 comprehensively evaluates the various chiplets of the SiP900 and provides design and process solutions for integrating the FMS circuit 902 based on product and platform selection. For example, the FMS circuit 902 manages the SiP900 and its accelerator circuitry, regardless of whether the accelerator circuitry is implemented on the accelerator chiplet 906, memory and I / O chiplet 910, and / or any other chiplet of the SiP900.

[0101] As described above, the architecture of the FMS circuit 902 allows it to be integrated into any of the aforementioned de-aggregated chiplets in an EPU such as a SiP 900. In a multi-chiplet de-aggregated SiP, each functionality provided by the SiP can be a chiplet. In this way, the FMS circuit 902 advantageously provides the flexibility to create scalable, multi-die packaged system combinations that can mix and match core chiplets, memory and I / O chiplets, accelerator chiplets, and networking chiplets, etc. Furthermore, the FMS circuit 902 advantageously provides an EPU tailored to specific use cases.

[0102] exist Figure 1 In the illustrated example, the FMS circuit 902 provides comprehensive cluster management for applications across a wide and diverse range of environments where EPUs (e.g., SiP 900s) are deployed. In this way, the FMS circuit 902 provides cluster management capabilities across EPUs designed for use cases such as AI and media processing, as well as across EPUs designed for use cases such as networking and security. Figure 9 In the example, FMS circuit 902 includes example interface circuit 916, example configuration circuit 918, example memory 920, one or more example processor circuits 922, example mailbox circuit 924, and example system control circuit 926.

[0103] exist Figure 9In the illustrated example, interface circuitry 916 supports multiple interface types that allow FMS circuitry 902 to connect to the host (e.g., chiplet 904) of the SiP900 (e.g., an Intel-based platform, a RISC-based platform, an ARM-based advanced RISC machine platform, etc.), regardless of where FMS circuitry 902 is integrated. In this way, after FMS circuitry 902 is loaded into the SiP900 using remote cluster management services, FMS circuitry 902 can be discovered, enumerated, and programmed by the SiP900's Basic Input / Output System (BIOS), OS, and / or drivers, without knowing its physical location within the SiP900.

[0104] exist Figure 9 In the illustrated example, interface circuitry 916 allows FMS circuitry 902 to connect to SiP 900 via standard SoC-specific and / or standard SiP-specific internal PCIe architectures and / or interfaces and be discovered by the host SW stack executing on core chiplet 904. Additionally or alternatively, interface circuitry 916 allows FMS circuitry 902 to connect to SiP 900 and be discovered by the host SW stack executing on core chiplet 904 via proprietary sidebands and / or low-performance global architectures. In some examples, interface circuitry 916 allows FMS circuitry 902 to connect to SiP 900 via a peripheral interface, such as an interface implemented according to an improved internal integrated circuit (I3C) protocol or a system management bus (SMBUS) protocol.

[0105] exist Figure 9 In the illustrated example, regardless of where the FMS circuit 902 is located or what physical interface it uses to connect to the SiP 900, the FMS circuit 902 provides standard register definitions, a standard programmable HW-SW interface, and a standard set of processing and communication messages for communicating with the core chiplet 904. In this way, the FMS circuit 902 can be integrated into any of the accelerator chiplet 906, the networking chiplet 908, and / or the memory and I / O chiplet 910. Additionally or alternatively, the FMS circuit 902 can be integrated into the package-on-ASIC (e.g., within the SiP 900) and / or as an external circuit (e.g., on the platform 912, but outside the SiP 900).

[0106] Regardless of where the FMS circuit 902 is integrated, it maintains a secure interconnection with the associated circuitry (e.g., protected by circuitry such as SPDM for circuit authentication and encryption protocols). For example, upon SiP 900 reset, the FMS circuit 902 creates a RoT (Royalty Transfer) to the SiP 900 via interface circuitry 916 (e.g., ...). Figure 1The RoT DCC circuit 120 provides a certified, protected channel to facilitate the supply of authorized firmware and security profiles to the SiP 900. Furthermore, the FMS circuit 902 is provided with an internet connection point regardless of (1) the physical tile or chip on which the FMS circuit 902 is physically located, and (2) the physical tile or chip on which networking circuits (e.g., IPU, fNIC, etc.) are physically located. As described above, the interface circuit 916 allows the FMS circuit 902 to connect to the SiP 900 via an interface implemented according to various protocols, such as the I3C protocol, the SMBUS protocol, or the Convergence Security and Management Engine (CSME) protocol.

[0107] exist Figure 9 In the illustrated example, the fabrication circuitry 918 is a circuit that connects components of the FMS circuitry 902. For example, the fabrication circuitry 918 can be implemented according to protocols such as the In-Die Interconnect (IDI) protocol (e.g., a proprietary protocol for agent-to-fabrication communication including memory coherence), the Advanced Extensible Interface (AXI) protocol, the AXI Coherence Extension (ACE) protocol, and / or the Intel System-on-Chip Architecture (IOSF) Sideband (IOSF-SB) protocol. Figure 9 In the example, memory 920 is implemented using static random access memory (SRAM). For example, memory 920 includes eight megabytes of SRAM.

[0108] exist Figure 10 In the illustrated example, one or more processor circuits 922 are implemented by one or more core processor circuits. For example, one or more processor circuits 922 support multithreading. Figure 9 In the example, mailbox circuit 924 is implemented as one or more of a DOE mailbox requester or a DOE mailbox responder. Additionally, system control circuit 926 connects to the RoT (e.g., ) of SiP900 via interface circuit 916. Figure 1 The RoTDCC circuit 120 communicates to facilitate the supply of licensed firmware and security profiles to the SiP 900.

[0109] exist Figure 11 In the illustrated example, the FMS circuit 902 reduces the operational complexity and cost of implementing SiP at the edge. For example, the FMS circuit 902 reduces the initial monetary cost of supplying the edge device. Furthermore, the FMS circuit 902 allows for proactive management of the edge device without requiring personnel to be dispatched to its deployment location (e.g., truck roll). Additionally, the FMS circuit 902 provides additional visibility across edge deployments.

[0110] exist Figure 9In the illustrated example, the FMS circuit 902 provides a cross-platform, secure, and autonomous management root within the device. For example, the FMS circuit 902 delivers a fully automated, consistent, cross-platform scalable cluster deployment and management suite of services, such as secure provisioning, key management based on dynamically unique device IDs, AI, and / or telemetry-based recoverability. As used herein, ID is used interchangeably to refer to an identifier or identifier. Furthermore, the FMS circuit 902 supports modular silicon architectures. For example, a SiP can be fabricated with the FMS circuit 902 implemented in various platforms as described herein.

[0111] Figure 11 The description depends on the FMS circuit 902 relative to Figure 11 A graphical illustration 1000 shows an example of the availability of the FMS circuit 902 implemented in the SiP 900. For example, in order to provide cluster management capabilities to the SiP 900, the FMS circuit 902 should be enabled and available even if no power is supplied to other components of the SiP 900.

[0112] For example, regardless of where the FMS circuit 902 is implemented, the FMS circuit 902 should be able to access power devices and networking paths independent of other components of the SiP 900 (e.g., via a dedicated network access port on the networking chip 908 and / or the FMS circuit 902), as well as the SiP 900's dedicated RoT (e.g., ...). Figure 11 The FMS circuit 902 can have this capability whether it is integrated on the SiP 900 package or on a chip within the SiP 900.

[0113] Figure 11 It includes Figure 11 A block diagram of an example system 1100 of the FMS circuit 902. In Figure 11 In the example, system 1100 includes a first example security domain 1102, a second example security domain 1104, and an example edge deployment 1106. Figure 11 In the example, the first security domain 1102 represents the software deployment of the first tenant (e.g., an enterprise) to implement one or more workloads on the edge deployment 1106. Furthermore, in Figure 11 In the example, the second security domain 1104 represents the software deployment of a second tenant (e.g., an enterprise) to carry out one or more workloads on the edge deployment 1106.

[0114] exist Figure 11 In the illustrated example, the first security domain 1102 includes a first example security policy and access control database 1108. AFirst Example Virtualized OS / AI Workload Infrastructure Manager 1110 A First example of a secure encrypted OS / AI workload storage library 1112 A And the first example, Edge AI Cluster Management (FM) System as a Service (SaaS) 1114 A .exist Figure 11 In the example, the second security domain 1104 includes a second example security policy and access control database 1108. B Second example: Virtualized OS / AI workload infrastructure manager 1110 B Second example: Secure encrypted OS / AI workload storage library 1112 B Second example: Edge AI Cluster Management (FM) Software as a Service (SaaS) 1114 B .

[0115] exist Figure 11 In the illustrated example, edge deployment 1106 includes first example edge processor unit (EPU) 11161 to Nth example edge processor unit (EPU) 1116 N In addition, edge deployment 1106 includes an example secure encrypted tenant OS / AI workload storage cache 1118, an example edge cluster orchestrator 1120, an example edge AI cluster management (FM) software-as-a-service (SaaS) 1122, and an example security controller 1124. First EPU 11161 to Nth EPU 1116 N Each instance is implemented similarly to the SiP 900. For example, the first EPU 11161 includes an FMS circuit 902, a core chiplet 904, a networking chiplet 908, and a memory and I / O chiplet 910.

[0116] exist Figure 11 In the example illustrated, the first security policy and access control database 1108 A And the second security policy and access control database 1108 B Each of these stores one or more security policies and access control parameters for the corresponding tenant in the first and second tenants. Figure 11 In the example, the first virtualized OS / AI workload infrastructure manager 1110 A Second Virtualization OS / AI Workload Infrastructure Manager 1110 B Each of these is deployed across the edge for the corresponding tenant in the first and second tenants, 1106, to deploy and / or manage one or more OSs and / or one or more AI workloads. For example, the first virtualized OS / AI workload infrastructure manager 1110. ASecond Virtualization OS / AI Workload Infrastructure Manager 1110 B From the first secure encrypted OS / AI workload storage library 1112 A Second secure encrypted OS / AI workload storage library 1112 B Access one or more OSes and / or one or more AI workloads.

[0117] exist Figure 11 In the example illustrated, the first edge AI FM SaaS1114 A Second Edge AI FMSaaS1114 B Cross-edge deployment 1106 deploys the first virtualized OS / AI workload infrastructure manager 1110 respectively. A Second Virtualization OS / AI Workload Infrastructure Manager 1110 B Select one or more OSes and / or one or more AI workloads. Figure 11 In the example, the secure encrypted tenant OS / AI workload storage library cache 1118 cache is from the first edge AIFM SaaS1114. A And / or Second Edge AI FM SaaS1114 B Receives one or more OSes and / or one or more AI workloads. Based on First Edge AI FM SaaS1114 A And / or Second Edge AI FM SaaS1114 B For communication, the edge cluster orchestrator 1120 supplies security keys to one or more tenant OSs and / or workloads in a trusted enclave within the FMS circuit 902.

[0118] exist Figure 11 In the illustrated example, the edge AIFM SaaS1122 is in the first EPU 11161 to the NEPU 1116. N One or more servers provide trusted tenant keys and one or more secure encrypted operating systems and / or one or more secure encrypted AI workloads. Additionally, security controller 1124 implements one or more AI security policies for the first and second tenants. Figure 11 In the example, according to the tenant's requirements, the first EPU 11161 to the second NEPU 1116 N One or more of them may not include any OS image and / or SW image and / or security context. For example, some tenants may need to deploy EPU 11161 through EPU 1116 in this manner. NThis allows for the dynamic supply of EPUs through geographically specific strategies (e.g., EPUs in the UK receive strategy one, and EPUs in the US receive strategy two).

[0119] Advantageously, each instance of the FMS circuit 902 can transmit internally initiated communications from within the out-of-band silicon of the FMS circuit 902. For example, when the FMS circuit 902 is powered on, the FMS circuit 902 includes features for discovering, authenticating, and associating with a remote cluster manager (e.g., a first virtualized OS / AI workload infrastructure manager 1110). A First Edge AI FM SaaS1114 A Second Virtualization OS / AI Workload Infrastructure Manager 1110 B Or the second edge AI FM SaaS1114 B Firmware for one or more of them. In this way, each instance of the FMS circuit 902 can initiate the dynamic and secure provisioning of the first EPU 11161 to the second NEPU 1116 via a "call headquarters" secure and configured certificate. N The process is different. Other methods (such as BMC and / or CSME) require a remote cluster manager to initiate communication.

[0120] exist Figure 9 In the illustrated example, FMS circuit 902 initiates communication with a remote cluster manager via a "Call Headquarters" feature to provide the remote cluster manager with the platform identifier of FMS circuit 902. For example, the firmware of FMS circuit 902 implements the Quick Identify Online (FIDO) Device Loading (FDO) protocol to perform discovery functionality, identifying one or more remote cluster managers that FMS circuit 902 should attempt to load during its supply lifecycle. Figure 12 In the example, the platform identifier of the FMS circuit 902 is based on the DICE standard and includes the security and device certificates of the FMS circuit 902.

[0121] exist Figure 9 In the illustrated example, one or more discovered remote cluster managers authenticate the security and device certificates of the FMS circuit 902. For example, the remote cluster manager uses the DICE identifier of the FMS circuit 902 to authenticate the FMS circuit 902. Figure 12 In the example, FMS circuit 902 uses a hardware-anchored identifier (e.g., derived according to the DICE standard) to authenticate the remote cluster manager. As further defined by IEEE 802.1AR, the use of the hardware identifier provides the basis for the non-repudiation of the connected device and the authenticity of the associated identifier. The process of generating and verifying the identifier is delegated to other silicon components in the EPU (e.g., RoT DCC circuit 120 as described above).

[0122] exist Figure 12 In the illustrated example, the remote cluster manager matches the platform identifier of the FMS circuit 902 with identifiers for tenant deployments and locations. For example, the identifier for a tenant deployment is based on the IEEE Device ID standard. In this way, the remote cluster manager dynamically identifies tenant-specific profiles and securely deploys them on the FMS circuit 902. For example, as part of the FDO protocol, the remote cluster manager provides the FMS circuit 902 with runtime configurations (e.g., OS, security context, SW and / or FW images, etc., for configuring EPUs, etc.) and payloads, which include ongoing operations and any new certificates required for communication with the remote cluster manager.

[0123] In this way, the FMS circuit 902 can program other components (e.g., BIOS processor circuitry, core chiplets, accelerator chiplets, memory and I / O chiplets, networking chiplets, etc.) using BIOS instructions and / or OS based on runtime configuration and / or payload received from remote cluster managers. Furthermore, the FMS circuit 902 communicates with one or more remote cluster managers to complete ownership transfer procedures (e.g., FIDO TO2 procedures), thereby transferring control of the EPU to one or more remote cluster managers.

[0124] exist Figure 12 In the example, the FMS circuit 902 also includes operations (e.g., procedures, mechanisms, etc.) that enable the host OS and / or BIOS to communicate with the FMS circuit 902 after BIOS instructions and / or OS are installed (e.g., on the core chiplet 904, on the accelerator chiplet 906, etc.). In this way, the host interface of the FMS circuit 902 (e.g., Figure 12 The interface circuit 916 can communicate with the host OS and / or BIOS to manage the EPU during active operation.

[0125] Figure 12 yes Figure 12 A block diagram of an example implementation of the FMS circuit 902. Figure 12 In the example, FMS circuit 902 includes example power control service 1202, example loading service 1204, example cluster manager client 1206, example identification service 1208, example recovery service 1210, and example AI telemetry service 1212. For example, power control service 1202, loading service 1204, cluster manager client 1206, identification service 1208, recovery service 1210, and AI telemetry service 1212 are implemented within example OS 1214 of FMS circuit 902.

[0126] exist Figure 12In the illustrated example, when power control service 1202 powers on FMS circuit 902, FMS circuit 902 discovers, authenticates, and associates with example remote cluster manager 1216. For example, load service 1204 performs discovery functionality according to the FDO protocol to identify the remote cluster manager 1216 that FMS circuit 902 should attempt to load during its supply lifecycle based on data from example manufacturing component 1218. Figure 12 In the example, the loading service 1204 communicates with the remote cluster manager 1216 using a standards-based interface (e.g., UCIe) and EPU hardware (e.g., integrated with the FMS circuitry 902).

[0127] exist Figure 12 In the illustrated example, after discovering the remote cluster manager 1216, the cluster manager client 1206 causes the example network interface card (NIC) circuitry 1220 of the EPU to transmit communication to the remote cluster manager 1216. For example, the cluster manager client 1206 utilizes a standards-based interface (UCIe) with the NIC circuitry 1220. Figure 13 In this example, the communication includes the platform identifier of the FMS circuit 902. To access the platform identifier, the identifier service 1208 communicates with the example root of trust (RoT) circuit 1222 of the EPU. For example, the identifier service 1208 utilizes a standards-based interface (UCIe) with the RoT circuit 1222.

[0128] exist Figure 9 In the illustrated example, the platform identifier for the FMS circuit 902 is based on the DICE standard and includes the FMS circuit 902's safety and device certifications. Figure 14 In the example, the remote cluster manager 1216 authenticates the security and device certificates of the FMS circuit 902. For instance, the remote cluster manager 1216 uses the DICE identifier of the FMS circuit 902 to authenticate the FMS circuit 902. Figure 9 In the example, the remote cluster manager 1216 matches the platform identifier of the FMS circuit 902 with the identifier of the tenant deployment and the location of the EPU.

[0129] In this way, the remote cluster manager 1216 identifies a tenant-specific profile and securely deploys it to the FMS circuit 902. For example, the tenant-specific profile includes runtime configurations for configuring the EPU (e.g., OS, security context, SW and / or FW images, etc.) and a payload, which includes ongoing operations and any new certificates required for communication with the remote cluster manager 1216. Figure 15In the example, based on the tenant-specific profile, recovery service 1210 communicates with example host interface firmware 1224 to program other components of the EPU (e.g., BIOS processor circuitry, core chiplet, accelerator chiplet, memory and I / O chiplet, networking chiplet, etc.) with BIOS instructions and / or OS.

[0130] Furthermore, the loading service 1204 communicates with the remote cluster manager 1216 to complete the ownership transfer process (e.g., FIDO TO1 process, FIDO TO2 process, etc.), thereby transferring control of the EPU to the remote cluster manager 1216. Figure 9 In the example, after BIOS instructions and / or the OS are installed (e.g., on core chiplet 904, on accelerator chiplet 906, etc.), the cluster manager client 1206 also communicates with the example host OS driver 1226 of the example host OS 1228. In this way, the cluster manager client 1206 can communicate with the host OS 1228 for managing the EPU during active operation.

[0131] For example, the cluster manager client 1206 collects data from the host OS 1228 and provides the data to the AI ​​telemetry service 1212. For example, the AI ​​telemetry service 1212 performs localized, independent recovery and operational optimization actions on the SiP's resources. In some examples, the AI ​​telemetry service 1212 forwards telemetry data to one or more data sources 1230 (e.g., outside the EPU, inside the EPU, etc.). In this way, the recovery service 1210 can communicate with the example watchdog timer circuit 1232 to recover the EPU as needed. As described herein, the cluster manager client 1206 acts as an example interface between the host OS 1228 and the remote cluster manager 1216.

[0132] As described above, the FMS circuit 902 can be implemented on a package within a SiP and / or together with any die, chiplet, tile, etc., of the SiP. For example, Figure 16 This is implemented in the example memory and input / output (I / O) chiplet 1302 of SiP 1300. Figure 9 A block diagram of an example SiP 1300 for the FMS circuit 902. Figure 13 It is implemented in the example accelerator chiplet 1402 of SiP 1400. Figure 9 A block diagram of an example SiP1400 FMS circuit 902.

[0133] Figure 13 It is included in the implementation outside of the example SiP 1502. Figure 9A block diagram of an example system 1500 for the FMS circuit 902. For example, the FMS circuit 902 is implemented in an example network interface card (NIC) circuit 1504 external to the SiP 1502. Figure 13 This is a block diagram of an example system 1600 including the example SiP 1602, where Figure 13 The FMS circuit 902 is implemented as a dedicated chip. For example, the SiP 1602 includes an example SoC 1604 and an example complex programmable logic device (CPLD) 1606 that implements the FMS circuit 902.

[0134] Back Figure 13 The memory and I / O chiplet 1302 includes input and output interface circuitry compliant with protocols such as PCIe, Serial Peripheral Interface (SPI), Enhanced SPI (eSPI), I3C, SMBUS, I2C, and Double Data Rate (DDR) protocols (e.g., DDR5). For example, the memory and I / O chiplet 1302 is similar to... Figure 14 This is achieved through the memory and I / O chip 910. Figure 14 In the example, the SiP 1300 also includes an example accelerator chiplet 1304. For example, the accelerator chiplet 1304 is similar to... Figure 9 It is implemented using the 906 accelerator chip.

[0135] exist Figure 14 In the illustrated example, when the FMS circuitry 902 is integrated with the memory and I / O chiplet 1302, there are at least two options for exposing the FMS circuitry 902 to the software of the SiP 1300 (e.g., the host EPU). First, the FMS circuitry 902 can be connected to the internal PCIe-compatible architecture of the memory and I / O chiplet 1302, exposing itself as a PCIeRCiEP device. Second, the FMS circuitry 902 can be connected to the memory and I / O chiplet 1302 via a low-performance global architecture. In the second case, the FMS circuitry 902 includes internal circuitry that maps the FMS circuitry 902 to the software memory space of the SiP 1300 (e.g., the host EPU). Furthermore, in the second case, the SiP 1300's BIOS is notified that the FMS circuitry 902 is enabled by resetting fuse settings. For example, the SiP 1300 BIOS communicates with the SiP 1300 host OS about the presence of the FMS circuit 902, and the host OS accesses the register space of the FMS circuit 902 through the mapped memory space.

[0136] exist Figure 14In the illustrated example, the FMS circuit 902 can be enabled when the rest of the SiP 1300 is reset or powered off. Figure 14 In the example, the FMS circuit 902 is powered via a dedicated power delivery rail and includes at least one circuit for early boot and reset control of the SiP 1300. If the SiP 1300 has an integrated networking controller, the FMS circuit 902 can utilize the networking controller to communicate with an external remote cluster manager (e.g., a remote cluster management administrator entity) (e.g., running in the cloud). Additionally or alternatively, the FMS circuit 902 can be connected to the platform's NIC circuitry, on which the SiP 1300 is configured for remote networking access using an SMBUS interface.

[0137] exist Figure 14 In the illustrated example, the FMS circuit 902 is integrated with the accelerator chiplet 1402. Figure 13 In the example, accelerator chip 1402 includes at least one non-networked accelerator circuit and at least one networked accelerator circuit. For example, accelerator chip 1402 is similar to Figure 15 The accelerator is implemented using the 906 accelerator chip. Figure 15 In the example, there are two options for exposing the FMS circuitry 902 to the software of the SiP 1400 (e.g., the host EPU). First, the FMS circuitry 902 can be connected to the internal PCIe-compatible architecture of the accelerator chiplet 1402 and expose itself as a PCIe RCiEP device. Second, the FMS circuitry 902 can be connected to the accelerator chiplet 1402 through a low-performance global architecture. In the second case, the FMS circuitry 902 includes internal circuitry that maps the FMS circuitry 902 to the software memory space of the SiP 1400 (e.g., the host EPU).

[0138] exist Figure 15 In the illustrated example, the FMS circuit 902 is powered via a dedicated power delivery rail and includes at least one circuit for early boot and reset control of the SiP 1400. In this way, the FMS circuit 902 can be fully enabled even when the SiP 1400 is offline (e.g., when reset or powered off). Figure 15 In the example, the FMS circuit 902 accesses the SiP 1400's telemetry and crash logs through the SiP 1400's global infrastructure.

[0139] exist Figure 15In the illustrated example, if the FMS circuit 902 is integrated with the networking accelerator circuitry of the accelerator chip 1402, the FMS circuit 902 utilizes the networking accelerator circuitry to communicate with an external remote cluster manager (e.g., a remote cluster management administrator entity) (e.g., running in the cloud). Additionally or alternatively, if the FMS circuit 902 is integrated with the non-networking accelerator circuitry of the accelerator chip 1402, the FMS circuit 902 is similar to... Figure 16 The example communicates with the remote cluster manager in the same way.

[0140] exist Figure 16 In the illustrated example, the FMS circuit 902 is integrated externally to the SiP 1502. As described above, the FMS circuit 902 is integrated with the NIC circuit 1504 external to the SiP 1502. Figure 16 In the example, when the FMS circuit 902 is integrated inside the external NIC circuit, the FMS circuit 902 uses the peripheral components of the NIC circuit to download firmware from the NIC SPI. Furthermore, the FMS circuit 902 performs self-authentication of the firmware.

[0141] exist Figure 16 In the illustrated example, FMS circuit 902 utilizes the Ethernet port of NIC circuit 1504 for remote network access. Figure 16 In the example, NIC circuit 1504 is designed to allow FMS circuit 902 to access the network without requiring SiP 1502 to access the network. Additionally, FMS circuit 902 communicates with the RoT of SiP 1502 via an I3C interface (e.g., between NIC circuit 1504 and SiP 1502) for secure flow including device ID provisioning. Figure 16 In the example, the FMS circuit 902 communicates with the telemetry circuit of the SiP 1502 through the I3C interface of the NIC circuit 1504.

[0142] exist Figure 16 In the illustrated example, the FMS circuitry 902 is integrated as an example CPLD 1606 (e.g., a CPLD FPGA) external to the SiP 1602 SoC 1604. For example, the SoC 1604 includes a core chiplet, an accelerator chiplet, a networking chiplet, and memory and I / O chiplets. Figure 17 In the example, the CPLD 1606 is used by the SoC 1604 for non-volatile random access memory (NVRAM) offloading.

[0143] exist Figure 9In the illustrated example, the CPLD 1606 connects to the example flash memory 1608 of the system 1600 (e.g., platform) via an SPI interface to download firmware to implement the FMS circuit 902. Furthermore, the FMS circuit 902 utilizes an I3C interface to communicate with the RoT of the SoC 1604 using an SPDM stream (e.g., to complete cluster management security streams). Figure 17 In the example, the FMS circuit 902 also uses an I3C interface to connect to the telemetry circuit of the SoC 1604.

[0144] exist Figure 9 In the illustrated example, the FMS circuit 902 exposes itself to the host interface of the SoC 1604 through the memory mapping space of the SoC 1604. Additionally, the CPLD 1606 includes an SMBUS interface to allow the FMS circuit 902 to connect to the example NIC circuit 1610 (or BMC) of the system 1600 (e.g., platform) for remote network access. Figure 9 In the example, the FMS circuit 902 is active and operational when the SoC 1604 is reset or powered off. Table 1 below illustrates the example capabilities of the FMS circuit 902 depending on where it is implemented. Additionally, Table 2 below illustrates the capabilities when... Figure 17 An example of the FMS circuit 902 implemented in the CPLD 1606 is available offline. Table 1 Table 2

[0145] Figure 17 It is a diagram. Figure 17 A block diagram illustrating example communication between the FMS circuit 902 and the network in the example platform 1700, where the example SiP 1702 includes an example infrastructure processor unit (IPU) circuit 1704 integrated within the SiP 1702. For example, the functionality and use of the FMS circuit 902 depend on network access. Thus, the FMS circuit 902 should be able to access a network (e.g., the Internet). Furthermore, network access performed by the FMS circuit 902 should be via a secure network channel, allowing tenant-specific private keys and certificates to be embedded within the FMS circuit 902.

[0146] exist Figure 17 In the illustrated example, SiP 1702 includes an example networking chiplet 1706 and an example memory and I / O chiplet 1708. For example, the networking chiplet 1706 is similar to... Figure 17The networking chip 908 is used for implementation, and the memory and I / O chip 1708 are similar. Figure 17 This is achieved through the memory and I / O chip 910. Figure 17 In the example, the networking chip 1706 includes an IPU circuit 1704. Figure 17 In the example, IPU circuit 1704 is integrated with networking chiplet 1706, and FMS circuit 902 is integrated with memory and I / O chiplet 1708 (e.g., a different chiplet from IPU circuit 1704).

[0147] exist Figure 18 In the illustrated example, IPU circuitry 1704 includes a management interface (e.g., an Integrated Management Controller (IMC) interface). In some examples, networking chiplet 1706 includes additional or alternative accelerator circuitry. Alternatively or additionally, FMS circuitry 902 may be integrated with networking chiplet 1706. Figure 9 In the example, FMS circuit 902 can communicate with the network in two ways. First, FMS circuit 902 can communicate with the network via IPU circuit 1704. Second, FMS circuit 902 can communicate with the network via tunneling through example BMC 1710 of platform 1700.

[0148] In the first approach, the management interface of IPU circuit 1704 is included (e.g., added to) the sideband network of SiP 1702. In this first approach, the sideband network of SiP 1702 (e.g., a UCIe SB network) allows IPU circuit 1704 to be discovered by any circuit on the same chiplet or by one or more circuits on different chiplets. In this way, FMS circuit 902 discovers IPU circuit 1704 interconnected via the UCIe sideband standard. In this first approach, FMS circuit 902 and IPU circuit 1704 establish a secure channel for mutual authentication. Mutual authentication can be based on manufacturer-supplied certificates (e.g., unique to each component and device) and / or via explicit authentication (e.g., using RoT of SiP 1702).

[0149] exist Figure 18 In the illustrated example, in the first approach, IPU circuit 1704 and FMS circuit 902 have silicon "bridge" circuitry that converts network packets from a network protocol (e.g., MCTP) to a sideband protocol (e.g., UCIe SB protocol) and vice versa. In the first approach, after a secure channel is established between IPU circuit 1704 and FMS circuit 902, network packets can traverse back and forth between FMS circuit 902 and IPU circuit 1704. Figure 9In the example, IPU circuit 1704 has a supplied Internet network interface (e.g., via a security orchestration as described herein).

[0150] exist Figure 18 In the illustrated example, in the second method, the management interface of IPU circuit 1704 is included (e.g., added to) the sideband network of BMC 1710. In this second method, the sideband network of BMC 1710 (e.g., a Network Controller Sideband Interface (NC-SI) network, a Simplified Media Independent Interface (RMII) network, etc.) allows BMC 1710 to discover IPU circuit 1704. In this way, BMC 1710 discovers IPU circuit 1704 and establishes a secure, mutually authenticated channel with IPU circuit 1704. Mutual authentication can be based on manufacturer-supplied certificates (e.g., unique to each component and each device) and / or via explicit certification (e.g., using RoT of SiP 1702).

[0151] exist Figure 18 In the illustrated example, in the second method, IPU circuit 1704 and BMC 1710 have silicon “bridge” circuitry that converts network packets from a network protocol (e.g., MCTP) to a sideband protocol (e.g., NC-SI, RMII, etc.) and vice versa. In the second method, after establishing a secure channel with IPU circuit 1704, BMC 1710 can forward network packets from IPU circuit 1704 to FMS circuit 902 via example I3C interface circuit 1712 and example out-of-band management service (OOBMS) circuit 1714. In this way, network packets can traverse back and forth between FMS circuit 902 and IPU circuit 1704 via BMC 1710.

[0152] As described above, the FMS circuit 902 has network access. Therefore, the FMS circuit 902 can establish a secure tunnel (e.g., mutually transport layer security (TLS) authentication and protection) between the FMS circuit 902 and the remote cluster manager. For example, the secure tunnel (e.g., mutually TLS authentication and protection) is based on the device-unique DICE-based identifier of the FMS circuit 902. As described above, the remote cluster manager is responsible for the secure key management of the SiP 1702 and the remote secure provisioning of the OS image.

[0153] Figure 18 It is a diagram. Figure 17A block diagram illustrating example communication between the FMS circuit 902 and the network in the example platform 1800, wherein the example SiP 1802 includes an example network interface card (NIC) circuit 1804 integrated externally to the SiP 1802. As mentioned above, the functionality and use of the FMS circuit 902 depend on network access. Thus, the FMS circuit 902 should be able to access a network (e.g., the Internet). Furthermore, network access performed by the FMS circuit 902 should be via a secure network channel, allowing tenant-specific private keys and certificates to be embedded within the FMS circuit 902.

[0154] exist Figure 18 In the illustrated example, SiP 1802 includes an example memory and I / O chiplet 1806. For example, the memory and I / O chiplet 1806 are similar to... Figure 19 This is achieved through the memory and I / O chip 910. Figure 9 In the example, the FMS circuitry 902 is integrated with the memory and I / O chiplet 1806. Furthermore, the memory and I / O chiplet 1806 includes example I3C interface circuitry 1808 and example OOBMS circuitry 1810. In some examples, the NIC circuitry 1804 may be implemented by an IPU. Additionally or alternatively, the NIC circuitry 1804 may be a standalone NIC on platform 1800, or integrated within example BMC 1812 of the platform. Figure 19 In the example, the NIC circuit 1804 includes a management interface (e.g., NC-SI) that provides connectivity via the RoT or BMC1812 (or LOP) of the platform 1800.

[0155] exist Figure 9 In the illustrated example, FMS circuit 902 can communicate with the network in two ways. First, FMS circuit 902 can communicate with the network via the example translator CPLD 1814 of platform 1800. For example, translator CPLD 1814 translates network packets from sideband protocols (e.g., NC-SI protocol) to network protocols (e.g., MCTP, I3C protocol, etc.) and vice versa. Second, FMS circuit 902 can communicate with the network via tunneling through BMC 1812 of platform 1800. In this way, FMS circuit 902 can connect to a remote cluster manager using NIC circuit 1804, as described herein.

[0156] like Figure 19 and Figure 19As illustrated, the FMS circuit 902 can communicate with other chiplets and / or dies in the SiP using die-to-die interconnect standards (e.g., UCIe standard, UCIe sideband standard, etc.). In this way, the FMS circuit 902 can discover network components to facilitate connectivity between the FMS circuit 902 and the network (e.g., to communicate with a remote cluster manager). Therefore, the FMS circuit 902 can achieve secure and protected communication with the network (e.g., via TLS, SPDM, TDISP, etc.).

[0157] Figure 19 yes Figure 19 A block diagram of an example implementation of the FMS circuit 902. For example, relative to other components in a SiP, Figure 19 The diagram shows... Figure 19 The components of the FMS circuit 902. In Figure 19 In the example, the FMS circuit 902 includes an interface circuit 916, a configuration circuit 918, a memory 920, one or more processor circuits 922, a mailbox circuit 924, and a system control circuit 926.

[0158] exist Figure 19 In the illustrated example, interface circuitry 916 provides a standard interface to the host of FMS circuitry 902, allowing FMS circuitry 902 to be integrated into chiplets from any vendor (e.g., Intel-based chiplets, ARM-based chiplets, RISC-based chiplets, etc.). In this way, interface circuitry 916 provides FMS circuitry 902 with the flexibility to exist anywhere in a SiP while maintaining a consistent set of HW-SW interfaces, programmable processes, and communication messages. In this way, interface circuitry 916 advantageously allows FMS circuitry 902 to be integrated into multi-chiplet, multi-watt, and / or multi-die devices.

[0159] exist Figure 19 In the illustrated example, interface circuitry 916 allows FMS circuitry 902 to be directly exposed as an RCIEP device to the host software of the SiP (e.g., EPU). For example, one or more core processor circuits of core chiplet 904 implement host software (e.g., OS, BIOS, etc.). In this way, host software can access the register space of FMS circuitry 902 and communicate with FMS circuitry 902 through various message passing streams to transfer data, receive error notifications, and / or receive interrupts.

[0160] Additionally or alternatively, interface circuitry 916 allows FMS circuitry 902 to be exposed as an RCIEP device via an indirect mechanism. For example, if FMS circuitry 902 is a sub-component within the chiplet's address space, FMS circuitry 902 can expose itself as an RCIEP device via interface circuitry 916, and SiP's host software can discover FMS circuitry 902 through SiP's internal infrastructure. For example, SiP's internal infrastructure is example IOSF configuration circuitry 1902. In this way, host software can access the register space of FMS circuitry 902 and communicate with FMS circuitry 902 through various message passing streams to transfer data, receive error notifications, and / or receive interrupts.

[0161] exist Figure 19 In the illustrated example, the configuration circuitry 918 allows the FMS circuitry 902 to be integrated into any internal configuration of the SiP (e.g., IOSF configuration circuitry 1902, ARM Advanced Microcontroller Bus Architecture (AMBA) configuration circuitry, RISC configuration circuitry, etc., and / or any combination thereof). Furthermore, the configuration circuitry 918 allows the FMS circuitry 902 to communicate with chiplets or internal components of the SiP via the example IOSF-SB router circuitry 1904. For example, the configuration circuitry 918 allows the FMS circuitry 902 to communicate with the accelerator chiplet 906, the example network interface card (NIC) circuitry 1906 of the SiP, the example OOBMS circuitry 1908 of the SiP, the example RoT circuitry 1910 of the SiP, and / or one or more example fuses 1912 of the SiP via the IOSF-SB router circuitry 1904.

[0162] exist Figure 19 In the illustrated example, memory 920 is implemented using SRAM as described above. Figure 17 In some examples, memory 920 stores the boot and runtime code of FMS circuitry 902 and / or other components of the SiP. For instance, memory 920 allows FMS circuitry 902 to become a fully persistent subsystem capable of managing its own boot. In some examples, memory 920 is configured as a field-programmable ROM device, which allows FMS circuitry 902 to self-contain and update its own boot code without accessing the flash memory of the SiP and / or another device.

[0163] exist Figure 18 In the illustrated example, one or more processor circuits 922 are expandable. Figures 9-19In the example, one or more processor circuits 922 perform the initial boot of the FMS circuit 902, verify the firmware of the FMS circuit 902, and communicate with the RoT circuit 1910 for security device ID provisioning. Furthermore, one or more processor circuits 922 communicate with the host EPU software (e.g., one or more core processor circuits of the core chiplet 904) to expose the FMS circuit 902 as a cluster management device. Figures 9-19 In the example, one or more processor circuits 922 communicate with OOBMS circuit 1908 to download one or more telemetry and / or crash reports and send one or more reports to one or more host EPU software or remote cluster manager (e.g., running in the cloud). Furthermore, one or more processor circuits 922 perform remote control boot and / or reset operations for the SiP and act as cluster manager clients to execute remote cluster management commands for the SiP.

[0164] exist Figures 9-19 In the illustrated example, mailbox circuit 924 is implemented as one or more of a DOE mailbox requester or a DOE mailbox responder. Furthermore, system control circuitry 926 communicates with RoT circuitry 1910 via interface circuitry 916 to facilitate the provision of licensed firmware and security profiles to the SiP as described above. Figures 9-19 In the example, NIC circuit 1906 communicates with FMS circuit 902, as described above. Figures 9-19 and / or Figure 20 As described above. In some examples, the NIC circuit 1906 is implemented as an IPU.

[0165] As described above, the example FMS circuit 902 can be incorporated into any of the depolymerized dies in a multi-chiplet SiP. For example, the FMS circuit 902 can be integrated into an Intel-based chiplet with Intel-based interconnects, a RISC-based or ARM-based chiplet with proprietary interconnects, and / or any combination of chiplets with different interconnects. In the examples disclosed herein, the standard physical interface, the standard definition of the consistent HW-SW interface, and the register definition of the FMS circuit 902 allow the FMS circuit 902 to be integrated at the platform component level anywhere within and / or outside the SiP. In some examples, as described above, the FMS circuit 902 is integrated within a chiplet (e.g., in a multi-vendor SiP with one or more interconnects). Key components of the FMS subsystem are shown below.

[0166] Figure 21 The FMS circuit 902 can be exemplified (e.g., instantiated, generated, materialized, implemented, etc.) by a programmable circuit module (such as a central processing unit (CPU) that executes the first instruction). Additionally or alternatively,Figure 22 The FMS circuit 902 can be exemplified (e.g., created, generated, materialized, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA) that can be constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that... Figure 23 Some or all of the circuit modules in the circuit module can therefore be exemplified at the same or different times. For example, Figure 20 Some or all of the circuit modules in the circuit module can be instantiated in hardware simultaneously and / or serially in hardware in one or more threads. Furthermore, in some examples, Figure 21 Some or all of the circuit modules in the circuit module can be implemented by a microprocessor circuit module that executes instructions and / or an FPGA circuit module that performs operations to implement one or more virtual machines and / or containers.

[0167] In some examples, one or more processor circuits 922 are executed by programmable circuit modules that execute cluster management instructions and / or are configured to perform operations such as those by... Figure 24 and Figures 9-19 Operations such as those represented by one or more flowcharts. In some examples, the FMS circuit 902 includes components for managing the computer. For example, the components for management may be implemented by one or more processor circuits 922. In some examples, one or more processor circuits 922 may be exemplified by a programmable circuit module, such as... Figure 9 Example programmable circuit module 2212. For example, one or more processor circuits 922 can be provided by Figures 9-19 The example microprocessor 2300 is used as an example, which executes machine-executable instructions, such as at least by... Figures 9-19 The boxes 2002, 2004, 2006, 2008 and 2010 and / or Figures 9-19 The instructions implemented in boxes 2102, 2104, 2106, and 2108.

[0168] In some examples, one or more processor circuits 922 may be exemplified by hardware logic circuit modules, which may be ASICs, XPUs, or other hardware logic circuit modules configured and / or constructed to perform operations corresponding to machine-readable instructions. Figures 9-19The FPGA circuit module 2400 is used for implementation. Additionally or alternatively, one or more processor circuits 922 may be exemplified by any other combination of hardware, software, and / or firmware. For example, one or more processor circuits 922 may be implemented by at least one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other configurations are equally suitable.

[0169] Although Figure 20 The diagram below illustrates the implementation. Figure 21 The example of the FMS circuit 902, but Figures 9-19 One or more of the elements, processes, and / or devices illustrated in the diagram may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, Figures 9-19 The example interface circuit 916, example configuration circuit 918, example memory 920, one or more example processor circuits 922, example mailbox circuit 924, example system control circuit 926, and / or more generally example FMS circuit 902 can be implemented by hardware alone, or by hardware in combination with software and / or firmware. Therefore, for example, any of the example interface circuit 916, example configuration circuit 918, example memory 920, one or more example processor circuits 922, example mailbox circuit 924, example system control circuit 926, and / or more generally example FMS circuit 902 can be implemented by a programmable circuit module in combination with machine-readable instructions (e.g., firmware or software), a processor circuit module, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (one or more GPUs), one or more digital signal processors (one or more DSPs), one or more ASICs, one or more programmable logic devices (one or more PLDs), and / or one or more field-programmable logic devices (one or more FPLDs, such as FPGAs). Furthermore, Figure 22 Example FMS circuit 902 may include as a pair Figure 23 The elements, processes and devices illustrated herein may be supplemented or replaced by one or more elements, processes and / or devices, and / or may include any or more of the elements, processes and devices illustrated herein.

[0170] Figure 24 and Figure 6 The diagram shows an example that can be implemented by a programmable circuit module and / or executor. Figure 7 Example machine-readable instructions and / or representations of the FMS circuit 902 can be implemented and / or exemplified by a programmable circuit module. Figure 8 The flowchart illustrates one or more example operations of the FMS circuit 902. Machine-readable instructions may be used by combining, for example, the following... Figure 20 The programmable circuit module 2212, as shown in the example programmable circuit module platform 2200 discussed in the discussion, executes one or more executable programs or one or more portions of one or more executable programs, and / or may be used for execution by the programmable circuit module 2212, as described below. Figure 21 and / or Figure 6 The examples discussed are programmable circuit modules (e.g., FPGAs) that perform one or more functions or portions of functions. In some examples, machine-readable instructions cause operations, tasks, etc., to be performed and / or executed in a real-world manner. As used herein, “automation” means without human intervention.

[0171] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, compact discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or disk. The instructions on the non-transitory computer-readable and / or machine-readable medium may be programmed and / or executed by a programmable circuit module located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or executed by one or more hardware devices other than the programmable circuit module, and / or embodied in dedicated hardware. Machine-readable instructions may be distributed across multiple hardware devices and / or implemented by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices may be implemented by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users) or intermediate client hardware device gateways (e.g., radio access networks (RAN)) that facilitate communication between server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media may include one or more media. Furthermore, although references are made to...Figure 7 , Figure 8 , Figure 20 , Figure 21 and / or Figure 20 The flowcharts(s) illustrated herein describe example programs, but alternatively, many other methods may be used to implement example TSM circuit 108, example CDSM circuit 114, example RoT DCC circuit 120, and / or example FMS circuit 902. For example, the execution order of the blocks in the flowcharts(s) may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all blocks in the flowcharts may be implemented by one or more hardware circuits (e.g., processor circuit modules, discrete and / or integrated analog and / or digital circuit modules, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware. Programmable circuit modules may be distributed in different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, a programmable circuit module may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, and / or any combination thereof.

[0172] The machine-readable instructions described herein may be stored in one or more formats, such as compressed formats, encrypted formats, segmented formats, compiled formats, executable formats, and encapsulated formats. As described herein, machine-readable instructions may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as parts of instructions (one or more), code, code representations, etc.), which may be used to create, manufacture, and / or generate machine-executable instructions. For example, machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, at an edge device, etc.) within a network or network set. Machine-readable instructions may require installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., to make them directly readable, interpretable, and / or executable by computing devices and / or other machines. For example, machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and / or stored on separate computing devices, wherein the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations of a program that together form a program such as the one described herein.

[0173] In another example, machine-readable instructions may be stored in a state in which they can be read by a programmable circuit module, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the machine-readable instructions on a specific computing device or other device. In another example, machine-readable instructions may need to be configured (e.g., settings are stored, data is entered, network addresses are recorded, etc.) before the machine-readable instructions and / or (one or more) corresponding programs can be executed fully or partially. Therefore, machine-readable, computer-readable, and / or machine-readable media as used herein may include instructions and / or (one or more) programs, regardless of the specific format or state of the machine-readable instructions and / or (one or more) programs.

[0174] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0175] As mentioned above, Figure 9 , Figure 20 , Figure 20 , Figure 20 and / or Figure 20 Example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms "non-transitory computer-readable medium," "non-transitory computer-readable storage medium," "non-transitory machine-readable medium," and / or "non-transitory machine-readable storage medium" are explicitly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk, wherein information can be stored for any duration (e.g., extended time periods, permanently, for short instances, for temporary buffering, and / or for caching information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as including any physical (mechanical, magnetic, and / or electrical) hardware used to retain information for a period of time, but excluding propagating signals and transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, hard disk, disk drive, and / or redundant array of independent disks (RAID) system. As used herein, the term "device" means a physical structure, such as mechanical and / or electrical equipment, hardware, and / or circuit modules, that can or may not be configured and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0176] Figure 20This is a flowchart illustrating example machine-readable instructions and / or example operations 2000, which can be implemented, executed, and / or executed by an example programmable circuit module to achieve... Figure 21 The FMS circuit 902 is used to identify and load data into the remote cluster manager. Figure 9 Example machine-readable instructions and / or example operations 2000 begin at block 2002, where FMS circuitry 902 performs a discovery function to identify a remote cluster manager to which FMS circuitry 902 is to load. For example, FMS circuitry 902 identifies at least one device, on behalf of a SiP (e.g., an integrated circuit package), with which it establishes a secure communication session, wherein the at least one device is located outside the integrated circuit package.

[0177] exist Figure 21 In the illustrated example, at block 2004, the FMS circuit 902 enables the SiP's interface circuitry to communicate with the remote cluster manager to authenticate the FMS circuit 902. For example, the SiP is to be managed by the FMS circuit 902. Figure 21 In the example, the communication includes the platform identifier of the FMS circuit 902. For example, the platform identifier includes the security and device certificates of the FMS circuit 902.

[0178] exist Figure 21 In the illustrated example, at block 2006, FMS circuit 902 accesses the tenant-specific profile of the SiP from a remote cluster manager via an interface circuit. For example, the tenant-specific profile includes runtime configuration for configuring the SiP (e.g., OS, security context, SW and / or FW image, etc.) and a payload, which includes ongoing operations and any new certificates required for communication with the remote cluster manager. Thus, after authenticating FMS circuit 902 to the remote cluster manager, FMS circuit 902 accesses the SiP's configuration profile from the remote cluster manager.

[0179] exist Figure 22 In the illustrated example, at box 2008, based on a tenant-specific profile, FMS circuitry 902 programs one or more components of the SiP (e.g., BIOS processor circuitry, core chiplets, accelerator chiplets, memory and I / O chiplets, networking chiplets, etc.). At box 2010, FMS circuitry 902 enables interface circuitry to communicate with a remote cluster manager to transfer control of the SiP from FMS circuitry 902 to the remote cluster manager.

[0180] Figure 6 This is a flowchart illustrating example machine-readable instructions and / or example operations 2100, which can be implemented, executed, and / or executed by an example programmable circuit module to achieve...Figure 7 The FMS circuit 902 is used to perform cluster management. Figure 8 Example machine-readable instructions and / or example operations 2100 begin at block 2102, where FMS circuitry 902 exposes itself to the host processor circuitry of the SiP using at least one of a plurality of interface circuits. For example, FMS circuitry 902 includes a plurality of interface circuits to enable it to be discovered by any of a plurality of dies of the depolymerization platform.

[0181] exist Figure 20 In the illustrated example, at box 2104, FMS circuitry 902 communicates with the telemetry circuitry of the SiP to collect at least one of a telemetry report or a crash report. For example, a telemetry report includes telemetry data related to one or more components of the SiP. Example telemetry data includes logs, metrics, events, and traces, and can appear in various forms such as environmental data, component status data, component performance data, etc. Example crash reports include information related to the state of hardware, software, and / or firmware components when a component crashes. For example, crash reports include data indicating the crash type, stack trace, software version, performance trends, system crash logs, settings information, and component activity logs. In some examples, crash reports include personal information of the user, such as passwords, email addresses, and payment information.

[0182] exist Figure 21 In the illustrated example, at block 2106, FMS circuitry 902 causes the SiP's interface circuitry to send at least one of a telemetry report or a crash report to the SiP's remote cluster manager. At block 2108, based on communication from the remote cluster manager, FMS circuitry 902 adjusts the SiP's operation. For example, based on the telemetry report, the remote cluster manager may instruct FMS circuitry 902 to adjust one or more operating parameters of at least one component of the SiP to meet the Service Level Agreement (SLA) and / or Service Level Objective (SLO) of the tenant utilizing the SiP. Additionally or alternatively, FMS circuitry 902 performs remote control boot and / or reset operations on the SiP based on communication from the remote cluster manager. In this way, FMS circuitry 902 delivers secure cluster management services in heterogeneous edge systems based on configuration profiles corresponding to the SiP.

[0183] As described above, the examples disclosed herein include architectures and systems for cross-platform root management that are anchored to hardware primitives with remote manageability and recoverability for ease of operation and security. Examples disclosed herein include self-contained silicon and firmware subsystems that operate independently and are isolated from host resources and services, capable of (1) initiating outbound communications for remote management, (2) facilitating physical system identification and authenticity challenges, (3) performing localized, independent, AI-driven recovery and operational optimization actions, and (4) providing a consistent management interface across heterogeneous silicon ecosystems.

[0184] The examples disclosed herein include processor architectures for edge cluster management systems designed for highly decentralized edge SoCs and / or SiPs. The examples disclosed herein deliver secure cluster management services to highly heterogeneous edge systems in a scalable and secure manner, consistently even when the SoC and / or SiP are in a functionally offline mode. The examples disclosed herein include details of SoC and / or SiP edge architectures and technical constructs for SoC and / or SiP cluster management.

[0185] Figures 1-5 This is a block diagram of an example programmable circuit module platform 2200, which is configured to implement and / or exemplify... Figures 1-5 , Figures 1-5 , Figures 9-19 , Figure 6 and / or Figure 7 Example machine-readable instructions and / or example operations to implement ​ TSM circuit 108, ​ CDSM circuit 114, ​ ROT DCC circuit 120 and / or ​ The FMS circuit 902. The programmable circuit module platform 2200 can be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, such as iPad). TM Tablet computers, personal digital assistants (PDAs), internet-connected appliances, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, headphones (e.g., augmented reality (AR) headphones, virtual reality (VR) headphones, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0186] The illustrated example programmable circuit module platform 2200 includes a programmable circuit module 2212. The illustrated example programmable circuit module 2212 is hardware. For example, the programmable circuit module 2212 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit module 2212 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit module 2212 implements example TSM circuit 108, example CDSM circuit 114, example RoT DCC circuit 120, and / or example FMS circuit 902.

[0187] The illustrated example programmable circuit module 2212 includes local memory 2213 (e.g., cache, registers, etc.). The illustrated example programmable circuit module 2212 communicates with main memories 2214 and 2216 (which include volatile memory 2214 and non-volatile memory 2216) via bus 2218. The volatile memory 2214 may be synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc. Dynamic Random Access Memory And / or any other type of RAM device. The non-volatile memory 2216 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 2214, 2216 of the illustrated example is controlled by the memory controller 2217. In some examples, the memory controller 2217 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuit module from any desired series or manufacturer to manage the data flow to and from the main memory 2214, 2216.

[0188] The illustrated example programmable circuit module platform 2200 also includes an interface circuit module 2220. The interface circuit module 2220 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, etc. Interfaces include Near Field Communication (NFC) interfaces, Peripheral Component Interconnect (PCI) interfaces, and / or Fast Peripheral Component Interconnect (PCIe) interfaces.

[0189] In the illustrated example, one or more input devices 2222 are connected to interface circuit module 2220. The input devices 2222 allow users (e.g., human users, machine users, etc.) to input data and / or commands into programmable circuit module 2212. The input devices 2222 can be implemented using, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, isopoint devices, and / or voice recognition systems.

[0190] One or more output devices 2224 are also connected to the interface circuit module 2220 of the illustrated example. The output devices 2224 may be implemented, for example, by display devices (e.g., light-emitting diode (LED), organic light-emitting diode (OLED), liquid crystal display (LCD), cathode ray tube (CRT) display, in-place switching (IPS) display, touchscreen, etc.), haptic output devices, printers, and / or speakers. Therefore, the interface circuit module 2220 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit module (such as a GPU).

[0191] The illustrated example interface circuit module 2220 also includes communication devices (such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces) to facilitate data exchange with external machines (such as any kind of computing device) via network 2226. Communication can be performed via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond-line-of-sight wireless systems, line-of-sight wireless systems, cellular telephone systems, optical connections, etc.

[0192] The illustrated example programmable circuit module platform 2200 also includes one or more mass storage disks or devices 2228 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 2228 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices (such as flash memory devices and / or SSDs).

[0193] can be ​ , ​ , Figure 8 , Figure 20 and / or Figure 21The machine-readable instructions 2232 implemented by the machine-readable instructions may be stored in a mass storage device 2228, a volatile memory 2214, a non-volatile memory 2216 and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD.

[0194] Figure 23 yes Figure 22 A block diagram of an example implementation of the programmable circuit module 2212. In this example, Figure 22 The programmable circuit module 2212 is implemented by the microprocessor 2300. For example, the microprocessor 2300 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit module). The microprocessor 2300 implements... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart contains some or all of the machine-readable instructions to effectively translate... Figures 1-5 and / or Figures 9-19 The circuit module is exemplified as a logic circuit used to perform operations corresponding to those machine-readable instructions. In some such examples, Figures 1-5 and / or Figures 9-19 The circuit modules are exemplified by the hardware circuitry of the microprocessor 2300 combined with machine-readable instructions. For example, the microprocessor 2300 can be implemented by a multi-core hardware circuit module such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of example cores 2302 (e.g., one core), this example microprocessor 2300 is a multi-core semiconductor device including N cores. The cores 2302 of the microprocessor 2300 can operate independently or collaboratively to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software programs, or software programs can be executed by one core of core 2302, or by multiple cores of core 2302 at the same or different times. In some examples, the machine code corresponding to firmware, embedded software programs, or software programs is split into threads and executed in parallel by two or more cores of core 2302. Software programs can correspond to... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart represents part or all of the machine-readable instructions and / or operations.

[0195] Core 2302 can communicate via a first example bus 2304. In some examples, the first bus 2304 may be implemented by a communication bus to enable communication associated with one or more cores of core 2302. For example, the first bus 2304 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 2304 may be implemented by any other type of computing or electrical bus. Core 2302 can obtain data, instructions, and / or signals from one or more external devices through example interface circuit module 2306. Core 2302 can output data, instructions, and / or signals to one or more external devices through interface circuit module 2306. While the core 2302 of this example includes example local memory 2320 (e.g., an L1 cache that can be partitioned into a Level 1 (L1) data cache and an L1 instruction cache), the microprocessor 2300 also includes example shared memory 2310 (e.g., a Level 2 (L2) cache) that can be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from shared memory 2310. The local memory 2320 and shared memory 2310 of each core in core 2302 can be part of a storage device hierarchy, including cache memory and main memory (e.g., Figure 22 The main memory (2214, 2216) is multi-level. Typically, higher-level memories in a hierarchy exhibit lower access times and have smaller storage capacities compared to lower-level memories. Changes within the various levels of the cache hierarchy are managed (e.g., coordinated) by cache coherence strategies.

[0196] Each core 2302 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit module. Each core 2302 includes a control unit circuit module 2314, an arithmetic and logic (AL) circuit module 2316 (sometimes referred to as an ALU), multiple registers 2318, local memory 2320, and a second example bus 2322. Other structures may exist. For example, each core 2302 may include a vector unit circuit module, a single instruction multiple data (SIMD) unit circuit module, a load / store unit (LSU) circuit module, a branch / jump unit circuit module, a floating-point unit (FPU) circuit module, etc. The control unit circuit module 2314 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 2302. The AL circuit module 2316 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on the data within the corresponding core 2302. Some examples of the AL circuit module 2316 perform integer-based operations. In other examples, the AL circuit module 2316 also performs floating-point operations. In other examples, the AL circuit module 2316 may include a first AL circuit module that performs integer-based operations and a second AL circuit module that performs floating-point operations. In some examples, the AL circuit module 2316 may be referred to as an arithmetic logic unit (ALU).

[0197] Register 2318 is a semiconductor-based structure used to store data and / or instructions, such as the results of one or more operations performed by the AL circuit module 2316 corresponding to core 2302. For example, register 2318 may include one or more vector registers, one or more SIMD registers, one or more general-purpose registers, one or more flag registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. Register 2318 may be arranged in a manner such as... Figure 23 The memory bank shown is used. Alternatively, register 2318 can be organized in any other arrangement, format, or structure, such as by distributing it throughout core 2302 to reduce access time. The second bus 2322 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0198] Each core 2302 and / or more generally, the microprocessor 2300 may include additional and / or alternative structures to those structures shown and described above. For example, one or more clock circuits, one or more power supply devices, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMS), one or more shifters (e.g., one or more barrel shifters), and / or other circuit modules may be present. The microprocessor 2300 is a semiconductor device fabricated to include a number of transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0199] The microprocessor 2300 may include one or more accelerators and / or cooperate with one or more accelerators (e.g., acceleration circuit modules, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuit modules to perform certain tasks faster and / or more efficiently than they could be performed by a general-purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. Accelerators may be on the microprocessor 2300 board, in the same chip package as the microprocessor 2300, and / or in one or more packages separate from the microprocessor 2300.

[0200] Figure 24 yes Figure 22 A block diagram illustrating another example implementation of the programmable circuit module 2212 is provided. In this example, the programmable circuit module 2212 is implemented by an FPGA circuit module 2400. For example, the FPGA circuit module 2400 can be implemented by an FPGA. The FPGA circuit module 2400 can be used, for example, to execute machine-readable instructions that might otherwise be executed by executing corresponding machine-readable instructions. Figure 23 The example microprocessor 2300 performs the operations. However, once configured, the FPGA circuit module 2400 executors operations and / or functions corresponding to machine-readable instructions in hardware, and therefore can typically perform the operations / functions faster than if they were executed by a general-purpose microprocessor executing the corresponding software.

[0201] More specifically, as described above Figure 23 The microprocessor 2300 (which can be programmed to perform via...) Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21A flowchart (or one or more) represents some or all of the common devices in machine-readable instructions, but whose interconnections and logic circuit modules are fixed once fabricated, forming a contrast. Figure 24 The example FPGA circuit module 2400 includes components that can be configured, constructed, programmed, and / or interconnected in different ways after fabrication, for example, via... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart(s) represent some or all of the interconnects and logic circuit modules corresponding to the operations / functions of machine-readable instructions. Specifically, the FPGA circuit module 2400 can be viewed as an array of logic gates, interconnects, and switches. Switches can be programmed to change how logic gates are interconnected via interconnects, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit module 2400 is reprogrammed). The configured logic circuits enable logic gates to cooperate in different ways to perform different operations on data received by the input circuit modules. Those operations can correspond to... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart(s) represent some or all of the instructions (e.g., software and / or firmware). In this way, the FPGA circuit module 2400 can be configured and / or constructed as dedicated logic circuitry to effectively represent instructions corresponding to… Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The FPGA circuit module 2400 executes some or all of the machine-readable instructions of one or more flowcharts, in a dedicated manner similar to that of an ASIC, to perform the operations / functions corresponding to those software instructions. Therefore, the FPGA circuit module 2400 can execute the corresponding operations / functions faster than a general-purpose microprocessor can perform the same operations / functions. Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 Some or all of the operations / functions in the machine-readable instructions.

[0202] exist Figure 24In some examples, the FPGA circuit module 2400 is configured and / or constructed in response to programming (and / or reprogramming once or multiple times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, VHSIC Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or programs corresponding to one or more operations / functions using HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., low-level language code / program) can be converted (e.g., by a compiler, software application, etc.) into a binary file. In some examples, Figure 24 The FPGA circuit module 2400 can access and / or load binary files to enable... Figure 24 The FPGA circuit module 2400 is configured and / or constructed to perform one or more operations / functions. For example, a binary file can be generated by... Figure 24 The FPGA circuit module 2400 can be implemented using bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to enable configuration and / or construction. Figure 24 The FPGA circuit module 2400 or one or more of it.

[0203] In some examples, binary files are compiled, generated, transformed, and / or otherwise output from a unified software platform used for programming the FPGA. For instance, the unified software platform can translate first instructions (e.g., code or program) corresponding to one or more operations / functions using a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions using HDL. In some such examples, binary files are compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 24 The FPGA circuit module 2400 can access and / or load binary files to enable... Figure 24 The FPGA circuit module 2400 is configured and / or constructed to perform one or more operations / functions. For example, a binary file can be generated by... Figure 24 The FPGA circuit module 2400 can be implemented using bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to enable configuration and / or construction. Figure 24 The FPGA circuit module 2400 or one or more of it.

[0204] Figure 24 The FPGA circuit module 2400 includes an example input / output (I / O) circuit module 2402 to obtain data from and / or output data to the example configuration circuit module 2404 and / or external hardware 2406. For example, the configuration circuit module 2404 may be implemented by an interface circuit module that can obtain a binary file, which may be implemented by bitstreams, data, and / or machine-readable instructions, to configure the FPGA circuit module 2400 or portions thereof. In some such examples, the configuration circuit module 2404 may obtain the binary file from a user, a machine (e.g., a hardware circuit module that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file (e.g., a programmable or dedicated circuit module)), and / or any combination thereof. In some examples, the external hardware 2406 may be implemented by an external hardware circuit module. For example, the external hardware 2406 may be... Figure 23 The microprocessor 2300 is implemented.

[0205] The FPGA circuit module 2400 also includes an array of example logic gate modules 2408, multiple example configurable interconnects 2410, and example memory circuit modules 2412. The logic gate modules 2408 and configurable interconnects 2410 are configurable to exemplify... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 One or more operations / functions and / or other desired operations in at least some of the machine-readable instructions. Figure 24 The logic gate module 2408 shown is fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NAND gates, etc.) that provide basic building blocks for the logic circuits. Each of the logic gate module 2408 contains electrically controllable switches (e.g., transistors) such that the configuration of the electrical structures and / or logic gates can form a circuit for performing a desired operation / function. The logic gate module 2408 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0206] The illustrated example of configurable interconnect 2410 may include conductive paths, traces, vias, etc., that may include electrically controllable switches (e.g., transistors), the states of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate modules in logic gate module 2408 in order to program the desired logic circuit.

[0207] The illustrated example storage circuit module 2412 is configured to store the results of one or more operations performed by the corresponding logic gates. The storage circuit module 2412 can be implemented using registers, etc. In the illustrated example, the storage circuit module 2412 is distributed within the logic gate circuit module 2408 to facilitate access and improve execution speed.

[0208] Figure 24 The example FPGA circuit module 2400 also includes an example dedicated operation circuit module 2414. In this example, the dedicated operation circuit module 2414 includes a dedicated circuit module 2416 that can be invoked to perform common functions, thereby avoiding the need for field programming of these functions. Examples of such dedicated circuit modules 2416 include memory (e.g., DRAM) controller circuit modules, PCIe controller circuit modules, clock circuit modules, transceiver circuit modules, and memory and multiplier-accumulator circuit modules. Other types of dedicated circuit modules may be present. In some examples, the FPGA circuit module 2400 may also include an example general-purpose programmable circuit module 2418, such as an example CPU 2420 and / or an example DSP 2422. Additionally or alternatively, other general-purpose programmable circuit modules 2418 that can be programmed to perform other operations, such as GPUs, XPUs, etc., may be present.

[0209] Although Figure 23 and Figure 24 The diagram shows... Figure 22 Two example implementations of the programmable circuit module 2212 are provided, but many other approaches are envisioned. For example, the FPGA circuit module may include an on-board CPU, such as... Figure 23 One or more of the example CPUs 2420. Therefore, Figure 22 The programmable circuit module 2212 can be additionally combined with at least Figure 23 Example microprocessor 2300 and Figure 24 The example FPGA circuit module 2400 is used for implementation. In some such hybrid examples, Figure 23 One or more cores of 2302 can be implemented by Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The first part of the flowchart (one or more) represents the machine-readable instructions to perform (one or more) first operations / (one or more) first functions. Figure 24 The FPGA circuit module 2400 can be configured and / or constructed to perform operations corresponding to those performed by... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart represents the second part of a machine-readable instruction (one or more) of a second operation / function (one or more), and / or the ASIC can be configured and / or constructed to perform an operation corresponding to the second operation / function of the second part of the machine-readable instruction ... second function of the second part of the machine-readable instruction (one or more), Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 The flowchart represents the third part of a machine-readable instruction, which is one or more third operations / one or more third functions.

[0210] It should be understood that Figures 1-5 and / or Figures 9-19 Some or all of the circuit modules in the circuit module can therefore be exemplified at the same or different times. For example, Figure 23 One or more identical and / or different parts of the microprocessor 2300 can be programmed to execute one or more machine-readable instructions at the same and / or different times. In some examples, Figure 24 One or more identical and / or different parts of the FPGA circuit module 2400 may be configured and / or constructed to perform operations / functions corresponding to one or more machine-readable instructions at the same and / or different times.

[0211] In some examples, Figures 1-5 and / or Figures 9-19 Some or all of the circuit modules in the circuit module can be instantiated, for example, in one or more threads that execute concurrently and / or serially. For example, Figure 23 The microprocessor 2300 can execute machine-readable instructions in one or more threads that execute concurrently and / or serially. In some examples, Figure 24 The FPGA circuit module 2400 can be configured and / or constructed to perform operations / functions concurrently and / or serially. Furthermore, in some examples, Figures 1-5 and / or Figures 9-19 Some or all of the circuit modules in the circuit module can be Figure 23 One or more virtual machines and / or containers are implemented and executed on the microprocessor 2300.

[0212] In some examples, Figure 22The programmable circuit module 2212 can be in one or more packages. For example, Figure 23 microprocessor 2300 and / or Figure 24 The FPGA circuit module 2400 can be housed in one or more packages. In some examples, the XPU can be comprised of components that can be housed in one or more packages. Figure 22 This is achieved using a programmable circuit module 2212. For example, the XPU may include a CPU (e.g., ...) in a package. Figure 23 microprocessor 2300, Figure 24 CPU2420, etc.), and include a DSP (e.g., in another package) Figure 24 The DSP2422), in another package includes a GPU, and in yet another package includes an FPGA (e.g., Figure 24 FPGA circuit module 2400).

[0213] The diagram is used to represent, for example, Figure 22 A block diagram of an example software distribution platform 2505, which distributes example machine-readable instructions 2232 to other hardware devices (e.g., hardware devices owned and / or operated by a third party from the owner and / or operator of the software distribution platform), is shown in [the diagram]. Figure 25 The example software distribution platform 2505 can be implemented by any computer server, data facility, cloud service, etc., capable of storing software and delivering it to other computing devices. A third party can be a customer of the entity that owns and / or operates the software distribution platform 2505. For example, the entity owning and / or operating the software distribution platform 2505 could be, for example, a customer of, the entity that owns and / or operates the software distribution platform 2505. Figure 22 The example machine-readable instructions 2232 pertain to the software's developer, seller, and / or licensor. Third parties may be consumers, users, retailers, OEMs, etc., who purchase and / or license the software for use and / or resell and / or sublicense. In the illustrated example, the software distribution platform 2505 includes one or more servers and one or more storage devices. As described above, the storage devices store the machine-readable instructions 2232, which may correspond to... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21Example machine-readable instructions. One or more servers of the example software distribution platform 2505 communicate with the example network 2510, which may correspond to any one or more of the Internet and / or any example networks described above. In some examples, as part of a business transaction, one or more servers respond to a request to deliver software to a requesting party. Payment for the delivery, sale, and / or licensing of the software may be handled by one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable purchasers and / or licensors to download machine-readable instructions 2232 from the software distribution platform 2505. For example, it may correspond to... Figure 6 , Figure 7 , Figure 8 , Figure 20 and / or Figure 21 Software with example machine-readable instructions can be downloaded to example programmable circuit module platform 2200, which executes machine-readable instructions 2232 to implement example TSM circuit 108, example CDSM circuit 114, example RoT DCC circuit 120, and / or example FMS circuit 902. In some examples, one or more servers of software distribution platform 2505 periodically provide software, deliver software, and / or force software updates (e.g., Figure 22 Example machine-readable instructions (2232) are used to ensure that improvements, patches, updates, etc., are distributed and applied to the software at the end-user device. Although referred to as software above, distributed “software” can alternatively be firmware.

[0214] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any kind of claim statement, it is understood that additional elements, terms, etc., may exist that do not fall outside the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term in, for example, the preamble of a claim, it is open-ended in the same way that the terms "comprising" and "including" are open-ended. When used, for example, in the form of A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, articles, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, articles, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" is intended to refer to an implementation that includes any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0215] As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude plurals. As used herein, the term “a” or “an” refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although listed separately, multiple parts, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these may be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0216] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and joining) may include intermediate components between elements referenced by the connection reference and / or relative movement between those elements. In this way, a connection reference does not necessarily imply that two elements are directly connected and / or in a fixed relationship with each other.

[0217] Unless otherwise specifically stated, descriptors such as “first,” “second,” “third,” etc., used herein are not intended to indicate any meaning of priority, physical order, arrangement in a list, and / or any sorting, but are merely used as labels and / or arbitrary names to distinguish elements for the purpose of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in a detailed description, while different descriptors such as “second” or “third” may be used in the claims to refer to the same element. In such instances, it should be understood that such descriptors are used only to clearly identify those elements within the context of the discussion (e.g., within the claims), where said elements may otherwise share the same name, for example.

[0218] As used herein, the phrase “in communication” (including its variations) includes direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but rather includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals and / or one-off events.

[0219] As used herein, a “programmable circuit module” is defined to include: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) configured to perform one or more specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based circuits programmable with instructions for performing one or more specific functions and / or one or more specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit modules include programmable microprocessors (such as a central processing unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) whose configuration and / or construction can be programmed with a second instruction to executor one or more operations and / or functions corresponding to the first instruction; a graphics processing unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP) capable of executing a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); and one or more microcontrollers and / or integrated circuits (such as application-specific integrated circuits (ASICs)) capable of executing a first instruction to perform one or more operations and / or functions. For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuit modules (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and orchestration techniques (e.g., one or more application programming interfaces (APIs)) that can assign one or more computing tasks to any one or more of the multiple types of programmable circuit modules suitable for performing the computing tasks.

[0220] As used herein, an integrated circuit / circuit module is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit module, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0221] As will be understood from the foregoing, example systems, devices, artifacts, and / or methods have been disclosed that utilize chiplets, tiles, and / or dies to identify, authenticate, and establish one or more keys for secure computation in multi-chiplet, multi-accelerator packages of AI processors, accelerators, and / or I / O devices. For example, the disclosed methods, devices, and / or artifacts enable secure workloads and, more specifically, enable AI and converter models at the edge. The examples disclosed herein deliver security to allow tenants to deploy AI models and data at the edge using AI accelerators.

[0222] Therefore, example systems, devices, articles of art, and / or methods have been disclosed that improve the security, confidentiality, and / or privacy of edge processor units (which allows for the deployment of AI workloads at the edge with the assurance that the AI ​​workloads will remain secure). The disclosed systems, devices, articles of art, and / or methods improve the operation of computing devices by increasing security in multi-chip, multi-die, and / or multi-watt block SiPs, thereby mitigating the risk of the computer being compromised. Therefore, the disclosed systems, devices, articles of art, and / or methods address one or more improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

[0223] Furthermore, the examples disclosed herein include processor architectures for delivering AI-based secure, intelligent, and self-healing services to edge platforms. The examples disclosed herein provide consistent and ubiquitous cluster management across edge deployments. Additionally, the examples disclosed herein protect edge deployments. Example systems, devices, artifacts, and / or methods that improve the security, visibility, and capability of remotely managing edge deployments have been disclosed. The disclosed systems, devices, artifacts, and / or methods improve the remote manageability of edge processor units. Therefore, the disclosed systems, devices, artifacts, and / or methods represent one or more improvements to the operation of machines such as computers or other electronic and / or mechanical devices.

[0224] This document discloses example methods, apparatuses, systems, and artifacts for secure computing management in multi-chiplet, multi-accelerator packages. Further examples and combinations thereof include the following:

[0225] Example 1 includes a system in a multi-die package (SiP) comprising: a first die including circuitry; and a second die for authenticating the circuitry to allow secure communication within the SiP.

[0226] Example 2 includes the SiP according to Example 1, wherein the first die includes a first interface circuit, and the SiP includes a third die, the third die including: at least one processor circuit for providing at least one Trusted Execution Environment (TEE); and a second interface circuit for sending a request to the first interface circuit for initiating a secure communication session between the circuit and the at least one TEE.

[0227] Example 3 includes the SiP according to Example 1, wherein the first die includes a first interface circuit, the second die includes a second interface circuit, and the first interface circuit is configured to add a header to a request from a third die and forward the request to the second interface circuit, the request being used to initiate a secure communication session with the circuit.

[0228] Example 4 includes a SiP according to any one of Examples 1, 2, or 3, wherein the second die includes a SiP security circuitry configured to: create a cryptographic identifier for the circuitry; and provide the cryptographic identifier to at least one processor circuitry based on a request to initiate a secure communication session with the circuitry, in order to authenticate the circuitry to the at least one processor circuitry.

[0229] Example 5 includes a SiP according to Example 1, wherein the first die includes a first interface circuit, the second die includes a second interface circuit, the SiP includes a third die, the third die includes at least one processor circuit and a third interface circuit, and the first interface circuit is used to forward communication between the second interface circuit and the third interface circuit, the communication involving the identification and authentication of the circuit.

[0230] Example 6 includes a SiP according to any one of Examples 1, 2, 3 or 5, wherein the first die includes a device security management (DSM) circuit, and the second die includes a SiP security circuit, the SiP security circuit being configured to: provide the DSM circuit with a key for a secure communication session between the circuit and at least one processor circuit after authentication of the circuit; delete the key from the SiP security circuit; and maintain a session record of the secure communication session.

[0231] Example 7 includes a SiP according to any one of Examples 1, 2, 3, 4, 5, or 6, further including a Cluster Management System (FMS) circuit, the FMS circuit comprising: a plurality of interface circuits for enabling the FMS circuit to be discovered by any die of the SiP, at least one of the plurality of interface circuits for communicating with at least one die of the SiP; machine-readable instructions; and one or more circuits for being programmed by the machine-readable instructions to deliver secure cluster management services in the SiP based on a configuration profile corresponding to the at least one die.

[0232] Example 8 includes a non-transitory computer-readable medium comprising instructions for causing one or more circuits of a first die of a system in a package (SiP) to authenticate circuits of a second die of the SiP to allow secure communication within the SiP.

[0233] Example 9 includes a non-transitory computer-readable medium according to Example 8, wherein the second die includes device security management (DSM) circuitry, and the instructions cause at least one of the one or more circuits to mutually authenticate with the DSM circuitry.

[0234] Example 10 includes a non-transitory computer-readable medium according to Example 8, wherein the second die includes device security management (DSM) circuitry, and the instructions cause at least one of the one or more circuits to generate an identifier certificate for the DSM circuitry and a public key / private key pair for the DSM circuitry.

[0235] Example 11 includes a non-transitory computer-readable medium according to Example 8, wherein the SiP includes a third die including at least one processor circuit, the second die includes device security management (DSM) circuitry, and the instructions cause at least one of the one or more circuits to derive a session key for the secure communication session based on a request received from the DSM circuitry for establishing a secure communication session between the at least one processor circuit and the circuitry, the request being generated by the at least one processor circuit.

[0236] Example 12 includes a non-transitory computer-readable medium according to any one of Examples 8, 9, 10, or 11, wherein the instructions cause at least one of the one or more circuits to collect at least one of a hash of a firmware image of the circuit or a security version number of the circuit.

[0237] Example 13 includes a non-transitory computer-readable medium according to any one of Examples 8 or 12, wherein the second die includes device security management (DSM) circuitry, and the instructions cause at least one of the one or more circuits to: provide the DSM circuitry with a key for a secure communication session between the circuitry and at least one processor circuitry after authentication of the circuitry; delete the key from the first die; and maintain a session record of the secure communication session.

[0238] Example 14 includes a non-transitory computer-readable medium according to any one of Examples 8, 9, 10, 11, 12, or 13, wherein the instructions cause at least one of the one or more circuits to: identify at least one means for establishing a secure communication session with the SiP on behalf of the SiP, the at least one means being external to the SiP; and, after authenticating the Cluster Management System (FMS) of the SiP with the at least one means, access a configuration profile of the FMS corresponding to a tenant of the SiP from the at least one means.

[0239] Example 15 includes a first semiconductor die of a system in a package (SiP), the first semiconductor die comprising: at least one interface circuit; machine-readable instructions; and one or more circuits configured to be programmed by the machine-readable instructions to authenticate circuitry of a second semiconductor die of the SiP, thereby enabling secure communication within the SiP.

[0240] Example 16 includes a first semiconductor die according to Example 15, wherein the second semiconductor die includes device security management (DSM) circuitry, and at least one of the one or more circuits is used for mutual authentication with the DSM circuitry.

[0241] Example 17 includes a first semiconductor die according to Example 15, wherein the second semiconductor die includes a device security management (DSM) circuit, and at least one of the one or more circuits is used to generate an identifier certificate for the DSM circuit and a public key / private key pair for the DSM circuit.

[0242] Example 18 includes a first semiconductor die according to Example 15, wherein the SiP includes a third semiconductor die, the third die including at least one processor circuit, the second semiconductor die including device security management (DSM) circuitry, and at least one of the one or more circuits is configured to derive a session key for the secure communication session based on a request received from the DSM circuitry for establishing a secure communication session between at least one processor circuit and the circuitry, the request being generated by the at least one processor circuit.

[0243] Example 19 includes a first semiconductor die according to Example 15, wherein the second semiconductor die includes device security management (DSM) circuitry, and at least one of the one or more circuits is configured to: provide the DSM circuitry with a key for a secure communication session between the circuitry and at least one processor circuitry after authentication of the circuitry; delete the key from the first semiconductor die; and maintain a session record of the secure communication session.

[0244] Example 20 includes a first semiconductor die according to any one of Examples 15, 16, 17, 18 or 19, wherein at least one of the one or more circuits is used for: identifying at least one device on behalf of the SiP and establishing a secure communication session with it, the at least one device being external to the SiP; and accessing a configuration profile of the FMS corresponding to a tenant of the SiP from the at least one device after authenticating the Cluster Management System (FMS) of the SiP with the at least one device.

[0245] The appended claims are hereby incorporated by reference into this specific embodiment. Although certain example systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles of manufacture, and methods that fall fully within the scope of the claims of this patent.

Claims

1. A system-in-package (SiP) in a multi-die package, the SiP comprising: a first die, the first die comprising a circuit; and a second die, the second die to authenticate the circuit to permit secure communication within the SiP.

2. The SiP of claim 1, wherein, the first die comprises a first interface circuit, and the SiP comprises a third die, the third die comprising: at least one processor circuit to provide at least one trusted execution environment (TEE); and a second interface circuit to send a request to the first interface circuit, the request to initiate a secure communication session between the circuit and the at least one TEE.

3. The SiP of any one of claims 1 or 2, wherein, the first die comprises a first interface circuit, the second die comprises a second interface circuit, and the first interface circuit to add a header to a request from a third die and forward the request to the second interface circuit, the request to initiate a secure communication session with the circuit.

4. The SiP of any one of claims 1 or 2, wherein, the second die comprises a SiP security circuit to: create a cryptographic identity for the circuit; and provide the cryptographic identity to the at least one processor circuit to authenticate the circuit to the at least one processor circuit based on a request to initiate a secure communication session with the circuit.

5. The SiP of claim 1, wherein, the first die comprises a first interface circuit, the second die comprises a second interface circuit, the SiP comprises a third die, the third die comprising at least one processor circuit and a third interface circuit, and the first interface circuit to forward communications between the second interface circuit and the third interface circuit, the communications involving an identity and authentication of the circuit.

6. The SiP of any one of claims 1, 2, or 5, wherein, the first die comprises a device security management (DSM) circuit, and the second die comprises a SiP security circuit to: provide a key for a secure communication session between the circuit and at least one processor circuit to the DSM circuit after authentication of the circuit; delete the key from the SiP security circuit; and maintain a session record of the secure communication session.

7. The SiP of any one of claims 1, 2, or 5, further comprising a fleet management system (FMS) circuit, the fleet management system (FMS) circuit comprising: a plurality of interface circuits to enable the FMS circuit to be discovered by any die of the SiP, at least one of the plurality of interface circuits to communicate with at least one die of the SiP; machine-readable instructions; and one or more circuits to be programmed by the machine-readable instructions to deliver secure fleet management services in the SiP based on a configuration profile corresponding to the at least one die.

8. A computer-readable medium comprising instructions to cause one or more circuits of a first die of a system-in-package (SiP) to authenticate a circuit of a second die of the SiP to permit secure communication within the SiP.

9. The computer readable medium of claim 8, wherein, the second die includes a device security management (DSM) circuit, and the instructions cause at least one of the one or more circuits to mutually authenticate with the DSM circuit.

10. The computer-readable medium of any one of claims 8 or 9, wherein, the second die includes a device security management (DSM) circuit, and the instructions cause at least one of the one or more circuits to generate an identifier certificate for the DSM circuit and a public-private key pair for the DSM circuit.

11. The computer-readable medium of any one of claims 8 or 9, wherein, the SiP includes a third die that includes at least one processor circuit, the second die includes a device security management (DSM) circuit, and the instructions cause at least one of the one or more circuits to, based on receiving a request from the DSM circuit to establish a secure communication session between the at least one processor circuit and the circuit, derive a session key for the secure communication session, the request being generated by the at least one processor circuit.

12. The computer readable medium of claim 8, wherein, the instructions cause at least one of the one or more circuits to collect at least one of a hash of a firmware image of the circuit or a security version number of the circuit.

13. The computer-readable medium of any one of claims 8, 9, or 12, wherein, the second die includes a device security management (DSM) circuit, and the instructions cause at least one of the one or more circuits to: provide the DSM circuit with a key for a secure communication session between the circuit and at least one processor circuit after authentication of the circuit; delete the key from the first die; and maintain a session record of the secure communication session.

14. The computer-readable medium of any one of claims 8, 9, or 12, wherein, the instructions cause at least one of the one or more circuits to: identify at least one device with which to establish a secure communication session on behalf of the SiP, the at least one device being external to the SiP; and after authenticating the SiP with a fleet management system (FMS) of the at least one device, access a configuration profile of the FMS from the at least one device, the configuration profile corresponding to a tenant of the SiP.

15. A first semiconductor die of a system-in-package (SiP), the first semiconductor die comprising: at least one interface circuit; machine-readable instructions; and one or more circuits for programming by the machine-readable instructions to authenticate a circuit of a second semiconductor die of the SiP, thereby permitting secure communication within the SiP.

16. The first semiconductor die of claim 15, wherein, the second semiconductor die includes a device security management (DSM) circuit, and at least one of the one or more circuits is to mutually authenticate with the DSM circuit.

17. The first semiconductor die of any one of claims 15 or 16, wherein, the second semiconductor die includes a device security management (DSM) circuit, and at least one of the one or more circuits is to generate an identifier certificate for the DSM circuit and a public-private key pair for the DSM circuit.

18. The first semiconductor die of any one of claims 15 or 16, wherein, The SiP includes a third semiconductor die including at least one processor circuit, the second semiconductor die includes a device security management (DSM) circuit, and at least one of the one or more circuits is to derive a session key for a secure communication session between the at least one processor circuit and the circuit based on receiving a request from the DSM circuit for establishing the secure communication session, the request generated by the at least one processor circuit.

19. The first semiconductor die of claim 15, wherein, The second semiconductor die includes a device security management (DSM) circuit, and at least one of the one or more circuits is to: provide the DSM circuit with a key for a secure communication session between the circuit and at least one processor circuit after authentication of the circuit; delete the key from the first semiconductor die; and maintain a session record of the secure communication session.

20. The first semiconductor die of any one of claims 15, 16, or 19, wherein, At least one of the one or more circuits is to: identify, on behalf of the SiP, at least one device with which to establish a secure communication session, the at least one device external to the SiP; and access, from the at least one device, a configuration profile of a fleet management system (FMS) of the at least one device after authentication of the SiP with the FMS, the configuration profile corresponding to a tenant of the SiP.

21. A method performed by the SiP of any one of claims 1, 2, 3, 4, 5, 6, or 7.

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