Display device

Abstract

The present disclosure relates to a display device including: a plurality of pixels connected to scan lines and data lines; a data driving circuit that outputs data signals to the pixels via the data lines; a scan driving circuit sequentially activating at least some of the pixels according to the data signal via the scan line; and a drive controller that controls the two circuits. The display panel includes a first display area having first pixels and a second display area having second pixels. The scan driving circuit activates the two display areas at a first scan rate in a first operation mode and activates the second display area at a second scan rate in a second operation mode, where the second scan rate is lower than the first scan rate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0121467, filed on September 6, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and more specifically, to display devices capable of segmenting and driving display areas. Background Technology

[0004] Display devices provide information to users by displaying various images on a screen. Typically, display devices operate within a defined screen area called the display area, which displays the visual content. Modern display devices are evolving to incorporate multiple display areas, thereby achieving greater functionality. For example, some display devices are designed to display images not only on the front surface but also include a rear display area, allowing images to be displayed on both sides. This multi-display configuration improves the utilization and versatility of the display device.

[0005] In recent years, flexible display devices with bendable display panels have been introduced. Unlike traditional flat panel displays, these flexible display devices can be folded, rolled, or bent, providing increased portability and adaptability beyond the limitations of conventional screen sizes. This flexibility improves user convenience by making devices more compact and versatile. Furthermore, integrating multiple display areas with flexible display panels further expands the device's functionality. For example, when unfolded, the display device can present images on both the front and back surfaces, and when folded, it can confine the image display to the rear display area, thus providing users with additional ways to interact with content and improving overall usability. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display device capable of segmenting and driving multiple display areas. Furthermore, embodiments of this disclosure can provide a display device that reduces power consumption in environments where some of multiple display areas are driven.

[0007] According to embodiments of this disclosure, a display device includes: a plurality of scan lines; a plurality of data lines; a display panel including a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; a data driving circuit configured to output a plurality of data signals to the plurality of pixels via the plurality of data lines; a scan driving circuit configured to sequentially activate at least some of the plurality of pixels according to the data signals via the plurality of scan lines; and a driving controller configured to control the data driving circuit and the scan driving circuit. The display panel includes a first display area in which a first pixel of the plurality of pixels is disposed and a second display area in which a second pixel of the plurality of pixels is disposed. The scan driving circuit is configured to activate the first display area and the second display area at a first scan rate in a first operating mode, and to activate the second display area at a second scan rate in a second operating mode. The second scan rate is lower than the first scan rate.

[0008] In one implementation, the drive controller is configured to output a first clock signal to the scan drive circuit in a first operating mode and to output a second clock signal to the scan drive circuit in a second operating mode, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal.

[0009] In this implementation, the rate at which the frequency of the second clock signal decreases relative to the frequency of the first clock signal is equal to the rate at which the second scan rate decreases relative to the first scan rate.

[0010] In one embodiment, the scan driving circuit is configured to output a first scan signal with a first pulse width to a plurality of scan lines in a first operating mode to activate a first display area and a second display area, and to output a second scan signal with a second pulse width to a scan line among the plurality of scan lines connected to a second pixel in a second operating mode to activate a second display area, wherein the first pulse width is less than the second pulse width.

[0011] In the implementation, the scanning time for the scanning driving circuit to activate the first display area and the second display area in the first operating mode is equal to the scanning time for the scanning driving circuit to activate the second display area in the second operating mode.

[0012] In this implementation, the lower second scan rate than the first scan rate corresponds to the ratio of the number of second pixels to the number of multiple pixels.

[0013] In one embodiment, the scan drive circuit is configured to sequentially activate the second display area in response to a start signal indicating the start of an indicator frame in a second operating mode, deactivate the first display area in response to a mask signal indicating the completion of activation of the second display area, and reactivate the second display area.

[0014] In one implementation, the drive controller is configured to provide a start signal to the scan drive circuit when the first display area is deactivated in response to a masking signal.

[0015] In one implementation, the drive controller is configured to: in a first operating mode, during the entire period of time used to activate multiple scan lines, provide a first image data signal corresponding to a first display area and a second display area of ​​a frame to the data drive circuit; and in a second operating mode, during the entire period of time used to activate multiple scan lines, provide a second image data signal corresponding to a second display area of ​​multiple frames to the data drive circuit.

[0016] In one implementation, the scan drive circuit is configured to sequentially activate a second pixel in a second display area line by line in a first operating mode before sequentially activating a first pixel in a first display area line by line.

[0017] According to embodiments of this disclosure, a display device includes: a plurality of scan lines; a plurality of data lines; a display panel including a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; a data driving circuit configured to output a plurality of data signals to the plurality of pixels via the plurality of data lines; a scan driving circuit configured to activate at least some of the plurality of pixels according to the data signals via the plurality of scan lines; and a driving controller configured to control the data driving circuit and the scan driving circuit based on an image signal and a synchronization signal. The display panel includes a first display area in which a first pixel of the plurality of pixels is disposed and a second display area in which a second pixel of the plurality of pixels is disposed. The data driving circuit is configured to: in a first operating mode, output data signals corresponding to the first display area and the second display area of ​​a frame during a frame segment defined by a synchronization signal to the display panel; and in a second operating mode, output data signals corresponding to the second display area of ​​a plurality of subframes to the display panel during a frame segment.

[0018] In one implementation, the drive controller is configured to output a start signal to the scan drive circuit in a second operating mode, and the start signal indicates the start of each of the plurality of subframes during a frame segment.

[0019] In the implementation, the frame segment in the first operation mode lasts for a first duration, and the frame segment in the second operation mode lasts for a second duration, and the second duration is longer than the first duration.

[0020] In one embodiment, the data driving circuit is configured to output a data signal corresponding to a second display area of ​​one of a plurality of subframes to the display panel during a first duration in a second operating mode.

[0021] In one implementation, the drive controller is configured to output a first clock signal to the data drive circuit in a first operating mode and to output a second clock signal to the data drive circuit in a second operating mode, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal.

[0022] According to embodiments of this disclosure, an electronic device includes: a processor; a memory having stored application programs for execution by the processor; and a display device. The display device includes: a plurality of scan lines; a plurality of data lines; a display panel including a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; a data driving circuit configured to output a plurality of data signals to the plurality of pixels via the plurality of data lines; a scan driving circuit configured to sequentially activate at least some of the plurality of pixels according to the data signals via the plurality of scan lines; and a drive controller configured to control the data driving circuit and the scan driving circuit. The display panel includes a first display area in which a first pixel of the plurality of pixels is disposed and a second display area in which a second pixel of the plurality of pixels is disposed. The scan driving circuit is configured to activate the first display area and the second display area at a first scan rate in a first operating mode, and to activate the second display area at a second scan rate in a second operating mode, wherein the second scan rate is lower than the first scan rate. The electronic device further includes: a user interface configured to sense user input by selecting an icon presented on the display panel via touch or a cursor, wherein the processor executes one or more of the stored application programs upon receiving user input.

[0023] In this implementation, the stored applications include one or more of camera applications, audio-visual streaming applications, and telephone applications.

[0024] In one implementation, the user interface is a touch screen embedded in a display panel, wherein the touch screen includes touch sensors for sensing the user's touch or click.

[0025] In one implementation, the user interface includes an audio sensor embedded in a display panel, wherein the audio sensor is configured to receive voice commands to induce access to one or more applications.

[0026] In one implementation, the user interface includes sensors mounted in the display panel for sensing eye movements.

[0027] According to embodiments of this disclosure, a display device includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel may have a first non-folding region, a second non-folding region, and a folded region between the first and second non-folding regions, and may include a plurality of pixels connected to a plurality of scan lines and a plurality of data lines. The data driving circuit may be configured to output data signals to the plurality of pixels via the plurality of data lines. The scan driving circuit may be configured to sequentially activate pixels based on data signals via the plurality of scan lines to display an image. The drive controller may be configured to control the data driving circuit and the scan driving circuit. A first display area corresponding to a first pixel among the plurality of pixels and a second display area corresponding to a second pixel among the plurality of pixels are defined in the display panel. The first display area may overlap with the first non-folding region, the second non-folding region, and the folded region, and the second display area may overlap with the first non-folding region. The scan driving circuit may be configured to activate the first and second display areas at a first scan rate when the display panel is unfolded, and to activate the second display area at a second scan rate lower than the first scan rate when the display panel is folded.

[0028] In one embodiment, the first display area and the second display area may be arranged to face each other on a plane in the first non-folded area.

[0029] In this implementation, the first display area and the second display area may not overlap each other on a plane.

[0030] In this implementation, the first display area and the second display area may be spaced apart from each other, but the first pixel and the second pixel may be connected to each other through multiple data lines.

[0031] In this implementation, the area of ​​the first display area may be larger than the area of ​​the second display area.

[0032] According to embodiments of this disclosure, an electronic device may include a display device, which includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel may include a plurality of pixels connected to a plurality of scan lines and a plurality of data lines. The data driving circuit may be configured to output data signals to the plurality of pixels via the plurality of data lines. The scan driving circuit may be configured to sequentially activate pixels via the plurality of scan lines according to the data signals to display an image. The drive controller may be configured to control the data driving circuit and the scan driving circuit. A first display area corresponding to a first pixel among the plurality of pixels and a second display area corresponding to a second pixel among the plurality of pixels may be defined in the display panel. The scan driving circuit may be configured to activate the first and second display areas at a first scan rate in a first operating mode, and to activate the second display area at a second scan rate in a second operating mode, the second scan rate being slower than the first scan rate.

[0033] According to embodiments of this disclosure, an electronic device may include a display device, which includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel may include a plurality of pixels connected to a plurality of scan lines and a plurality of data lines. The data driving circuit may be configured to output data signals to the plurality of pixels via the plurality of data lines. The scan driving circuit may be configured to sequentially activate pixels via the plurality of scan lines to display an image corresponding to the data signals. The drive controller may be configured to control the data driving circuit and the scan driving circuit based on an image signal and a synchronization signal. A first display area corresponding to a first pixel among the plurality of pixels and a second display area corresponding to a second pixel among the plurality of pixels may be defined in the display panel. The data driving circuit may be configured to: in a first operating mode, output data signals corresponding to the first and second display areas of a frame to the display panel during a frame segment defined by the synchronization signal; and in a second operating mode, output data signals corresponding to the second display areas of a plurality of subframes to the display panel during a frame segment.

[0034] According to embodiments of this disclosure, an electronic device may include a display device, which includes a display panel, a data driving circuit, a scan driving circuit, and a drive controller. The display panel may have a first non-folding region, a second non-folding region, and a folded region between the first and second non-folding regions, and may include a plurality of pixels connected to a plurality of scan lines and a plurality of data lines. The data driving circuit may be configured to output data signals to the plurality of pixels via the plurality of data lines. The scan driving circuit may be configured to sequentially activate pixels based on data signals via the plurality of scan lines to display an image. The drive controller may be configured to control the data driving circuit and the scan driving circuit. A first display area corresponding to a first pixel among the plurality of pixels and a second display area corresponding to a second pixel among the plurality of pixels are defined in the display panel. The first display area may overlap with the first non-folding region, the second non-folding region, and the folded region, and the second display area may overlap with the first non-folding region. The scan driving circuit may be configured to activate the first and second display areas at a first scan rate when the display panel is unfolded, and to activate the second display area at a second scan rate slower than the first scan rate when the display panel is folded.

[0035] According to embodiments of this disclosure, by centrally configuring multiple subframes in a specific display area during the duration of a frame, it is possible to prevent unnecessary images from being driven when only some of the multiple display areas are driven.

[0036] Furthermore, according to embodiments of this disclosure, by reducing the clock frequency, when driving some of the multiple display areas in a concentrated manner with multiple subframes, power consumption can be reduced while maintaining the operating speed of the display device. Attached Figure Description

[0037] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1A and Figure 1B This is a perspective view of a display device according to an embodiment of the present disclosure; Figure 2 It is along Figure 1A An exemplary cross-sectional view of a display device with line I-I'; Figure 3 yes Figure 2 An exemplary plan view of the display device in its unfolded state; Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure; Figure 5 yes Figure 4 An exemplary equivalent circuit diagram of the pixels shown; Figure 6 It is shown Figure 5 The timing diagram of the operations of the pixels shown; Figure 7 yes Figure 4 An exemplary block diagram of the scan drive circuit shown; Figure 8 yes Figure 7 An exemplary equivalent circuit diagram of the driver stage shown; Figure 9 It is shown Figure 8 The timing diagram of the driver-level operation is shown below; Figure 10 It is shown that in the first operating mode, by Figure 4 The timing diagram of the scan control signals and image data signals provided by the drive controller is shown. Figure 11 It is used to describe according to the first operating mode Figure 4 A diagram showing the data signal output of the display device shown; Figure 12 It is shown that in the first operating mode, by Figure 4 The timing diagram of the scan signal output by the scan drive circuit shown is shown. Figure 13 This is shown as being operated in the second mode by Figure 4 The timing diagram of the scan control signals and image data signals provided by the drive controller is shown. Figure 14It is used to describe according to the second operating mode Figure 4 A diagram showing the data signal output of the display device shown; Figure 15 It is shown in the second operating mode from Figure 4 The timing diagram of the scan signal output by the scan drive circuit shown is shown. Figure 16 yes Figure 4 An exemplary block diagram of the driver integrated circuit shown; Figure 17A and Figure 17B This is a perspective view of a display device according to an embodiment of the present disclosure; Figure 18 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and Figure 19 A schematic diagram of an electronic device according to one or more embodiments is shown. Detailed Implementation

[0038] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. The same reference numerals may denote the same elements throughout the drawings.

[0039] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0040] It should be understood that the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

[0041] As used in this article, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] A singular term may include a plural form unless the context clearly indicates otherwise.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of..." follows a list of elements, it modifies the entire list of elements, not individual elements within the list.

[0044] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to also encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both above and below orientations.

[0045] It will be understood that when a component is referred to as being "on," "connected to," "linked to," or "adjacent to" another component, it can be directly on, directly connected to, directly linked to, or directly adjacent to the other component, or there can be intervening components. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there can be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering the other component, or one or more intervening components can also cover the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0046] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the value and mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. For example, “about” or “approximately” may mean within one or more standard deviations, or, for example, within ±30%, ±20%, ±10%, or ±5% of the value.

[0047] Expressions such as “comprising” or “including” are intended to indicate a characteristic, quantity, step, operation, element, part or combination thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, parts or combinations thereof.

[0048] Embodiments of this application provide a display device that improves power consumption and display efficiency by selectively driving certain display areas while preventing unnecessary image driving. This can be achieved by configuring multiple subframes within a specific display area during a single frame duration. By doing so, the embodiment allows only the necessary portions of the display to be actively updated, which reduces overall processing and power requirements.

[0049] Embodiments of this application provide a method for controlling display operation in a partial operating mode. For example, when operating in this mode, the drive controller can reduce the clock frequency, while the scan drive circuit can activate only specific display areas at a lower scan rate. Simultaneously, the data drive circuit can use multiple subframes within a defined frame segment to output data signals for that specific display area. This coordinated approach allows for efficient image rendering while maintaining the operating speed of the display device and reducing power consumption, including, for example, in foldable or multi-area display configurations.

[0050] By implementing the above technologies, the embodiments of this application can improve the usability of modern display devices, including, for example, display devices comprising multiple display areas, such as foldable or double-sided displays. The ability to dynamically adjust the scan rate and clock frequency in partial operating modes provides improvements in power management, thereby making the display device more energy-efficient without sacrificing image quality or responsiveness.

[0051] Figure 1A and Figure 1B This is a perspective view of a display device according to an embodiment of the present disclosure. Figure 1A The expanded state of the display device DD is shown, while Figure 1B The folded state of the display device DD is shown.

[0052] The display device DD can be, for example, but not limited to, a mobile phone. For instance, the display device DD can be used in various portable electronic devices, such as tablet PCs, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), or gaming devices. Additionally, the display device DD can be used in various electronic devices, including, for example, televisions, personal computers, laptops, and kiosks.

[0053] refer to Figure 1A The display device DD includes a first display area DA1 and a non-display area NDA. The display device DD can be configured to display an image in the first display area DA1. In its unfolded state, the first display area DA1 may have a display surface parallel to a plane defined by a first direction DR1 and a second direction DR2. The first display area DA1 is configured to display an image on a third direction DR3 perpendicular to the display surface and corresponding to the thickness direction of the display device DD. The non-display area NDA is adjacent to the first display area DA1 (e.g., surrounding the first display area DA1) and may provide a boundary portion of the display device DD. The non-display area NDA may be printed in a predetermined color. The non-display area NDA may be defined as a border area.

[0054] The display device DD may include a folded region FDA and multiple non-folded regions NFA1 and NFA2. The folded region FDA may be disposed between a first non-folded region NFA1 and a second non-folded region NFA2. The folded region FDA, the first non-folded region NFA1, and the second non-folded region NFA2 may be arranged along a second direction DR2. In a plan view, a first display area DA1 may overlap with the folded region FDA, the first non-folded region NFA1, and the second non-folded region NFA2.

[0055] refer to Figure 1B When the folding region FDA bends, the display device DD can be folded. The folding region FDA can be folded around the folding axis FX, in which case the first non-folding region NFA1 and the second non-folding region NFA2 can face each other along the third direction DR3. When the display device DD is folded, it can fold inward, so that the display surface remains hidden.

[0056] The display device DD includes a second display area DA2 and a non-display area NDA. The display device DD can also be configured to display images through the second display area DA2. In the folded state of the display device DD, the second display area DA2 may have a display surface parallel to the plane defined by the first direction DR1 and the second direction DR2. The display device DD can also display images through the second display area DA2. The non-display area NDA may be positioned adjacent to the second display area DA2 (e.g., surrounding the second display area DA2). In a plan view, the second display area DA2 may overlap with the first non-folded area NFA1.

[0057] In the unfolded state, a first display area DA1 is formed on the front surface of the display device DD, and a second display area DA2 is formed on the rear surface of the display device DD. The first display area DA1 and the second display area DA2 can overlap at the first non-folded area NFA1. In the unfolded state, since both the first display area DA1 and the second display area DA2 are visible, they can display images simultaneously. In the folded state, since the first display area DA1 is invisible, only the second display area DA2 can display images. This will be described in more detail below.

[0058] Figure 2 It corresponds to Figure 1A An exemplary cross-sectional view of a display device with line I-I'.

[0059] refer to Figure 2The display device DD may include a display panel DP, windows WD1, WD2, and a driver integrated circuit IC. It should be understood that the components included in the display device DD are simplified to focus on the display panel DP, and additional components included in the display device DD are not shown. For example, the display device DD may also include a housing for housing the display panel DP, a touch panel for providing user input, and an application processor configured to supply image signals and control signals to the driver integrated circuit IC.

[0060] The display panel DP may include curved regions BA1 and BA2 and a non-curved region NBA. The non-curved region NBA may overlap with the first display region DA1 and the second display region DA2. A first window WD1 is disposed on the display panel DP to cover the first display region DA1. A second window WD2 is disposed on the display panel DP to cover the second display region DA2. The first window WD1 and the second window WD2 may also extend in the first direction DR1 and the second direction DR2 to cover the non-display region NDA of the display panel DP.

[0061] The first curved region BA1 can be curved at a predetermined curvature between the first display region DA1 and the second display region DA2. Therefore, a single display panel DP can be used to form both the first display region DA1 in front of the display device DD and the second display region DA2 in front of the display device DD. The first display region DA1 and the second display region DA2 can be driven together by a driver integrated circuit IC.

[0062] The second curved region BA2 can be curved at a predetermined curvature, such that the driver integrated circuit IC is positioned behind the display device DD. The driver integrated circuit IC can be arranged to overlap with the non-curved region NBA at one end of the display panel DP that extends further from the second curved region BA2. The driver integrated circuit IC is configured to drive the display panel DP such that the first display area DA1 and the second display area DA2 display images, as will be described in more detail below.

[0063] Figure 3 yes Figure 2 An exemplary plan view of a display device is shown, illustrating a display device with a curved area unfolded.

[0064] refer to Figure 3 The display device DD may include a display panel DP, windows WD1, WD2 and a driver integrated circuit IC. Figure 3 The display panel DP, windows WD1, WD2, and driver integrated circuit IC shown correspond to respectively Figure 2 The display panel DP, windows WD1, WD2, and driver integrated circuit IC are included. It should be understood that... Figure 3 The planar diagram is an unfolded representation of the first curved region BA1 and the second curved region BA2. Figure 2 A floor plan of the display panel (DP) in the image.

[0065] The display panel DP may include multiple data lines DL1 to DLm and multiple pixels PX, where m is a positive integer. Pixels PX are electrically connected to the data lines DL1 to DLm, respectively. Pixels PX can be configured to receive data signals for displaying images from a driver integrated circuit IC via the data lines DL1 to DLm. Some of the pixels PX may be located in a first display area DA1, while others may be located in a second display area DA2. For example, the first display area DA1 may be larger than the second display area DA2, and correspondingly, the number of pixels PX arranged in the first display area DA1 may be greater than the number of pixels PX arranged in the second display area DA2.

[0066] The first display area DA1 and the second display area DA2 are configured to be driven by a single driver integrated circuit IC on a single display panel DP. For this purpose, pixels PX arranged in the same column can be electrically connected to one of the data lines DL1 to DLm, regardless of whether the pixel PX is located in the first display area DA1 or the second display area DA2. In this case, compared to implementing the first display area DA1 and the second display area DA2 with different driver integrated circuits on separate display panels, the thickness of the display device DD can be reduced, and the interface and data load for image signal transmission and driving can be reduced. However, when the first display area DA1 and the second display area DA2 are driven on a single display panel DP, the first display area DA1 can also be driven even when the intention is to activate only the second display area DA2. A specific solution to this problem will be described in more detail below.

[0067] Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0068] refer to Figure 4 The display device DD may include a display panel DP and a driver integrated circuit IC. The display panel DP and the driver integrated circuit IC respectively correspond to Figure 2 and Figure 3 The display panel DP and driver integrated circuit IC are shown. The display device DD is not limited to... Figure 4 The configuration shown may also include additional components. For example, the display device DD may also include a voltage generator for generating voltages for the display panel DP and the driving integrated circuit IC.

[0069] The driver integrated circuit IC can be configured to drive a display panel (DP) to display an image. The driver integrated circuit IC may include a driver controller 100 (also called a driver controller circuit) and a data driver circuit 200. The driver controller 100 and the data driver circuit 200 can be implemented as, but are not limited to, a single embedded integrated circuit. For example, the driver controller 100 and the data driver circuit 200 can also be implemented as separate chips.

[0070] The drive controller 100 is configured to receive an image signal RGB and a control signal CTRL. For example, the image signal RGB and the control signal CTRL may be provided by an application processor. The image signal RGB should be understood as a graphic source of the image to be displayed on the display panel DP. The control signal CTRL may include a synchronization signal that synchronizes the image output to a precise position on the display panel DP. The synchronization signal may include, for example, a vertical synchronization signal for separating frames, a horizontal synchronization signal for separating lines, and a data enable signal for distinguishing output intervals of image data. Furthermore, the control signal CTRL may also include a system clock signal and signals related to the operating mode of the display device DD.

[0071] The drive controller 100 is configured to generate an image data signal DATA. Within the drive controller 100, the RGB data format of the image signal is converted to conform to the interface specification of the data drive circuit 200. The drive controller 100 can be configured to generate a scan control signal SCS for controlling the scan drive circuit SD, a transmit drive control signal ECS for controlling the transmit drive circuit EDC, and a data control signal DCS for controlling the data drive circuit 200, based on the control signal CTRL.

[0072] The data drive circuit 200 can be configured to receive a data control signal DCS and an image data signal DATA from the drive controller 100. The data drive circuit 200 can be configured to convert the digital image data signal DATA into an analog data signal. The data signal can be converted into a grayscale value corresponding to the image data signal DATA. The data drive circuit 200 can be electrically connected to multiple data lines DL1 to DLm, as described in more detail below, and can output the converted data signal to the multiple data lines DL1 to DLm.

[0073] The display panel DP may include multiple first scan lines GIL0 to GILn, multiple second scan lines GWL1 to GWLn, multiple emission control lines EML1 to EMLn, multiple data lines DL1 to DLm, and multiple pixels PX, where each of n and m is a positive integer. The display panel DP may also include scan drive circuitry SD connected to the first scan lines GIL0 to GILn and the second scan lines GWL1 to GWLn, and emission drive circuitry EDC connected to the emission control lines EML1 to EMLn.

[0074] The first scan lines GIL0 to GILn and the second scan lines GWL1 to GWLn extend from the scan drive circuit SD in the first direction DR1, and the transmit control lines EML1 to EMLn extend from the transmit drive circuit EDC in the first direction DR1. The first scan lines GIL0 to GILn, the second scan lines GWL1 to GWLn, and the transmit control lines EML1 to EMLn are spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data drive circuit 200 in the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0075] Multiple pixels PX are electrically connected to the first scan lines GIL0 to GILn, the second scan lines GWL1 to GWLn, the transmit control lines EML1 to EMLn, and the data lines DL1 to DLm, respectively. For example, each of the multiple pixels PX can be connected to four lines extending in the first direction DR1 and one data line extending in the second direction DR2. The circuit configuration and operation of each of the multiple pixels PX will be described in more detail below.

[0076] The scan drive circuit SD is configured to receive a scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can be configured to output a first scan signal to first scan lines GIL0 to GILn and a second scan signal to second scan lines GWL1 to GWLn. The scan drive circuit SD can be configured to sequentially activate multiple pixels PX line by line using the first and second scan signals. Here, activation refers to the state where data signals can be input to multiple pixels PX via data lines DL1 to DLm. The circuit configuration and operation of the scan drive circuit SD will be described in more detail below.

[0077] The transmit drive circuit EDC is configured to receive the transmit drive control signal ECS from the drive controller 100. The transmit drive circuit EDC can be configured to output transmit control signals to the transmit control lines EML1 to EMLn in response to the transmit drive control signal ECS. The transmit drive circuit EDC can be configured to sequentially cause multiple pixels PX to emit light line by line via the transmit control signals.

[0078] The display panel DP may include a first display area DA1 and a second display area DA2. The first display area DA1 corresponds to... Figure 1A , Figure 2 and Figure 3 The first display area DA1 is shown, and the second display area DA2 corresponds to... Figure 1B , Figure 2 and Figure 3The second display area DA2 is shown in the diagram. For example, by bending the display panel DP, the first display area DA1 and the second display area DA2 can be positioned so that they face each other on different surfaces of the display device DD.

[0079] A first display area DA1 can be configured to display an image using a first pixel among a plurality of pixels PX. A second display area DA2 can be configured to display an image using a second pixel among a plurality of pixels PX that is different from the first pixel. The number of the first pixel and the number of the second pixel can be different. For example, the number of the first pixel can be greater than the number of the second pixel. The number of the first pixel and the number of the second pixel can respectively determine the area of ​​the first display area DA1 and the area of ​​the second display area DA2. Figure 1A , Figure 1B , Figure 2 and Figure 3 As shown, the first display area DA1 and the second display area DA2 can be spaced apart from each other. Even though the first display area DA1 and the second display area DA2 are spaced apart from each other, the first pixel and the second pixel are connected by multiple data lines DL1 to DLm.

[0080] In such Figure 1A In the unfolded state of the display device DD shown (hereinafter referred to as the "first operating mode"), both the first display area DA1 and the second display area DA2 can be configured to be activated. Therefore, the scan drive circuit SD and the emission drive circuit EDC can be configured to sequentially activate multiple pixels PX row by row and cause light emission from the multiple pixels PX. Figure 4 In the structure shown, the scan drive circuit SD and the emission drive circuit EDC can be configured to sequentially scan the second pixel included in the second display area DA2 and cause light emission in the second pixel included in the second display area DA2, and then sequentially scan the first pixel included in the first display area DA1 and cause light emission in the first pixel included in the first display area DA1.

[0081] In such Figure 1BIn the folded state (hereinafter referred to as the "second operating mode") of the display device DD shown, the first display area DA1 is invisible due to the fold, and only the second display area DA2 can be configured to be activated. For example, the folded state can be a state in which the first non-folded area NFA1 and the second non-folded area NFA2, which overlap with the first display area DA1, are folded at a predetermined angle sufficient to allow them to face each other. In the second operating mode, the first display area DA1 can be configured to be activated at a relatively low frequency (e.g., about 0.1 Hz to about 1 Hz). The scan drive circuit SD and the emission drive circuit EDC can be configured to sequentially scan the second pixel included in the second display area DA2 and cause light to be emitted from the second pixel included in the second display area DA2, and not scan the first pixel included in the first display area DA1. For this purpose, the scan control signal SCS can include a masking signal indicating the start of the first display area DA1. The specific operation of the masking signal in the second operating mode will be described in more detail below.

[0082] For example, according to an implementation, when the display device DD is in an unfolded state, such as Figure 1A As shown in the (first operating mode), both the first display area DA1 and the second display area DA2 can be fully activated to display an image. The scan drive circuit SD and the transmit drive circuit EDC work together to sequentially activate pixels PX line by line, thereby allowing the image to be properly rendered across the entire display panel DP. Figure 4 In the structural configuration depicted, the scan drive circuit SD and the transmit drive circuit EDC can scan and activate the second pixel in the second display area DA2 before scanning and activating the first pixel in the first display area DA1. This sequential scanning method helps maintain consistent display performance and alleviates problems related to power distribution and refresh synchronization across multiple display areas. Furthermore, this arrangement allows for improved signal processing within a single display panel DP, while ensuring consistent operation of the two display areas when necessary.

[0083] Conversely, when the display device DD is folded, such as Figure 1BIn the (second operating mode) shown, the first display area DA1 is no longer externally visible due to folding, while the second display area DA2 remains exposed and continues to display the image. The folding process positions the first non-folded area NFA1 and the second non-folded area NFA2 facing each other, effectively hiding the first display area DA1 from the viewing angle. To improve power efficiency in this state, the first display area DA1 can still be activated intermittently, but at a significantly lower frequency, for example, in the range of about 0.1 Hz to about 1 Hz. This low-frequency activation helps keep the display ready while reducing unnecessary power consumption. On the other hand, the scan drive circuit SD and the emission drive circuit EDC are configured to selectively activate only the second pixel within the second display area DA2, while preventing unnecessary scanning of the first pixel in the first display area DA1 and causing light emission from the first pixel in the first display area DA1. This selective activation can be achieved by using a masking signal embedded in the scan control signal SCS to indicate the start of the first display area DA1. By employing this method, the display device DD can dynamically manage power distribution, extend battery life, and improve the efficiency of its multi-display operation without compromising the responsiveness of the effective display area.

[0084] Figure 5 yes Figure 4 An exemplary equivalent circuit diagram of the pixels shown.

[0085] refer to Figure 5 Pixel PXij (where each of i and j is a positive integer) is electrically connected to the i-th data line DL1 to DLm, the (j-1)-th first scan line GILj-1 and the j-th first scan line GILj among the first scan lines GIL0 to GILn, the j-th second scan line GWLj among the second scan lines GWL1 to GWLn, and the j-th transmission control line EMLj among the transmission control lines EML1 to EMLn. Pixel PXij corresponds to Figure 4 One of the multiple pixels PX shown.

[0086] Pixel PXij is configured to receive a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2 can be supplied using, for example, voltages generated by the power management circuitry of the display device DD. For example, the first initialization voltage VINT1 and the second initialization voltage VINT2 can be converted from voltages generated by the power management circuitry by the drive controller 100 and then transmitted to pixel PXij.

[0087] Pixel PXij may include pixel circuitry PXC and light-emitting element ED. Pixel circuitry PXC may include first transistors T1 to seventh transistors T7 and a capacitor Cst. Each of the first transistors T1 to seventh transistors T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, but this disclosure is not limited to this configuration. For example, in an embodiment, the transistor may instead be an N-type transistor having an oxide semiconductor layer. Furthermore, in an embodiment, with... Figure 5 Unlike other transistors, at least one of the first transistor T1 to the seventh transistor T7 can be an N-type transistor, and the other transistors can be P-type transistors. The circuit configuration of pixel PXij according to embodiments of this disclosure is not limited to... Figure 5 Furthermore, the structure of the pixel circuit PXC can be implemented in a modified form.

[0088] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting element ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can be configured to receive the data signal DI transmitted by the i-th data line DL1 according to the switching operation of the second transistor T2 and supply drive current Id to the light-emitting element ED.

[0089] The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line GILj. The second transistor T2 can be configured to be turned on according to the scan signal GIj transmitted through the j-th first scan line GILj, so as to transmit the data signal DI received from the i-th data line DLi to the first electrode of the first transistor T1.

[0090] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the j-th first scan line GILj. The third transistor T3 can be configured to be turned on according to the scan signal GIj transmitted through the j-th first scan line GILj, and to connect the gate electrode and the second electrode of the first transistor T1 as a diode.

[0091] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third voltage line VL3 to which a first initialization voltage VINT1 is transmitted, and a gate electrode connected to the (j-1)th first scan line GILj-1. The fourth transistor T4 is configured to be turned on according to the scan signal GIj-1 transmitted through the (j-1)th first scan line GILj-1 to perform an initialization operation by initializing the voltage of the gate electrode of the first transistor T1 by transmitting the first initialization voltage VINT1 to the gate electrode of the first transistor T1.

[0092] The fifth transistor T5 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th emission control line EMLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the j-th emission control line EMLj. The fifth transistor T5 and the sixth transistor T6 are configured to be turned on simultaneously according to the emission control signal EMj received through the j-th emission control line EMLj. The first drive voltage ELVDD applied through the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and transmitted to the light-emitting element ED.

[0093] The seventh transistor T7 includes a first electrode connected to a fourth voltage line VL4 to which a second initialization voltage VINT2 is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a gate electrode connected to a j-th second scan line GWLj. The seventh transistor T7 is configured to be turned on according to a scan signal GWj received via the j-th second scan line GWLj. The second initialization voltage VINT2 can be applied to the anode of the light-emitting element ED for initialization via the turned-on seventh transistor T7.

[0094] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first drive voltage line VL1. The cathode of the light-emitting element ED can be connected to the second drive voltage line VL2 configured to supply the second drive voltage ELVSS.

[0095] A light-emitting element (ED) may include a light-emitting diode (LED). The LED may include, for example, organic light-emitting materials, inorganic light-emitting materials, quantum dots, or quantum rods as the light-emitting layer. The ED may be configured to emit light based on a luminescent current (Ied).

[0096] Figure 6 It is used to show Figure 5 The timing diagram shows the operation of the pixels shown. (Refer to...) Figure 5 The figure labels used to describe Figure 6 .

[0097] refer to Figure 6 The pixel PXij is operated in the first interval p1, the second interval p2, the third interval p3 and the fourth interval p4 for emission operation.

[0098] In the first interval p1, the node used for programming pixel PXij is initialized. During the first interval p1, a low-level first scan signal GIj-1 is provided through the (j-1)th first scan line GILj-1. In response to the low-level first scan signal GIj-1, the fourth transistor T4 is turned on, and the first initialization voltage VINT1 is transmitted through the fourth transistor T4 to the gate electrode of the first transistor T1, thereby initializing the first transistor T1.

[0099] In the second interval p2, pixel PXij is programmed. When a low-level j-th first scan signal GIj is supplied via the j-th first scan line GILj during the second interval p2, the third transistor T3 is turned on. The first transistor T1 can be diode-connected and forward-biased by the turned-on third transistor T3. Additionally, the second transistor T2 is turned on by the low-level j-th first scan signal GIj. Therefore, a compensation voltage, equal to the threshold voltage of the first transistor T1, is applied to the gate electrode of the first transistor T1, from the data signal DI supplied from the i-th data line DL1. This gate voltage should be understood as the compensation voltage. The first drive voltage ELVDD and the compensation voltage can be applied across the capacitor Cst, and a charge corresponding to the voltage difference across the capacitor Cst can be stored.

[0100] In the third interval p3, the anode of the light-emitting element ED is initialized. The seventh transistor T7 is turned on by a low-level second scan signal GWj supplied through the second scan line GWLj. If the light-emitting element ED emits light even when the minimum current for displaying a black image flows from the first transistor T1 as the drive current, the black image may not be properly displayed. Therefore, the seventh transistor T7 is configured to divert a portion of the minimum current of the first transistor T1 as a bypass current Ibp to an alternative current path, thereby bypassing the current path to the light-emitting diode. The light-emitting current Ied of the light-emitting element ED, obtained by subtracting the bypass current Ibp from the drive current Id, is minimized to a level that ensures accurate display of the black image, thereby enhancing contrast.

[0101] In the fourth interval p4, the light-emitting element ED emits light based on the programmed data signal DI. The emission control signal EMj supplied from the j-th emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on according to the low-level emission control signal EMj. Therefore, a drive current Id is generated corresponding to the voltage difference between the voltage at the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and this drive current Id is supplied to the light-emitting element ED through the sixth transistor T6, thereby allowing the light-emitting current Ied to flow through the light-emitting element ED.

[0102] Figure 7 yes Figure 4 An exemplary block diagram of the scan drive circuit shown is presented.

[0103] refer to Figure 7 The scan drive circuit SD includes multiple drive stages ST0 to STn+1, where n is a positive integer. The scan drive circuit SD is configured to start from... Figure 4 The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS may include clock signals CLK1 and CLK2, masking signals MS1 and MS2, and a start signal FLM. The scan drive circuit SD can also be configured to receive signals from a voltage generator or... Figure 4 The drive controller 100 shown receives the drive voltage.

[0104] Driver stages ST0 to STn+1 can be configured to output first scan signals GI0 to GIn and second scan signals GW1 to GWn. The first scan signals GI0 to GIn can provide... Figure 4 The first scan lines GIL0 to GILn shown are provided, and the second scan signals GW1 to GWn can be provided to... Figure 4 The second scan lines GWL1 to GWLn are shown in the figure.

[0105] The initial driver stage ST0 can be configured to receive the start signal FLM as a carry signal. The start signal FLM can be understood as a signal indicating the start of a frame. Each of the driver stages ST1 to STn+1 has a dependent connection to receive carry signals CR0 to CRn output from the previous driver stage. For example, driver stage ST1 can receive the carry signal CR0 output from the previous driver stage ST0.

[0106] In normal operation, the carry signals CR0 to CRn output by the drive stages ST0 to STn+1 can be the same as the scan signals. However, according to the implementation, unlike the scan signals, each of the drive stages ST0 to STn+1 outputs a carry signal to the subsequent drive stage without relying on the masking signals MS1 and MS2.

[0107] Masking signals MS1 and MS2 can be signals configured to mask scan signals output from certain drive stages ST0 to STn+1 to a predetermined level. For example, when the scan in the second display area DA2 ends, masking signals MS1 and MS2 can have changed levels to deactivate them. Figure 4 The first display area DA1 is shown. The first masking signal MS1 and the second masking signal MS2 can have opposite phases.

[0108] Clock signals CLK1 and CLK2 can be used to control the output timing of the first scan signals GI0 to GIn, the second scan signals GW1 to GWn, and the carry signals CR0 to CRn for each output of driver stages ST0 to STn+1. The first clock signal CLK1 and the second clock signal CLK2 can have opposite phases. The terminal receiving the first clock signal CLK1 in an odd-numbered driver stage can correspond to the terminal receiving the second clock signal CLK2 in an even-numbered driver stage. Similarly, the terminal receiving the second clock signal CLK2 in an odd-numbered driver stage can correspond to the terminal receiving the first clock signal CLK1 in an even-numbered driver stage.

[0109] Figure 8 yes Figure 7 An exemplary equivalent circuit diagram of the driver stage is shown.

[0110] refer to Figure 8 The driver level STj corresponds to Figure 7 The j-th drive level in, and Figure 7 Each of the drive levels ST0 to STn+1 in the middle can have the same as Figure 8 The driver stage STj shown has the same circuit configuration. Driver stage STj includes a driver circuit DC, masking circuits MSC1 and MSC2, first input terminals IN1 to fifth input terminals IN5, a first voltage terminal V1 and a second voltage terminal V2, and a first output terminal OUT1 and a second output terminal OUT2. The masking circuit may include a first masking circuit MSC1 and a second masking circuit MSC2.

[0111] The drive circuit DC includes transistors PT1 to PT7 and capacitors PC1 and PC2. The drive circuit DC is configured to receive a first clock signal CLK1, a second clock signal CLK2, and a carry signal CRj-1 through first input terminals IN1 to third input terminals IN3. The drive circuit DC is also configured to receive a first voltage VGL and a second voltage VGH through first voltage terminals V1 and second voltage terminals V2. The first voltage VGL and the second voltage VGH can be obtained from a voltage generator or from... Figure 4 The drive controller 100 shown receives this.

[0112] The DC drive circuit is configured to output a scan signal GIj and a carry signal CRj through the first output terminal OUT1 and the second output terminal OUT2. The carry signal CRj can be provided to the next drive stage STj+1 (see [link]). Figure 9 The carry signal CRj-1 received via the third input terminal IN3 can be from the previous driver stage STj-1 (see...). Figure 9 The carry signal CRj-1 of the initial drive stage ST0 can be the start signal FLM.

[0113] Figure 7 In the driver stages ST0 to STn+1 shown, the first input terminal IN1 of each of the driver stages (e.g., odd-numbered driver stages) can be configured to receive a first clock signal CLK1, and the second input terminal IN2 can be configured to receive a second clock signal CLK2. Furthermore, in the other driver stages ST0 to STn+1 (e.g., even-numbered driver stages), the first input terminal IN1 of each of the driver stages can be configured to receive a second clock signal CLK2, and the second input terminal IN2 can be configured to receive a first clock signal CLK1.

[0114] The first transistor PT1 includes a first electrode connected to the third input terminal IN3, a second electrode connected to the first node N1, and a gate electrode connected to the first input terminal IN1. The first transistor PT1 is configured to transmit a carry signal CRj-1 to the first node N1 based on a first clock signal CLK1 received from the first input terminal IN1.

[0115] The second transistor PT2 includes a first electrode connected to the second voltage terminal V2, a second electrode connected to the third node N3, and a gate electrode connected to the second node N2.

[0116] The third transistor PT3 includes a first electrode connected to the third node N3, a second electrode connected to the first node N1, and a gate electrode connected to the second input terminal IN2. The second transistor PT2 and the third transistor PT3 can be configured to reduce the level of the first node N1 based on a second clock signal CLK2 received from the second input terminal IN2.

[0117] The fourth transistor PT4 includes a first electrode connected to the second node N2, a second electrode connected to the first input terminal IN1, and a gate electrode connected to the first node N1. The fourth transistor PT4 can be configured to increase the level of the second node N2 at the rising edge of the first clock signal CLK1.

[0118] The fifth transistor PT5 includes a first electrode connected to the second node N2, a second electrode connected to the first voltage terminal V1, and a gate electrode connected to the first input terminal IN1. The fifth transistor PT5 can be configured to initialize the second node N2 based on a first clock signal CLK1.

[0119] The sixth transistor PT6 includes a first electrode connected to the second voltage terminal V2, a second electrode connected to the second output terminal OUT2, and a gate electrode connected to the second node N2. The sixth transistor PT6 can be configured to output a second voltage VGH as a scan signal GIj or a carry signal CRj.

[0120] The seventh transistor PT7 includes a first electrode connected to the second output terminal OUT2, a second electrode connected to the second input terminal IN2, and a gate electrode connected to the first node N1. The seventh transistor PT7 can be configured to output a first voltage VGL as a scan signal GIj or a carry signal CRj. The seventh transistor PT7 can also be configured to transmit the level of the second clock signal CLK2 input to the second input terminal IN2 to the second output terminal OUT2 based on the voltage level at the first node N1.

[0121] The first capacitor PC1 is connected between the first node N1 and the second output terminal OUT2. The second capacitor PC2 is connected between the second voltage terminal V2 and the second node N2.

[0122] The first masking circuit MSC1 includes a first masking transistor MT1. The first masking circuit MSC1 is configured to stop (or mask) the output of the scan signal GIj in response to a first masking signal MS1 received via the fourth input terminal IN4. The first masking transistor MT1 is connected between the second voltage terminal V2 and the first output terminal OUT1, and includes a gate electrode connected to the fourth input terminal IN4.

[0123] The second masking circuit MSC2 includes a second masking transistor MT2. The second masking transistor MT2 is connected between the first output terminal OUT1 and the second output terminal OUT2, and includes a gate electrode connected to the fifth input terminal IN5. The second masking circuit MSC2 is configured to output a carry signal CRj, identical to the scan signal GIj, in response to a second masking signal MS2 received through the fifth input terminal IN5.

[0124] Figure 9 It is shown Figure 8 The timing diagram of the driver-level operation is shown.

[0125] refer to Figure 9The operation of the (j-1)th driver stage STj-1, the jth driver stage STj, and the (j+1)th driver stage STj+1 of the scan driver circuit SD is illustrated. For ease of explanation, Figure 9 Use and Figure 7 and Figure 8 The same reference numerals are used to describe the figures.

[0126] The first clock signal CLK1 and the second clock signal CLK2 are signals that have the same frequency in different horizontal intervals (e.g., horizontal intervals Hj-4 to Hj+1) and transition to an active level (e.g., low level). A horizontal interval is defined as the interval during which... Figure 4 The time when pixels PX in a row of the display panel DP shown are driven.

[0127] When the first masking signal MS1 is at the second level (e.g., high level), the first masking transistor MT1 is turned off, keeping the second voltage terminal V2 and the first output terminal OUT1 electrically disconnected. When the second masking signal MS2 is at the first level (e.g., low level), the second masking transistor MT2 is turned on, keeping the first output terminal OUT1 and the second output terminal OUT2 electrically connected.

[0128] The (j-1) driver stage STj-1 receives the second clock signal CLK2 at the first input terminal IN1 and the first clock signal CLK1 at the second input terminal IN2.

[0129] In the (j-2)th horizontal interval Hj-2, if the second clock signal CLK2 received at the first input terminal IN1 is low, the first transistor PT1 is turned on. Because the first transistor PT1 is turned on, the low-level carry signal CRj-2 is transmitted to the first node N1 through the first transistor PT1. When the second clock signal CLK2 is low, the fifth transistor PT5 is turned on, discharging the second node N2 to the first voltage VGL. When the second node N2 is low, the sixth transistor PT6 is turned on, causing the second output terminal OUT2 to output a high-level carry signal CRj-1. When the first node N1 is low, the seventh transistor PT7 is turned on, thereby maintaining the second output terminal OUT2 at a high level through the first clock signal CLK1 received at the second input terminal IN2.

[0130] In the (j-1)th horizontal interval Hj-1, if the second clock signal CLK2 is high, the fifth transistor PT5 is off, the second node N2 rises to a high level through the conducting fourth transistor PT4, and the sixth transistor PT6 is off. If the first clock signal CLK1 received at the second input terminal IN2 is low, the first node N1 changes to an even lower level due to the first capacitor PC1, and the seventh transistor PT7 turns on, thereby allowing the second output terminal OUT2 to output a low-level carry signal CRj-1. Since the second masking transistor MT2 is turned on by the low-level second masking signal MS2, the scan signal GIj-1 is also activated to a low level.

[0131] The j-th driver stage STj receives the first clock signal CLK1 at the first input terminal IN1 and the second clock signal CLK2 at the second input terminal IN2. In the j-th horizontal interval Hj, if the first masking signal MS1 transitions from high to low and the second masking signal MS2 transitions from low to high, then the first masking transistor MT1 in the first masking circuit MSC1 is turned on, and the second masking transistor MT2 in the second masking circuit MSC2 is turned off.

[0132] In the (j-1)th horizontal interval Hj-1, if the first clock signal CLK1 is low, the first transistor PT1 is turned on. Because the first transistor PT1 is turned on, the low-level carry signal CRj-1 is transmitted to the first node N1 through the first transistor PT1. When the first clock signal CLK1 is low, the fifth transistor PT5 is turned on, causing the second node N2 to discharge to the first voltage VGL. When the second node N2 is low, the sixth transistor PT6 is turned on, causing the second output terminal OUT2 to output a high-level carry signal CRj. Additionally, when the first node N1 is low, the seventh transistor PT7 is turned on, thereby maintaining the second output terminal OUT2 at a high level through the second clock signal CLK2 received at the second input terminal IN2.

[0133] In the j-th horizontal interval Hj, if the first clock signal CLK1 is high, the fifth transistor PT5 is turned off, and the second node N2 is raised from the conducting fourth transistor PT4 to a high level, causing the sixth transistor PT6 to turn off. If the second clock signal CLK2 received at the second input terminal IN2 is low, the first node N1 is changed to an even lower low level through the first capacitor PC1, and the seventh transistor PT7 is turned on, thereby allowing the second output terminal OUT2 to output a low-level carry signal CRj. Here, since the second masking transistor MT2 is turned off by the high-level second masking signal MS2, and the first masking transistor MT1 is turned on by the low-level first masking signal MS1, the scan signal GIj remains at a high level. That is, the j-th driver stage STj can output a high-level scan signal GIj and a low-level carry signal CRj in the j-th horizontal interval Hj.

[0134] The (j+1)th driver stage STj+1 receives the second clock signal CLK2 at the first input terminal IN1 and the first clock signal CLK1 at the second input terminal IN2. In the j-th horizontal interval Hj, if the second clock signal CLK2 received at the first input terminal IN1 is low, the first transistor PT1 is turned on. Because the first transistor PT1 is turned on, the high-level carry signal CRj is transmitted to the first node N1 through the first transistor PT1. When the first node N1 is high, the third transistor PT3, the fourth transistor PT4, and the seventh transistor PT7 remain off.

[0135] In the (j+1)th horizontal interval Hj+1, if the second clock signal CLK2 is low, the fifth transistor PT5 is turned on. The turned-on fifth transistor PT5 keeps the second node N2 low, and the sixth transistor PT6 is turned on, thereby allowing the output of a high-level carry signal CRj+1. On the other hand, since the first masking transistor MT1 is turned on by the low-level first masking signal MS1, the scan signal GIj+1 is kept high. That is, the (j+1)th driver stage STj+1 outputs a high-level carry signal CRj+1 and a high-level scan signal GIj+1.

[0136] Figure 4The second display area DA2 shown includes pixels PX from the first row to the (a-1)th row, and the first display area DA1 includes pixels PX from the ath row to the nth row, where each of a and n is a positive integer. In this case, the ath scan signal can be masked at a high level by changing the first masking signal MS1 from high to low and the second masking signal MS2 from low to high in the ath horizontal interval. Subsequently, the (a+1)th scan signal can be kept at a high level by keeping the first clock signal CLK1 and the second clock signal CLK2 at low levels.

[0137] Figure 4 The pixel PX in the a-th row shown is connected to the (a-1)th first scan line, the a-th first scan line GILa, the a-th second scan line GWLa, and the a-th emission control line EMLa. When the a-th first scan signal provided to the pixel PX in the a-th row corresponding to the first display area DA1 is masked at a high level, the (a-1)th second scan signal is output normally to ensure that the pixel PX in the (a-1)th row corresponding to the second display area DA2 correctly displays the image.

[0138] Figure 10 It is shown that in the first operating mode, by Figure 4 The timing diagram of the scan control signal and image data signal provided by the drive controller 100 shown is shown.

[0139] The first operating mode should be understood as the normal operating mode, in which the image is displayed in both the first display area DA1 and the second display area DA2, as shown in... Figure 1A The display device DD shown is in its unfolded state. For ease of explanation, Figure 10 Use and Figure 4 The same reference numerals are used to describe the figures.

[0140] The drive controller 100 is configured to provide a scan control signal SCS to the scan drive circuit SD. (Reference) Figure 10 The diagram illustrates the start signal FLM, the first masking signal MS1, and the second masking signal MS2 included in the scan control signal SCS. In the first operating mode, the start signal FLM is activated low 120 times per second. That is, for each frame from the first frame F1 to the 120th frame F120, the start signal FLM is activated low. In this case, the driving frequency of the first display area DA1 and the second display area DA2 can be understood as 120Hz. During the first operating mode, the first masking signal MS1 remains high, and the second masking signal MS2 remains low. Therefore, the first display area DA1 and the second display area DA2 can be activated for each frame.

[0141] The drive controller 100 can be configured to sequentially provide image data signals DATA to the data drive circuit 200, the image data signals DATA including a first image data signal D1 corresponding to the first frame F1 to a 120th image data signal D120 corresponding to the 120th frame F120. The image data signal corresponding to each frame can be converted into a data signal by the data drive circuit 200 and then output to the pixel PX corresponding to the first display area DA1 and the second display area DA2.

[0142] Figure 11 It is used to describe according to the first operating mode Figure 4 The diagram shows the data signal output of the display device DD.

[0143] refer to Figure 11 In the first operating mode, the display device DD displays images in the first display area DA1 and the second display area DA2. Figure 11 The display device DD, the first display area DA1, and the second display area DA2 shown correspond to Figure 1A , Figure 1B and Figure 4 The display device shown includes DD, a first display area DA1, and a second display area DA2.

[0144] In the first operating mode, the display device DD can be configured to display images in the first display area DA1 and the second display area DA2 for each frame from the first frame F1 to the 120th frame F120, based on the first image data signal D1 to the 120th image data signal D120. Since the first operating mode does not use a separate masking signal to pause the operation of a specific display area, the first display area DA1 and the second display area DA2 can be activated for each frame.

[0145] Figure 12 It is shown in the first operating mode from Figure 4 The timing diagram of the scan signal output by the scan drive circuit shown is shown.

[0146] refer to Figure 12 The diagram illustrates the start signal FLM and the first scan signals GI0 to GI3388. As an example, it should be understood that the second display area DA2 includes pixels up to row 748, and the first display area DA1 includes pixels from row 749 to row 3388. For ease of explanation, Figure 12 Use and Figure 4 The same reference numerals are used to describe the figures.

[0147] In the first operating mode, the first display area DA1 and the second display area DA2 can be configured for each display image in the first frame F1 to the 120th frame F120. In response to the start signal FLM, the scan drive circuit SD can be configured to... Figure 4 The first scan lines GIL0 to GILn shown sequentially output each of the first scan signals GI0 to GI3388. When the first scan signals GI0 to GI3388 are low, the pixels that receive the low level of the first scan signals GI0 to GI3388 via the first scan lines GIL0 to GILn can be activated to receive data signals via the data lines. Since the first operating mode does not use a separate masking signal to pause operation of a specific display area, the first display area DA1 and the second display area DA2 can be activated for each frame.

[0148] Figure 13 This is shown as being operated in the second mode by Figure 4 The timing diagram shown illustrates the scan control signals and image data signals provided by the drive controller. The second operating mode can be understood as a partial operating mode, focusing on displaying the image in the second display area DA2, as in... Figure 1B The display device DD shown is in its folded state. However, the second operating mode is not limited to the folded state, and can be, for example, an operating mode that utilizes a specific display area depending on various environments or settings. For ease of explanation, Figure 13 Use and Figure 4 The same reference numerals are used to describe the figures.

[0149] refer to Figure 13 The drive controller 100 is configured to provide a scan control signal SCS, including a start signal FLM, a first masking signal MS1, and a second masking signal MS2, to the scan drive circuit SD. (Reference) Figure 13 When the initial start signal FLM is activated to a low level in the second operating mode, the drive controller 100 is configured to output a first image data signal D1 corresponding to the first frame F1 to the data drive circuit 200. During the first frame F1, the first display area DA1 and the second display area DA2 can be activated to output an image. For example, the first display area DA1 can display, but is not limited to, a black image. The first display area DA1 can also display, for example, a still image. The segment corresponding to the first frame F1 can be the same as the frame segment distinguished by the vertical synchronization signal included in the control signal CTRL provided to the drive controller 100.

[0150] Subsequently, the drive controller 100 can be configured to output a second image data signal D2 corresponding to the second frame F2 to the data drive circuit 200. When the scan drive circuit SD scans some of the pixels PX in response to the low-level activated start signal FLM, the first masking signal MS1 can switch to a low level, and the second masking signal MS2 can switch to a high level. For example, the first masking signal MS1 and the second masking signal MS2 can switch when the scanning of the second display area DA2 is completed. Therefore, the scan drive circuit SD can be configured to stop scanning the first display area DA1. The second image data signal D2 can correspond to the image corresponding to the second display area DA2.

[0151] The drive controller 100 can be configured to output a low-level start signal FLM to the scan drive circuit SD after stopping scanning according to the mask, and to output a third image data signal D3 corresponding to the third frame F3 to the data drive circuit 200. Similar to the second frame F2, when scanning some pixels PX in response to the start signal FLM, the first mask signal MS1 can switch to a low level, and the second mask signal MS2 can switch to a high level. The second frame F2 and the third frame F3 can output an image corresponding to the second display area DA2 for the same duration. This operation can be repeated in the fourth frame F4 and the fifth frame F5. That is, in the second operating mode, the start signal FLM can indicate the start of each of the multiple subframes.

[0152] The segments corresponding to each of the second frames F2 to the fifth frames F5 can be shorter than the segments of the first frame F1, and shorter than the frame segments distinguished by the aforementioned vertical synchronization signal. Furthermore, the second image data signals D2 to the fifth image data signals D5 can all correspond to the image displayed in the second display area DA2. In the example, the first display area DA1 can be three times the size of the second display area DA2. In this case, the sum of the times used to drive the second frames F2 to the fifth frames F5 can be equal to the driving time of the first frame F1, and correspond to the frame segments distinguished by the vertical synchronization signal. That is, each of the second frames F2 to the fifth frames F5 can be understood as a subframe that divides the frame segment defined by the vertical synchronization signal into four parts.

[0153] The drive controller 100 can be configured to control the scan drive circuit SD and the data drive circuit 200 to divide a frame segment into multiple subframes and display an image in the second display area DA2 in a second operating mode. If the scan rate in the second operating mode is the same as the scan rate in the first operating mode, the drive frequency of the second display area DA2 in the second operating mode will be four times the drive frequency of the first operating mode.

[0154] The drive controller 100 can be configured to reduce the operating speed or scan rate in the second operating mode compared to the first operating mode, so as to drive the second display area DA2 at the same drive frequency as in the first operating mode. For example, the scan drive circuit SD can be configured to activate pixel PX in the second operating mode at a scan rate one-quarter of that in the first operating mode. In this case, Figure 13 The duration of F1 in the first frame can be Figure 10 The duration of F1 in the first frame is four times longer. Furthermore, Figure 13 The duration of F2 in the second frame can be compared with Figure 10 The duration of F2 in the second frame is the same.

[0155] The drive controller 100 can be configured to reduce the frequency of the clock signals CLK1 and CLK2 output to the scan drive circuit SD, thereby reducing the scan rate in the second operating mode compared to the first operating mode. For example, the drive controller 100 can be configured to generate clock signals CLK1 and CLK2 with a frequency one-quarter that of the clock signals in the first operating mode in the second operating mode. Therefore, the scan rate can be reduced proportionally to the reduction in the frequency of the clock signals in the second operating mode compared to the first operating mode. Furthermore, in the second operating mode, the pulse widths of signals such as the start signal FLM and the masking signals MS1 and MS2 output from the drive controller 100 can be increased relative to their pulse widths in the first operating mode.

[0156] By implementing the second operating mode, the display device DD can reduce power consumption by limiting unnecessary driving of the first display area DA1 through masking. Furthermore, since the drive controller 100 reduces the frequency of clock signals CLK1 and CLK2 in the second operating mode, the total power consumption of the display device DD can be further reduced. Although the full-frame drive frequency is reduced from 120Hz to 30Hz, the drive frequency of the second display area DA2 remains unchanged between the first and second operating modes. Therefore, the display performance of the effective display area can be maintained without degradation.

[0157] Still referencing Figure 13 The drive controller 100 can be configured to drive the second display area DA2 up to frame 117 F117 by reducing the clock speed by four times in the second operating mode. This provides the same performance as in... Figure 10The performance shown in the first operating mode is similar to driving the second display area DA2 up to frame 120 F120. Second image data signals D2 through 117 correspond to the image data signals for the second display area DA2. The drive controller 100 can be configured to slice the received image signal RGB into segments corresponding to each subframe for operation in the second operating mode. For example, the drive controller 100 can be configured to discard the image data signal corresponding to the first display area DA1 and process the image data signal corresponding to the second display area DA2 for continuous output. In this embodiment, the image processing can also be performed by an application processor and reflected in the image signal RGB. In this case, the power consumption of the application processor and interface can also be reduced.

[0158] After frame 117 (F117), the first display area DA1 and the second display area DA2 can be activated, as in the first frame (F1). In this case, the first display area DA1 can have a drive frequency of approximately 1 Hz. However, this disclosure is not limited to this, and the first display area DA1 can also be activated after further repetition of the subframe that activates the second display area DA2.

[0159] Figure 14 It is used to describe according to the second operating mode Figure 4 The diagram shows the data signal output of the display device.

[0160] refer to Figure 14 The display device DD is configured to display an image in the first display area DA1 and the second display area DA2 in the second operating mode. Figure 14 The display device DD, the first display area DA1, and the second display area DA2 shown correspond to Figure 1A , Figure 1B and Figure 4 The display device shown includes DD, a first display area DA1, and a second display area DA2.

[0161] In the second operating mode, the display device DD can be configured to display an image in the first display area DA1 and the second display area DA2 based on the first image data signal D1 in the first frame F1. Thereafter, the second operating mode stops driving the first display area DA1 by masking. Therefore, for each frame from the second frame F2 to the 117th frame F117, the first display area DA1 can be deactivated, and the second display area DA2 can be activated.

[0162] For example, in one implementation, in the second operating mode, the display device DD can initially display an image in both the first display area DA1 and the second display area DA2 using the first image data signal D1 in the first frame F1. After this, operation can switch to a selective driving method, where the first display area DA1 is deactivated by masking, thereby allowing only the second display area DA2 to remain active. This masking process effectively prevents unnecessary power consumption by ensuring that the first display area DA1 does not receive redundant image data when it is not visible or does not require display output.

[0163] Therefore, from frame 2 (F2) to frame 117 (F117), only the second display area DA2 continues to operate, while the first display area DA1 remains inactive. During this period, the system can improve image rendering for the second display area DA2 by adjusting parameters such as refresh rate, power distribution, and signal processing parameters to improve efficiency. This selective driving method can reduce power consumption, extend device operating time, and maintain high display performance when only a portion of the screen needs to be active. According to the implementation, additional techniques such as adjusting the driving frequency or dynamically allocating processing resources can be employed to further improve display functionality during the second operating mode.

[0164] As referenced above Figure 13 As described, each of the second frames F2 to the fifth frames F5 can be understood as a subframe that divides the frame segment defined by the vertical synchronization signal into four parts. The second frames F2 to the fifth frames F5 can operate during the operation time of the first frame F1. Furthermore, the drive controller 100 can be configured to reduce the frequency of the clock signals CLK1 and CLK2 in the second operating mode compared to the first operating mode. Therefore, Figure 14 Each of the scan times or operation times in the second frame F2 to the fifth frame F5 shown can be compared with... Figure 11 The scan time or operation time of each of the second frame F2 to the fifth frame F5 shown is the same.

[0165] Figure 15 It is shown in the second operating mode from Figure 4 The timing diagram of the scan signal output by the scan drive circuit shown is shown.

[0166] refer to Figure 15 This describes the start signal FLM and the first scan signals GI0 to GI3388. For example, it should be understood that the second display area DA2 includes pixels up to row 748, and the first display area DA1 includes pixels from row 749 to row 3388. For ease of explanation, Figure 15 Use and Figure 4 The same reference numerals are used to describe the figures.

[0167] In the second operating mode, the first display area DA1 and the second display area DA2 can be activated sequentially in the first frame F1. The scan drive circuit SD can be configured to respond to the initial start signal FLM. Figure 4 The first scan lines GIL0 to GILn shown in the diagram sequentially output each of the first scan signals GI0 to GI3388.

[0168] In frames F2 through F117, the second display area DA2 can be activated sequentially, but the first display area DA1 can be masked and therefore not activated. Therefore, the scan drive circuit SD can be configured to activate some of the first scan signals GI0 through GI3388 (e.g., GI0 through GI748) corresponding to the second display area DA2 at a low level. Therefore, the scan time or drive time of frames F2 through F117 can be shorter than the scan time or drive time of the first frame F1. Assuming the ratio between the pixels of the first display area DA1 and the second display area DA2 is 2640:748, or approximately 3.5:1, the scan time or drive time of the first frame F1 can be approximately 3.5 times longer than the scan time or drive time of the other frames. For example, the scan rate in the second operating mode can be lower than the scan rate in the first operating mode corresponding to the ratio of the number of second pixels to the number of pixels.

[0169] Figure 15 The timing diagram in the middle can be based on Figure 12 It is generated using a quarter of the clock frequency used. Therefore, the pulse widths of the start signal FLM and the first scan signals GI0 to GI3388 can be... Figure 12 Four times the pulse width shown. The length of the first frame F1 can be... Figure 12 The length of the first frame F1 shown is four times that of the first frame, and... Figure 12 During the frame segment shown, it is possible to drive one of the second frames F2 to the 117th frame F117. That is, the frame segment in the second operating mode can be longer than the frame segment in the first operating mode.

[0170] Figure 16 yes Figure 4 An exemplary block diagram of the driver integrated circuit is shown.

[0171] refer to Figure 16 The driver integrated circuit IC includes and Figure 4 The drive controller 100 and data drive circuit 200 shown correspond to the drive controller 100 and data drive circuit 200, respectively. It should be understood that... Figure 16 The functional blocks shown are for illustrative purposes only.

[0172] The drive controller 100 may include a timing controller 110, a clock generator 120, an image processing circuit 130, an interface circuit 140, and a power controller 150. The timing controller 110 may be configured to control the timing of components included in the drive integrated circuit IC. The timing controller 110 may be configured to generate a clock control signal CC, an image processing control signal IPC, and a data control signal DCS based on the control signal CTRL and the operating mode of the display device DD.

[0173] Clock generator 120 can be configured to generate scan control signals SCS for driving display panel DP based on clock control signal CC. For example, clock generator 120 can be configured to receive the system clock signal included in control signal CTRL via clock control signal CC, and convert the system clock signal into clock signals CLK1, CLK2 for operation of scan drive circuit SD. Furthermore, clock generator 120 can be configured to generate start signal FLM and masking signal to be transmitted to scan drive circuit SD based on clock control signal CC generated by timing controller 110, according to the operating mode. Alternatively, start signal FLM or masking signal can be generated by timing controller 110.

[0174] Clock generator 120 can be configured to generate a scan control signal SCS for activating both the first display area DA1 and the second display area DA2 at a first scan rate in a first operating mode. Clock generator 120 can also be configured to generate a scan control signal SCS for activating the second display area DA2 at a second scan rate lower than the first scan rate in a second operating mode. The scan control signal SCS in the first operating mode may include a clock signal having a first frequency, and the scan control signal SCS in the second operating mode may include a clock signal having a second frequency lower than the first frequency. The clock signal can be output not only to the scan drive circuit SD but also to the data drive circuit 200 for synchronizing data signal output.

[0175] Image processing circuit 130 can be configured to process image signal RGB based on image processing control signal IPC. Image processing circuit 130 can be configured to perform image enhancement and compensation operations, such as gamma correction of image signal RGB. Furthermore, image processing circuit 130 can be configured to process image signal RGB such that image data signal corresponding to second display area DA2 is repeated based on the second operating mode of display device DD. Image processing circuit 130 is configured to generate image data signal DATA by converting the data format of image signal RGB to match the interface specification of data driving circuit 200.

[0176] Interface circuit 140 can be configured to perform communication with an external device (e.g., an application processor). Interface circuit 140 can be configured to receive image signals RGB and control signals CTRL from an external source and transmit the received image signals RGB and control signals CTRL to timing controller 110 or image processing circuit 130.

[0177] The power controller 150 can be configured to receive a DC voltage Vdc from an external device (e.g., a voltage generator) and generate and output voltages for driving the integrated circuit IC or for the display panel DP and scan drive circuit SD. For example, the power controller 150 can be configured to generate voltages for initialization. Figure 5 The initialization voltages VINT1 and VINT2 of the pixel PXij shown, the driving voltages used to drive the drive controller 100 and the data drive circuit 200, and the voltages used for operation Figure 8 The first voltage VGL and the second voltage VGH of the drive stage STj shown are illustrated.

[0178] The data driving circuit 200 includes a digital-to-analog converter (DAC) 210 and a source driving circuit 220. The DAC 210 is configured to convert the image data signal DATA generated by the image processing circuit 130 into analog form. The DAC 210 can be configured to receive a reference voltage (gamma voltage) from the drive controller 100 and convert the image data signal DATA into analog form based on the reference voltage.

[0179] The source drive circuit 220 can be configured to receive the converted data signal DATA' from the digital-to-analog converter circuit 210, and output the data signal DI to the pixel PX via the data line based on the data control signal DCS. The source drive circuit 220 can also be configured to receive a clock signal from the clock generator 120, thereby synchronizing the data signal DI with the scanning operation of the scan drive circuit SD, and outputting a synchronized data signal DI. Therefore, the time for outputting the data signal DI in the first operating mode can be shorter than the time for outputting the data signal DI in the second operating mode.

[0180] Figure 17A and Figure 17B This is a perspective view of a display device according to an embodiment of the present disclosure.

[0181] Figure 17A The unfolded state of the display device DD is shown, and Figure 17B The folded state of the display device DD is shown. Figure 17A The display device DD shown can display images based on the first operating mode described above, and Figure 17B The display device DD shown can display images based on the second operating mode described above.

[0182] refer to Figure 17A The display device DD includes a first display area DA1, a second display area DA2, and a non-display area NDA. Figure 1A Unlike other display areas, the first display area DA1 and the second display area DA2 do not overlap in the plan view and can instead be formed on the same side (e.g., the front surface). The non-display area NDA is configured to be adjacent to the first display area DA1 and the second display area DA2 (e.g., surrounding the first display area DA1 and the second display area DA2).

[0183] The display device DD may include multiple folded regions FDA1, FDA2 and multiple non-folded regions NFA1, NFA2, NFA3. The first folded region FDA1 may be located between the first non-folded region NFA1 and the second non-folded region NFA2. The second folded region FDA2 may be located between the second non-folded region NFA2 and the third non-folded region NFA3. The first display region DA1 may overlap with the second folded region FDA2, the second non-folded region NFA2, and the third non-folded region NFA3 in a plan view. The second display region DA2 may overlap with the first non-folded region NFA1.

[0184] refer to Figure 17B The display device DD can be configured to fold so that the first folding region FDA1 and the second folding region FDA2 are bent. In this configuration, multiple non-folding regions NFA1, NFA2, and NFA3 can face each other along the third direction DR3. When the display device DD is folded, the second folding region FDA2 can fold inward, thereby hiding the first display region DA1. When the display device DD is folded, the first folding region FDA1 can fold outward, making the second display region DA2 visible.

[0185] In the expanded state, both the first display area DA1 and the second display area DA2 are visible, similar to... Figure 1A Their configuration allows them to be displayed together, thus enabling the display of images. Therefore, operation can be performed in the first operating mode described above. In the folded state, since the first display area DA1 is invisible, only the second display area DA2 can display images. Therefore, operation can be performed in the second operating mode described above.

[0186] Figure 18 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0187] refer to Figure 18According to embodiments of the present disclosure, the electronic device 1000 can output various information (e.g., images, text, music, etc.) through the display module 1140, which may correspond, for example, to the display device DD described above. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide application information to the user through the display panel 1141.

[0188] In some embodiments, the electronic device 1000 may be configured as, for example, a smartphone, camera, smart TV, monitor, smartwatch, tablet computer, automotive display, or AR / VR headset. For example, the electronic device 1000 may be a smartphone including a touch-sensitive display area for interaction and a non-display area NDA including sensors and circuitry for enhanced functionality. For example, the electronic device 1000 may be a television or monitor including a large display area for high-resolution image playback and a non-display area NDA incorporating driving circuitry or a connection module for external input. For example, the electronic device 1000 may be a smartwatch including a display area optimized for compact and high-definition visuals and a non-display area NDA integrating biometric sensors for health monitoring. In some cases, the electronic device 1000 is an AR / VR headset.

[0189] In some implementations, memory 1120 may store information such as software code for operating application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may operate under the control of processor 1110 and utilizes data stored in memory 1120 to provide a wide range of features, such as productivity tools, multimedia streaming and playback, file or email transfer, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touch screen 1142, allowing users to launch, browse, and use the program via user input such as touch, click, gestures, or voice interaction.

[0190] After a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123 corresponding to the selected application retrieved from memory 1120 to perform the application's functions. For example, when a user selects a camera application by clicking an icon (or camera application icon) presented on display panel 1141, processor 1110 activates the camera module. Processor 1110 can transmit image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can display the image corresponding to the captured image via display panel 1141.

[0191] In one implementation, when a user wishes to make a phone call, the user clicks the phone icon displayed on the display module 1140, and the processor 1110 can execute the phone application stored in the memory 1120. To allow the user to input the phone number to call, phone keypads can be displayed on the display panel 1141.

[0192] In this implementation, the display module 1140 can be integrated into an electronic device 1000, such as a laptop computer, smart TV, or tablet computer. Users wishing to access multimedia streaming applications (e.g., watching music videos or movies) can do so by clicking the corresponding icon. This action activates the application, allowing the user to watch the streamed content.

[0193] Processor 1110 may include a main processor 1111 and an auxiliary processor or coprocessor 1112. Main processor 1111 may include a central processing unit (CPU). Main processor 1111 may also include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0194] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. The controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specification of the display module 1140, and output the image data. The controller 1112-1 can output various control signals to drive the display module 1140. For example, the controller 1112-1 can drive the display module 1140 to display an icon suitable for user selection on the display screen, thereby triggering the execution of the application 1123.

[0195] The memory 1120 may store one or more applications 1123 and various data used by at least one component of the electronic device 1000 (e.g., processor 1110 or user interface 1161), as well as input or output data for commands associated therewith. For example, after a user selects a corresponding icon presented on a display screen (or display panel 1141) via touch screen 1142 or user interface 1161, the processor 1110 may execute camera applications, GPS applications, augmented reality and virtual reality applications, and other applications. Furthermore, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0196] Display module 1140 can output visual information (images) to a user. Display module 1140 may include a display panel 1141, a gate driver, a source driver, a voltage generation circuit, and a touch screen 1142. Display module 1140 may also include a window, a base, and a bracket to protect the display panel 1141. Display module 1140 may include at least a portion of the configuration of the display device DD described above.

[0197] User interface 1161 serves as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input from a part of the user's body (e.g., a finger) or from a pen or mouse, and generate electrical signals or data values ​​corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0198] The fingerprint sensor 1162 can sense a fingerprint used for a user's biometric identification and can also measure one or more biometric signals, such as blood pressure, water content, or weight.

[0199] Input sensor 1163 can sense user interactions including, for example, touch, click, gesture, motion, verbal commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared photodetectors or semiconductor photodetectors. Input sensor 1163 includes audio and sound sensors, which can be MEMS microphones for speech recognition or voice-based interaction. The audio and sound sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0200] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of pen or mouse input to control cursor movement on the screen. The digitizer 1164 can also generate data values ​​from electromagnetic changes caused by input. The digitizer 1164 can detect input from a passive pen or transmit and receive data with an active pen or remote control.

[0201] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer, which is formed on the top layer of the display panel 1141 by a process that is sequential to the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 1141.

[0202] In addition, the user interface 1161 may also include, for example, a gesture sensor, a gyroscope sensor for sensing rotational movement, an accelerometer sensor for tracking translational movement, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, a camera sensor for tracking gaze direction and eye movement, and an infrared (IR) emitter, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer, infrared emitter, and camera may be particularly suitable for AR / VR headset functionality.

[0203] The touchscreen 1142 includes a touch sensor embedded in a semiconductor layer of the display panel 1141 to sense pressure applied to the top layer (screen) of the display panel 1141. The touch sensor can be capacitive or resistive. The touchscreen 1142 can serve as a primary interface for users to select and browse applications, control and interact with the electronic device 1000.

[0204] The display panel 1141 (or display) may include, for example, a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. However, the type of display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type or a flexible type that can be rolled or folded. The display module 1140 may also include a support member, bracket, heat dissipation member, etc., supporting the display panel 1141. The display panel 1141 may include the display device DD described above.

[0205] Power module 1150 can supply power to the components of electronic device 1000. Power module 1150 may include a battery that is charged by a power supply voltage. The battery may include a non-rechargeable primary battery or a rechargeable secondary battery or fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the components described above, including display module 1140.

[0206] Figure 19 A schematic diagram of an electronic device according to one or more embodiments is shown.

[0207] refer to Figure 19One or more suitable electronic devices having a display device according to one or more embodiments may include not only image display electronic devices, such as smartphones 1000_1a, tablet PCs 1000_1b, laptop computers 1000_1c, TVs 1000_1d, and desktop monitors 1000_1e; but also wearable electronic devices including display modules, such as smart glasses 1000_2a, head-mounted displays 1000_2b, and / or smartwatches 1000_2c; and / or vehicle electronic devices 1000_3 including display modules, such as central information displays (CID) and / or interior mirror displays on the dashboard, center console, and / or instrument panel of a car.

[0208] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display apparatus comprising: a plurality of scan lines; a plurality of data lines; a display panel including a plurality of pixels connected to the plurality of scan lines and the plurality of data lines; a data driving circuit configured to output a plurality of data signals to the plurality of pixels via the plurality of data lines; a scan driving circuit configured to sequentially activate at least some of the plurality of pixels via the plurality of scan lines according to the data signals; and a driving controller configured to control the data driving circuit and the scan driving circuit, wherein the display panel includes a first display area in which a first pixel of the plurality of pixels is disposed and a second display area in which a second pixel of the plurality of pixels is disposed, wherein the scan driving circuit is configured to activate the first display area and the second display area at a first scan rate in a first operation mode and to activate the second display area at a second scan rate in a second operation mode, and wherein the second scan rate is lower than the first scan rate.

2. The display device according to claim 1, wherein the driving controller is configured to output a first clock signal to the scan driving circuit in the first operation mode and to output a second clock signal to the scan driving circuit in the second operation mode, and wherein a frequency of the second clock signal is lower than a frequency of the first clock signal.

3. The display device of claim 2, wherein, a reduction ratio of the frequency of the second clock signal with respect to the frequency of the first clock signal is equal to a reduction ratio of the second scan rate with respect to the first scan rate.

4. The display device according to claim 1, wherein the scan driving circuit is configured to output a first scan signal having a first pulse width to the plurality of scan lines to activate the first display area and the second display area in the first operation mode and to output a second scan signal having a second pulse width to a scan line connected to the second pixel among the plurality of scan lines to activate the second display area in the second operation mode, and wherein the first pulse width is smaller than the second pulse width.

5. The display device according to claim 1, wherein a scan time for the scan driving circuit to activate the first display area and the second display area in the first operation mode is equal to a scan time for the scan driving circuit to activate the second display area in the second operation mode.

6. The display device according to claim 1, wherein the second scan rate is lower than the first scan rate by a ratio corresponding to a proportion of the second pixel with respect to a number of the plurality of pixels.

7. The display device according to claim 1, wherein the scan driving circuit is configured to sequentially activate the second display area in response to a start signal indicating a start of a frame in the second operation mode, to deactivate the first display area in response to a masking signal indicating completion of activation of the second display area, and to reactivate the second display area.

8. The display device of claim 7, wherein, the driving controller is configured to provide the start signal to the scan driving circuit when the first display area is deactivated in response to the masking signal.

9. The display device according to claim 1, wherein the driving controller is configured to: In the first operation mode, first image data signals corresponding to the first display area and the second display area of one frame are provided to the data driving circuit during a time for activating all of the plurality of scan lines, and In the second operation mode, second image data signals corresponding to the second display area of a plurality of frames are provided to the data driving circuit during the time for activating all of the plurality of scan lines.

10. The display device according to claim 1, wherein The scan driving circuit is configured to sequentially activate the second pixels in the second display area line by line before sequentially activating the first pixels in the first display area line by line in the first operation mode.

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