Low-delay differential signal single-line chain communication system suitable for LED backlight driving device

Abstract

The invention discloses a single-wire chain type communication system which comprises a main controller and a plurality of single-wire communication links, each single-wire communication link is formed by connecting a plurality of driving chips in series, and each driving chip is further provided with a control logic circuit and a signal output control unit. Signals input by the first positive phase signal data transmission port and the first negative phase signal data transmission port pass through the differential comparator to generate input signals, and the input signals are input to the control logic circuit and the signal output control unit. And meanwhile, the signal output control unit outputs the output signal to a second positive-phase signal data transmission port, negates the output signal of the signal output control unit and outputs the negated output signal to a second negative-phase signal data transmission port. The control logic circuit generates a first control signal and a second control signal at the same time and transmits the first control signal and the second control signal to the signal output control unit.

Description

Technical Field

[0001] This invention relates to the field of LED backlight driving technology, and in particular to a low-latency differential signal single-wire chain communication system suitable for LED backlight driving devices. Background Technology

[0002] With the development of display technology, Mini-LED, OLED, and Micro-LED displays have gradually become the three main directions of display technology development, building upon traditional LCD displays. However, OLED display technology is limited by material characteristics, and the pixel ablation problem remains difficult to solve. Micro-LED technology still needs to improve the efficiency of mass transfer technology to make it more cost-effective for large-size displays. Therefore, currently, LCD displays using direct-lit Mini-LED backlight panels are the best display solution. A direct-lit Mini-LED backlight panel refers to a high-density LED array composed of even finer Mini LED chips (smaller than 100 micrometers in size), and the entire backlight panel can be divided into multiple backlight zones, with the number of each zone increasing from tens to hundreds or even thousands compared to traditional LEDs.

[0003] like Figure 1 As shown, in current mini-LED applications, the increasing number of backlight zones necessitates a large number of LED driver chips. To simplify physical connections, most applications use a chain-like structure. This structure, with its numerous signal lines all routed from the backlight controller (BCON) via ribbon cables, is highly susceptible to interference due to the similarity of signal transitions. On larger screens, only waveforms up to 2MHz to 5MHz can be transmitted. Higher frequencies either exhibit significant overshoot, causing substantial EMI problems, or are too slow for the chip to recognize.

[0004] Meanwhile, using differential signal transmission can greatly improve data transmission rate. However, the traditional method of trigger-based acquisition and retransmission causes the signal to be distorted due to clock differences as it passes through each chip. After the error accumulates after passing through several chips, the signal may become so distorted that it becomes unrecognizable.

[0005] Therefore, it is evident that a new single-line chain communication system is needed in the existing technology to solve the problem that LED backlight panels in the current technology have difficulty transmitting high-frequency backlight drive signals. Summary of the Invention

[0006] The technical objective of this invention is to provide a low-latency differential signal single-wire chain communication system suitable for LED backlight driving devices, and to solve the problem of clock error accumulation in communication systems based on this single-wire chain communication system.

[0007] Based on the above technical objectives, the present invention provides a single-line chain communication system, which includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a pair of first differential signal data transmission ports and a pair of second differential signal data transmission ports. The pair of first differential signal data transmission ports includes a first positive phase signal data transmission port and a first negative phase signal data transmission port; the pair of second differential signal data transmission ports includes a second positive phase signal data transmission port and a second negative phase signal data transmission port.

[0008] Each driver chip is further provided with a control logic circuit and a signal output control unit. Signals input from the first positive phase signal data transmission port and a first negative phase signal data transmission port are processed by a differential comparator to generate input signals, which are then input to the control logic circuit and the signal output control unit. Simultaneously, the signal output control unit outputs an output signal to the second positive phase signal data transmission port and inverts its output signal, outputting it to the second negative phase signal data transmission port. The control logic circuit simultaneously generates a first control signal and a second control signal, and transmits both to the signal output control unit.

[0009] In one embodiment, the control logic of the signal output control unit includes:

[0010] When both the first control signal and the second control signal are at the first level, the signal output control unit directly transmits the input signal to the second positive phase signal data transmission port, and simultaneously inverts the input signal and outputs it to the second negative phase signal data transmission port.

[0011] When the second control signal output is at the second level, the signal output control unit forces the output of the first level to the second positive signal data transmission port.

[0012] When the first control signal is at the second level and the second control signal output is at the first level, the signal output control unit forces the output of the second level to the second positive signal data transmission port.

[0013] In one embodiment, the signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an OR operator, with the input signal input at one end and a first control signal input at the other end. The second arithmetic unit is an AND operator, with the result of the OR operator input at one end and the inverted signal of the second control signal input at the other end. The output of the AND operator serves as the output of the signal output control unit.

[0014] In one embodiment, the signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an AND operator, with the input signal input at one end and the inverted signal of a second control signal input at the other end. The second arithmetic unit is an OR operator, with the result of the AND operator input at one end and the first control signal input at the other end. The output of the OR operator serves as the output of the signal output control unit.

[0015] In one embodiment, the signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an AND operator, with the input signal input at one end and a second control signal input at the other end. The second arithmetic unit is an OR operator, with the result of the AND operator input at one end and the first control signal input at the other end. The output of the OR operator serves as the output of the signal output control unit.

[0016] In one embodiment, the signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an OR operator, with the input signal input at a first terminal and a first control signal input at the other terminal. The second arithmetic unit is also an OR operator, with the inverted result of the first arithmetic unit input at a first terminal and the second control signal input at the other terminal. The inverted result of the second arithmetic unit is used as the output of the signal output control unit.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 This is a schematic diagram of an existing LED backlight panel structure;

[0020] Figure 2 This is a schematic diagram of the LED driver chip structure of the present invention;

[0021] Figure 3 This is a schematic diagram of the first circuit structure of the signal output control unit of the present invention;

[0022] Figure 4 This is a schematic diagram of a second circuit structure of the signal output control unit of the present invention;

[0023] Figure 5 This is a schematic diagram of the third circuit structure of the signal output control unit of the present invention;

[0024] Figure 6 This is a schematic diagram of the fourth circuit structure of the signal output control unit of the present invention; Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] Example 1

[0030] like Figure 2 As shown, the single-line chain communication system of this embodiment includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a pair of first differential signal data transmission ports and a pair of second differential signal data transmission ports. The pair of first differential signal data transmission ports includes a first positive phase signal data transmission port and a first negative phase signal data transmission port; the pair of second differential signal data transmission ports includes a second positive phase signal data transmission port and a second negative phase signal data transmission port.

[0031] The single-wire communication link connects the second positive-phase signal data transmission port of each driver chip to the first positive-phase signal data transmission port of the next adjacent driver chip, and the second negative-phase signal data transmission port of each driver chip to the first negative-phase signal data transmission port of the next adjacent driver chip. The first positive-phase signal data transmission port and the first negative-phase signal data transmission port of the first driver chip in the single-wire communication link are connected to the main controller.

[0032] In this invention, the first positive phase signal data transmission port and the second positive phase signal data transmission port of the driver chip are used to transmit the original driver data signal, while the first negative phase signal data transmission port and the second negative phase signal data transmission port are used to transmit the negative phase signal of the original driver data.

[0033] In this embodiment, each driver chip is further provided with a control logic circuit and a signal output control unit. The signals input from the first positive phase signal data transmission port and the first negative phase signal data transmission port are processed by a differential comparator to generate an input signal, which is then input to the control logic circuit and the signal output control unit. Simultaneously, the signal output control unit outputs an output signal to the second positive phase signal data transmission port and inverts its output signal, outputting it to the second negative phase signal data transmission port. The control logic circuit simultaneously generates a first control signal and a second control signal, and transmits both to the signal output control unit.

[0034] In this embodiment, the control logic of the signal output control unit is as follows:

[0035] When both the first control signal and the second control signal are in a first level state (such as a low level state), the signal output control unit directly transmits the input signal to the second positive phase signal data transmission port, and simultaneously inverts the input signal and outputs it to the second negative phase signal data transmission port.

[0036] When the second control signal output is in a second level state (such as a high level state), the signal output control unit forces the output of a first level state to the second positive signal data transmission port.

[0037] When the first control signal is in a second level state (e.g., high level state) and the second control signal output is in a first level state (e.g., low level state), the signal output control unit forces the output of the second level state to the second positive signal data transmission port.

[0038] like Figure 3 As shown, one circuit structure of the signal output control unit in this invention is as follows:

[0039] The signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an OR operator, with the input signal input at one end and a first control signal input at the other end. The second arithmetic unit is an AND operator, with the result of the OR operator input at one end and the inverted value of the second control signal input at the other end. The output of the AND operator serves as the output of the signal output control unit.

[0040] like Figure 4 As shown, another circuit structure of the signal output control unit in this invention is as follows:

[0041] The signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an AND operator, with the input signal input at one end and the inverted signal of a second control signal input at the other end. The second arithmetic unit is an OR operator, with the result of the AND operation input at one end and the first control signal input at the other end. The output of the OR operator serves as the output of the signal output control unit.

[0042] like Figure 5 As shown, another circuit structure of the signal output control unit in this invention is as follows:

[0043] The signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an AND operator, with the input signal input at one end and a second control signal input at the other end. The second arithmetic unit is an OR operator, with the result of the AND operator input at one end and the first control signal input at the other end. The output of the OR operator serves as the output of the signal output control unit.

[0044] like Figure 6 As shown, another circuit structure of the signal output control unit in this invention is as follows:

[0045] The signal output control unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit is an OR operator, with the input signal input at one end and a first control signal input at the other end. The second arithmetic unit is also an OR operator, with the inverted result of the first arithmetic unit input at one end and the second control signal input at the other end. The inverted result of the second arithmetic unit is used as the output of the signal output control unit.

[0046] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A single-wire chain communication system, characterized in that: the single-wire chain communication system comprises a master controller and a plurality of single-wire communication links, each of the single-wire communication links is formed by a plurality of driving chips connected in series, each of the driving chips is provided with a pair of first differential signal data transmission ports and a pair of second differential signal data transmission ports, the pair of first differential signal data transmission ports comprises a first positive-phase signal data transmission port and a first negative-phase signal data transmission port, and the pair of second differential signal data transmission ports comprises a second positive-phase signal data transmission port and a second negative-phase signal data transmission port; each of the driving chips is further provided with a control logic circuit and a signal output control unit, an input signal is generated by a differential comparator from signals input from the first positive-phase signal data transmission port and the first negative-phase signal data transmission port and is input to the control logic circuit and the signal output control unit, the signal output control unit outputs an output signal to the second positive-phase signal data transmission port and outputs an inverted output signal of the signal output control unit to the second negative-phase signal data transmission port, and the control logic circuit generates a first control signal and a second control signal and transmits the first control signal and the second control signal to the signal output control unit. The control logic of the signal output control unit comprises: when the first control signal and the second control signal are both in a first level state, the signal output control unit directly transmits the input signal to the second positive-phase signal data transmission port and simultaneously outputs an inverted input signal to the second negative-phase signal data transmission port; when the second control signal is output in a second level state, the signal output control unit forcibly outputs a first level state to the second positive-phase signal data transmission port; and when the first control signal is in a second level state and the second control signal is output in a first level state, the signal output control unit forcibly outputs a second level state to the second positive-phase signal data transmission port. The signal output control unit comprises a first operation unit and a second operation unit, wherein the first operation unit is an OR operator, a first end of the OR operator inputs the input signal, and the other end inputs the first control signal; the second operation unit is an AND operator, a first end of the AND operator inputs an operation result of the OR operator, and the other end inputs an inverted signal of the second control signal; and an output result of the AND operator is taken as an output result of the signal output control unit.

2. The single-wire bus communication system of claim 1, wherein The signal output control unit comprises a first operation unit and a second operation unit, wherein the first operation unit is an AND operator, a first end of the AND operator inputs the input signal, and the other end inputs an inverted signal of the second control signal; the second operation unit is an OR operator, one end of the OR operator inputs an operation result of the AND operator, and the other end inputs the first control signal; and an output result of the OR operator is taken as an output result of the signal output control unit. ​ ​ ​ 3. The single-wire bus communication system of claim 1, wherein, ​ 4. The single-wire bus communication system of claim 1, wherein, ​ 5. The single-wire bus communication system of claim 1, wherein, The signal output control unit comprises a first operation unit and a second operation unit, wherein the first operation unit is an AND operator, a first end of the AND operator inputs the input signal, and another end inputs a second control signal. The second operation unit is an OR operator, one end of the OR operator inputs an operation result of the AND operator, and another end inputs the first control signal. An output result of the OR operator is taken as an output result of the signal output control unit.

6. The single-wire bus communication system of claim 1, wherein, The signal output control unit comprises a first operation unit and a second operation unit, wherein the first operation unit is an OR operator, a first end of the OR operator inputs the input signal, and another end inputs a first control signal. The second operation unit is an OR operator, a first end of the second operation unit inputs an inverse signal of an operation result of the first operation unit, and another end inputs the second control signal. An inverse signal of an output result of the second operation unit is taken as an output result of the signal output control unit.

7. An LED backlight panel, characterized by, The LED backlight panel uses the single-wire chain communication system as claimed in any one of claims 1-6 to control the LED driving chip.

8. An LED display device, characterized by, The LED display device uses the LED backlight panel as claimed in claim 7 for backlight illumination.

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