Display panel driving circuit, partition control method and liquid crystal display panel

Abstract

The application discloses a display panel driving circuit, a partition control method and a liquid crystal display panel, and belongs to the technical field of display, and comprises a plurality of column driving pixel modules and a driving control module. Each column driving pixel module comprises: a plurality of driving units, a first end of one driving unit being connected with one gate driving voltage; a multiplexing control unit, a first end of the multiplexing control unit being connected with a second end of the driving unit, and a second end of the multiplexing control unit being connected with a third end of the driving unit; a first end of the driving control module being used for outputting a partition control voltage, a second end of the driving control module being used for outputting a data voltage, and the driving control module being used for controlling the driving units in at least one column driving pixel module to sequentially write the partition control voltage and the data voltage, so that column direction partition of the display panel is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display panel driving circuits, partition control methods, and liquid crystal display panels. Background Technology

[0002] As display technology is used more and more frequently, users are placing higher demands on the driving circuits on display panels.

[0003] Traditional display panel driving circuits typically employ a vertical partitioning structure, which divides the panel horizontally into two or more regions, and achieves partitioned refresh by independently controlling the scanning timing of each row (or row group). However, with the development of user habits or display panels, the horizontal partitioning method is no longer suitable for all display panel usage scenarios. Therefore, there is an urgent need for a new partitioning method to achieve column-oriented partitioning of the display panel.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a display panel driving circuit, a partition control method, and a liquid crystal display panel, aiming to solve the technical problem of how to achieve column-direction partitioning of a display panel.

[0006] To achieve the above objectives, this application provides a display panel driving circuit, which includes multiple columns of driving pixel modules and a driving control module. Each column of the driving pixel modules includes:

[0007] Multiple driving units, wherein a gate driving voltage is connected to the first terminal of one of the driving units;

[0008] A multiplexing control unit, wherein a first terminal of the multiplexing control unit is connected to a second terminal of the drive unit, and a second terminal of the multiplexing control unit is connected to a third terminal of the drive unit;

[0009] The first end of the drive control module is connected to the third end of the multiplexing control unit, the second end of the drive control module is connected to the fourth end of the multiplexing control unit, the control end of the drive control module is connected to the controlled end of the multiplexing control unit, the first end of the drive control module is used to output partition control voltage, the second end of the drive control module is used to output data voltage, and the drive control module is used to control the drive units in at least one column of the drive pixel modules to sequentially write the partition control voltage and the data voltage to realize the column direction partitioning of the display panel.

[0010] In one embodiment, the driving unit includes:

[0011] A first thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the first terminal of the multiplexing control unit, and the first terminal of the first thin-film transistor is connected to the gate driving voltage;

[0012] A second thin-film transistor, wherein the control terminal of the second thin-film transistor is connected to the second terminal of the first thin-film transistor, and the first terminal of the second thin-film transistor is connected to the second terminal of the multiplexing control unit;

[0013] A charging capacitor, wherein the first end of the charging capacitor is connected to the second end of the second thin-film transistor, and the second end of the charging capacitor is grounded.

[0014] In one embodiment, the driving unit further includes:

[0015] A first capacitor, wherein a first terminal of the first capacitor is connected to the control terminal of the first thin-film transistor, and a second terminal of the first capacitor is connected to the control terminal of the second thin-film transistor.

[0016] In one embodiment, the driving unit further includes:

[0017] The first control subunit has a first terminal connected to the first terminal of the multiplexing control unit, a second terminal connected to the gate drive voltage of the previous stage, and a third terminal connected to the control terminal of the first thin-film transistor.

[0018] The second control subunit has a first terminal connected to the gate drive voltage, a second terminal connected to the gate drive voltage of the next stage, and a third terminal connected to the control terminal of the first thin-film transistor.

[0019] A third thin-film transistor, wherein the control terminal of the third thin-film transistor is connected to the control terminal of the first thin-film transistor, the first terminal of the third thin-film transistor is connected to the second terminal of the multiplexing control unit, and the second terminal of the third thin-film transistor is connected to the first terminal of the second thin-film transistor.

[0020] In one embodiment, the first control subunit includes:

[0021] A fourth thin-film transistor, the control terminal of which is connected to the gate drive voltage of the previous stage, the first terminal of which is connected to the first terminal of the multiplexing control unit, and the second terminal of which is connected to the control terminal of the first thin-film transistor.

[0022] The second control subunit includes:

[0023] A fifth thin-film transistor, wherein the control terminal of the fifth thin-film transistor is connected to the gate drive voltage of the next stage, the first terminal of the fifth thin-film transistor is connected to the gate drive voltage, and the second terminal of the fifth thin-film transistor is connected to the control terminal of the first thin-film transistor.

[0024] In one embodiment, the control terminal of the drive control module includes a first control terminal and a second control terminal, and the multiplexing control unit includes:

[0025] A sixth thin-film transistor, wherein the control terminal of the sixth thin-film transistor is connected to the first control terminal, the first terminal of the sixth thin-film transistor is connected to the control terminal of the first thin-film transistor in the driving unit, and the second terminal of the sixth thin-film transistor is connected to the first terminal of the driving control module;

[0026] A seventh thin-film transistor, wherein the control terminal of the seventh thin-film transistor is connected to the second control terminal, the first terminal of the seventh thin-film transistor is connected to the first terminal of the second thin-film transistor in the driving unit, and the second terminal of the seventh thin-film transistor is connected to the second terminal of the driving control module.

[0027] In one embodiment, the drive control module includes:

[0028] A data receiver, the first end of which is connected to a driver chip;

[0029] A data output processing unit, wherein a first end of the data output processing unit is connected to a second end of the data receiver;

[0030] A partition output processing unit, wherein the first end of the partition output processing unit is connected to the third end of the data receiver, the second end of the partition output processing unit is connected to the fourth end of the multiplexing control unit, and the third end of the partition output processing unit is connected to a scanning voltage;

[0031] An output switching controller is provided, wherein a first terminal of the output switching controller is connected to a fourth terminal of the partition output processing unit, a second terminal of the output switching controller is connected to a second terminal of the data output processing unit, a third terminal of the output switching controller is connected to a third terminal of the multiplexing control unit, and a fourth terminal of the output switching controller is connected to a fourth terminal of the multiplexing control unit.

[0032] Furthermore, to achieve the above objectives, this application also provides a partition control method, which is applied to the display panel driving circuit described above, and the partition control method includes:

[0033] When the driving pixel module is a target driving pixel module that needs to be displayed in partitions, in the invalid data interval of the current frame, the multiplexing control unit is controlled to connect the second end of the driving unit and the first end of the driving control module so as to write the partition control voltage into the driving unit in the target driving pixel module.

[0034] Within the valid data range of the current frame, the multiplexing control unit is controlled to connect the third terminal of the driving unit and the second terminal of the driving control module to write the data voltage into the driving unit in the target driving pixel module.

[0035] In one embodiment, the partition control method further includes:

[0036] When the multiplexing control unit connects the second end of the drive unit and the first end of the drive control module, the sixth thin-film transistor in the multiplexing control unit is turned on, and the seventh thin-film transistor in the multiplexing control unit is turned off.

[0037] When the multiplexing control unit connects the third terminal of the drive unit and the second terminal of the drive control module, the sixth thin-film transistor in the multiplexing control unit is turned off, and the seventh thin-film transistor in the multiplexing control unit is turned on.

[0038] In addition, to achieve the above objectives, this application also provides a liquid crystal display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the array substrate row driving circuit as described above.

[0039] This application proposes a display panel driving circuit, a partition control method, and a liquid crystal display panel. The application optimizes the display panel driving circuit, resulting in a circuit comprising multiple rows of driving pixel modules and a driving control module. Each row of driving pixel modules includes multiple driving units and a multiplexed control unit. The multiplexed control unit can connect the first terminal of the driving control module to the second terminal of a driving unit, or the second terminal of the driving control module to the third terminal of a driving unit. This allows the driving units to sequentially write partition control voltage and data voltage, enabling the column of driving pixel modules that have received the partition control voltage and data voltage to display pixels, while those not received will display pixels. By maintaining the voltage of the driving pixel module in that column or turning it black, the column-direction partitioning of the entire display panel can be achieved. That is, this application combines the above modules and controls the multiplexing control unit through the control terminal of the driving control module, so that the multiplexing control unit connects the first terminal of the driving control module to the second terminal of the driving unit, or connects the second terminal of the driving control module to the third terminal of the driving unit. This allows the partition control voltage and data voltage to be written sequentially to the driving pixel modules that need to be displayed, so that the partition control voltage or data voltage is not written to the driving pixel modules that do not need to be displayed, so that they are maintained or turned black. Thus, the column-direction partitioning of the display panel is achieved by separately controlling the driving units in the multiple column driving pixel modules. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0041] Figure 1 This is a functional module diagram of an embodiment of the display panel driving circuit of this application;

[0042] Figure 2 This is a schematic diagram of a single-zone display on the display panel;

[0043] Figure 3 This is a schematic diagram of another section of the display panel;

[0044] Figure 4 This is a circuit connection diagram of the first embodiment of the display panel driving circuit of this application;

[0045] Figure 5 This is a circuit connection diagram of the second embodiment of the display panel driving circuit of this application;

[0046] Figure 6 This is a circuit connection diagram of the third embodiment of the display panel driving circuit of this application;

[0047] Figure 7 This is a schematic diagram of the control waveforms of the third embodiment of the display panel driving circuit of this application;

[0048] Figure 8 This is a schematic diagram of the overall circuit connection of the display panel driving circuit of this application;

[0049] Figure 9 This is a connection diagram of the drive control model in the display panel drive circuit of this application;

[0050] Figure 10 This is a schematic diagram of the overall control waveform of the display panel driving circuit of this application;

[0051] Figure 11 This is another overall circuit diagram of the display panel driving circuit of this application;

[0052] Figure 12 This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0053] Explanation of icon numbers:

[0054] 110-1m0, First driving pixel module - m-th driving pixel module; G1-Gn, First gate driving voltage - n-th gate driving voltage; 11, Driving unit; 12, Multiplexing control unit; 200, Driving control module; G, Gate driving voltage; Scan, Partition control voltage; D, Data voltage; T1, First thin-film transistor; T2, Second thin-film transistor; Cp, Charging capacitor; 1A, First control subunit; 1B, Second control subunit; C1, First capacitor; T3, Third thin-film transistor; T4, Fourth thin-film transistor; T5, Fifth thin-film transistor; Gn-1, Gate driving voltage of the previous stage; Gn+1, Gate driving voltage of the next stage; T6, Sixth thin-film transistor; T7. Seventh thin-film transistor; A, First control signal; B, Second control signal; 210, Data output processing unit; 220, Partition output processing unit; T8, Eighth thin-film transistor; T9, Ninth thin-film transistor; VGL, Low voltage; VGH, High voltage; 230, Data receiver; 240, Output switching controller; 211, Data latch; 212, First level converter; 213, Analog-to-digital converter; 214, Analog output buffer; 221, Shift register; 222, Second level converter; 223, Digital output buffer; 224, Multiplexed signal controller; OUT, Output signal; 225, Timing controller; 226, D flip-flop; CLK, Clock signal; SW, Selection signal.

[0055] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0057] This application provides a display panel driving circuit, referring to... Figure 1 , Figure 1 This is a schematic diagram of the functional modules of an embodiment of a display panel driving circuit according to this application.

[0058] In this embodiment, the display panel driving circuit includes a multi-column driving pixel module 110-1m0 and a driving control module 200. Each column driving pixel module 110-1m0 includes:

[0059] Multiple driving units 11, with a gate driving voltage G connected to the first terminal of each driving unit 11;

[0060] The multiplexing control unit 12 is connected to the second end of the drive unit 11, and the second end of the multiplexing control unit 12 is connected to the third end of the drive unit 11.

[0061] The first end of the drive control module 200 is connected to the third end of the multiplexing control unit 12, the second end of the drive control module 200 is connected to the fourth end of the multiplexing control unit 12, the control end of the drive control module 200 is connected to the controlled end of the multiplexing control unit 12, the first end of the drive control module 200 is used to output the partition control voltage Scan, the second end of the drive control module 200 is used to output the data voltage D, and the drive control module 200 is used to control the drive unit 11 in at least one column of drive pixel modules 110-1m0 to sequentially write the partition control voltage Scan and the data voltage D, so as to realize the column direction partitioning of the display panel.

[0062] For example, as mobile terminals, automotive displays, wearable devices, and other electronic products develop towards higher resolutions, higher refresh rates, and larger sizes, partial refresh (PartialRefresh / PartialUpdate), as a dynamic power management technology, significantly reduces overall refresh power consumption by updating only the areas that change on the screen while keeping static areas unchanged. This is particularly suitable for applications where content updates are spatially uneven (such as text reading, user interface interaction, and game graphics). Currently, most mainstream partial refresh solutions adopt a vertical partition structure, which can be referenced... Figure 2 , Figure 2This is a schematic diagram of a single-partition display panel, where the panel is divided horizontally into two or more areas (displayed by different refresh rates in different areas). Partition refresh is achieved by independently controlling the scanning sequence of each row (or row group). However, with the increasing popularity of applications such as horizontal widescreen, split-screen multitasking, landscape gaming, and video playback, the demand for horizontal partitioning is becoming increasingly prominent. For example, refer to... Figure 3 , Figure 3 This diagram illustrates another partitioned display on the display panel. During landscape video playback, the central area of ​​the screen changes frequently, while the side black borders or subtitle areas remain relatively static. In a dual-screen vehicle setup, the left instrument panel area needs to refresh in real-time, while the right entertainment information area can be updated less frequently. Therefore, a new column-oriented partitioning control method is urgently needed to achieve column-oriented partitioning of the display panel.

[0063] In this embodiment, the display panel driving circuit includes multiple column driving pixel modules 110-1m0 and a driving control module 200. Each column driving pixel module 110-1m0 includes multiple driving units 11 and a multiplexed control unit 12. For example, the entire display panel has n There are m driving units 11, i.e., there are m driving pixel modules, namely the first driving pixel module 110 to the mth driving pixel module 1m0, and each driving pixel module includes n driving units 11, and each driving unit 11 is connected to a gate driving voltage G. At this time, the first terminal of the multiplexing control unit 12 is connected to the second terminal of the driving unit 11, and the second terminal of the multiplexing control unit 12 is connected to the third terminal of the driving unit 11. For example, the second terminal of the driving unit 11 is the port for receiving partition control voltage Scan for writing, and the third terminal of the driving unit 11 is the port for receiving data voltage D for writing. Thus, the conduction relationship inside the multiplexing control unit 12 can be controlled to write data voltage D or partition control voltage Scan. For example, the driving unit 11 can be configured to complete the display of the column driving pixel module by writing the data voltage D after the partition control voltage Scan allows writing. For example, if the partition control voltage Scan allows writing, it is written at a high level (e.g., 25V). If the partition control voltage Scan does not allow writing, the column driving pixel module is either black or remains in the previous frame. For example, if the partition control voltage Scan allows writing, it is written at a low level (e.g., -6V). In other words, writing the partition control voltage Scan and data voltage D sequentially includes at least the following scenarios: Scenario 1: After writing the partition control voltage Scan, writing the data voltage D will complete the display of the driving pixel module in that column; Scenario 2: When writing the partition control voltage Scan is not allowed, there is no need to consider whether to write the data voltage D, and the display will not be refreshed; Scenario 3: After writing the partition control voltage Scan, there is no case where the data voltage D is not written, that is, the operation of Scenario 1 is then performed on the driving unit 11 in one or more columns of driving pixel modules to achieve a high refresh rate display of one or more columns of driving pixel modules, while other operations that do not perform Scenario 1 will result in a black screen or retain the previous frame, because the whole process is to drive the display of the driving pixel modules of the vertical column to achieve column-oriented partitioning of the display panel.

[0064] For example, the sequential writing of partition control voltage Scan and data voltage D by the driving unit 11 can control the controlled end of the multiplexing control unit 12 from the control terminal of the driving control module 200. This allows the first terminal of the multiplexing control unit 12 to be connected to its third terminal, inputting the partition control voltage Scan to the second terminal of the driving unit 11 to achieve the writing of the partition control voltage Scan. Conversely, it can also connect the second terminal of the multiplexing control unit 12 to its fourth terminal, inputting the data voltage D to the third terminal of the driving unit 11 to achieve the writing of the data voltage D. This allows for the writing of both the partition control voltage Scan and the data voltage D, enabling targeted display control of the driving pixel modules in that column. For example, the entire process of sequentially writing the partition control voltage Scan and the data voltage D can be performed in a time-division multiplexing manner within a display frame, thus avoiding interference with the normal data voltage D writing process and ensuring the accuracy of the entire data writing and display. For instance, the writing of the partition control voltage Scan can be set within a time period of invalid data writing within a frame.

[0065] In some feasible embodiments, refer to Figure 4 , Figure 4 This is a circuit connection diagram of the first embodiment of the display panel driving circuit of this application. The driving unit 11 includes:

[0066] The first thin-film transistor T1 has its control terminal connected to the first terminal of the multiplexing control unit 12, and the first terminal of the first thin-film transistor T1 is connected to the gate drive voltage G.

[0067] The control terminal of the second thin-film transistor T2 is connected to the second terminal of the first thin-film transistor T1, and the first terminal of the second thin-film transistor T2 is connected to the second terminal of the multiplexing control unit 12.

[0068] The charging capacitor Cp has its first terminal connected to the second terminal of the second thin-film transistor T2, and its second terminal is grounded.

[0069] In this embodiment, a control transistor can be added to determine whether the data voltage D is connected to the pixel. A separate control signal is used to control whether the control transistor is turned on. In this case, the switching transistor for writing data is directly driven by the gate drive voltage G (described below using the control transistor scheme). However, for column pixels that do not need to write data, the gate drive voltage G will still turn on the switching transistor, leading to pixel voltage decay. This application improves the connection relationship between the first thin-film transistor T1 and the second thin-film transistor T2 (equivalent to the switching transistor in the control transistor scheme), thereby connecting the control terminal of the first thin-film transistor T1 to the first terminal of the multiplexing control unit 12. The first terminal of the first thin-film transistor T1 is connected to the gate drive voltage G. At this time, the second thin-film transistor T2 is not directly controlled by the gate drive voltage G, but indirectly controlled by the first thin-film transistor T1 and the partition control voltage Scan connected to the control terminal of the first thin-film transistor T1, so as to achieve independent column-level control of data writing and avoid pixel voltage decay in non-refresh areas. For example, refer to Figure 4 Assuming the gate drive voltage G signal and the partition control voltage Scan are 25 / -6V respectively, the following control instructions are provided for this drive unit 11:

[0070] In the driving unit 11, the pixels (i.e., the charging capacitor Cp) need to be written with data normally (high refresh rate area): At this time, the partition control voltage Scan write voltage is 25V, the gate drive voltage G refreshes line by line. When the gate drive voltage G is -6V, it is the holding stage. The first thin film transistor T1 is turned on, the voltage at point P2 is -6V, and the second thin film transistor T2 is turned off. When the gate drive voltage G is 25V, it is the data writing stage. The first thin film transistor T1 is turned on, the voltage at point P2 is 25V, the second thin film transistor T2 is turned on, and the data voltage D is written to the charging capacitor Cp normally. It is worth noting that after the partition control voltage Scan is written, the multiplexing control unit 12 will control the data voltage D to start writing to the charging capacitor Cp, and then when the gate drive voltage G is 25V, the entire data writing process begins.

[0071] In the low refresh rate region (where no data is written to the pixel in driving unit 11): At this time, the partition control voltage Scan write voltage is -6V, and the gate drive voltage G performs line-by-line refresh. When the gate drive voltage G is -6V, it is in the hold phase. The first thin-film transistor T1 is turned on (assuming Vth=-1V, then it is turned off when Vgs≤-1V), the voltage at point P2 is -6V, and the second thin-film transistor T2 is turned off. That is, at this time, the source of the first thin-film transistor T1 is -6V from the previous moment, so Vgs=0. When the gate drive voltage G is 25V, it is in the data writing phase, but this pixel does not need to be written. At this time, the gate of the first thin-film transistor T1 is -6V, the drain is 25V, and the source is -6V. The first thin-film transistor T1 will first turn on and then turn off. The source voltage of the first thin-film transistor T1 will rise slightly to about -5V. At this time, the second thin-film transistor T2 remains in the off state, and the data voltage D cannot be written to the charging capacitor Cp, thus completing the entire column display control. This is because the second thin-film transistor T2 is indirectly controlled by the first thin-film transistor T1 and the partition control voltage Scan connected to the control terminal of the first thin-film transistor T1, in order to avoid the pixel voltage attenuation problem and ensure the overall display effect.

[0072] In some feasible embodiments, refer to Figure 5 , Figure 5 This is a circuit connection diagram of the second embodiment of the display panel driving circuit of this application. The driving unit 11 further includes:

[0073] The first capacitor C1 has its first terminal connected to the control terminal of the first thin-film transistor T1, and its second terminal connected to the control terminal of the second thin-film transistor T2.

[0074] In this embodiment, a first capacitor C1 can be further connected between the control terminal of the first thin-film transistor T1 and the control terminal of the second thin-film transistor T2. This can optimize the conduction speed of the first thin-film transistor T1. For example, assuming the partition control voltage Scan is written at 25V, after the partition control voltage Scan is written, the multiplexing control unit 12 will disconnect the connection between the control terminal of the first thin-film transistor T1 and the first terminal of the drive control module 200. That is, in the following embodiment, the sixth thin-film transistor T6 is in the off state. At this time, the wire where the partition control voltage Scan is located is in a floating state. When the gate drive voltage G switches from -6V to 25V, the first thin-film transistor T1 turns on. During the process of the P2 potential gradually increasing, due to the effect of capacitive coupling, the P1 voltage will be coupled to a higher voltage. Here, assuming the coupling factor is 0.2, the P1 voltage increase is 0.2. (25-6) = 0.2 31 = 6V. At this point, the gate voltage of the first thin-film transistor T1 is 31V. Therefore, the first thin-film transistor T1 conducts more strongly, the voltage of P2 rises faster, and the pixel charges faster. Furthermore, the first capacitor C1 can improve the potential maintenance level of point P1. That is, after the P1 potential is written to the VBK (Vertical Blanking Period) through the partition control voltage Scan line, it will be in a floating state and will be written again after one frame scan is completed. This is because the first capacitor C1 can act as a storage capacitor, reducing leakage current at point P1. It should be noted that increasing the first capacitor C1 will increase the capacitance of the partition control voltage Scan line, thus increasing its power consumption.

[0075] Furthermore, in some feasible embodiments, reference is made to Figure 6 , Figure 6 This is a circuit connection diagram of the third embodiment of the display panel driving circuit of this application. The driving unit 11 further includes:

[0076] The first control subunit 1A has its first terminal connected to the first terminal of the multiplexing control unit 12, its second terminal connected to the gate drive voltage Gn-1 of the previous stage, and its third terminal connected to the control terminal of the first thin film transistor T1.

[0077] The second control subunit 1B has a first terminal connected to the gate drive voltage G, a second terminal connected to the gate drive voltage Gn+1 of the next stage, and a third terminal connected to the control terminal of the first thin film transistor T1.

[0078] The control terminal of the third thin-film transistor T3 is connected to the control terminal of the first thin-film transistor T1. The first terminal of the third thin-film transistor T3 is connected to the second terminal of the multiplexing control unit 12. The second terminal of the third thin-film transistor T3 is connected to the first terminal of the second thin-film transistor T2.

[0079] For example, because the drive unit 11 in the above embodiment also has a partition control voltage Scan line write voltage of 25V, after the gate drive voltage G of that row is scanned, the P2 voltage is -6V, and the Vgs of the first thin film transistor T1 is 31V. Long-term forward bias may cause the characteristics of the first thin film transistor T1 to shift, thereby affecting the P2 voltage write and affecting pixel charging. Moreover, the partition control voltage Scan line is a control line shared by a column of pixels. Considering the parasitic capacitance of the gate and drain of the first thin film transistor T1, the stability of the partition control voltage Scan line may be affected when the gate drive voltage G signal changes in each row. At the same time, since the gate drive voltage G line and the partition control voltage Scan line are routed in parallel, the coupling effect of parasitic capacitance also needs to be considered. Therefore, the entire driving unit 11 was further improved by adding a first control subunit 1A and a second control subunit 1B, which are controlled by the gate drive voltage Gn-1 of the previous stage and the gate drive voltage Gn+1 of the next stage, respectively. The first control subunit 1A can disconnect the connection between P1 and the partition control voltage Scan to avoid affecting the voltage of P2. Simultaneously, the second control subunit 1B can write a high voltage to P1 using the gate drive voltage Gn+1 of the next stage, thus avoiding forward bias. Finally, a third thin-film transistor T3 was added, with its control terminal connected to the control terminal of the first thin-film transistor T1. The first terminal of the third thin-film transistor T3 is connected to the second terminal of the multiplexing control unit 12, and the second terminal of the third thin-film transistor T3 is connected to the first terminal of the second thin-film transistor T2. This ensures that the input of the data voltage D is disconnected during the maintenance interval, further reducing the current leakage of the charging capacitor Cp and ensuring the display effect.

[0080] Furthermore, the first control subunit 1A includes:

[0081] The fourth thin-film transistor T4 has its control terminal connected to the gate drive voltage Gn-1 of the previous stage. The first terminal of the fourth thin-film transistor T4 is connected to the first terminal of the multiplexing control unit 12, and the second terminal of the fourth thin-film transistor T4 is connected to the control terminal of the first thin-film transistor T1.

[0082] The second control subunit 1B includes:

[0083] The fifth thin-film transistor T5 has its control terminal connected to the gate drive voltage Gn+1 of the next stage, its first terminal connected to the gate drive voltage G, and its second terminal connected to the control terminal of the first thin-film transistor T1.

[0084] In this embodiment, the first control subunit 1A adds a fourth thin-film transistor T4, and the control terminal of the fourth thin-film transistor T4 is connected to the gate drive voltage Gn-1 of the previous stage. When the high level of the gate drive voltage Gn-1 of the previous stage controls the fourth thin-film transistor T4 to turn on, the partition control voltage Scan is written to P1, thus disconnecting the connection between P1 and the partition control voltage Scan line to avoid affecting the voltage of P1 and even P2. The second control subunit 1B adds a fifth thin-film transistor T5 to reset the voltage at point P1. After the gate drive voltage Gn+1 of the next stage refreshes the voltage, the gate drive voltage Gn+1 of the next stage controls the fifth thin-film transistor T5 to turn on, writing the voltage of P1 as VGL. Therefore, during the maintenance phase, Vgs of the first thin-film transistor T1 is 0, avoiding forward bias. Further, refer to Figure 7 , Figure 7 This is a schematic diagram of the control waveform of the third embodiment of the display panel driving circuit of this application. By scanning and driving with different gate driving voltages G each time, the final continuous pull-up can be achieved so that Vgs=0 of the first thin film transistor T1 during the maintenance phase, thus avoiding forward bias.

[0085] In another embodiment, the control terminal of the drive control module 200 includes a first control terminal and a second control terminal, and the multiplexing control unit 12 includes:

[0086] The sixth thin-film transistor T6 has a control terminal connected to the first control terminal, a first terminal of the sixth thin-film transistor T6 connected to the control terminal of the first thin-film transistor T1 in the drive unit 11, and a second terminal of the sixth thin-film transistor T6 connected to the first terminal of the drive control module 200.

[0087] The seventh thin-film transistor T7 has its control terminal connected to the second control terminal, its first terminal connected to the first terminal of the second thin-film transistor T2 in the drive unit 11, and its second terminal connected to the second terminal of the drive control module 200.

[0088] In this embodiment, addressing the issue of the control tube scheme described in the above embodiment requiring 2m control lines, i.e., needing to simultaneously bind data signal lines and partition control lines in the panel bonding area, the number of lines required doubles, potentially increasing costs and expanding the display area by increasing the bezel. This application proposes a control scheme using a multiplexed control unit 12 to multiplex control partitioning and data writing. This is achieved by designing a sixth thin-film transistor T6 and a seventh thin-film transistor T7. The sixth thin-film transistor T6 is controlled by a first control signal A from a first control terminal to connect the control terminal of the first thin-film transistor T1 in the driving unit 11 to the first terminal of the driving control module 200, thereby writing the partition control voltage Scan to the control terminal of the first thin-film transistor T1. The seventh thin-film transistor T7 is controlled by a second control signal B from a second control terminal to connect the first terminal of the second thin-film transistor T2 in the driving unit 11 to the second terminal of the driving control module 200, thereby writing the data voltage D to the first terminal of the second thin-film transistor T2. This multiplexing of the data voltage D line and the partition control voltage Scan line reduces the overall control cost. For example, refer to... Figure 8 , Figure 8This is a schematic diagram of the overall circuit connection of the display panel driving circuit of this application. The partition control voltage Scan line and the data voltage D line are routed in parallel. A multiplexed control area is designed at the lower part of the display area. The output signal OUT line, partition control voltage Scan line, and data voltage D line can be connected through two sets of sixth thin-film transistors T6 and seventh thin-film transistors T7. Of course, the switching of multiplexed control should be completed within the vertical display blanking interval. It should be noted that since the sixth thin-film transistor T6 only controls the writing of the partition control voltage Scan high and low voltages, and the writing time is longer than the pixel charging time in the display area, the W / L ratio of the sixth thin-film transistor T6 can be designed to be smaller than that of the seventh thin-film transistor T7 to reduce the area of ​​the lower bezel. Furthermore, the drive control module 200 can be a source driver, and a partition output processing unit 220 is added inside it, which is the module that generates the partition control voltage Scan signal. This source driver mainly performs two functions: ① In the VBK range, the sixth thin-film transistor T6 on the output multiplexing control signal control panel is turned on, and the seventh thin-film transistor T7 is turned off. At the same time, the output signal OUT line is connected to the internal partition output processing unit 220 to configure the partition control voltage Scan of each column of pixels, so as to control whether the column of pixels is refreshed; ② In the normal display range, the sixth thin-film transistor T6 on the output multiplexing control signal control panel is turned on and off, and the seventh thin-film transistor T7 is turned on. At the same time, the output signal OUT line is connected to the internal data output processing unit 210, such as OutputBuffer, to output the analog voltage of each gray level normally. Then, by using the routing method of multiplexing data voltage D line and partition control voltage Scan line, a multiplexing control unit 12 can be set at the bottom of the panel to reduce the number of bonding pins and compress the bottom bezel.

[0089] It should be noted that the transistors used in all embodiments of this application can be TFTs (Thin Film Transistors), field-effect transistors, or other devices with similar characteristics. Since the second terminal and drain of the transistors used here are symmetrical, their source and drain terminals are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. Figure 4 In the diagram, the G (gate), D (drain), and S (source) terminals of the first thin-film transistor T1 are labeled with port characteristics, where G is the control terminal of T1, S is the second terminal of T1, and D is the first terminal of T1. The remaining transistors can be determined according to... Figure 4The configuration of the transistors is defined as follows: the middle terminal of each transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the transistors used in the embodiments of this application may include both P-type and N-type transistors. P-type transistors conduct when the gate is low and are cut off when the gate is high, while N-type transistors conduct when the gate is high and are cut off when the gate is low. The conduction modes of the corresponding N-type and P-type transistors are different, and the corresponding control methods also differ. The specific control depends on the actual transistor and is not limited here.

[0090] Furthermore, in some feasible embodiments, the first thin-film transistor T1 to the ninth thin-film transistor T9 can be a low-temperature polycrystalline silicon thin-film transistor, an oxide semiconductor thin-film transistor, or an amorphous silicon thin-film transistor. The transistors in the driving circuit provided in this application embodiment are all made of the same material, thereby avoiding the influence of differences between transistors of different materials on the driving circuit.

[0091] In another embodiment, reference Figure 9 , Figure 9 This is a connection diagram of the drive control model in the display panel drive circuit of this application. The drive control module 200 includes:

[0092] Data receiver 230, the first end of data receiver 230 is connected to driver chip;

[0093] The data output processing unit 210 has its first end connected to the second end of the data receiver 230.

[0094] The partition output processing unit 220 has its first terminal connected to the third terminal of the data receiver 230, its second terminal connected to the fourth terminal of the multiplexing control unit 12, and its third terminal connected to the scanning voltage.

[0095] The output switching controller 240 has its first terminal connected to the fourth terminal of the partition output processing unit 220, its second terminal connected to the second terminal of the data output processing unit 210, its third terminal connected to the third terminal of the multiplexing control unit 12, and its fourth terminal connected to the fourth terminal of the multiplexing control unit 12.

[0096] In this embodiment, a partitioned output processing unit 220 and an output switching controller 240 are added to the drive control module 200. The principle of the output switching controller 240 is as follows: Figure 8The eighth thin-film transistor T8 and the ninth thin-film transistor T9 have the same function, namely, selecting the partition output processing unit 220 or the data output processing unit 210 for output control. The partition output processing unit 220 includes a multiplexing signal controller 224, a shift register 221, a second level converter 222, and a digital output buffer 223. The multiplexing signal controller 224 is a multiplexing control signal generation module used to generate control signals for the multiplexing control unit 12. This signal is connected to the gates of the panel multiplexing control sixth thin-film transistor T6 and the seventh thin-film transistor T7 to control whether the source driver output (i.e., the output signal OUT output by the output switching controller 240) is connected to the partition control voltage Scan line or the data voltage D line. This signal is high only in the VBK range, i.e., connected to the partition control voltage Scan line, and the sixth thin-film transistor T6 and the seventh thin-film transistor T7 must not be high simultaneously. In the pixel scan range, it is low, i.e., connected to the data voltage D line. Shift register 221 serves as an output channel. Assuming the source driver has 960 output channels, this is represented by 960 shift registers. Of course, 1:6 or 1:8 multiplexing can be used to reduce the number of shift registers. The function of shift register 221 is to receive scan control signals written by the timing controller in the VBK range, using 1 bit of data to indicate whether a column of pixels needs to be refreshed. For example, if the source driver controls 960 columns of pixels, the timing controller transmits the following serial data 00..11..00 through a data package. The shifted data converts the serial data into parallel data and sends it to the second level converter 222. The second level converter 222 converts the low-level data (3.3V / 0V) into a higher potential (high voltage VGH / low voltage VGL) control signal. This signal is then output through the digital output buffer 223, which is typically composed of an even number of CMOS inverters to enhance driving capability. The final signal reaches the output switching controller 240: only when the first control signal A is high, the partition control voltage Scan is used as the output signal OUT, and is connected to the partition control voltage Scan line through the sixth thin film transistor T6; while in the pixel scanning interval, the analog output buffer 214 is connected to the output signal OUT through the output switching controller 240, and is connected to the data voltage D line through the seventh thin film transistor T7. Of course, the entire control can also use other components, which will not be described one by one here.

[0097] For example, the first end of the data receiver 230 is connected to the driver chip, which can then determine whether partitioned display is required based on the driver chip. Based on this information, the control signals for the sixth thin-film transistor T6 and the seventh thin-film transistor T7 are determined to write the data voltage D or partition control voltage Scan to the driver unit 11. Of course, the driver chip also has the function of outputting other driving instructions, such as refresh rate, brightness, color, etc. In this application, it is only necessary to further use the relevant information of partitioned display to control the output information of the sixth thin-film transistor T6, the seventh thin-film transistor T7, and the output switching controller 240.

[0098] Based on the above embodiments of the display panel driving circuit, a first embodiment of the partition control method of this application is proposed, the partition control method including:

[0099] When the driving pixel module 110-1m0 is the target driving pixel module that needs to be displayed in partitions, in the invalid data interval of the current frame, the control multiplexing control unit 12 connects the second end of the driving unit 11 and the first end of the driving control module 200 to write the partition control voltage Scan into the driving unit 11 in the target driving pixel module.

[0100] Within the valid data range of the current frame, the control multiplexing control unit 12 connects the third terminal of the drive unit 11 and the second terminal of the drive control module 200 to write the data voltage D into the drive unit 11 in the target drive pixel module.

[0101] In this embodiment, when the driving pixel module 110-1m0 is the target driving pixel module that needs to be displayed in partitions, the multiplexing control unit 12 can be controlled to connect the second terminal of the driving unit 11 and the first terminal of the driving control module 200 within the invalid data interval of the current frame, so as to write the partition control voltage Scan into the driving unit 11 in the target driving pixel module. The partition control voltage Scan written at this time is a voltage that allows refreshing, such as 25V. After writing the partition control voltage Scan, within the valid data interval of the current frame, the multiplexing control unit 12 is controlled to connect the third terminal of the driving unit 11 and the first terminal of the driving control module 200. At the second end of the motion control module 200, data voltage D is written to the driving unit 11 in the target driving pixel module, thereby controlling the target driving pixel module to display. Other non-target driving pixel modules that do not require display can be directly written with partition control voltage Scan. However, the partition control voltage Scan is a voltage that is not allowed to be refreshed, such as -6V. Alternatively, the partition control voltage Scan can be a voltage that is allowed to be refreshed, but subsequent data voltage D is not written, or the same data voltage D as the previous frame is written, to complete the column-oriented partitioned display of the entire display panel, thereby expanding the functionality of the display panel. Further details can be found in... Figure 10, Figure 10 This is a schematic diagram of the overall control waveform of the display panel driving circuit of this application. Assuming that in frame N, both the first and third column pixels need to be written to data, while in frame N+1, only the third column pixels need to be written to data, it can be understood that the area where the first column pixels are located is a low refresh rate area, and the area where the third column pixels are located is a high refresh rate area. Therefore, the signals of the first and third columns are explained as follows:

[0102] Data: This refers to the data voltage D, which is a high-speed differential signal input from the timing controller to the source driver. Each frame of data includes an invalid data range (VBK) and a valid data range (including the configuration command cmd used to configure the source driver startup and the display RGB data). At this time, the data of the partition control voltage Scan is selected to be transmitted in the VBK range, without occupying the time for valid data transmission.

[0103] iSTB: Output control signal of the source driver. When it is high, the output signal OUT is not output and it is in the Hi-z state. At the beginning of the falling edge, all channels start to output pixel drive voltage. This signal is usually a 3.3V / 0V square wave signal.

[0104] A / B: Control signals of the multiplexed control unit 12 on the panel, wherein the rising edge of the first control signal A needs to be later than the falling edge of the second control signal B, i.e., t1≥0; correspondingly, the falling edge of the first control signal A also needs to be earlier than the rising edge of the second control signal B. That is, the interval in which the sixth thin-film transistor T6 is turned on needs to ensure that the seventh thin-film transistor T7 is turned off, which is a 25 / -6V square wave signal in this embodiment.

[0105] DScan1 / DScan3 (where D stands for SourceDriver): This is the partition control voltage Scan for the first / third column of pixels. This signal originates from the partition output processing unit 220 inside the source driver. It should be noted that the switching time of the partition control voltage Scan signal level must be later than the falling edge of the first control signal A, as shown in Figure t2≥0. In this embodiment, it is a square wave signal of 25 / -6V.

[0106] OUT1 / OUT3: The first / third column output channels of the source driver. During the high level range of the first control signal A, the output signal OUT is connected to the digital output buffer 223 of the partition output processing unit 220. At this time, the output signal is a control signal of 25 / -6V. During the low level range of the first control signal A, the output signal OUT is connected to the analog output buffer 214. At this time, the output signal is a pixel driving voltage of 0V~15V.

[0107] PScan1 / PScan3 (where P stands for Panel): The partition control voltage Scan for the first / third column of pixels remains at 25V throughout the Nth frame, so all pixels in this column will be refreshed; in the N+1th frame, the partition control voltage Scan for the first column remains at -6V, and the pixels in this column will not be refreshed. The entire control process outputs the partition control voltage Scan during the vertical blanking period to achieve partition configuration without the need for an external control chip and without affecting normal data display.

[0108] In another embodiment, refer to Figure 11 , Figure 11 This is another overall circuit diagram of the display panel driving circuit of this application. Regarding the panel architecture, if LTPS technology is used, both N-type and P-type TFTs can be fabricated on the panel simultaneously. A D flip-flop 226 architecture can be considered to implement a shift register function on the panel, thereby enabling the writing of the partition control voltage Scan. Of course, it should be considered that this scheme requires the fabrication of a large number of TFTs; a 1:2 or 1:3 shift register design can be used. It should also be noted that, to reduce power consumption, this shift register should only operate on devices writing partition control voltage Scan data in the VBK interval. In this case, only the selection signal SW, the clock signal CLK, and the partition control voltage Scan are needed for control.

[0109] Furthermore, when the multiplexing control unit 12 is connected to the second end of the drive unit 11 and the first end of the drive control module 200, the sixth thin-film transistor T6 in the multiplexing control unit 12 is turned on, and the seventh thin-film transistor T7 in the multiplexing control unit 12 is turned off.

[0110] When the multiplexing control unit 12 is connected to the third terminal of the drive unit 11 and the second terminal of the drive control module 200, the sixth thin-film transistor T6 in the multiplexing control unit 12 is turned off, and the seventh thin-film transistor T7 in the multiplexing control unit 12 is turned on.

[0111] In this embodiment, it can be referred to Figure 8When partition control voltage Scan needs to be written, the sixth thin-film transistor T6 is turned on, and the seventh thin-film transistor T7 in the multiplexing control unit 12 is turned off. At this time, the multiplexing control unit 12 connects the second terminal of the driving unit 11 and the first terminal of the driving control module 200, and disconnects the third terminal of the driving unit 11 and the second terminal of the driving control module 200, thereby realizing partition control voltage Scan writing independently. When data voltage D needs to be written, the sixth thin-film transistor T6 is turned off, and the seventh thin-film transistor T7 in the multiplexing control unit 12 is turned on. At this time, the multiplexing control unit 12 disconnects the second terminal of the driving unit 11 and the first terminal of the driving control module 200, and connects the third terminal of the driving unit 11 and the second terminal of the driving control module 200, thereby realizing data voltage D writing independently. After partition control voltage Scan and data voltage D are written in sequence, column driving of the target driving pixel module (column pixel) can be realized.

[0112] Furthermore, this application also proposes a liquid crystal display panel, which includes at least a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes a display panel driving circuit. The liquid crystal display panel may also include the display panel driving circuit described above, see reference. Figure 12 , Figure 12 This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0113] like Figure 12 As shown, the liquid crystal display panel may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0114] Those skilled in the art will understand that Figure 12The structure shown does not constitute a limitation on the liquid crystal display panel and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0115] like Figure 12 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.

[0116] exist Figure 12 In the liquid crystal display panel shown, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the liquid crystal display panel. The liquid crystal display panel calls the computer program stored in the memory 1005 through the processor 1001 and controls the above-mentioned display panel driving circuit.

[0117] The various embodiments of the liquid crystal display panel of this application can be referred to the various embodiments of the display panel driving circuit of this application, and will not be repeated here.

[0118] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0119] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of the various embodiments of this application.

[0121] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel driving circuit, characterized in that, The display panel driving circuit includes multiple columns of driving pixel modules and a driving control module, each column of the driving pixel module including: Multiple driving units, wherein a gate driving voltage is connected to the first terminal of one of the driving units; A multiplexing control unit, wherein a first terminal of the multiplexing control unit is connected to a second terminal of the drive unit, and the second terminal of the multiplexing control unit is connected to a third terminal of the drive unit, the drive unit comprising: A first thin-film transistor, wherein the control terminal of the first thin-film transistor is connected to the first terminal of the multiplexing control unit, and the first terminal of the first thin-film transistor is connected to the gate driving voltage; A second thin-film transistor, wherein the control terminal of the second thin-film transistor is connected to the second terminal of the first thin-film transistor, and the first terminal of the second thin-film transistor is connected to the second terminal of the multiplexing control unit; A charging capacitor, wherein a first terminal of the charging capacitor is connected to a second terminal of the second thin-film transistor, and the second terminal of the charging capacitor is grounded; A first capacitor, wherein a first terminal of the first capacitor is connected to the control terminal of the first thin-film transistor, and a second terminal of the first capacitor is connected to the control terminal of the second thin-film transistor; The first control subunit has a first terminal connected to the first terminal of the multiplexing control unit, a second terminal connected to the gate drive voltage of the previous stage, and a third terminal connected to the control terminal of the first thin-film transistor. The second control subunit has a first terminal connected to the gate drive voltage, a second terminal connected to the gate drive voltage of the next stage, and a third terminal connected to the control terminal of the first thin-film transistor. A third thin-film transistor, wherein the control terminal of the third thin-film transistor is connected to the control terminal of the first thin-film transistor, the first terminal of the third thin-film transistor is connected to the second terminal of the multiplexing control unit, and the second terminal of the third thin-film transistor is connected to the first terminal of the second thin-film transistor; The first end of the drive control module is connected to the third end of the multiplexing control unit, the second end of the drive control module is connected to the fourth end of the multiplexing control unit, the control end of the drive control module is connected to the controlled end of the multiplexing control unit, the first end of the drive control module is used to output partition control voltage, the second end of the drive control module is used to output data voltage, and the drive control module is used to control the drive units in at least one column of the drive pixel modules to sequentially write the partition control voltage and the data voltage to realize the column direction partitioning of the display panel.

2. The display panel driving circuit as described in claim 1, characterized in that, The first control subunit includes: The fourth thin-film transistor has its control terminal connected to the gate drive voltage of the previous stage, its first terminal connected to the first terminal of the multiplexing control unit, and its second terminal connected to the control terminal of the first thin-film transistor. The second control subunit includes: A fifth thin-film transistor, wherein the control terminal of the fifth thin-film transistor is connected to the gate drive voltage of the next stage, the first terminal of the fifth thin-film transistor is connected to the gate drive voltage, and the second terminal of the fifth thin-film transistor is connected to the control terminal of the first thin-film transistor.

3. The display panel driving circuit as described in claim 1, characterized in that, The control terminal of the drive control module includes a first control terminal and a second control terminal, and the multiplexing control unit includes: A sixth thin-film transistor, wherein the control terminal of the sixth thin-film transistor is connected to the first control terminal, the first terminal of the sixth thin-film transistor is connected to the control terminal of the first thin-film transistor in the driving unit, and the second terminal of the sixth thin-film transistor is connected to the first terminal of the driving control module; A seventh thin-film transistor, wherein the control terminal of the seventh thin-film transistor is connected to the second control terminal, the first terminal of the seventh thin-film transistor is connected to the first terminal of the second thin-film transistor in the driving unit, and the second terminal of the seventh thin-film transistor is connected to the second terminal of the driving control module.

4. The display panel driving circuit as described in claim 1, characterized in that, The drive control module includes: A data receiver, the first end of which is connected to a driver chip; A data output processing unit, wherein a first end of the data output processing unit is connected to a second end of the data receiver; A partition output processing unit, wherein the first end of the partition output processing unit is connected to the third end of the data receiver, the second end of the partition output processing unit is connected to the fourth end of the multiplexing control unit, and the third end of the partition output processing unit is connected to a scanning voltage; An output switching controller is provided, wherein a first terminal of the output switching controller is connected to a fourth terminal of the partition output processing unit, a second terminal of the output switching controller is connected to a second terminal of the data output processing unit, a third terminal of the output switching controller is connected to a third terminal of the multiplexing control unit, and a fourth terminal of the output switching controller is connected to a fourth terminal of the multiplexing control unit.

5. A partition control method, characterized in that, The partition control method uses the display panel driving circuit as described in any one of claims 1 to 4, and the partition control method includes: When the driving pixel module is a target driving pixel module that needs to be displayed in partitions, in the invalid data interval of the current frame, the multiplexing control unit is controlled to connect the second end of the driving unit and the first end of the driving control module so as to write the partition control voltage into the driving unit in the target driving pixel module. Within the valid data range of the current frame, the multiplexing control unit is controlled to connect the third terminal of the driving unit and the second terminal of the driving control module to write the data voltage into the driving unit in the target driving pixel module.

6. The partition control method as described in claim 5, characterized in that, The partition control method further includes: When the multiplexing control unit connects the second end of the drive unit and the first end of the drive control module, the sixth thin-film transistor in the multiplexing control unit is turned on, and the seventh thin-film transistor in the multiplexing control unit is turned off. When the multiplexing control unit connects the third terminal of the drive unit and the second terminal of the drive control module, the sixth thin-film transistor in the multiplexing control unit is turned off, and the seventh thin-film transistor in the multiplexing control unit is turned on.

7. A liquid crystal display panel, characterized in that, The liquid crystal display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a display panel driving circuit as described in any one of claims 1 to 4.

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