Incremental analog-to-digital converter and signal processing method based on passive noise shaping

Abstract

The application provides a kind of delta-sigma analog-digital converter based on passive noise shaping and signal processing method, which can be applied to quantization technical field.The delta-sigma analog-digital converter includes: input integration circuit, configured to generate j-1 low bit integration voltage according to input signal from signal input end;According to input signal, generate k high bit integration voltage;Passive amplification circuit, configured to obtain k gain voltage according to k high bit integration voltage based on predetermined amplification coefficient;Passive noise shaping circuit, configured to obtain k passive integration voltage by passive integration on k high bit integration voltage, and obtain k high bit gain voltage by passive gain on k passive integration voltage using k gain voltage;Quantization circuit, configured to quantize M1 low bit integration voltages respectively in M1 periods, generate M1 coarse quantization values;Quantize M2 high bit gain voltages respectively in M2 periods, generate M2 fine quantization values.

Description

Technical Field

[0001] This invention relates to the field of quantization technology, and more specifically to an incremental analog-to-digital converter and signal processing method based on passive noise shaping. Background Technology

[0002] Analog-to-digital converters (ADCs) can include Nyquist ADCs and oversampling ADCs. For example, oversampling ADCs can include Δ-Σ ADCs. In instrumentation fields such as sensor interfaces, array image processing, or digital voltmeters, there are stringent requirements for the accuracy, power consumption, and area of ​​ADCs. Incremental ADCs (IADCs) are well-suited for these multi-channel applications. However, incremental ADCs struggle to simultaneously meet the demands for high accuracy and low power consumption. Summary of the Invention

[0003] In view of the above problems, the present invention provides an incremental analog-to-digital converter and signal processing method based on passive noise shaping.

[0004] According to one aspect of the present invention, an incremental analog-to-digital converter based on passive noise shaping is provided, comprising: an input integrator circuit configured to generate a j-th low-order integral voltage based on an input signal from a signal input terminal during the j-th period of M1 periods, under the control of a (j-1)-th coarse quantization value; and to generate a k-th high-order integral voltage based on an input signal during the k-th period of M2 periods following M1 periods, under the control of a (k-1)-th fine quantization value; wherein j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k; and a passive amplifier circuit configured to, during the integration phase of the k-th period, based on a predetermined... The amplification factor is obtained by using the k-th high-order integral voltage to obtain the k-th gain voltage. The passive noise shaping circuit is configured to passively integrate the k-th high-order integral voltage during the integration phase to obtain the k-th passive integral voltage, and is electrically connected to the passive amplifier circuit during the gain phase of the k-th cycle to passively gain the k-th passive integral voltage using the k-th gain voltage to obtain the k-th high-order gain voltage. The quantization circuit is configured to quantize M1 low-order integral voltages in M1 cycles to generate M1 coarse quantization values; and to quantize M2 high-order gain voltages in M2 cycles to generate M2 fine quantization values. The fine quantization values ​​have higher precision than the coarse quantization values.

[0005] According to another aspect of the present invention, a signal processing method is provided, applied to the above-described incremental analog-to-digital converter. The signal processing method includes: an input integrator circuit generating a j-th low-order integrated voltage based on an input signal from a signal input terminal during the j-th period of M1 periods, under the control of a (j-1)-th coarse quantization value; and generating a k-th high-order integrated voltage based on the input signal during the k-th period of the M2 periods following the M1 periods, under the control of a (k-1)-th fine quantization value; wherein j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k; a passive amplifier circuit during the integration phase of the k-th period... Based on a predetermined amplification factor, the k-th gain voltage is obtained from the k-th high-order integral voltage. During the integration phase, the passive noise shaping circuit passively integrates the k-th high-order integral voltage to obtain the k-th passive integral voltage. During the gain phase of the k-th cycle, it is electrically connected to the passive amplifier circuit so that the k-th gain voltage can be used to passively gain the k-th passive integral voltage to obtain the k-th high-order gain voltage. The quantization circuit quantizes M1 low-order integral voltages in M1 cycles to generate M1 coarse quantization values. It quantizes M2 high-order gain voltages in M2 cycles to generate M2 fine quantization values. The fine quantization values ​​have higher precision than the coarse quantization values.

[0006] According to an embodiment of the present invention, an incremental analog-to-digital converter (ADC) based on passive noise shaping is provided. In this incremental ADC, the input integrator circuit can generate M1 low-order integrated voltages in M1 cycles. The quantization circuit can quantize the M1 low-order integrated voltages to obtain M1 coarse quantization values. Thus, the first step of quantization is completed. Further, in the k-th cycle of M2 cycles, the input integrator circuit can generate the k-th high-order integrated voltage according to the input signal under the control of the (k-1)-th fine quantization value. Subsequently, during the integration phase, the passive noise shaping circuit can passively integrate the k-th high-order integrated voltage to obtain the k-th passive integrated voltage. Furthermore, the passive amplifier circuit can obtain the k-th gain voltage based on the k-th high-order integrated voltage according to a predetermined amplification factor. Subsequently, the passive amplifier circuit can be electrically connected to the passive noise shaping circuit and provide the k-th gain voltage to the passive noise shaping circuit to passively gain the k-th passive integrated voltage to obtain the k-th high-order gain voltage. Thus, by using the k-th gain voltage to passively amplify the k-th passive integral voltage generated by passive integration, noise shaping of the k-th higher-order integral voltage can be achieved, resulting in the k-th higher-order gain voltage. Subsequently, the vectorization circuit provides the k-th higher-order gain voltage, enabling the quantization circuit to obtain a finer quantization value with relatively higher accuracy. Furthermore, since noise shaping of the k-th higher-order integral voltage is achieved through a combination of passive integration and passive gain, the number of active components in the analog-to-digital converter (ADC) is reduced. Therefore, while achieving the same quantization accuracy as some other ADC solutions, the ADC of this embodiment has lower power consumption, simultaneously meeting the requirements of high accuracy and low power consumption. Attached Figure Description

[0007] The above-mentioned contents, other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, which will be described in conjunction with the drawings.

[0008] Figure 1 A schematic diagram of an incremental analog-to-digital converter according to an embodiment of the present invention is shown.

[0009] Figure 2A A schematic diagram of an incremental analog-to-digital converter according to another embodiment of the present invention is shown.

[0010] Figure 2B The present invention is shown Figure 2A Timing diagram of the incremental analog-to-digital converter in the embodiment.

[0011] Figure 2C A schematic diagram of charge redistribution according to an embodiment of the present invention is shown.

[0012] Figure 2DA schematic diagram of the parallel connection of the integrating capacitors during the integration stage is shown according to an embodiment of the present invention.

[0013] Figure 2E A schematic diagram of the series connection of the integrating capacitor during the gain stage according to an embodiment of the present invention is shown.

[0014] Figure 3 A schematic diagram of the overall system of an analog-to-digital converter according to an embodiment of the present invention is shown.

[0015] Figure 4 A schematic diagram of an analog-to-digital converter in the first step of the quantization process according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of the analog-to-digital converter in the second step of the quantization process according to an embodiment of the present invention is shown.

[0017] Figure 6 A schematic diagram of the analog-to-digital converter quantizing the residual voltage in the second quantization process according to an embodiment of the present invention is shown.

[0018] Figure 7 A schematic diagram of a signal processing method according to an embodiment of the present invention is shown. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0022] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0023] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, where the range of similar situations is within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] Analog-to-digital converters (ADCs) can include Nyquist ADCs and oversampling ADCs. A Nyquist ADC is one whose sampling frequency and signal bandwidth satisfy the Nyquist sampling theorem, while an oversampling ADC has a sampling frequency higher than the Nyquist frequency. For example, Nyquist ADCs can include pipelined ADCs, flash ADCs, and successive approximation ADCs. However, due to limitations such as device mismatch and design and manufacturing process deviations, there are bottlenecks in improving the accuracy of Nyquist ADCs.

[0025] Oversampling analog-to-digital converters (ADCs) can include Δ-Σ ADCs. These converters, utilizing noise shaping techniques combined with high sampling frequencies, can effectively improve the signal-to-noise ratio of the output signal. Furthermore, they have relatively lower requirements for analog device matching, making them more suitable for high-precision applications such as data acquisition or medical imaging. However, these ADCs suffer from drawbacks such as slower speed and higher power consumption.

[0026] In some solutions, the accuracy of a delta-Σ (Δ-Σ) analog-to-digital converter (ADC) can be improved by increasing its order and oversampling ratio (OSR). However, single-loop multi-order structures suffer from stability issues. Furthermore, the higher the order of this structure, the worse the loop stability. Multi-stage noise shaping (MASH) technology can effectively alleviate this problem. However, structures based on this technology are prone to noise leakage due to mismatch between analog and digital transfer functions, thus limiting accuracy improvements.

[0027] In instrumentation fields such as sensor interfaces, array image processing, and digital voltmeters, stringent requirements are placed on the accuracy, power consumption, and area of ​​analog-to-digital converters (ADCs). Incremental ADCs, with their global reset pulse, can clear residual signals from oversampling modulators and decimation filters, making them well-suited for these multi-channel applications. For example, such ADCs can be used in wearable device image sensors, scales, digital voltmeters, temperature / magnetic / pressure sensors, and biopotential sensors. For battery-powered integrated sensors, high-resolution ADCs that balance energy and area efficiency are particularly important.

[0028] Furthermore, incremental Δ-Σ analog-to-digital converters (ADCs) are adaptable to the aforementioned fields and the biological field because they require a reset after each analog-to-digital conversion, resulting in high accuracy. Specifically, biological signals generally have low frequency bands, mostly below 10kHz. For example, the frequency range of an electroencephalogram (EEG) signal is 0.1Hz-50Hz, and that of a portable electrocardiogram (ECG) signal is 0.5Hz-100Hz; the frequency of neural signals is also within 10kHz. Therefore, ADCs used for biological signal acquisition do not need to operate at high frequencies and are allowed to operate within a narrow signal bandwidth. Even so, to ensure conversion accuracy, the accuracy of such ADCs must be at least 14 bits, or even higher. Simultaneously, considering the reset requirements of ADCs in multi-channel biological signal acquisition systems, incremental Δ-Σ ADCs are suitable for applications with reset, high accuracy requirements, and low signal bandwidth, making them appropriate for this field.

[0029] The incremental delta-sigm (Δ-Σ) analog-to-digital converter (ADC) combines the advantages of both dual-sigm ADCs and Δ-Σ ADCs, making it a preferred solution for low-frequency, high-precision sensor interfaces. Its built-in modulator achieves high-precision conversion through noise shaping. Unlike some ADCs, the incremental Δ-Σ ADC operates in an intermittent mode: after each conversion cycle lasting several clock cycles, a reset signal clears all data from memory elements such as the modulator's integrator and the storage registers of the decimation filter, completing one sampling-conversion cycle. This characteristic makes it highly efficient in multi-channel multiplexing scenarios for high-precision, low-frequency signals. Compared to dual-sigm ADCs, incremental Δ-Σ ADCs offer higher resolution and operating frequency; compared to successive approximation ADCs, incremental Δ-Σ ADCs offer superior accuracy and have broad application prospects.

[0030] However, incremental Δ-Σ analog-to-digital converters (ADCs) are mutually constrained in terms of accuracy and power consumption. For example, in incremental Δ-Σ ADCs, a transfer function is constructed based on active devices such as amplifiers to perform active noise shaping. However, amplifiers consume a lot of power. Therefore, although this type of ADC has good accuracy, the extensive use of active devices such as amplifiers results in significant power consumption.

[0031] In view of this, embodiments of the present invention provide an incremental Δ-Σ analog-to-digital converter (ADC) based on passive noise shaping. This ADC employs a two-step extended counting method for analog-to-digital conversion (or quantization). Compared to the multi-stage noise shaping structure described above, the two-step extended counting method used in this embodiment has a simpler digital decimation filter structure and does not require strict matching between analog and digital filter characteristics, thus achieving higher accuracy. Furthermore, compared to incremental Δ-Σ ADCs in some other solutions, the ADC in this embodiment uses passive noise shaping instead of active noise shaping in the second step of the extended technique, that is, using passive amplifier circuits and passive noise shaping circuits instead of active amplifiers, reducing power consumption. Therefore, the ADC in this embodiment has relatively low power consumption at the same signal-to-noise ratio, balancing the requirements of high accuracy and low power consumption. The following description is in conjunction with the accompanying drawings.

[0032] Figure 1 A schematic diagram of an incremental analog-to-digital converter according to an embodiment of the present invention is shown.

[0033] like Figure 1 As shown, the incremental analog-to-digital converter of this embodiment includes an input integration circuit, a passive amplifier circuit, a passive noise shaping circuit, and a quantization circuit.

[0034] The input integrator circuit receives the input signal and integrates it over M1 cycles to generate M1 low-order integrated voltages. The input signal can be analog. Furthermore, the circuit integrates the input signal over M2 cycles following the M1 cycles to generate M2 high-order integrated voltages. The M1 cycles correspond to the first quantization step (coarse quantization), and the M2 cycles correspond to the second quantization step (fine quantization). It should be understood that the second quantization step essentially quantizes the error between the coarse quantization value obtained in the first step and the input signal, to obtain a fine quantization value with higher accuracy than the coarse quantization value. For example, the quantization circuit can quantize the M1 low-order integrated voltages over M1 cycles to generate M1 coarse quantization values, and then generate M2 fine quantization values ​​corresponding to the M2 high-order integrated voltages over M2 cycles. Based on this, an accurate target quantized value can be obtained from the M1 coarse quantization values ​​and the M2 fine quantization values.

[0035] Specifically, taking the j-th cycle out of M1 cycles as an example, the input integrator circuit, under the control of the (j-1)-th coarse quantization value, generates the j-th low-order integrated voltage based on the input signal from the signal input terminal. Subsequently, the quantization circuit can generate the j-th coarse quantization value in the j-th cycle based on the j-th low-order integrated voltage. This process is repeated to obtain M1 coarse quantization values.

[0036] Further, taking the kth cycle out of M2 cycles as an example, the input integrator circuit, under the control of the (k-1)th fine quantization value, generates the kth passive integrator voltage based on the input signal. Unlike the M1 cycle, in this embodiment, since the quantization accuracy corresponding to the kth cycle is relatively higher, in the M2 cycle, a passive noise shaping circuit and a passive amplification circuit are needed to passively amplify the kth passive integrator voltage to obtain an accurate kth fine quantization value. In this embodiment, j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k.

[0037] Specifically, the k-th period may include an integration phase and a gain phase. It should be understood that this is only an example of the k-th period; in fact, each of the M2 periods includes this integration phase and gain phase, which will not be elaborated here.

[0038] Furthermore, during the integration phase, the passive noise shaping circuit passively integrates the k-th high-order integral voltage to obtain the k-th passive integral voltage. Simultaneously, the passive amplifier circuit charges using the k-th high-order integral voltage based on a predetermined amplification factor, and uses the voltage stored during charging as the k-th gain voltage. Subsequently, during the gain phase, the passive noise shaping circuit is electrically connected to the passive amplifier circuit to receive the k-th gain voltage, thereby passively gaining the k-th passive integral voltage based on the predetermined amplification factor to improve voltage quality and achieve passive noise shaping of the k-th high-order integral voltage (i.e., removing noise voltage from the k-th high-order integral voltage), thus obtaining the k-th high-order gain voltage. This process is repeated to obtain M² high-order gain voltages. Based on this, the quantization circuit can quantize each of the M² high-order gain voltages, generating M² fine quantization values.

[0039] Based on this, in the incremental analog-to-digital converter of this invention, the input integrator circuit can generate M1 low-order integrated voltages in M1 cycles. The quantization circuit can quantize each of the M1 low-order integrated voltages to obtain M1 coarse quantization values. This completes the first step of quantization. Further, in the k-th cycle of M2 cycles, the input integrator circuit, under the control of the (k-1)-th fine quantization value, generates the k-th high-order integrated voltage based on the input signal. Subsequently, during the integration phase, the passive noise shaping circuit passively integrates the k-th high-order integrated voltage to obtain the k-th passive integrated voltage. Furthermore, the passive amplifier circuit can obtain the k-th gain voltage based on the k-th high-order integrated voltage using a predetermined amplification factor. Subsequently, the passive amplifier circuit can be electrically connected to the passive noise shaping circuit and provide the k-th gain voltage to the passive noise shaping circuit to passively gain the k-th passive integrated voltage, obtaining the k-th high-order gain voltage. Thus, by using the k-th gain voltage to passively amplify the k-th passive integral voltage generated by passive integration, noise shaping of the k-th higher-order integral voltage can be achieved, resulting in the k-th higher-order gain voltage. Subsequently, the vectorization circuit provides the k-th higher-order gain voltage, enabling the quantization circuit to obtain a finer quantization value with relatively higher accuracy. Furthermore, since noise shaping of the k-th higher-order integral voltage is achieved through a combination of passive integration and passive gain, the number of active components in the analog-to-digital converter (ADC) is reduced. Therefore, while achieving the same quantization accuracy as some other ADC solutions, the ADC of this embodiment has lower power consumption, simultaneously meeting the requirements of high accuracy and low power consumption.

[0040] Furthermore, in this embodiment of the invention, the signal input terminal is a differential input terminal. The input integration circuit, passive amplifier circuit, and passive noise shaping circuit are electrically connected. The passive amplifier circuit includes multiple capacitors. During the integration phase, the multiple capacitors receive the k-th highest integrated voltage and are charged using the k-th highest integrated voltage. During the gain phase, the charged multiple capacitors, based on a predetermined amplification factor, jointly provide the k-th gain voltage to the passive noise shaping circuit. It should be understood that the capacitance values ​​of these multiple capacitors correspond to the predetermined amplification factor described above. The following description is in conjunction with Figure 2.

[0041] Figure 2A A schematic diagram of an incremental analog-to-digital converter according to another embodiment of the present invention is shown. Figure 2B The present invention is shown Figure 2A Timing diagram of the incremental analog-to-digital converter in the embodiment.

[0042] like Figure 2A As shown, the signal input terminal is a differential input terminal. For clarity, Figure 2 shows the positive signal terminal Vin and the common-mode terminal Vcm of the differential input terminal, but not the negative signal terminal. Based on this, the common-mode terminal Vcm can be considered a virtual ground. It should be understood that since the input signal is a differential signal, the common-mode terminal Vcm can be used to provide the common-mode signal of the differential signal.

[0043] The input integration circuit may include a digital-to-analog converter (DAC), an active integrator, a first connection switch S21, and a second connection switch S22. The DAC may include multiple input feedback capacitor arrays corresponding to 3 bits, for example, seven input feedback capacitor arrays. Each input feedback capacitor array may include a positive input sampling capacitor Cp and a negative input sampling capacitor Cn. Furthermore, each input feedback capacitor array may also include a positive input sampling switch Sd (e.g., a bootstrap switch), a first positive reference voltage feedback switch S11, a first negative reference voltage feedback switch S12, a negative input sampling switch Xd, a second positive reference voltage feedback switch X11, and a second negative reference voltage feedback switch X12. It should be noted that, for illustrative purposes, only one set of input feedback capacitor arrays is shown in Figure 2. Additionally, the input feedback capacitor array may also include positive and negative reference voltage feedback capacitors not shown in Figure 2, which will not be elaborated upon here.

[0044] Furthermore, in the input integration circuit of this embodiment, the positive signal terminal Vin can be electrically connected to the first terminal of the positive input sampling capacitor Cp via the positive input sampling switch Sd, so as to provide an input signal to the positive input sampling capacitor Cp. The first terminals of the first positive reference voltage feedback switch S11 and the first negative reference voltage feedback switch S12 can be electrically connected to the positive reference signal terminal Vrefp and the negative reference signal terminal Vrefn, respectively, and the second terminals of the first positive reference voltage feedback switch S11 and the first negative reference voltage feedback switch S12 can be electrically connected to the first terminal of the positive input sampling capacitor Cp.

[0045] Based on this, in the j-th cycle within M1 cycles, the positive input sampling switch Sd closes, causing the positive input sampling capacitor Cp to sample the input signal and obtain the sampling voltage. The (j-1)-th coarse quantization value controls the closing state of the first positive reference voltage feedback switch S11 and the first negative reference voltage feedback switch S12 in the multiple input feedback capacitor array, so that the positive reference signal of the corresponding positive reference signal terminal Vrefp and the negative reference signal of the corresponding negative reference signal terminal Vrefn are provided to the positive input sampling capacitor Cp through the first positive reference voltage feedback switch S11 and the first negative reference voltage feedback switch S12 corresponding to the (j-1)-th coarse quantization value, thereby adjusting the sampling voltage of the positive input sampling capacitor Cp.

[0046] The second terminal of the positive input sampling capacitor Cp can be electrically connected to the first input terminal of the amplifier in the active integrator via the first connection switch S21 to provide the sampled voltage to the first input terminal of the amplifier. The second input terminal of the amplifier can be connected to the common-mode terminal Vcm.

[0047] Furthermore, the active integrator may also include an input integrating capacitor CII. The input integrating capacitor CII may be electrically connected between the first input terminal and the negative output terminal of the amplifier. Thus, the input integrating capacitor CII can be integrated and charged using the regulated sampling voltage of the positive input sampling capacitor Cp. Additionally, a chopper for processing the voltage of the input integrating capacitor CII may be connected to the first and second input terminals of the amplifier. A chopper for processing the k-th higher-order integrated voltage may also be connected to the positive and negative output terminals of the amplifier. The chopper can be used to filter noise, which will not be elaborated here. Furthermore, the switching timing φ of the first chopper switch of the chopper... CHA The switching timing φ of the second chopper switch CHB like Figure 2A As shown. Furthermore, φ CHAD Indicates the switching timing φ of the first chopper switch CHA The delay (e.g., a delay of 15 ns). φ CHBD Indicates the switching timing φ of the first chopper switch CHB The delay (e.g., a delay of 15 ns).

[0048] The positive and negative output terminals of the input integrating circuit can be electrically connected to the passive noise shaping circuit via the third connection switch S3 and the fourth connection switch S4, respectively. The passive noise shaping circuit can be electrically connected to the quantization circuit. Thus, when the third connection switch S3, the fourth connection switch S4, and the first integrating switch IS1 and the second integrating switch IS2 in the passive noise shaping circuit are closed, the active integrator (specifically, an amplifier) ​​of the input integrating voltage can provide the j-th low-order integrating voltage via the vectorization circuit of the passive noise shaping circuit based on the voltage of the charged input integrating capacitor CII and the common-mode terminal Vcm. The positive signal terminal Vin can also be electrically connected to the first terminal of the quantization circuit via the fifth connection switch S5, the first filter capacitor Co1, and the sixth connection switch S6, so that the vectorization circuit can provide the input signal. The common-mode terminal Vcm can also be electrically connected to the second terminal of the quantization circuit via the seventh connection switch S7, the second filter capacitor Co2, and the eighth connection switch S8, so that the vectorization circuit can provide the common-mode signal. Thus, the quantization circuit can generate the j-th coarse quantization value based on the j-th low-order integrating voltage, the input signal, and the common-mode signal. This process is repeated to obtain M1 coarse quantization values. The sixth connecting switch S6 and the eighth connecting switch S8 are closed within M1 cycles and open within M2 cycles, which will not be elaborated upon here.

[0049] Furthermore, the common-mode terminal Vcm can be electrically connected to the first terminal of the negative input sampling capacitor Cn via the negative input sampling switch Xd, so as to provide a common-mode signal to the negative input sampling capacitor Cn. The first terminals of the second positive reference voltage feedback switch X11 and the second negative reference voltage feedback switch X12 can be electrically connected to the positive reference signal terminal Vrefp and the negative reference signal terminal Vrefn, respectively, and the second terminals of the second positive reference voltage feedback switch X11 and the second negative reference voltage feedback switch X12 can be electrically connected to the first terminal of the negative input sampling capacitor Cn.

[0050] Based on this, in the k-th cycle within M2 cycles, the negative input sampling switch Xd closes, causing the negative input sampling capacitor Cn to sample the input signal. The (k-1)-th fine quantization value controls the closing state of the second positive reference voltage feedback switch X11 and the second negative reference voltage feedback switch X12 in the multiple input feedback capacitor array, so that the positive reference signal of the corresponding positive reference signal terminal Vrefp and the negative reference signal of the negative reference signal terminal Vrefn are provided to the negative input sampling capacitor Cn through the second positive reference voltage feedback switch X11 and the second negative reference voltage feedback switch X12 corresponding to the (j-1)-th coarse quantization value, thereby adjusting the sampling voltage of the negative input sampling capacitor Cn. For example, the capacitance value of the input integrating capacitor CII can be 4.2pF. In the input integrating circuit, the capacitance value of the capacitor charged in M1 cycles (such as the aforementioned positive input sampling capacitor Cp) is 600f*7=4.2pF. Based on this, the amplification factor corresponding to the capacitor charged in M1 cycles is 1. In the input integrating circuit, the capacitance of the capacitor charging over M2 cycles (e.g., the negative input sampling capacitor Cn mentioned above) is 40f * 7 = 0.28pF. Based on this, the amplification factor corresponding to this capacitor charging over M2 cycles is 1 / 15. This amplification factor corresponds to the amplification factor of the feedback voltage in the input integrating circuit. It should be understood that this is merely an example.

[0051] The second terminal of the negative input sampling capacitor Cn can be electrically connected to the first input terminal of the amplifier in the active integrator via the second connection switch S22, so as to provide the sampling voltage of the negative input sampling capacitor Cn to the first input terminal of the amplifier. It should be noted that in the k-th cycle, the positive input sampling capacitor Cp stores the residual voltage corresponding to the input signal that has not yet been quantized in the k-th cycle. Thus, the sampling voltage of the negative input sampling capacitor Cn and this residual voltage are together provided to the input integrating capacitor CII to charge the input integrating capacitor CII.

[0052] Furthermore, the amplifier can output the k-th high-order integrated voltage based on the voltage of the charged input integrating capacitor CII and the common-mode signal. The k-th high-order integrated voltage includes the k-th residual positive voltage provided by the positive output terminal of the input integrating circuit and the k-th residual negative voltage provided by the negative output terminal of the input integrating circuit.

[0053] Furthermore, the input integrator circuit can provide the k-th high-order integral voltage to the passive amplifier circuit and the passive noise shaping circuit. In addition to the preliminary stage for generating the k-th high-order integral voltage, the k-th period also includes a sampling stage, an integration stage after the sampling stage, and a gain stage after the integration stage.

[0054] The passive noise shaping circuit may include a sampling capacitor and multiple integrating capacitors. During the sampling phase, the passive noise shaping circuit is electrically connected to the input integrating circuit. Thus, the sampling capacitor samples the k-th highest-order integrated voltage to obtain the k-th sampled voltage. The multiple integrating capacitors may be charged during the sampling phase using the k-th highest-order integrated voltage (e.g., integral charging).

[0055] During the integration phase following the sampling phase, the passive amplifier circuit can be charged using the k-th high-order integral voltage. Specifically, the multiple capacitors in the passive amplifier circuit may include I first capacitors C1 and I second capacitors C2. I is an integer greater than 1, for example, I can be 3. For example, the capacitance values ​​of the three first capacitors C1 can be 100f, 700f, and 100f. The capacitance values ​​of the three second capacitors C2 can be 100f, 700f, and 100f. Specifically, in Figure 2, from left to right, the capacitance values ​​of the three first capacitors C1 can be 100f, 700f, and 100f respectively. The capacitance values ​​of the three second capacitors C2 can be 100f, 700f, and 100f respectively. The predetermined amplification factor includes a first amplification factor and a second amplification factor. The first amplification factor corresponds to the capacitance value of the I first capacitors C1. The second amplification factor corresponds to the capacitance value of the I second capacitors C2.

[0056] During the integration phase, the positive output terminal of the input integrator is electrically connected to the first terminal of one first capacitor C1 via the first energy storage switch S1, and the negative output terminal of the input integrator is electrically connected to the first terminal of one second capacitor C2 via the second energy storage switch S2. The second terminals of the one first capacitor C1 and the one second capacitor C2 are electrically connected to the common-mode terminal Vcm during the integration phase. Thus, during the integration phase, the first energy storage switch S1 and the second energy storage switch S2 are closed, allowing the one first capacitor C1 to be charged using the k-th residual positive voltage, and the one second capacitor C2 to be charged using the k-th residual negative voltage.

[0057] Specifically, the passive amplifier circuit also includes a first parallel switch P1 electrically connected between the first terminals of adjacent first capacitors C1 in a portion of the first capacitors C1; a second parallel switch P2 electrically connected between the second terminals of adjacent first capacitors C1 in a portion of the first capacitors C1; a first grounding switch GS1 electrically connected between the second terminal of a portion of the first capacitors C1 and the common-mode terminal Vcm; and a first series switch SR1 electrically connected between the second terminal of a portion of the first capacitors C1 and the first terminal of another portion of the first capacitors C1. The second terminal of the other portion of the first capacitors C1 is directly electrically connected to the common-mode terminal Vcm. During the integration phase, the first parallel switch P1, the second parallel switch P2, and the first series switch SR1 are open, and the first grounding switch GS1 is closed, so that the input integration circuit can charge the I first capacitors C1.

[0058] Similarly, the passive amplifier circuit may also include a third parallel switch P3 electrically connected between the first terminals of adjacent second capacitors C2 in a portion of the second capacitors C2; a fourth parallel switch P4 electrically connected between the second terminals of adjacent second capacitors C2 in a portion of the second capacitors C2; a second grounding switch GS2 electrically connected between the second terminal of a portion of the second capacitors C2 and the common-mode terminal Vcm; and a second series switch SR2 electrically connected between the second terminal of a portion of the second capacitors C2 and the first terminal of another portion of the second capacitors C2. The second terminal of the other portion of the second capacitors C2 is directly electrically connected to the common-mode terminal Vcm. During the integration phase, the third parallel switch P3, the fourth parallel switch P4, and the second series switch SR2 are open, and the second grounding switch GS2 is closed, so that the input integration circuit can charge the I second capacitors C2.

[0059] Furthermore, the principle of the passive noise shaping circuit of the present invention will be described below.

[0060] Figure 2C A schematic diagram of charge redistribution according to an embodiment of the present invention is shown.

[0061] like Figure 2C As shown, in the first stage, capacitor C stores a first voltage and capacitor 7C stores a second voltage, which are different from each other. In the second stage, capacitors C and 7C are electrically connected to each other for charge redistribution. The capacitance of capacitor 7C is 7 times that of capacitor C; therefore, after charge redistribution, the stored voltages of capacitors C and 7C are equal, both being the sum of 1 / 8 of the first voltage and 7 / 8 of the second voltage. Subsequently, in the third stage, when capacitors C and 7C are electrically disconnected, both capacitors C and 7C retain their respective stored voltages. Thus, charge redistribution between capacitors C and 7C is achieved. It should be noted that z represents a complex frequency variable, z... -1 This represents a delay of one cycle. The passive integration in this embodiment of the invention is based on this, and the following is combined with this embodiment of the invention. Figure 2A , Figure 2B , Figure 2D and Figure 2E Please provide an explanation. Figure 2D A schematic diagram of the parallel connection of the integrating capacitors during the integration stage is shown according to an embodiment of the present invention. Figure 2E A schematic diagram of the series connection of the integrating capacitor during the gain stage according to an embodiment of the present invention is shown.

[0062] Continue to refer to Figure 2A and Figure 2BThe passive noise shaping circuit includes sampling capacitors: a first sampling capacitor CA1 and a second sampling capacitor CA2. The passive noise shaping circuit also includes multiple integrating capacitors: Q first integrating capacitors CI1 and Q second integrating capacitors CI2, where Q is an integer greater than 1 (e.g., Q can be 3). The passive noise shaping circuit further includes multiple first integrating switches IS1 and multiple second integrating switches IS2. The multiple first integrating switches IS1 are connected between the first terminal of each integrating capacitor and the first terminal of the first sampling capacitor CA1. The multiple second integrating switches IS2 are connected between the second terminal of each integrating capacitor and the first terminal of the second sampling capacitor CA2. Further, the first integrating switches IS1 and IS2 are open during the sampling and gain phases and closed during the integration phase, so that the multiple integrating capacitors passively integrate the k-th sampled voltage to obtain the k-th passive integrated voltage. This passive integration is achieved based on the charge redistribution between the integrating capacitors and sampling capacitors of the passive noise shaping circuit.

[0063] For example, the capacitance values ​​of the first sampling capacitor CA1 and the second sampling capacitor CA2 can each be Cu, where Cu represents unit capacitance. In this embodiment of the invention, the analog-to-digital converter can adopt a fully differential structure. Based on this, the capacitance values ​​of the first integrating capacitor CI1 and the second integrating capacitor CI2 can each be 3.5Cu. It should be understood that if the analog-to-digital converter is a single-ended structure, the capacitance value of the integrating capacitor can be 7Cu, which will not be elaborated here. It should also be noted that the integrating capacitor and the sampling capacitor can be controlled by two non-overlapping clock signals to form the desired passive transfer function.

[0064] Based on this, during the sampling period, the third connection switch S3 and the fourth connection switch S4 are closed, the first integration switch IS1 and the second integration switch IS2 are open, the k-th residual positive voltage of the k-th high-order integration voltage Vres will be sampled onto the first sampling capacitor CA1, and the k-th residual negative voltage will be sampled onto the second sampling capacitor CA2.

[0065] refer to Figure 2D During the integration phase, the third connection switch S3 and the fourth connection switch S4 are open, while the first integration switch IS1 and the second integration switch IS2 are closed. Charge redistribution occurs between the first sampling capacitor CA1 and the first integrating capacitor CI1, and between the second sampling capacitor CA2 and the second integrating capacitor CI2. This causes the voltages of the first integrating capacitor CI1 and the second integrating capacitor CI2 to continuously change, thus forming a passive integrator to complete passive integration and obtain the k-th passive integration voltage. At the end of the integration phase, it can be assumed that the voltage difference across each integrating capacitor is Vint. Figure 2D The diagram also shows the relationship between Vint and the k-th higher-order integral voltage Vres after charge redistribution, where z -1The delay of one cycle is not elaborated here. It should be noted that in passive integration, if the circuit changes from single-ended to differential, the capacitance value of the integrating capacitor can be halved. Furthermore, the first integrating capacitor CI1 and the second integrating capacitor CI2 have the same capacitance value, so that after passive integration, the voltages across each of the first integrating capacitor CI1 and the second integrating capacitor CI2 are the same. Subsequently, Q first integrating capacitors CI1 can be connected in series between the first terminal of the passive amplifier circuit and the quantization circuit, and Q second integrating capacitors CI2 can be connected in series between the second terminal of the passive amplifier circuit and the quantization circuit. Thus, refer to... Figure 2E Q first integrating capacitors CI1 and Q second integrating capacitors CI2 are stacked on the first and second terminals of the quantization circuit, respectively, so that the differential voltage between the first and second terminals of the quantization circuit changes from Vint to 6Vint. This achieves a six-fold passive summation; however, this is only for illustrative purposes. Based on this, the differential voltage is the k-th high-order gain voltage. It should be further noted that the stacked Q first integrating capacitors CI1 and Q second integrating capacitors CI2 can be connected to the first and second terminals of the quantization circuit via corresponding quantization switches EN. The quantization switch EN is closed for M2 cycles to provide the aforementioned k-th high-order gain voltage to the quantization circuit. Furthermore, the quantization switch EN can be opened for M1 cycles to electrically disconnect the passive noise shaping circuit from the quantization circuit for M1 cycles. Additionally, the sixth connection switch S6 and the eighth connection switch S8 can be closed for half a cycle less than M1 cycles. The quantization switch EN can be closed for half a cycle more than M2 cycles. This improves the signal-to-noise ratio of the target quantization value.

[0066] Based on this, continue to refer to Figure 2E During the gain phase, multiple integrating capacitors in the passive noise shaping circuit can be electrically disconnected from the sampling capacitor and electrically connected to the passive amplifier circuit. This allows for passive gain of the k-th passive integrated voltage using the k-th gain voltage, resulting in the k-th higher gain voltage. Specifically, during the gain phase, multiple integrating capacitors are connected in series between the passive amplifier circuit and the quantization circuit to passively gain the k-th passive integrated voltage using the k-th gain voltage and provide the k-th higher gain voltage to the quantization circuit.

[0067] For example, during the gain phase, the first terminal of the passive noise shaping circuit and the first terminal of the I first capacitors are configured to be electrically connected, and the second terminal of the passive noise shaping circuit and the first terminal of the I second capacitors are configured to be electrically connected, such that the charged I first capacitors and the charged I second capacitors together provide the k-th gain voltage to the passive noise shaping circuit.

[0068] Specifically, during the gain phase, a portion of the charged I first capacitors C1 are configured to be connected in parallel with each other and connected in series with the other portion of the first capacitors C1 and the common-mode terminal Vcm, so that the I first capacitors C1 provide the k-th residual positive voltage to the passive noise shaping circuit. During the gain phase, the first parallel switch P1, the second parallel switch P2, and the first series switch SR1 are closed, and the first ground switch GS1 is open, so that a portion of the first capacitors C1 are connected in parallel and in series with the other portion of the first capacitors C1, so as to provide the k-th residual positive voltage to the passive noise shaping circuit. It should be noted that in this case, the 700F first capacitor C1 is simultaneously connected in parallel with a 100F first capacitor C1 and in series with another 100F first capacitor C1.

[0069] Furthermore, during the gain phase, a portion of the charged second capacitors C2 are configured to be connected in parallel with each other and connected in series with the other portion of the second capacitors C2 and the common-mode terminal Vcm, so that the I second capacitors C2 provide the k-th residual negative voltage to the passive noise shaping circuit. During the gain phase, the third parallel switch P3, the fourth parallel switch P4, and the second series switch SR2 are closed, and the second grounding switch GS2 is open, so that a portion of the second capacitors C2 are connected in parallel and in series with the other portion of the second capacitors C2, so as to provide the k-th residual negative voltage to the passive noise shaping circuit. It should be noted that in this case, the 700F second capacitor C2 is simultaneously connected in parallel with a 100F second capacitor C2 and in series with another 100F second capacitor C2.

[0070] When the first parallel switch P1, the second parallel switch P2, the third parallel switch P3, the fourth parallel switch P4, the first series switch SR1, and the second series switch SR2 are closed, the charge of the parallel portions of the first capacitor C1 (e.g., a 700f first capacitor C1 and a 100f first capacitor C1 connected in parallel) is redistributed, and the voltage of both becomes 7 / 8 of their original values. Similarly, the charge of the parallel portions of the second capacitor C2 (e.g., a 700f second capacitor C2 and a 100f second capacitor C2 connected in parallel) is redistributed, and the voltage of both becomes 7 / 8 of their original values. This parallel portion of the first capacitor C1 is then connected in series with another portion of the first capacitor C1 (e.g., a 100f first capacitor C1). Furthermore, this parallel portion of the second capacitor C2 is then connected in series with another portion of the second capacitor C2 (e.g., a 100f second capacitor C2). Thus, I first capacitors C1 and I second capacitors C2 can provide the k-th gain voltage. The k-th gain voltage can be 1.875 (15 / 8) times the k-th high-order integral voltage Vres.

[0071] The incremental analog-to-digital converter may further include a first gain switch QS1 and a second gain switch QS2. The first gain switch QS1 is electrically connected between the first output terminal AP of the passive amplifier circuit and the first terminal of the passive noise shaping circuit. The second gain switch QS2 is electrically connected between the second output terminal AN of the passive amplifier circuit and the second terminal of the passive noise shaping circuit. Further, the first gain switch QS1 and the second gain switch QS2 are open during the integration phase, such that both the first output terminal AP and the second output terminal AN of the passive amplifier circuit are electrically disconnected from the passive noise shaping circuit. They are closed during the gain phase, so that the passive noise shaping circuit receives the k-th gain voltage.

[0072] The passive noise shaping circuit may further include a first summing switch H1 connected between adjacent first integrating capacitors CI1 in the Q first integrating capacitors CI1, and a second summing switch H2 connected between adjacent second integrating capacitors CI2 in the Q second integrating capacitors CI2.

[0073] The first summing switch H1, the second summing switch H2, the first gain switch QS1, and the second gain switch QS2 are open during the sampling and integration phases. Furthermore, during the gain phase, the first summing switch H1, the second summing switch H2, the first gain switch QS1, and the second gain switch QS2 are closed, such that Q first integrating capacitors CI1 are connected in series between the first terminal of the passive noise shaping circuit and the first terminal of the quantization circuit, and Q second integrating capacitors CI2 are connected in series between the second terminal of the passive noise shaping circuit and the second terminal of the quantization circuit. Thus, when the passive amplifier circuit provides the k-th gain voltage to the passive noise shaping circuit, the Q first integrating capacitors CI1 and the Q second integrating capacitors CI2 passively gain the k-th passive integrated voltage via the k-th gain voltage, so that the vectorization circuit provides the k-th higher-order gain voltage. Furthermore, during the gain phase, I first capacitors C1 and multiple first integrating capacitors CI1 are connected in series, and the multiple first integrating capacitors CI1 are connected in series with each other; I second capacitors C2 and second integrating capacitors CI2 are connected in series, and the multiple second integrating capacitors CI2 are connected in series with each other. In this way, the vectorizable circuit provides a differential k-th higher-order gain voltage.

[0074] During the gain phase, three first integrating capacitors CI1 and three second integrating capacitors CI2 are connected in series, allowing the voltages of the three first integrating capacitors CI1 and CI2 to be passively summed. Based on this, the k-th gain voltage can amplify the passively summed voltages of the three first integrating capacitors CI1 and CI2. Under the gain of the k-th gain voltage, the vectorization circuit of the three first integrating capacitors CI1 and CI2 provides the k-th higher gain voltage. The k-th higher gain voltage can be 15 / 8Vres + 6Vint, where Vres represents the k-th higher integration voltage and 6Vint represents the passively summed voltage of the three first integrating capacitors CI1 and CI2. Figure 2E The diagram also shows the relationship between the k-th high-order integral voltage Vres, the aforementioned Vint, and the aforementioned k-th high-order gain voltage, where z -1 This indicates a delay of one cycle, which will not be elaborated upon here.

[0075] Based on this, the quantization circuit can quantize the k-th higher-order gain voltage to obtain the k-th fine quantization value. By repeating this process, M2 fine quantization values ​​can be obtained.

[0076] Figure 3 A schematic diagram of the overall system of an analog-to-digital converter according to an embodiment of the present invention is shown. Figure 4 A schematic diagram of an analog-to-digital converter in the first step of the quantization process according to an embodiment of the present invention is shown. Figure 5 A schematic diagram of the analog-to-digital converter in the second step of the quantization process according to an embodiment of the present invention is shown. Figure 6 A schematic diagram of the analog-to-digital converter quantizing the residual voltage in the second quantization process according to an embodiment of the present invention is shown.

[0077] exist Figure 3 In the middle, with F M1 This refers to the switch that was closed during the first step of quantization, as described above, in F. M1 After closing, the analog-to-digital converter system is as follows: Figure 4 As shown. Similarly, in Figure 3 In the middle, with F M2 This refers to the switch that was closed during the second quantization step described above, in F. M2 After closing, the analog-to-digital converter system is as follows: Figure 5 As shown.

[0078] in, This represents the active transfer function of the active integrator. This represents the passive transfer function of a passive integrator.

[0079] DAC stands for Digital-to-Analog Converter. A circle with a cross inside indicates summation; a circle with a cross and a minus sign in the lower right corner indicates differential or subtraction. 15 / 8 represents the predetermined gain of the passive amplifier circuit. 6 represents the gain coefficient of the integrating capacitor in the passive noise shaping circuit. G1 and G2 represent predetermined filter coefficients. G3 represents the efficiency coefficient. D1 represents the coarse quantization value. D2 represents the fine quantization value. D0 represents the target quantization value. 1 / 8z -1 This represents the transfer function of the sampling capacitor after charge redistribution. 7 / 8z -1 This represents the transfer function of the integral capacitor after charge redistribution. -1 This indicates a delay of one cycle. The first-step quantization digital decimation filter is used to filter the coarse quantization value to obtain a more accurate coarse quantization value. The second-step quantization digital decimation filter is used to filter the fine quantization value to obtain a more accurate fine quantization value, which will not be elaborated here. RST represents the reset signal, which will not be elaborated here.

[0080] refer to Figures 3-6 In this embodiment of the invention, the active transfer function of the active integrator has an attenuation coefficient in noise shaping effect relative to the passive transfer function based on the passive amplifier circuit and the passive noise shaping circuit, and the attenuation coefficient is less than or equal to 1 / 8. The predetermined amplification factor of the passive amplifier circuit is greater than or equal to 1.875 (i.e., 15 / 8).

[0081] In the first step of quantization, the key transfer function of the analog-to-digital converter Based on an active integrator.

[0082] By designing the coefficients, the noise transfer function (NTF1) of the analog-to-digital converter can be made as follows:

[0083] (1)

[0084] Among them, z -1 This indicates a delay of one cycle.

[0085] In the first step of quantization, the oversampling rate is 130, i.e., M1 = 130. At the end of M1 cycles, the residual voltage is stored in the active integrator. Based on this, the analog-to-digital converter can be reconfigured for passive noise shaping.

[0086] In the second quantization step, due to the attenuation coefficient of the passive transfer function formed by the integrating capacitor in the passive noise shaping circuit, it is difficult to construct the aforementioned noise transfer function (NTF1). Therefore, the passive noise shaping circuit will construct an approximate transfer function, which is... , where z -1This represents a delay of one cycle. Based on this, coefficients can be designed such that the noise transfer function (NTF²) of the analog-to-digital converter is:

[0087] (2)

[0088] Among them, z -1 This indicates a delay of one cycle.

[0089] The oversampling rate for the second quantization step is 36, i.e., M2 = 36. Subsequently, the M1 coarse quantization values ​​obtained from the first step and the fine quantization values ​​obtained from the second step can be combined to obtain the target quantization value. For example, for a 16-bit target quantization value, in the multi-bit target quantization values ​​b15, ..., b0, b15~b8 can belong to the higher bits (bit weight 2). 15 ~2 8 Corresponding to the coarse quantization values, b7~b0 can be considered low bits (bit weight 2). 7 ~2 0 This corresponds to the finer quantization value. The entire conversion cycle of the analog-to-digital converter in this embodiment of the invention can be 166 clock cycles.

[0090] In this embodiment of the invention, the analog-to-digital converter is a first-order loop during the first quantization step. An active integrator is used for active noise shaping during the first quantization step. At the end of the first quantization step, the residual voltage is stored in the active integrator, and its magnitude is:

[0091] (3)

[0092] In formula (3), Vres1 represents the residual voltage of the active integrator at the end of the first quantization step. M1 represents the number of cycles in the first quantization step described above, for example, 130. Vin[i] represents the input voltage of the i-th cycle. i=1,……,M1-1. M1-1 means subtracting "1" from the value of M1. Vref represents the feedback voltage, which includes the positive or negative reference voltage described above. D1[i] represents the i-th coarse quantization value.

[0093] In the first step of quantization, the magnitude of the residual voltage of the active integrator in the M1 cycle is limited by the feedback voltage Vref of the input integrator circuit (such as the positive and negative reference voltages described above). Therefore, when using the coarse quantization value D1 to represent the input voltage Vin, the residual voltage Vres1 can be regarded as a small amount, or a relatively small value.

[0094] In the second quantization step, a passive noise shaping circuit is used as a passive integrator to construct a near-first-order passive transfer function through passive gain and passive summation. Simultaneously, an efficiency coefficient G3 is configured to scale the step size of the input feedback capacitor array DAC of the input integrator circuit to the original G3, i.e., Vref * G3. This dual approach allows the analog-to-digital converter to achieve a near-second-order signal-to-noise ratio while maintaining only a first-order order. At the end of the M2 cycle, the residual voltage of the passive noise shaping circuit is:

[0095] (4)

[0096] In formula (4), Vres2 represents the residual voltage of the passive noise shaping circuit at the end of the second quantization step. Vres1 represents the residual voltage of the active integrator at the end of the first quantization step. i=0,……, . =1,……,M2-2. M2-2 means subtracting “2” from the value of M2. M2 represents the number of cycles in the second quantization step described above. G3 represents the efficiency coefficient. Vref represents the feedback voltage, which includes the positive or negative reference voltage described above. D2[i] represents the i-th fine quantization value. It should be noted that, for ease of illustration, the same letters are used in formulas (3) and (4) to represent similar meanings. The meaning of the letters should be based on the corresponding text descriptions, and will not be repeated here.

[0097] Additionally, in this embodiment of the invention, the analog-to-digital converter may further include a capacitor reset switch IRST connected in parallel with the input integrating capacitor. This capacitor reset switch IRST can be used to reset the input integrating capacitor.

[0098] Furthermore, the analog-to-digital converter may also include: a first reset switch RST1 connected between the first terminal of the first connection switch S21 and the common-mode terminal Vcm; a second reset switch RST2 connected between the first terminal of the second connection switch S22 and the common-mode terminal Vcm; a third reset switch RST3 connected between the first terminal of the first sampling capacitor CA1 and the common-mode terminal; a fourth reset switch RST4 connected between the first terminal of the second sampling capacitor CA2 and the common-mode terminal; a fifth reset switch RST5 connected between the first terminal of the fifth connection switch S5 and the common-mode terminal Vcm; and a sixth reset switch RST6 connected between the first terminal of the seventh connection switch S7 and the common-mode terminal Vcm. The operating timing reference for the first reset switch RST1, the second reset switch RST2, the third reset switch RST3, the fourth reset switch RST4, the fifth reset switch RST5, and the sixth reset switch RST6 is provided. Figure 2B That's sufficient; I won't elaborate further here. It's worth noting that you can continue to refer to [the relevant resources / references]. Figure 2AThe switching timing of the fifth connection switch S5 and the first reset switch RST1 is the same. The switching timing of the positive input sampling switch Sd can be delayed by 15ns relative to the fifth connection switch S5 and the first reset switch RST1. The switching timing of the first positive reference voltage feedback switch S11 or the first negative reference voltage feedback switch S12 can also be delayed by 15ns relative to the first connection switch S21 and the fifth reset switch RST5. This is the timing relationship of the part of the input integrator circuit connected to the signal input terminal. It should be understood that the timing relationship of the part of the input integrator circuit connected to the common-mode terminal is similar and will not be elaborated here.

[0099] In addition, such as Figure 2A As shown, the analog-to-digital converter in this embodiment of the invention may further include a data weighted averaging module (DWA). This DWA module can be used to suppress harmonic distortion caused by capacitor mismatch in the digital-to-analog conversion unit. Specifically, the DWA module can control the digital-to-analog conversion process of the digital-to-analog conversion unit according to a coarse quantization value or a fine quantization value to suppress capacitor mismatch. It should be noted that the output voltage of the data weighted averaging module can be a 7-bit wide digital signal, including 7 binary bits from bit 1 to bit 7, which will not be elaborated further here.

[0100] In some solutions, a first-order analog-to-digital converter (ADC) requires 2N clock cycles to achieve N-bit resolution, while higher-order ADCs with single-loop or multi-stage noise shaping suffer from potential instability issues and poor noise cancellation due to mismatches between analog and digital circuits. To address these issues, the ADC provided in this invention utilizes a multi-step extended counting method. This method can further quantize by recovering the residual voltage from the previous coarse quantization step to achieve extended accuracy, while also improving conversion speed. Thus, accuracy is improved while conversion speed is reduced.

[0101] Furthermore, in this embodiment of the invention, when the oversampling rate is low, the noise shaping effect of the passive transfer function is better than that of the first-order active transfer function, but slightly worse than that of the second-order active transfer function. Therefore, when the oversampling rate is high, the passive transfer function and the active integrator can be applied to the second-step quantization to reduce quantization power consumption while maintaining approximately the same quantization accuracy.

[0102] Figure 7 A schematic diagram of a signal processing method according to an embodiment of the present invention is shown.

[0103] like Figure 7 As shown, the signal processing method of this embodiment can be applied to the incremental analog-to-digital converter of any of the above embodiments. The signal processing method includes operations S710 to S740.

[0104] During operation S710, the input integrator circuit generates the j-th low-order integrated voltage based on the input signal from the signal input terminal during the j-th cycle of M1 cycles, under the control of the (j-1)-th coarse quantization value; and generates the k-th high-order integrated voltage based on the input signal during the k-th cycle of the M2 cycles following the M1 cycles, under the control of the (k-1)-th fine quantization value.

[0105] When operating S720, the passive amplifier circuit obtains the k-th gain voltage based on the k-th high-order integral voltage during the integration phase of the k-th cycle, according to a predetermined amplification factor.

[0106] When operating S730, the passive noise shaping circuit passively integrates the k-th high-order integrated voltage during the integration phase to obtain the k-th passive integrated voltage. During the gain phase of the k-th cycle, it is electrically connected to the passive amplifier circuit so that the k-th passive integrated voltage can be passively gained using the k-th gain voltage to obtain the k-th high-order gain voltage.

[0107] When operating the S740, the quantization circuit quantizes M1 low-order integral voltages in M1 cycles to generate M1 coarse quantization values; and quantizes M2 high-order gain voltages in M2 cycles to generate M2 fine quantization values.

[0108] It should be understood that the signal processing method in this embodiment of the invention can be performed with reference to the operation of the analog-to-digital converter described above, and will not be repeated here.

[0109] Building upon this foundation, this invention proposes an incremental analog-to-digital converter (ADC) based on passive noise shaping, which reduces power consumption while maintaining multi-channel multiplexing and high accuracy. Compared to some other ADC solutions, this invention decomposes a single-ring high-order structure into two low-order steps, improving system stability and reducing conversion time while maintaining accuracy. Furthermore, without adding additional active components, this invention uses a passive capacitor array instead of an active integrator to construct the transfer function in the second noise shaping step, which has a smaller oversampling number, thus reducing power consumption while essentially maintaining accuracy.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0111] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0112] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. An incremental analog-to-digital converter based on passive noise shaping, characterized in that, include: The input integrator circuit is configured to generate the j-th low-order integrated voltage based on the input signal from the signal input terminal during the j-th period of M1 periods, under the control of the (j-1)-th coarse quantization value; and to generate the k-th high-order integrated voltage based on the input signal during the k-th period of M2 periods following the M1 periods, under the control of the (k-1)-th fine quantization value; where j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k. A passive amplifier circuit is configured to obtain the k-th gain voltage based on a predetermined amplification factor and the k-th higher-order integral voltage during the integration phase of the k-th cycle. A passive noise shaping circuit is configured to passively integrate the k-th high-order integral voltage during the integration phase to obtain the k-th passive integral voltage, and to be electrically connected to a passive amplifier circuit during the gain phase of the k-th cycle so as to passively gain the k-th passive integral voltage using the k-th gain voltage to obtain the k-th high-order gain voltage. The quantization circuit is configured to quantize M1 low-order integral voltages over M1 cycles to generate M1 coarse quantization values; and to quantize M2 high-order gain voltages over M2 cycles to generate M2 fine quantization values; wherein the fine quantization values ​​have higher precision than the coarse quantization values.

2. The incremental analog-to-digital converter according to claim 1, characterized in that, The signal input terminal is a differential input terminal; The input integration circuit, the passive amplifier circuit, and the passive noise shaping circuit are electrically connected; The passive amplifier circuit includes multiple capacitors, wherein, during the integration phase, the multiple capacitors receive the k-th high-order integration voltage and are charged using the k-th high-order integration voltage; during the gain phase, the charged multiple capacitors, based on the predetermined amplification factor, jointly provide the k-th gain voltage to the passive noise shaping circuit.

3. The incremental analog-to-digital converter according to claim 2, characterized in that, The plurality of capacitors includes I first capacitors and I second capacitors; I is an integer greater than 1; Wherein, the k-th high-order integrated voltage includes the k-th residual positive voltage provided by the positive output terminal of the input integration circuit and the k-th residual negative voltage provided by the negative output terminal of the input integration circuit; During the integration phase, the positive output terminal of the input integrator circuit and the first terminal of the I first capacitors are electrically connected, and the negative output terminal of the input integrator circuit and the first terminal of the I second capacitors are electrically connected, such that the I first capacitors are charged via the k-th residual positive voltage, and the I second capacitors are charged via the k-th residual negative voltage; wherein the second terminals of the I first capacitors and the second terminals of the I second capacitors are electrically connected to the common-mode terminal corresponding to the differential input terminal during the integration phase. The predetermined amplification factor includes a first amplification factor and a second amplification factor; the first amplification factor corresponds to the capacitance value of the I first capacitors; the second amplification factor corresponds to the capacitance value of the I second capacitors; during the gain phase, the first terminal of the passive noise shaping circuit and the first terminal of the I first capacitors are configured to be electrically connected, and the second terminal of the passive noise shaping circuit and the first terminal of the I second capacitors are configured to be electrically connected, so that the charged I first capacitors and the charged I second capacitors together provide the k-th gain voltage to the passive noise shaping circuit.

4. The incremental analog-to-digital converter according to claim 2, characterized in that, Also includes: A first gain switch electrically connected between the first output terminal of the passive amplifier circuit and the first terminal of the passive noise shaping circuit; A second gain switch electrically connected between the second output terminal of the passive amplifier circuit and the second terminal of the passive noise shaping circuit; The first gain switch and the second gain switch are configured to: be open during the integration phase so that the passive amplifier circuit is electrically disconnected from the passive noise shaping circuit; and be closed during the gain phase so that the passive noise shaping circuit receives the k-th gain voltage from the passive amplifier circuit.

5. The incremental analog-to-digital converter according to claim 3, characterized in that, During the gain phase, a portion of the charged I first capacitors are configured to be connected in parallel with each other and connected between another portion of the first capacitors and the common-mode terminal in series with the other portion of the first capacitors, so that the I first capacitors provide the k-th residual positive voltage to the passive noise shaping circuit. During the gain phase, some of the charged second capacitors are configured to be connected in parallel with each other and connected between the other second capacitors and the common-mode terminal in series with the other second capacitors, so that the I second capacitors provide the k-th residual negative voltage to the passive noise shaping circuit.

6. The incremental analog-to-digital converter according to claim 5, characterized in that, The incremental analog-to-digital converter also includes: A first parallel switch electrically connected between the first terminals of adjacent first capacitors in the portion of the first capacitors; a second parallel switch electrically connected between the second terminals of adjacent first capacitors in the portion of the first capacitors; a first grounding switch electrically connected between the second terminal of the portion of the first capacitors and the common-mode terminal; and a first series switch electrically connected between the second terminal of the portion of the first capacitors and the first terminal of the other portion of the first capacitors; the second terminal of the other portion of the first capacitors is directly electrically connected to the common-mode terminal. During the integration phase, the first parallel switch, the second parallel switch, and the first series switch are open, and the first grounding switch is closed, so that the input integration circuit can charge the I first capacitors; during the gain phase, the first parallel switch, the second parallel switch, and the first series switch are closed, and the first grounding switch is open, so that some of the first capacitors are connected in parallel and in series with the other part of the first capacitors. A third parallel switch is electrically connected between the first terminals of adjacent second capacitors in the portion of the second capacitors; a fourth parallel switch is electrically connected between the second terminals of adjacent second capacitors in the portion of the second capacitors; a second grounding switch is electrically connected between the second terminal of the portion of the second capacitors and the common-mode terminal; a second series switch is electrically connected between the second terminal of the portion of the second capacitors and the first terminal of the other portion of the second capacitors; the second terminal of the other portion of the second capacitors is directly electrically connected to the common-mode terminal; During the integration phase, the third parallel switch, the fourth parallel switch, and the second series switch are open, and the second grounding switch is closed, so that the input integration circuit can charge the I second capacitors; during the gain phase, the third parallel switch, the fourth parallel switch, and the second series switch are closed, and the second grounding switch is open, so that some of the second capacitors are connected in parallel and in series with the other part of the second capacitors.

7. The incremental analog-to-digital converter according to any one of claims 4 to 6, characterized in that, The passive noise shaping circuit includes: The sampling capacitor is configured to sample the k-th higher-order integral voltage during the sampling phase to obtain the k-th sampled voltage; Multiple integrating capacitors are configured to be charged via the k-th high-order integrating voltage during the sampling phase to obtain a charging voltage, and then electrically connected to the sampling capacitors during the integration phase after the sampling phase to passively integrate the k-th sampling voltage based on the charging voltage to obtain the k-th passive integrating voltage. During the gain phase, the capacitors are electrically disconnected from the sampling capacitors and electrically connected to the passive amplifier circuit to passively gain the k-th passive integrating voltage using the k-th gain voltage to obtain the k-th high-order gain voltage.

8. The incremental analog-to-digital converter according to claim 7, characterized in that, The plurality of integrating capacitors are also configured to be connected in parallel between the positive and negative output terminals of the input integrating circuit during the sampling phase, so as to be charged via the k-th high-order integrating voltage; and, during the gain phase, to be connected in series between the passive amplifier circuit and the quantization circuit, so as to passively gain the k-th passive integrating voltage using the k-th gain voltage and provide the k-th high-order gain voltage to the quantization circuit.

9. The incremental analog-to-digital converter according to claim 8, characterized in that, The sampling capacitor of the passive noise shaping circuit includes a first sampling capacitor and a second sampling capacitor. The passive noise shaping circuit also includes: Multiple first integral switches are respectively connected between the first terminal of each of the multiple integral capacitors and the first terminal of the first sampling capacitor; Multiple second integral switches are respectively connected between the second terminal of each of the multiple integral capacitors and the first terminal of the second sampling capacitor; The first integrating switch and the second integrating switch are configured to be open during the sampling phase and the gain phase, and closed during the integration phase, so that the plurality of integrating capacitors perform passive integration of the k-th sampled voltage based on the charging voltage to obtain the k-th passive integrated voltage.

10. The incremental analog-to-digital converter according to claim 8, characterized in that, The plurality of integrating capacitors includes: Q first integrating capacitors and Q second integrating capacitors; Q is an integer greater than 1; The passive noise shaping circuit also includes: A first summation switch is connected between adjacent first integrating capacitors in the Q first integrating capacitors; A second summation switch is connected between adjacent second integrating capacitors in the Q second integrating capacitors; The first summation switch, the second summation switch, the first gain switch, and the second gain switch are configured to be open during the sampling phase and the integration phase; and closed during the gain phase, such that the plurality of first integrating capacitors are connected in series between the first terminal of the passive noise shaping circuit and the first terminal of the quantization circuit, and that the plurality of second integrating capacitors are connected in series between the second terminal of the passive noise shaping circuit and the second terminal of the quantization circuit, so that when the passive amplifier circuit provides the k-th gain voltage to the passive noise shaping circuit, the Q first integrating capacitors and the Q second integrating capacitors passively gain the k-th passive integrating voltage via the k-th gain voltage to provide the k-th high-order gain voltage to the quantization circuit.

11. The incremental analog-to-digital converter according to any one of claims 1 to 6, characterized in that, The input integration circuit includes an active integrator; the active transfer function of the active integrator has an attenuation coefficient in noise shaping effect relative to the passive transfer function based on the passive amplifier circuit and the passive noise shaping circuit, and the attenuation coefficient is less than or equal to 1 / 8. The predetermined amplification factor of the passive amplifier circuit is greater than or equal to 1.

875.

12. A signal processing method, characterized in that, The signal processing method, applied to the incremental analog-to-digital converter as described in any one of claims 1 to 11, comprises: The input integrator circuit generates the j-th low-order integrated voltage in the j-th cycle of M1 cycles, under the control of the (j-1)-th coarse quantization value, based on the input signal from the signal input terminal; and generates the k-th high-order integrated voltage in the k-th cycle of M2 cycles following the M1 cycles, under the control of the (k-1)-th fine quantization value, based on the input signal; where j and k are integers greater than 1, M1 is an integer greater than or equal to j, and M2 is an integer greater than or equal to k; During the integration phase of the k-th cycle, the passive amplifier circuit obtains the k-th gain voltage based on a predetermined amplification factor and the k-th higher-order integral voltage. During the integration phase, the passive noise shaping circuit passively integrates the k-th high-order integrated voltage to obtain the k-th passive integrated voltage. During the gain phase of the k-th cycle, it is electrically connected to the passive amplifier circuit so that the k-th passive integrated voltage can be passively gained using the k-th gain voltage to obtain the k-th high-order gain voltage. The quantization circuit quantizes M1 low-order integral voltages within M1 cycles to generate M1 coarse quantization values; and quantizes M2 high-order gain voltages within M2 cycles to generate M2 fine quantization values; the fine quantization values ​​have higher precision than the coarse quantization values.

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