Method, device, storage medium and product for refresh trigger control based on link performance

Abstract

The embodiment of the application relates to the technical field of communication, discloses a Refresh trigger control method and device based on link performance, a storage medium and a product, the method is applied to a physical layer chip, the method comprises the following steps: periodically generating a Refresh control signal according to a preset time interval when the physical layer chip is in a low-power sleep mode; real-time receiving a monitoring result signal representing a link health state; judging whether the monitoring result signal indicates that the link performance is deteriorated; if the link performance is deteriorated, switching from a periodic timer control mode to a performance control mode; in the performance control mode, terminating the timing process of the preset time interval, executing a fast trigger strategy, and forcibly starting a next Refresh segment within a preset short time after the current Refresh segment ends, so that the signal quality can be rapidly repaired without exiting the low-power idle mode, and the connection stability of the physical layer link is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a refresh trigger control method, device, storage medium and product based on link performance. Background Technology

[0002] According to the IEEE 802.3az standard (Energy Efficient Ethernet), when the Ethernet physical layer chip enters Low Power Sleep Mode (LPI), the sending and receiving ends maintain the connection through alternating Quiet and Refresh states. The standard protocol employs an open-loop fixed timer mechanism to control the transmission of Refresh segments, such as... Figure 1 As shown, the device primarily switches between an active state and a low-power idle state. Once the device completes its current data transmission or processing task, it switches from the active state to the low-power idle state. In the low-power idle state, the device does not completely stop working but primarily remains in sleep mode to conserve power. To maintain network connectivity or internal state, the device periodically performs a refresh. The sending end starts a timer (Tw_sys_tx), and whenever the timer reaches a preset fixed period (e.g., 20ms or more), it sends a refresh segment until an external trigger or the timer expires. Subsequently, the device executes a wake-up procedure, powering on and resetting the relevant hardware modules, ultimately returning to the active state on the right to handle new services.

[0003] However, the existing physical layer chips' EEE low-power design and refresh mechanism have significant drawbacks in practical applications. First, in LPI mode, the chip shuts down some signal processing units to reduce power consumption. If noise interference increases in the link environment at this time, it will directly lead to a decrease in the signal-to-noise ratio (SNR) and an increase in the bit error rate (BER) at the receiver. Since the existing mechanism can only mechanically rely on sending refresh segments at fixed periods, it cannot dynamically adjust the transmission timing according to signal quality. As a result, the link barely maintains a low-power state in harsh environments, which leads to data transmission errors and triggers the upper-layer retransmission mechanism. The additional retransmission operation actually causes the overall power consumption of the chip to increase instead of decrease, which violates the original intention of low-power design.

[0004] Secondly, existing chips do not link the refresh mechanism to the signal performance convergence process. When early signs of link instability appear, such as a significant increase in the parameter convergence time of the previous refresh segment (e.g., from the normal 500ns to 1.5μs) or a locking anomaly in the clock data recovery (CDR) module (e.g., lock jitter exceeding 100ps), the existing mechanism ignores these risks and continues to wait for the fixed period to end before initiating the next refresh. This delayed response causes the link synchronization state to deteriorate further during the silent period, ultimately leading to an unexpected link disconnection.

[0005] Furthermore, existing solutions lack closed-loop control capabilities within the chip. Most chips can only passively exit LPI mode when the signal quality is severely abnormal, failing to achieve an active self-healing cycle of "signal anomaly detection - rapid refresh - performance convergence - maintaining LPI mode". Moreover, their evaluation of signal quality relies heavily on a single SNR metric, lacking comprehensive consideration of multi-dimensional parameters such as convergence time and CDR lock-up status, making it difficult to accurately balance low power consumption and signal reliability. Summary of the Invention

[0006] One objective of this application is to provide a Refresh trigger control method, device, storage medium, and product based on link performance, at least to solve the technical problem that existing physical layer chips, in low-power sleep mode, cannot dynamically adjust the Refresh transmission frequency when early signs of deterioration such as increased convergence time, increased CDR jitter, or decreased signal-to-noise ratio are detected due to the use of a fixed timer mechanism and the lack of a multi-dimensional performance feedback closed loop, which leads to increased bit error rate, increased power consumption due to invalid retransmissions, and unexpected link lockout.

[0007] To achieve the above objectives, some embodiments of this application provide the following aspects:

[0008] Firstly, this application provides a Refresh trigger control method based on link performance, the method being applied to a physical layer chip, the method comprising:

[0009] When the physical layer chip is in low-power sleep mode, it runs in periodic timer control mode, and periodically generates refresh control signals according to preset time intervals to drive the transmitter to send refresh segments.

[0010] Receive monitoring result signals characterizing the health status of the link in real time; determine whether the monitoring result signals indicate link performance degradation;

[0011] If the indicated link performance deteriorates, switch from the periodic timer control mode to the performance control mode;

[0012] In the performance control mode, the timing process of the preset time interval is terminated, and a fast triggering strategy is executed to force the start of the next refresh segment within a preset time after the current refresh segment ends.

[0013] Secondly, some embodiments of this application also provide an electronic device, the electronic device comprising: one or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method described above.

[0014] Thirdly, some embodiments of this application also provide a computer-readable medium having computer program instructions stored thereon, which can be executed by a processor to implement the method described above.

[0015] Fourthly, some embodiments of this application also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the method described above.

[0016] Compared with related technologies, the solution provided in this application breaks through the open-loop mechanism of the IEEE 802.3az standard, which relies solely on a fixed-period timer to send refresh segments. It innovatively constructs a chip-level closed-loop control logic of "signal anomaly detection - fast refresh start - performance convergence - maintaining LPI mode". When link performance deterioration is detected, it can automatically shield the preset period timing constraint and immediately execute a fast triggering strategy. By providing a dense refresh training sequence in a short period of time, it forces the receiver equalizer and clock recovery module to quickly reconverge under harsh conditions, thereby realizing active self-healing of the link inside the chip. This effectively avoids upper-layer protocol retransmission caused by increased bit error rate and the resulting overall power consumption rebound, achieving true system-level low power consumption while ensuring connection stability.

[0017] Furthermore, it can accurately detect early synchronization risks that are difficult to detect with a single signal-to-noise ratio indicator, and accordingly realize the on-demand dynamic adjustment of the refresh trigger frequency. That is, it strictly maintains long-term silence to maximize energy saving when the link is healthy, and precisely intervenes when there are signs of slowed convergence or increased jitter. Thus, without exiting the low-power mode, it significantly improves the robustness of the physical layer chip against complex electromagnetic environments and sudden noise, achieving a dynamic and precise balance between low power consumption and high signal reliability. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a diagram of a typical low-power idle mode timing control mechanism in the prior art;

[0020] Figure 2 A flowchart illustrating a link performance-based refresh trigger control method provided as an exemplary embodiment of this disclosure;

[0021] Figure 3 An exemplary structural diagram of the electronic device provided for some embodiments of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] Figure 2 A flowchart illustrating a link performance-based refresh trigger control method provided as an exemplary embodiment of this disclosure, the method being applied to a physical layer chip, the method comprising:

[0024] S101. When the physical layer chip is in low-power sleep mode, it runs in periodic timer control mode and periodically generates refresh control signals according to preset time intervals to drive the transmitter to send refresh segments.

[0025] Specifically, after the physical layer chip completes the handshake and enters low-power sleep mode, the system initializes and runs in periodic timer control mode by default. In this mode, the control logic strictly follows the timing constraints defined by the IEEE 802.3az standard, starting a long-period hardware timer (e.g., set to 20 milliseconds). This timer continuously counts down, and each time the preset time interval expires, the system generates a refresh control signal, driving the transmitting circuit to send a set of refresh segments to the link, thereby maintaining basic clock synchronization and connection survival at the receiving end. After the transmission is completed, the timer automatically resets and restarts counting.

[0026] S102. Receive monitoring result signals that characterize the health status of the link in real time; determine whether the monitoring result signals indicate that the link performance has deteriorated.

[0027] Specifically, during the aforementioned periodic operation, the system executes step S102 in parallel, establishing a real-time feedback monitoring mechanism. Through the internal signal bus, it continuously receives monitoring result signals from the signal performance monitoring unit. These monitoring result signals carry the current link health status information, and the internal decision logic analyzes the signal in real time to determine whether it contains status bits indicating link performance deterioration, such as "low signal-to-noise ratio," "abnormal convergence time," or "CDR loss of lock risk."

[0028] S103. If the indicated link performance deteriorates, switch from the periodic timer control mode to the performance control mode.

[0029] Specifically, once the decision logic in step S102 confirms that the monitoring result signal indicates that the link performance is deteriorating, the system immediately executes step S103, triggering an instantaneous switch in the control mode. At this time, the original periodic timer control logic will be immediately suspended or disabled, forcing the system state machine to jump to the performance control mode, no longer relying on a fixed standard period to trigger signal transmission.

[0030] S104. In the performance control mode, the timing process of the preset time interval is terminated, and a fast triggering strategy is executed to force the start of the next refresh segment within a preset time after the current refresh segment ends.

[0031] Specifically, the system then proceeds to step S104. In performance control mode, the system executes an aggressive, rapid triggering strategy. The control logic first sends a command to terminate or reset the running preset time interval (i.e., long period) timing process, no longer waiting for it to expire naturally. Immediately afterwards, the system starts a microsecond-level short-delay timer, corresponding to the minimum silence interval (Tw_phyp_min) allowed by the physical layer protocol. Once this preset short timer expires and the currently transmitted Refresh segment has been sent, the system immediately forces the generation of the next Refresh control signal, seamlessly initiating the transmission process of the next Refresh segment. In this way, the system injects a high-density training sequence into the link in a short time until the link performance returns to normal.

[0032] In this embodiment, a closed-loop control mechanism based on link state feedback is introduced to overcome the limitations of existing technologies that rely solely on open-loop timers to trigger refresh segments. When fluctuations in link performance are detected, the system can automatically disable the default long-cycle timing constraints and instead execute a high-frequency, fast-triggering strategy. This adaptive timing adjustment mechanism can provide dense physical layer training signals to the receiver, prompting the adaptive equalizer and the clock recovery circuit, which has drifted due to excessively long silent periods, to quickly reconverge within a short time. This achieves dynamic calibration and performance recovery of link parameters without exiting the low-power sleep mode, significantly improving the anti-interference capability and connection stability of the physical layer chip in complex electromagnetic environments.

[0033] In one embodiment, the monitoring result signal indicates at least one of the following specific situations where link performance deteriorates:

[0034] The signal-to-noise ratio (SNR) of the received signal is lower than the preset SNR threshold.

[0035] The refresh convergence time of the current refresh segment exceeds a preset multiple of the historical statistical reference value;

[0036] The clock data recovery lock state is abnormal, and the corresponding lock jitter data exceeds the jitter threshold.

[0037] Specifically, the received monitoring result signal includes three independent decision dimensions: First, amplitude domain judgment: the system compares the signal-to-noise ratio (SNR) of the received signal in real time. If the value is lower than the preset SNR threshold, it indicates that the link is affected by strong background noise interference, causing the signal eye diagram to close. Second, time domain response judgment: the system dynamically compares the convergence time of the current refresh segment with the historical statistical reference value (i.e., the recent average level). If the current convergence time exceeds a preset multiple of the historical reference value, it indicates that the equalizer's ability to adapt to channel changes is decreasing. Finally, synchronization domain judgment: the system checks the locking status of the clock data recovery module. If it finds that the locked jitter data exceeds the allowable jitter threshold, it indicates that there is excessive clock phase drift. The control logic uses an "OR" operation to process the above conditions. As long as any one or more of them are met, the system determines that the link performance has deteriorated and immediately generates a trigger signal to activate the performance control mode.

[0038] In this embodiment, by integrating parameters from three key dimensions—signal-to-noise ratio (signal quality), convergence time (equalizer response), and lockout jitter (clock stability)—the blind spots that may exist with a single monitoring method are effectively eliminated. This multi-parameter joint judgment mechanism ensures that whether it is an instantaneous bit error caused by external electromagnetic interference or a gradual performance degradation caused by cable aging and temperature drift, it can be keenly captured and identified as a deterioration event by the system. This ensures the timeliness and accuracy of the Refresh trigger strategy intervention and avoids unexpected link interruptions due to missed judgments.

[0039] Furthermore, in one embodiment, the monitoring result signal indicating link performance degradation further includes:

[0040] The signal-to-noise ratio of the received signal and / or the first derivative of the lock jitter data over time are calculated in real time to obtain the rate of change of signal quality.

[0041] The rate of change of the signal quality is compared with a preset slope threshold;

[0042] When the rate of change of the signal quality exceeds the slope threshold, it is directly determined that the monitoring result signal indicates that the link performance has deteriorated, and a switch to the performance control mode is triggered.

[0043] Specifically, existing triggering logic is typically based on static threshold determination (e.g., switching modes only when the signal-to-noise ratio (SNR) is below 26dB). However, when faced with sudden, strong interference pulses, signal quality often undergoes a very rapid attenuation process. If the response is only initiated after the absolute value falls below the threshold, it may be too late, resulting in bit errors in data packets or link loss. Therefore, this embodiment performs differential or differential operations on the real-time acquired received signal-to-noise ratio (SNR) or CDR lock jitter data during periodic operation to calculate its first derivative over time, i.e., the rate of change of signal quality. A preset "slope threshold" (e.g., 4dB / ms) is stored in the system configuration register to define the boundary of signal degradation. Subsequently, the calculated rate of change of signal quality is compared with the slope threshold in real time. Assume the current SNR is 30dB (within a safe range), but due to external interference, it drops sharply by 4dB within 1 millisecond. At this point, although the current absolute value (26dB or higher) may not have triggered the conventional degradation threshold, the calculated descent slope has exceeded the preset limit. Based on this, the system determines that the link is in a deterioration process and a failure is imminent. Therefore, the control logic ignores the current absolute value, directly determines that the link performance is deteriorating, and immediately triggers step S103 to forcibly switch from the periodic timer control mode to the performance control mode, and starts the fast refresh trigger strategy.

[0044] In this embodiment, by monitoring the slope of signal quality changes, the system can intervene before the link is actually disconnected. This predictive logic provides the equalizer at the receiving end with a valuable millisecond-level lead time, enabling it to obtain high-density refresh training sequence support in the early stages of degradation. This greatly improves the robustness of the physical layer chip against fast-moving interference sources or transient noise, effectively avoiding unexpected link drops.

[0045] In one embodiment, the execution of the fast triggering strategy specifically includes:

[0046] If a monitoring result signal indicating link performance degradation is received during the current Refresh segment, maintain the complete transmission of the current Refresh segment until the end;

[0047] When the current Refresh segment ends, reset the timing logic of the silent state;

[0048] After the minimum interval waiting time, the next Refresh control signal is generated.

[0049] Specifically, when the physical layer chip is sending or receiving the current Refresh segment, if a monitoring signal indicating link performance degradation is received synchronously, the control logic will not forcibly interrupt the current transmission process. Instead, it will keep the state machine locked and continue sending the current Refresh segment until it is fully transmitted according to the code length specified in the standard. Immediately afterward, at the end of the current Refresh segment, the timing logic used to measure the duration of the quiet state is reset to zero. Subsequently, the system waits only for a preset minimum interval (e.g., the minimum quiet duration Tw_phyp_min required for the physical layer electrical characteristics to recover). Once this short, microsecond-level interval has passed, the system immediately generates the next Refresh control signal, forcibly starting a new round of Refresh transmission, thus skipping the remaining long waiting time in the original periodic timer and achieving tight continuation of Refresh segments.

[0050] In this embodiment, by maintaining the complete transmission of the current refresh segment, human truncation errors or protocol violations caused by abrupt interruption signals are avoided, ensuring that the receiving end can correctly parse the current data. Furthermore, by immediately retransmitting after inserting only the minimum physical interval after the segment ends, this embodiment minimizes invalid silence time and maximizes the refresh signal transmission density per unit time. This transmission strategy can provide the receiving end with sufficient equalizer training sequences at the fastest speed, thereby curbing the trend of performance degradation in the shortest possible time.

[0051] In one embodiment, the method further includes:

[0052] After entering the performance control mode, record the number of consecutive executions of the fast trigger strategy;

[0053] If the number of consecutive executions reaches a preset threshold and the monitoring result signal still indicates link performance deterioration, an exit control signal is generated to force the physical layer chip to exit the low-power sleep mode and return to the normal working mode.

[0054] Specifically, when the control logic switches from periodic timer control mode to performance control mode, the system synchronously activates and resets an internal counter. During subsequent operation, this counter automatically increments each time the system executes a fast trigger strategy and forcibly starts the next Refresh segment. The system compares the current value of this counter with a preset threshold (e.g., set to 10 times) in real time. If the counter value reaches or exceeds this preset threshold, and the received monitoring signal still indicates that the link performance is deteriorating (i.e., the link quality has not improved after multiple intensive training sessions), the system determines that the repair methods in the current sleep mode have failed. Subsequently, a highest-priority exit control signal is generated, directly driving the physical layer chip's state machine to terminate the current LPI process, forcing the chip to exit low-power sleep mode and switch back to normal operating mode (Active Mode) to initiate a full-featured link retraining or renegotiation process.

[0055] In this embodiment, when faced with a severe physical layer fault that cannot be repaired by simply sending Refresh fragments, the physical layer chip can be prevented from endlessly consuming power in performance control mode. By setting a retry limit and forcibly switching to normal working mode, the maintenance attempt in low power mode can be decisively abandoned, and the processing power in normal working mode can be used to rebuild the connection, thus ensuring the final recovery capability of the network connection.

[0056] In one embodiment, the execution fast trigger strategy further includes:

[0057] When sending a Refresh segment in the performance control mode, a power consumption control signal is generated to enable only the transmitter and receiver front-end circuits of the physical layer chip, while keeping the non-critical data processing circuits within the chip in a closed state.

[0058] Specifically, when sending high-density refresh segments in performance control mode, the system's internal power management logic synchronously generates a dedicated power control signal. This signal, through the chip's internal power distribution network, performs selective circuit activation: only the core modules directly related to physical signal transmission in the physical layer chip are activated, namely the transmitter driver circuit and the receiver analog front-end circuit, to ensure that the refresh signal can be correctly modulated and sent to the cable and detected by the other end. At the same time, the system forcibly maintains the non-critical data processing circuits within the chip in a powered-off or clock-gated state. These circuits include, but are not limited to, upper-layer protocol parsing logic, media access control (MAC) interface buffers, and complex digital signal processing units unrelated to link training. Thus, during the entire fast trigger sequence transmission, the chip's activity is strictly limited to the minimum set of the Physical Medium Interconnect (PMA) and Physical Medium Dependent (PMD) layers.

[0059] In this embodiment, it is ensured that even with a significant increase in the transmission density of Refresh segments in performance control mode, the overall dynamic power consumption of the physical layer chip remains at a low level, far lower than the power consumption when switching back to normal operating mode (Active Mode). This design enables the chip to easily cope with the high-frequency signal maintenance needs in harsh environments without sacrificing the core energy-saving advantages of Energy Efficient Ethernet (EEE).

[0060] In one embodiment, the method further includes:

[0061] In the performance control mode, the monitoring result signal is monitored in real time;

[0062] If the monitoring result signal indicates that the link performance has recovered to the normal range, then the fast triggering strategy is terminated;

[0063] Switch the control logic from the performance control mode back to the periodic timer control mode;

[0064] Restart the timing process for the preset time interval and resume periodically sending Refresh segments.

[0065] Specifically, when in performance control mode and executing a fast trigger strategy, the system continuously monitors the monitoring results from the signal performance monitoring unit in real time. Once the monitored feedback data shows that the signal-to-noise ratio of the received signal has risen above the safety threshold, the refresh convergence time has shortened to the historical average level, and the CDR lock jitter data has decreased to the normal range, the system determines that the link performance has successfully recovered to a stable state. In response to this determination, a termination command is immediately executed, stopping the currently looping high-frequency fast trigger strategy and no longer forcibly inserting new refresh segments after short intervals. Immediately afterwards, the system performs a mode switching operation, smoothly switching the state machine's control logic from performance control mode back to the initial periodic timer control mode. Subsequently, the system restarts the hardware timer process for a preset time interval (e.g., 20ms) and resets its count value, thereby restoring the physical layer chip to standard low-power sleep behavior, i.e., sending refresh segments only according to the sparse period specified by the protocol.

[0066] In this embodiment, by promptly terminating high-frequency transmission and switching back to periodic mode after the link recovers its health, unnecessary intensive refreshes are avoided after the interference is eliminated, thus preventing excessive energy consumption. This flexible control mechanism allows the physical layer chip to switch only when necessary, while maintaining energy-saving effects during most stable periods.

[0067] In one embodiment, the step of switching to performance control mode includes:

[0068] The state transition logic of the EEE protocol state machine is reconstructed, and the trigger condition for the state machine to exit the silent state is changed from the timer expiration event to the trigger event of the monitoring result signal.

[0069] Specifically, the system introduces a switchable conditional selection path in the digital control logic of the physical layer chip. In the default configuration, the sole trigger condition for the state machine (which can implement all the logic of the IEEE 802.3 Clause 78 protocol using pure hardware circuitry) to transition from the Quiet state to the Refresh state is hardware-locked as a "timer countdown event" (i.e., the Timer_Done signal is valid). However, when switching to performance control mode, the trigger condition is changed in real-time to a "monitoring result signal trigger event" by modifying the state machine's transition judgment register or activating the internal multiplexer. This means that the state machine's logic decision no longer depends on the accumulation of the timer count value, but is directly linked to the link monitoring result; once the monitoring logic outputs a deterioration warning, the state machine immediately determines that the transition condition is met, ignoring the remaining duration of the current timer, and forcibly drives the transmitting side circuit to exit the Quiet state and enter the Refresh transmission process.

[0070] In this embodiment, by reconstructing the migration logic at the underlying state machine level, the inherent response delay caused by the traditional timer mechanism is eliminated. This design ensures that the physical layer chip has the highest priority in responding to link deterioration events, no longer constrained by the remaining silent time, and achieves near-zero waiting time for immediate intervention. This is crucial for combating rapidly changing channel interference (such as transient impulse noise), thereby greatly improving the system's survivability and connection retention rate in extreme dynamic environments.

[0071] Furthermore, in one embodiment, the steps of switching from the periodic timer control mode to the performance control mode and switching back from the performance control mode to the periodic timer control mode include:

[0072] A first threshold is preset as a deterioration trigger boundary and a second threshold is preset as a recovery confirmation boundary for the same performance parameter, and a hysteresis interval with numerical differences is formed between the first threshold and the second threshold.

[0073] In the periodic timer control mode, the performance parameter is compared with the first threshold in real time. If the performance parameter meets the deterioration condition and crosses the first threshold, then the switch to the performance control mode is executed.

[0074] In the performance control mode, the performance parameter is compared with the second threshold in real time. When the performance parameter meets the recovery condition and crosses the second threshold, the switch to the periodic timer control mode is executed.

[0075] If the performance parameter is within the hysteresis range between the first threshold and the second threshold, the current control mode remains unchanged.

[0076] Specifically, to enhance the stability of the control system under critical environments, the system no longer uses a single numerical value to determine entering and exiting performance control modes. Instead, it configures a set of hysteresis threshold pairs with safety margins for each key performance parameter (such as signal-to-noise ratio, convergence time, or jitter value). Taking the signal-to-noise ratio (SNR) of the received signal as an example, the system sets the "deterioration threshold" to 26dB (corresponding to the first threshold) and the "recovery threshold" to 28dB (corresponding to the second threshold) in the configuration register, thereby constructing a hysteresis range between 26dB and 28dB that can accommodate small signal fluctuations.

[0077] Based on the above configuration, the system executes the following decision control process: When the physical layer chip is running in periodic timer control mode, the control logic continuously monitors the signal-to-noise ratio (SNR); assuming that the current SNR gradually decreases from 30dB due to external interference, even if it drops to 27dB (within the hysteresis range), the system still considers the link to be within the tolerable range and does not switch modes; only when the SNR further deteriorates and falls below the 26dB deterioration threshold does the system determine that the link has suffered a substantial failure, immediately switch to performance control mode, and start the fast trigger strategy.

[0078] Conversely, when the system is in performance control mode performing high-frequency refresh repair, the system continuously evaluates the repair effect. Assuming the signal-to-noise ratio (SNR) begins to recover, even if it rises to 27dB (i.e., above the trigger point but not yet at the recovery point), the system's decision logic considers the link state still unstable and therefore refuses to switch modes, continuing to maintain high-density refresh transmissions to solidify the link. Only when the SNR continues to rise and stably exceeds the 28dB recovery threshold does the system confirm that the interference has been completely eliminated and the link quality has sufficient safety margin. At this point, a mode switching instruction is generated, allowing the state machine to safely switch back to the periodic timer control mode and resume low-power operation.

[0079] In this embodiment, by introducing a hysteresis comparison mechanism, the "ping-pong effect" that easily occurs in control systems under critical disturbance environments is fundamentally solved. In practical applications, if only a single threshold is used, random small fluctuations in link parameters around the threshold will cause the system to oscillate repeatedly between "low-power mode" and "high-performance mode." By constructing a numerical buffer, sufficient controllability of mode switching is ensured, that is, the system only adjusts the control strategy when there is a definite and significant change in the link quality, thereby avoiding ineffective mode switching and significantly improving the stability and logic robustness of the physical layer chip operation.

[0080] Furthermore, some embodiments of this application also provide an electronic device. The electronic device can be various forms of digital computer, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device can also be various forms of mobile devices, such as cellular phones, smartphones, wearable devices, and other similar computing devices.

[0081] The electronic device includes: one or more processors; and a memory storing computer program instructions that, when executed, cause the processor to perform the steps of the methods provided in any one or more of the above embodiments. Figure 3An exemplary structural diagram of the electronic device is disclosed. The electronic device includes one or more processors 1101, a memory 1102, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations. The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0082] The electronic device may further include an input device 1103 and an output device 1104. The processor 1101, memory 1102, input device 1103 and output device 1104 may be connected by a bus or other means, as shown in the figure, which is connected by a bus.

[0083] Input device 1103 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 1104 may include a display device, auxiliary lighting device (e.g., LED), and haptic feedback device (e.g., vibration motor). The display device may include, but is not limited to, a liquid crystal display, a light-emitting diode display, and a plasma display. In some embodiments, the display device may be a touch screen.

[0084] To provide interaction with the user, the electronic device can be a computer. The computer has: a display device (e.g., a cathode ray tube or LCD monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback); and input from the user can be received in any form (e.g., voice input or tactile input).

[0085] In this embodiment, a computer-readable medium stores a computer program / instructions that, when executed by a processor, implement the steps of the methods provided in any one or more of the above embodiments. This computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into that device. The aforementioned computer-readable medium carries one or more computer-readable instructions.

[0086] The memory 1102 can serve as a non-transitory computer-readable storage medium, used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 1101 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the program instructions / modules corresponding to the methods provided in any one or more of the embodiments described above in this application.

[0087] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0088] It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, electrical connections having one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0089] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory, static random access memory, dynamic random access memory, other types of random access memory, read-only memory, electrically erasable programmable read-only memory, flash memory or other memory technologies, read-only optical discs, digital versatile optical discs or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0090] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including local area networks (LANs) or wide area networks (WANs), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0091] In the above embodiments, all or part of the implementation can be achieved through software, hardware, firmware, or any combination thereof. For example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the above steps or functions. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, and similar devices. In addition, some steps or functions of this application can be implemented in hardware, for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0092] The computer program product provided in this application includes one or more computer programs / instructions. When executed by a processor, these computer programs / instructions generate, in whole or in part, the processes or functions described in this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0093] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0095] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A refresh trigger control method based on link performance, characterized in that, The method is applied to a physical layer chip based on the IEEE 802.3az energy-efficient Ethernet protocol and is executed when the physical layer chip is in low-power idle mode (LPI). The method includes: When the physical layer chip is in low-power sleep mode, it runs in periodic timer control mode, and periodically generates refresh control signals according to preset time intervals to drive the transmitter to send refresh segments. Receive monitoring result signals characterizing the health status of the link in real time; determine whether the monitoring result signals indicate link performance degradation; If the indicated link performance deteriorates, switch from the periodic timer control mode to the performance control mode; In the performance control mode, the timing process of the preset time interval is terminated, and a fast triggering strategy is executed to force the start of the next Refresh segment within a preset time after the current Refresh segment ends. The execution of the fast trigger strategy specifically includes: If a monitoring result signal indicating link performance degradation is received during the current Refresh segment, maintain the complete transmission of the current Refresh segment until the end; When the current Refresh segment ends, reset the timing logic of the silent state; After the minimum interval waiting time, the next Refresh control signal is generated; The fast-trigger execution strategy also includes: When sending a Refresh segment in the performance control mode, a power consumption control signal is generated to enable only the transmitter and receiver front-end circuits of the physical layer chip, while keeping the non-critical data processing circuits within the chip in a closed state. The steps for switching to performance control mode include: The state transition logic of the EEE protocol state machine is reconstructed, and the trigger condition for the state machine to exit the silent state is changed from the timer expiration event to the trigger event of the monitoring result signal.

2. The Refresh Trigger Control Method Based on Link Performance according to claim 1, characterized in that, The monitoring result signal indicates at least one of the following specific situations where link performance deteriorates: The signal-to-noise ratio (SNR) of the received signal is lower than the preset SNR threshold. The refresh convergence time of the current refresh segment exceeds a preset multiple of the historical statistical reference value; The clock data recovery lock state is abnormal, and the corresponding lock jitter data exceeds the jitter threshold.

3. The Refresh Trigger Control Method Based on Link Performance according to claim 1, characterized in that, The method further includes: After entering the performance control mode, record the number of consecutive executions of the fast trigger strategy; If the number of consecutive executions reaches a preset threshold and the monitoring result signal still indicates link performance deterioration, an exit control signal is generated to force the physical layer chip to exit the low-power sleep mode and return to the normal working mode.

4. The Refresh Trigger Control Method Based on Link Performance according to claim 1, characterized in that, The method further includes: In the performance control mode, the monitoring result signal is monitored in real time; If the monitoring result signal indicates that the link performance has recovered to the normal range, then the fast triggering strategy is terminated; Switch the control logic from the performance control mode back to the periodic timer control mode; Restart the timing process for the preset time interval and resume periodically sending Refresh segments.

5. An electronic device, characterized in that, The electronic device includes: One or more processors; and A memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method as described in any one of claims 1 to 4.

6. A computer-readable medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 4.

7. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method described in any one of claims 1 to 4.

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