Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a semiconductor layer having a cell region and a terminal region surrounding the cell region; a first insulating film disposed on the semiconductor layer; and a semi-insulating film disposed on the first insulating film. The semiconductor layer includes: a first semiconductor portion of a first conductivity type provided in the cell region and the terminal region; and a second semiconductor part of a second conductivity type provided on the first semiconductor part in the terminal region, the second semiconductor part having a plurality of concentration peak regions in which the concentration of impurities of the second conductivity type is the highest in the second semiconductor part. An end portion of the first insulating film on the end region side is located between any two adjacent concentration peak regions among the plurality of concentration peak regions.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2024-146933 (filed on August 28, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] For example, in semiconductor devices used for power control, an end structure with a semi-insulating film has been proposed to shorten the end region. However, depending on the location of the semi-insulating film, the necessary withstand voltage cannot always be guaranteed. Summary of the Invention

[0005] One embodiment of a semiconductor device includes: a semiconductor layer having a cell region and an end region surrounding the cell region; a first insulating film disposed on the semiconductor layer; and a semi-insulating film disposed on the first insulating film. The semiconductor layer includes: a first semiconductor portion of a first conductivity type disposed in the cell region and the end region; and a second semiconductor portion of a second conductivity type disposed in the end region on the first semiconductor portion, and having a plurality of concentration peak regions within the second semiconductor portion where the impurity concentration of the second conductivity type is highest. Furthermore, the end portion of the first insulating film on the end region side is located between any two adjacent concentration peak regions among the plurality of concentration peak regions.

[0006] According to this embodiment, a semiconductor device capable of shortening the end region and suppressing voltage drop can be provided. Attached Figure Description

[0007] Figure 1 This is a top view that schematically represents the semiconductor device of the first embodiment.

[0008] Figure 2 It is along Figure 1 The cross-sectional view shown is cut off from AA.

[0009] Figure 3 This is a cross-sectional view showing the construction of the first simulation model.

[0010] Figure 4 This is a cross-sectional view showing the construction of the second simulation model.

[0011] Figure 5 This is a cross-sectional view showing the construction of the third simulation model.

[0012] Figure 6 This is a cross-sectional view showing the construction of the fourth simulation model.

[0013] Figure 7 This is a cross-sectional view showing the construction of the fifth simulation model.

[0014] Figure 8 This is a line graph representing the results of TCAD simulations of the pressure resistance characteristics using various simulation models.

[0015] Figure 9 This is a cross-sectional view of the semiconductor device according to the second embodiment. Detailed Implementation

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, these embodiments do not limit the scope of the invention.

[0017] (First Implementation)

[0018] Figure 1 This is a top view that schematically represents the semiconductor device of the first embodiment. Additionally, Figure 2 It is along Figure 1 The cross-sectional view shown is cut off from AA.

[0019] In the following description, the X, Y, and Z axes shown in the figures are sometimes used to illustrate the configuration and structure of the various parts of the semiconductor device. The X, Y, and Z axes are orthogonal to each other and represent the X, Y, and Z directions, respectively. Additionally, in some cases, the Z direction is set upwards and its opposite direction downwards for illustration.

[0020] In addition, p, p + These statements refer to the concentration of p-type impurities increasing in this order. Furthermore, n - n, n + These statements refer to the fact that the concentration of n-type impurities increases in this order.

[0021] Impurity concentration can be determined, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative levels of impurity concentration can be determined, for example, by the levels of carrier concentration obtained through SCM (Scanning Capacitance Microscopy). Additionally, the equidistant depth of the semiconductor region can be determined, for example, by SIMS.

[0022] exist Figure 1The semiconductor device 1 shown can, for example, use an IGBT (Insulated Gate Bipolar Transistor), an IEGT (Injection Enhanced Gate Transistor), or a diode. The semiconductor device 1 in this embodiment includes a semiconductor layer 10, a first electrode 21, a second electrode 22, and a third electrode 23. When the semiconductor device 1 is a diode, the third electrode 23 is not required.

[0023] The semiconductor layer 10 is, for example, made of a silicon substrate. The semiconductor layer 10 has, for example, a back side where the first electrode 21 is disposed and a front side opposite to it. A second electrode 22 and a third electrode 23 are disposed on the front side of the semiconductor layer 10. The semiconductor layer 10 has a unit region R1 and an end region R2.

[0024] The cell region R1 switches between an on and off state depending on the voltage applied to the third electrode 23. In the on state, a current path is generated for current to flow from the first electrode 21 to the second electrode 22. In the off state, no such current path is generated, therefore current does not flow from the first electrode 21 to the second electrode 22.

[0025] The end region R2 is located outside the unit region R1. In the end region R2, the aforementioned current path is not generated regardless of whether a voltage is applied to the third electrode 23, so current does not flow from the first electrode 21 to the second electrode 22.

[0026] Semiconductor layer 10 has a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, a fourth semiconductor layer 14, a fifth semiconductor layer 15, and a sixth semiconductor layer 16. The first semiconductor layer 11 and the sixth semiconductor layer 16 are n-type (first conductivity type). On the other hand, the second semiconductor layer 12, the third semiconductor layer 13, the fourth semiconductor layer 14, and the fifth semiconductor layer 15 are p-type (second conductivity type).

[0027] First Semiconductor Division 11 is n - Type-type drift section. A first semiconductor section 11 is provided in the unit region R1 and the end region R2 respectively.

[0028] The second semiconductor section 12 is a p-type diffusion section. The second semiconductor section 12 is disposed on the first semiconductor section 11 in the terminal region R2. A plurality of concentration peak regions 121 are provided in the second semiconductor section 12. Each concentration peak region 121 is a p-type impurity implantation region, which is the region with the highest concentration of p-type impurities in the second semiconductor section 12.

[0029] like Figure 1As shown, the top view shape of each concentration peak region 121 is a frame that continuously surrounds the unit region R1. In this embodiment, the width (length in the X direction) of each concentration peak region 121 is the same. On the other hand, the distance between the concentration peak regions 121, in other words, the interval between the concentration peak regions 121, decreases as they move away from the unit region R1.

[0030] The third semiconductor section 13 is a p disposed in the end region R2. + Type semiconductor section. The third semiconductor section 13 is connected to the innermost concentration peak region 121 of the plurality of concentration peak regions 121, that is, the concentration peak region 121 closest to the unit region R1.

[0031] The fourth semiconductor unit 14 is disposed in the Z direction between the first semiconductor unit 11 and the first electrode 21, and is connected to the first electrode 21. The fourth semiconductor unit 14 is p in the unit region R1. + Type semiconductor section, p in terminal region R2 - Semiconductor section.

[0032] A fifth semiconductor section 15 is disposed on the first semiconductor section 11 in the cell region R1. The fifth semiconductor section 15 is p + Type base part.

[0033] The sixth semiconductor section 16 is disposed on the fifth semiconductor section 15. The sixth semiconductor section 16 is n + Type contact portion. The sixth semiconductor portion 16 is electrically connected to the second electrode 22 via the contact via 19.

[0034] In the case where semiconductor device 1 is an IGBT or IEGT, such as Figure 2 As shown, a plurality of trench gates 17 are arranged at a predetermined spacing (e.g., 2 μm). Additionally, an n-type semiconductor layer 20 is formed on the front side of the outermost periphery of the end region R2. Furthermore, when the semiconductor device 1 is a diode, neither the trench gates 17 nor the semiconductor layer 20 are provided.

[0035] For example, a trench gate 17 is formed by burying polysilicon in a trench that runs through the fifth semiconductor section 15 and the sixth semiconductor section 16 and terminates at the first semiconductor section 11. Each trench gate 17 is electrically insulated from the first semiconductor section 11, the fifth semiconductor section 15, and the sixth semiconductor section 16 by a gate insulating film 18.

[0036] The first electrode 21 is disposed over the entire area including the cell region R1 and the terminal region R2 on the back side of the semiconductor layer 10. When the semiconductor device 1 is an IGBT or IEGT, the first electrode 21 is the collector. When the semiconductor device 1 is a diode, the first electrode 21 is the anode.

[0037] The second electrode 22 is disposed on the front side of the semiconductor layer 10 via the first insulating film 31. When the semiconductor device 1 is an IGBT or IEGT, the second electrode 22 is the emitter electrode. When the semiconductor device 1 is a diode, the second electrode 22 is the cathode electrode.

[0038] The third electrode 23 is disposed on the front side of the semiconductor layer 10 via the first insulating film 31. In the case that the semiconductor device 1 is an IGBT or an IEGT, the third electrode 23 is the gate electrode.

[0039] The third electrode 23 is positioned opposite the conductor 24 through the first insulating film 31. The third electrode 23 is electrically connected to the conductor 24 via a contact via 25. The conductor 24 is electrically connected to each trench gate 17. Therefore, the potential of each trench gate 17 is controlled by the applied voltage of the third electrode 23. If the applied voltage exceeds a threshold voltage, a channel is formed in the fifth semiconductor section 15. As a result, current flows between the first electrode 21 and the second electrode 22, and the semiconductor device 1 becomes conductive.

[0040] like Figure 2 As shown, in semiconductor device 1, a second insulating film 32 is continuously disposed with a first insulating film 31 in the end region R2. The thickness of the second insulating film 32 is thinner than that of the first insulating film 31. The first insulating film 31 and the second insulating film 32 are, for example, silicon oxide films (SiO2). For example, the second insulating film 32 can be formed by dry etching or wet etching of an insulating film with the same thickness as the first insulating film 31.

[0041] Furthermore, in the semiconductor device 1, a semi-insulating film 40 is disposed on each of the first insulating film 31, the second insulating film 32, the third electrode 23, and the second electrode 22. The top view of the semi-insulating film 40 is a ring shape that continuously surrounds the unit region R1. The resistivity of the semi-insulating film 40 is higher than that of the semiconductor layer 10 and lower than that of the first insulating film 31 and the second insulating film 32. The semi-insulating film 40 contains, for example, nitrogen and silicon. The nitrogen content in the semi-insulating film 40 is preferably 40% or more and 55% or less.

[0042] Furthermore, in the semiconductor device 1, a protective film 50 is disposed on the semi-insulating film 40. The protective film 50 is formed, for example, using a resin such as polyimide.

[0043] In the semiconductor device 1 configured as described above, the semi-insulating film 40 is connected to the second electrode 22 and the third electrode 23. The resistivity of the semi-insulating film 40 is not so low as to short-circuit the second electrode 22 and the third electrode 23 when the semiconductor device 1 is operated. That is, when the semiconductor device 1 is operated, a current of a magnitude that would affect the operation of the semiconductor device 1 will not flow from the third electrode 23 through the semi-insulating film 40 to the second electrode 22, which has a lower potential than the third electrode 23, from the third electrode 23.

[0044] On the other hand, when a high electric field is generated in the end region R2 from the outside of the protective film 50, electrons flow through the semi-insulating film 40 to the third electrode 23. Therefore, electrons are difficult to accumulate in the semi-insulating film 40.

[0045] Furthermore, in semiconductor device 1, if the thickness of the second insulating film 32 is large, the probability of electrons tunneling through the second insulating film 32 becomes lower. Therefore, holes flowing near the boundary between the semiconductor layer 10 and the second insulating film 32 are easily captured by the semi-insulating film 40. If the number of holes captured by the semi-insulating film 40 increases, the electric field distribution in the end region R2 changes, which may cause a change in the breakdown voltage.

[0046] Therefore, in this embodiment, the thickness of the second insulating film 32 disposed between the second semiconductor layer 12 and the semi-insulating film 40 is thinner than the thickness of the first insulating film 31. As a result, a certain amount of electrons tunnel through the semiconductor layer 10, making it difficult for both electrons and holes to be excessively captured by the semi-insulating film 40.

[0047] However, the withstand voltage of semiconductor device 1 may depend on the position of the end 33 of the first insulating film 31 that connects to the second insulating film 32, or in other words, the position of the step portion of the semi-insulating film 40 formed by the thickness change from the first insulating film 31 to the second insulating film 32. Here, refer to Figures 3-8 This is to illustrate the results of TCAD (Technology Computer Aided Design) simulation of the withstand voltage characteristics when the position of the end 33 of the first insulating film 31 is changed.

[0048] Figure 3 This is a cross-sectional view showing the construction of the first simulation model. Figure 3 The first simulation model M1 shown corresponds to the semiconductor device 1 of this embodiment. In the first simulation model M1, a diffusion region 122 is formed around each concentration peak region 121. The diffusion region 122 is a region obtained by thermal diffusion of p-type impurities injected into the concentration peak regions 121. The concentration of p-type impurities in the diffusion region 122 is lower than the concentration of p-type impurities in the concentration peak regions 121.

[0049] The diffusion region 122 can also be formed in an actual semiconductor device 1. Figure 3 In the middle, the end 33 of the first insulating film 31, that is, the step portion where the height position of the semi-insulating film 40 changes, is located between the first concentration peak region 121a, which is closest to the unit region R1 and is connected to the third semiconductor part 13, and the second concentration peak region 121b, which is located outside the first concentration peak region 121a.

[0050] Figure 4 This is a cross-sectional view showing the construction of the second simulation model. Figure 4 In the second simulation model M2 shown, the position of the end 33 of the first insulating film 31 is shifted in the direction from the cell region R1 toward the end region R2 (to the right) compared to the first simulation model M1. As a result, the position of the end 33 of the first insulating film 31 is moved to the left half of the second concentration peak region 121b.

[0051] Figure 5 This is a cross-sectional view showing the construction of the third simulation model. Figure 5 In the third simulation model M3 shown, the position of the end 33 of the first insulating film 31 is further shifted to the right compared to the second simulation model M2. As a result, the position of the end 33 of the first insulating film 31 moves to the center of the second concentration peak region 121b.

[0052] Figure 6 This is a cross-sectional view showing the construction of the fourth simulation model. Figure 6 In the fourth simulation model M4 shown, the position of the end 33 of the first insulating film 31 is further shifted to the right compared to the third simulation model M3. As a result, the end 33 of the first insulating film 31 moves to the right half of the second concentration peak region 121b.

[0053] Figure 7 This is a cross-sectional view showing the construction of the fifth simulation model. Figure 7 In the fifth simulation model M5 shown, the position of the end 33 of the first insulating film 31 is further shifted to the right compared to the fourth simulation model M4. As a result, the end 33 of the first insulating film 31 moves between the second concentration peak region 121b and the third concentration peak region 121c located outside the second concentration peak region 121b.

[0054] Figure 8 This is a line graph showing the results of TCAD simulations of the pressure resistance characteristics using various simulation models. Figure 8 In the diagram, the horizontal axis represents the collector-emitter voltage VCE, and the vertical axis represents the collector-emitter current ICE. Furthermore, in this simulation, the condition is set to a cutoff state where the gate-emitter voltage is lower than the threshold voltage.

[0055] according to Figure 8 The simulation results show that the breakdown voltage V1 of the fourth simulation model M4, the breakdown voltage V2 (>V1) of the third simulation model M3, and the breakdown voltage V3 (>V2) of the second simulation model M2 are lower than the breakdown voltage V4 of the first simulation model M1 and the fifth simulation model M5.

[0056] In the terminal region R2, the electric field strength increases in the concentration peak region 121 with high p-type impurity concentration and at the end 33 of the first insulating film 31 (the stepped portion of the semi-insulating film 40). Therefore, in the second simulation model M2, the third simulation model M3, and the fourth simulation model M4, the electric field strength mutually reinforces each other due to the overlapping structure of the end 33 of the first insulating film 31 and the concentration peak region 121. As a result, the withstand voltage decreases.

[0057] In contrast, in the first simulation model M1 and the fifth simulation model M5, the end 33 of the first insulating film 31 is located between the concentration peak regions 121, and the two do not overlap. That is, the stepped portion of the semi-insulating film 40 is located outside the concentration peak region 121. As a result, the voltage drop can be suppressed.

[0058] As described above, according to this embodiment, the position of the end 33 of the first insulating film 31, or in other words, the stepped portion of the semi-insulating film 40, is optimized, thereby shortening the end region R2 and suppressing the decrease in withstand voltage.

[0059] Furthermore, in this embodiment, the end 33 of the first insulating film 31 is tapered. That is, the end 33 is inclined in such a way that its thickness gradually decreases as it approaches the front side of the semiconductor layer 10. As a result, the electric field strength at the end can be mitigated, thereby further suppressing the decrease in breakdown voltage.

[0060] (Second Implementation)

[0061] Figure 9 This is a cross-sectional view of the semiconductor device according to the second embodiment. Figure 9 In this document, the same reference numerals are used to denote the same constituent elements as those in the semiconductor device 1 of the first embodiment described above, and repeated descriptions are omitted.

[0062] The semiconductor device 2 of the second embodiment differs from the semiconductor device 1 of the first embodiment in that it does not have a second insulating film 32. In the semiconductor device 2 of this embodiment, the semi-insulating film 40 is in contact with the front side of the semiconductor layer 10 at a position opposite to the second semiconductor portion 12.

[0063] On the other hand, in the semiconductor device 2 of this embodiment, similarly to the first embodiment, the end 33 of the first insulating film 31 is located between the concentration peak region 121 connected to the third semiconductor section 13 and other concentration peak regions 121 adjacent to the concentration peak region 121 in the X direction. Therefore, the stepped portion of the semi-insulating film 40 is also located outside the concentration peak region 121. As a result, voltage drop can be suppressed.

[0064] Therefore, according to this embodiment, even if the second insulating film 32 is not formed, the position of the end 33 of the first insulating film 31, in other words, the stepped portion of the semi-insulating film 40, is optimized. Thus, in this embodiment, it is also possible to shorten the end region R2 and suppress the decrease in withstand voltage.

[0065] Furthermore, in this embodiment, since the end 33 of the first insulating film 31 is also tapered, the electric field strength at the end can be mitigated. As a result, the voltage drop can be further suppressed.

[0066] Furthermore, in this embodiment, the terminal region R2 of the semiconductor device 2 may also be provided with the diffusion region 122 described in the first embodiment around the concentration peak region 121. In this case, the end 33 of the first insulating film 31 is located on the diffusion region 122.

[0067] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a semiconductor layer having a cell region and a terminal region surrounding the cell region; a first insulating film provided on the semiconductor layer; and a semi-insulating film provided on the first insulating film; the semiconductor layer includes: a first semiconductor portion of a first conductivity type provided in the cell region and the terminal region; and a second semiconductor portion of a second conductivity type provided on the first semiconductor portion in the terminal region and having a plurality of concentration peak regions of impurities of the second conductivity type having the highest concentration within the second semiconductor portion, an end portion of the first insulating film on the terminal region side is located between any two adjacent concentration peak regions of the plurality of concentration peak regions.

2. The semiconductor device according to claim 1, characterized in that: the semiconductor device further possesses a second insulating film provided between the semi-insulating film and the second semiconductor portion in the terminal region, a thickness of the second insulating film is thinner than a thickness of the first insulating film.

3. The semiconductor device according to claim 1, characterized in that: the semi-insulating film is in contact with the semiconductor layer at a position in the terminal region opposite to the second semiconductor portion (12).

4. The semiconductor device according to claim 1, characterized in that: the second semiconductor portion further has a diffusion region of impurities of the second conductivity type provided around the concentration peak regions, the end portion is located on the diffusion region.

5. The semiconductor device according to claim 2, characterized in that: the second semiconductor portion further has a diffusion region of impurities of the second conductivity type provided around the concentration peak regions, the end portion is located on the diffusion region.

6. The semiconductor device according to claim 3, characterized in that: the second semiconductor portion further has a diffusion region of impurities of the second conductivity type provided around the concentration peak regions, the end portion is located on the diffusion region.

7. The semiconductor device according to claim 1, characterized in that: the end portion is located between a first concentration peak region closest to the cell region and a second concentration peak region located outside the first concentration peak region among the plurality of concentration peak regions.

8. The semiconductor device according to claim 2, characterized in that: the end portion is located between a first concentration peak region closest to the cell region and a second concentration peak region located outside the first concentration peak region among the plurality of concentration peak regions.

9. The semiconductor device according to claim 3, characterized in that: the end portion is located between a first concentration peak region closest to the cell region and a second concentration peak region located outside the first concentration peak region among the plurality of concentration peak regions.

10. The semiconductor device according to claim 1, characterized in that: the semi-insulating film contains silicon and nitrogen, a composition ratio of nitrogen in the semi-insulating film is 40% or more and 55% or less.

11. The semiconductor device according to claim 2, characterized in that: the semi-insulating film contains silicon and nitrogen, a composition ratio of nitrogen in the semi-insulating film is 40% or more and 55% or less. The composition ratio of nitrogen in the semi-insulating film is 40% or more and 55% or less.

12. The semiconductor device according to claim 3, wherein The semi-insulating film contains silicon and nitrogen, The composition ratio of nitrogen in the semi-insulating film is 40% or more and 55% or less.

13. The semiconductor device according to claim 7, wherein The semiconductor layer further has a third semiconductor portion of the second conductivity type in the end region in contact with the first concentration peak region, The impurity concentration in the third semiconductor portion is higher than the impurity concentration in the first concentration peak region.

14. The semiconductor device according to claim 1, wherein The planar shape of the concentration peak region is a frame shape continuously surrounding the cell region.

15. The semiconductor device according to claim 1, wherein The interval of the concentration peak regions from each other becomes shorter as it is farther from the cell region.

16. The semiconductor device according to claim 1, wherein The resistivity of the semi-insulating film is higher than the resistivity of the semiconductor layer and lower than the resistivity of the first insulating film.

17. The semiconductor device according to claim 3, wherein The end portion is located between a second concentration peak region located on the outer side of a first concentration peak region closest to the cell region among the plurality of concentration peak regions and a third concentration peak region located on the outer side of the second concentration peak region.

18. The semiconductor device according to claim 1, wherein Further comprising: a first electrode provided on the back surface side of the semiconductor layer; and a second electrode and a third electrode provided on the front surface side of the semiconductor layer, The semi-insulating film is in contact with the second electrode and the third electrode.

19. The semiconductor device according to claim 18, wherein The semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) or an IEGT (Injection Enhanced Gate Transistor).

20. The semiconductor device according to claim 1, wherein The first conductivity type is n-type and the second conductivity type is p-type.

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