Semiconductor device, preparation method thereof and power device
By forming the gate dielectric layer of a semiconductor device through a single thermal oxidation process, the problem of complex gate oxide layer preparation is solved, the process steps are simplified, and production efficiency and device performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-03-31
AI Technical Summary
In the prior art, the gate oxide fabrication process of shielded gate field-effect transistors (SGT) and super barrier rectifiers (SBR) is complex and prone to accumulating process errors, which affects the performance of semiconductor devices.
The first gate dielectric layer is formed by a single thermal oxidation process, and the first dielectric layer retained in the second gate trench serves as the second gate dielectric layer, thus eliminating the need for etching a portion of the thin gate dielectric layer and multiple processes of secondary thermal oxidation.
It simplifies the fabrication process, shortens the production cycle, improves production efficiency, reduces process errors, and enhances device yield and reliability.
Smart Images
Figure CN121772307A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a power device. Background Technology
[0002] Integrated devices combining shielded gate field-effect transistors (SGT FETs) and super barrier rectifiers (SBRs) are widely used in high-efficiency, high-frequency power conversion applications, such as DC-DC converters, AC-DC converters, and power factor correction (PFC) circuits.
[0003] The aforementioned semiconductor devices need to achieve both high dynamic switching performance and low on-state voltage drop. Therefore, the high dynamic switching performance of shielded gate field-effect transistors (SGTs) requires a thinner gate oxide layer to reduce on-resistance, while the low on-state voltage drop of super-power rectifiers (SBRs) requires a thicker gate oxide layer to achieve barrier characteristics.
[0004] However, the fabrication processes for the gate oxide layers of current shielded gate field-effect transistors (SGTs) and super barrier rectifiers (SBRs) are relatively complex, which can easily lead to the accumulation of process errors in semiconductor devices and reduce their performance. Summary of the Invention
[0005] In view of the above problems, this application provides a semiconductor device and its fabrication method, as well as a power device, which can reduce the complexity of the semiconductor device fabrication process.
[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:
[0007] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, comprising:
[0008] A substrate having a cell region and a terminal region is provided, and the substrate is patterned to form a plurality of gate trenches in the substrate; wherein the plurality of gate trenches include a plurality of first gate trenches and a plurality of second gate trenches;
[0009] A dielectric layer is formed, which at least covers the inner walls of the plurality of gate trenches. The dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together, wherein the material of the second dielectric layer is silicon nitride.
[0010] A shielding gate is formed within the plurality of gate trenches, and the top surface of the shielding gate located within the cell region is lower than the top surface of the substrate;
[0011] Using the second dielectric layer as an etching stop layer, at least the exposed third dielectric layer is removed;
[0012] A first mask layer is formed, wherein the first mask layer exposes at least a first gate trench located within the cell region;
[0013] Using the first mask layer as a mask, the second dielectric layer and the first dielectric layer located in the first gate trench are removed, as well as the first mask layer is removed;
[0014] A first thermal oxidation process is performed to form a first gate dielectric layer on the inner wall of the first gate trench, wherein the thickness of the first gate dielectric layer is greater than the thickness of the first dielectric layer.
[0015] The second dielectric layer exposed in the second gate trench is removed such that the retained first dielectric layer constitutes the second gate dielectric layer, and the dielectric layer retained in the gate trench and surrounding the shielding gate constitutes the field oxide layer.
[0016] A gate is formed in the gate trench. The gate located in the first gate trench and the second gate dielectric layer constitute a rectifier transistor. The gate located in the second gate trench and the second gate dielectric layer constitute a control transistor.
[0017] In one possible implementation, the step of forming the dielectric layer includes:
[0018] A second thermal oxidation process is performed to form a first dielectric layer, which covers the inner walls of the plurality of gate trenches and the top surface of the substrate. The material of the first dielectric layer is silicon oxide.
[0019] A first deposition process is performed to form a second dielectric layer, which covers the first dielectric layer.
[0020] A second deposition process is performed to form a third dielectric layer, which covers the second dielectric layer and is made of silicon oxide.
[0021] In one possible implementation, the step of forming a shielding gate within the plurality of gate trenches includes:
[0022] A shielding gate material layer is formed within the plurality of gate trenches, and a portion of the thickness of the shielding gate material layer is removed;
[0023] A second mask layer is formed, which exposes the gate trench located within the cell region;
[0024] Using the second mask layer as a mask, a portion of the thickness of the shielding grid material layer is removed to form the shielding grid;
[0025] Remove the second mask layer.
[0026] In one possible implementation, the step of using the second dielectric layer as an etch stop layer further includes:
[0027] The third dielectric layer, which surrounds the shielding grid, is also partially removed to create a gap between the shielding grid and the dielectric layer.
[0028] In one possible implementation, the step of using the first mask layer as a mask further includes:
[0029] The dielectric layer, including a portion of its thickness surrounding the shielding grid, is also removed such that the top surface of the remaining dielectric layer is lower than the top surface of the shielding grid.
[0030] In one possible implementation, prior to the step of forming the gate within the gate trench, the fabrication method further includes:
[0031] A third deposition process is performed to form a fourth dielectric layer, which covers the top surface of the inner structure located in the gate trench.
[0032] In one possible implementation, after the step of forming the gate within the gate trench, the fabrication method includes:
[0033] A fourth mask layer is formed, which covers the terminal area;
[0034] Using the fourth mask layer as a mask, a doping process is performed to form a doped region, which includes a first doped region and a second doped region stacked together. The conductivity type of the first doped region is different from that of the second doped region.
[0035] In one possible implementation, after the step of forming the doped region, the fabrication method further includes:
[0036] A conductive plug is formed, and the conductive plug is electrically connected to the doped region.
[0037] Secondly, embodiments of this application provide a semiconductor device, which is fabricated by the semiconductor device fabrication method described in the first aspect, and the semiconductor device includes:
[0038] The base consists of interconnected cell regions and terminal regions;
[0039] A shielding grid is disposed within the substrate;
[0040] A field oxide layer is disposed within the substrate and surrounds the shielding gate. The field oxide layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together, wherein the material of the second dielectric layer is silicon nitride.
[0041] A rectifier transistor is disposed within a cell region of the substrate and is insulated from the shielding gate;
[0042] A control transistor is disposed within the cell region of the substrate and is offset from the rectifier transistor.
[0043] Thirdly, embodiments of this application provide a power device, including the semiconductor device described in the second aspect.
[0044] In the semiconductor device and its fabrication method provided in this application embodiment, and in the power device, only a single thermal oxidation process is used to form the first gate dielectric layer, and the first dielectric layer retained in the second gate trench constitutes the second gate dielectric layer. This eliminates the need for multiple steps of "etching a portion of the thin gate dielectric layer + secondary thermal oxidation," reducing repetitive process steps, effectively shortening the semiconductor device production cycle, and improving production line efficiency.
[0045] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor devices and their preparation methods and power devices provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;
[0048] Figure 2 A schematic diagram illustrating the formation of a third mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0049] Figure 3 A schematic diagram illustrating the formation of a gate trench in a method for fabricating a semiconductor device according to an embodiment of this application;
[0050] Figure 4A schematic diagram illustrating the removal of a portion of the third mask layer in the fabrication process of the semiconductor device provided in this application embodiment;
[0051] Figure 5 This is a schematic diagram illustrating the formation of a dielectric layer in the fabrication process of a semiconductor device provided in this application embodiment;
[0052] Figure 6 A schematic diagram illustrating the formation of a shielding gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0053] Figure 7 This is a schematic diagram of the removal of a portion of the shielding gate material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 1 ;
[0054] Figure 8 This is a schematic diagram of the removal of a portion of the shielding gate material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 2 ;
[0055] Figure 9 A schematic diagram of the formation of a shielding gate in the method for fabricating a semiconductor device provided in this application embodiment. Figure 2 ;
[0056] Figure 10 This is a schematic diagram illustrating the removal of the third dielectric layer in the fabrication method of the semiconductor device provided in this application embodiment;
[0057] Figure 11 A schematic diagram illustrating the formation of a first mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0058] Figure 12 A schematic diagram of the removal of the second dielectric layer and the first dielectric layer in the method for fabricating a semiconductor device provided in this application embodiment. Figure 1 ;
[0059] Figure 13 A schematic diagram of the removal of the second dielectric layer and the first dielectric layer in the method for fabricating a semiconductor device provided in this application embodiment. Figure 2 ;
[0060] Figure 14 A schematic diagram of the formation of the first gate dielectric layer in the method for fabricating the semiconductor device provided in the embodiments of this application;
[0061] Figure 15 This is a schematic diagram illustrating the removal of a portion of the film layer within the second gate trench in the fabrication method of the semiconductor device provided in this application embodiment;
[0062] Figure 16 This is a schematic diagram illustrating the formation of a fourth dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0063] Figure 17 This is a schematic diagram illustrating the formation of a gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0064] Figure 18 This is a schematic diagram of the formation of a gate in a method for fabricating a semiconductor device provided in an embodiment of this application;
[0065] Figure 19 A schematic diagram illustrating the formation of a fourth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0066] Figure 20 This is a schematic diagram illustrating the formation of an insulating layer in a method for fabricating a semiconductor device according to an embodiment of this application.
[0067] Figure 21 A schematic diagram illustrating the formation of a fifth mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;
[0068] Figure 22 This is a schematic diagram illustrating the formation of contact holes in a method for fabricating a semiconductor device according to an embodiment of this application.
[0069] Figure 23 This is a schematic diagram of forming a conductive plug in a method for fabricating a semiconductor device provided in an embodiment of this application.
[0070] Explanation of reference numerals in the attached figures:
[0071] 10: Substrate; 11: Cell region; 12: Termination region; 13: First gate trench; 14: Second gate trench;
[0072] 20: Third mask layer; 21: Sub-mask layer; 22: Photoresist layer;
[0073] 30: Dielectric layer; 31: First dielectric layer; 32: Second dielectric layer; 33: Third dielectric layer; 34: Gap;
[0074] 40: Shielding grid; 41: Shielding grid material layer; 42: Filling area;
[0075] 50: Second mask layer;
[0076] 60: First mask layer;
[0077] 70: First gate dielectric layer;
[0078] 80: Second gate dielectric layer;
[0079] 90: Fourth dielectric layer;
[0080] 100: Gate; 101: Gate material layer;
[0081] 110: Field oxide layer;
[0082] 120: Fourth mask layer;
[0083] 130: Doped region; 131: First doped region; 132: Second doped region; 133: Heavily doped region;
[0084] 140: Insulation layer;
[0085] 150: Fifth mask layer;
[0086] 160: Conductive plug; 161: Contact hole. Detailed Implementation
[0087] In related technologies, the fabrication processes of the gate oxide layer in shielded gate field-effect transistors (SGTs) and super barrier rectifiers (SBRs) are relatively complex, which easily leads to the accumulation of process errors in semiconductor devices and reduces their performance. Research has revealed that it is necessary to first remove the material layer located within the gate trench using an etching process, followed by a first thermal oxidation process to form a thinner gate dielectric layer within the gate trench. Then, a portion of the thinner gate dielectric layer within the gate trench is removed using etching, followed by a second thermal oxidation process to form a thicker gate dielectric layer in this portion of the gate trench. This increases the number of thermal oxidation processes.
[0088] To address the aforementioned technical problems, this application provides a semiconductor device and its fabrication method, as well as a power device, which uses only a single thermal oxidation process to form the first gate dielectric layer. The first dielectric layer retained within the second gate trench constitutes the second gate dielectric layer. This eliminates the need for multiple steps involving "etching a portion of the thin gate dielectric layer + secondary thermal oxidation," reducing repetitive process steps, effectively shortening the semiconductor device production cycle, and improving production line efficiency.
[0089] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0090] Please refer to Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:
[0091] Step S100: Provide a substrate having a cell region and a terminal region, and pattern the substrate to form a plurality of gate trenches in the substrate; wherein the plurality of gate trenches include a plurality of first gate trenches and a plurality of second gate trenches.
[0092] Please refer to Figure 2 The substrate 10 serves as a support component for a semiconductor device, supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 includes a substrate and an epitaxial layer disposed on the substrate.
[0093] The substrate 10 includes adjacent cell regions 11 and terminal regions 12. Cell regions 11 are the main functional regions in a semiconductor device, typically containing multiple repeating unit structures or cells. Terminal regions 12 are areas located around cell regions 11, typically used to support and protect the normal operation of cell regions 11.
[0094] Subsequently, a third mask layer 20 can be formed on the substrate 10. The third mask layer 20 can be a photoresist layer or other stacked structures. Exemplarily, the third mask layer 20 includes at least two sub-mask layers 21 and a photoresist layer 22, which are stacked on the substrate 10. In some embodiments of this application, the at least two sub-mask layers 21 are two layers, where both the sub-mask layer and the other sub-mask layer are made of silicon oxide. The sub-mask layer 21 connected to the substrate 10 can be prepared using a thermal oxidation process. This ensures that the sub-mask layer 21 has high purity and quality, and makes the top surface of the sub-mask layer 21 as flat as possible, improving the interface flatness of the sub-mask layer 21.
[0095] Subsequently, another sub-mask layer 21 of a certain thickness is formed on the sub-mask layer 21 through a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0096] Next, please refer to Figure 3 Using the third mask layer 20 as a mask, the substrate 10 is patterned to form a plurality of gate trenches on the substrate 10, wherein the plurality of gate trenches include a plurality of first gate trenches 13 and a plurality of second gate trenches 14.
[0097] Please refer to Figure 4 Remove the photoresist layer 22 and a portion of the sub-mask layer 21. This step can be performed using a cleaning and etching process, or a cleaning and chemical mechanical polishing process.
[0098] In this embodiment, the third mask layer 20 includes at least two sub-mask layers 21, thereby improving the accuracy of the pattern in the photoresist layer 22 during the transfer to the substrate 10.
[0099] It should be noted that the extension direction of the gate trench can be tilted relative to the horizontal direction, and Figure 3 The mid-section lines can be parallel to the horizontal direction to allow multiple gate trenches to be displayed on the cross-sectional view. Some of these gate trenches are located within the cell region, and some are located within the termination region. Figure 3 For example, from right to left, we cut out a section of the first, second and third gate trenches in cell region 11, and a section of the fourth gate trench in terminal region 12.
[0100] Step S200: Form a dielectric layer, which covers at least the inner walls of multiple gate trenches. The dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together. The material of the second dielectric layer is silicon nitride.
[0101] Please refer to Figure 5 For example, a second thermal oxidation process is performed to form a first dielectric layer 31, which covers the inner walls of a plurality of gate trenches and the top surface of the substrate 10. The material of the first dielectric layer 31 is silicon oxide.
[0102] A first deposition process is performed to form a second dielectric layer 32, which covers the first dielectric layer 31.
[0103] A second deposition process is performed to form a third dielectric layer 33, which covers the second dielectric layer 32, and the material of the third dielectric layer 33 is silicon oxide.
[0104] Step S300: A shielding gate is formed in a plurality of gate trenches, wherein the top surface of the shielding gate located in the cell region is lower than the top surface of the substrate.
[0105] Please refer to Figure 6 For example, a shielding gate material layer 41 is formed within a plurality of gate trenches, and a portion of the thickness of the shielding gate material layer 41 is removed. In this embodiment, the shielding gate material layer 41 is made of polysilicon.
[0106] For details, please refer to Figure 7A chemical mechanical polishing (CMP) process is performed to remove part of the thickness of the shielding grid material layer 41 in order to planarize the shielding grid material layer 41 so that the top surface of the shielding grid material layer 41 is flush with the top surface of the dielectric layer 30.
[0107] Please refer to Figure 8 An etching process is performed to remove a portion of the shielding gate material layer 41, leaving the top surface of the remaining shielding gate material layer 41 between the top surface of the dielectric layer 30 and the top surface of the substrate 10. This creates a filling region 42 between the shielding gate material layer 41 and the dielectric layer 30.
[0108] Please refer to Figure 9 A second mask layer 50 is formed, which exposes the gate trench located in the cell region 11.
[0109] Please refer to Figure 10 Using the second mask layer 50 as a mask, a portion of the thickness of the shielding grid material layer 41 is removed to form the shielding grid 40.
[0110] Please refer to Figure 11 Perform a cleaning process to remove the second mask layer 50.
[0111] Step S400: Using the second dielectric layer as an etching stop layer, at least the exposed third dielectric layer is removed.
[0112] In this embodiment, the second dielectric layer 32 is made of silicon nitride and the third dielectric layer 33 is made of silicon oxide. By utilizing the difference in materials, the etching rates of the second dielectric layer 32 and the third dielectric layer 33 are different under the same etching process.
[0113] This allows for adjustment of the etching parameters in the etching process, using the second dielectric layer as the etching stop layer, and at least removing the exposed third dielectric layer 33. This setup reduces the need for a single photomask, saving on design and manufacturing costs, shortening the lithography process operation time, and lowering the equipment occupancy and maintenance costs of the lithography machine. This reduces overall process costs from both material and labor perspectives.
[0114] It should be noted that, in this embodiment, removing at least the exposed third dielectric layer 33 can be understood as removing the third dielectric layer 33 within the gate trench and the third dielectric layer 33 located on the substrate 10. Other interpretations are also possible.
[0115] In one possible implementation, the step of using the second dielectric layer as the etch stop layer further includes:
[0116] Please refer to Figure 10Furthermore, a portion of the thickness of the third dielectric layer 33 surrounding the shielding gate 40 is removed, so that a gap 34 is formed between the shielding gate 40 and the dielectric layer 30. It should be noted that the gap 34 may be located in the third dielectric layer 33 surrounding the outer periphery of the shielding gate 40, or the gap 34 may be located between the outer periphery of the shielding gate 40 and the second dielectric layer 32.
[0117] Step S500: Form a first mask layer, the first mask layer at least exposing a first gate trench located within a cell region.
[0118] Please refer to Figure 11 The first mask layer 60 also covers a portion of the second dielectric layer 32 located on the substrate 10.
[0119] Step S600: Using the first mask layer as a mask, remove the second dielectric layer and the first dielectric layer located in the first gate trench, and remove the first mask layer.
[0120] Please refer to Figure 12 and Figure 13 Using the first mask layer 60 as a mask, an etching process is performed to remove the second dielectric layer 32 and the first dielectric layer 31 located within the first gate trench 13, thereby exposing a portion of the inner wall of the first gate trench 13. It should be noted that the etching process can be either dry etching or wet etching.
[0121] It should be noted that in this step, a portion of the dielectric layer 30 surrounding the shielding grid 40 is also removed so that the top surface of the remaining dielectric layer 30 is lower than the shielding grid 40.
[0122] Step S700: Perform a first thermal oxidation process to form a first gate dielectric layer on the inner wall of the first gate trench, wherein the thickness of the first gate dielectric layer is greater than the thickness of the first dielectric layer.
[0123] Please refer to Figure 14 The first gate dielectric layer 70 is made of silicon oxide, and the thickness of the first gate dielectric layer 70 is greater than the thickness of the first dielectric layer 31.
[0124] Step S800: Remove the second dielectric layer exposed in the second gate trench, such that the retained first dielectric layer constitutes the second gate dielectric layer, and the dielectric layer retained in the gate trench and surrounding the shielding gate constitutes the field oxide layer.
[0125] Please refer to Figure 15In this embodiment, the material of the second dielectric layer 32 is different from that of the first gate dielectric layer 70 and the first dielectric layer 31. This allows for adjustment of the etching parameters in the etching process, and the first dielectric layer 31 and the first gate dielectric layer 70 are used as etching stop layers to at least remove the exposed second dielectric layer 32. This configuration reduces the number of photomasks, saving on photomask design and manufacturing costs, shortening the lithography process operation time, and reducing the equipment occupancy and maintenance costs of the lithography machine. This reduces the overall process cost from both material and time perspectives.
[0126] It should be noted that, in this embodiment of the application, in addition to the second dielectric layer 32 exposed in the second gate trench 14, a portion of the thickness of the second dielectric layer 32 surrounding the outer periphery of the shielding gate 40 is also removed.
[0127] Step S900: A gate is formed in the gate trench. The gate in the first gate trench and the second gate dielectric layer constitute a rectifier transistor, and the gate in the second gate trench and the second gate dielectric layer constitute a control transistor.
[0128] Please refer to Figure 17 For example, a gate material layer 101 is formed, which fills the gate trench and extends to the top surface of the substrate 10.
[0129] Please refer to Figure 18 A chemical mechanical polishing process is performed to remove the gate material layer 101 on the top surface of the substrate 10 to form the gate 100. The gate located in the first gate trench and the second gate dielectric layer constitute a rectifier transistor, and the gate located in the second gate trench and the second gate dielectric layer constitute a control transistor.
[0130] In related technologies, it is necessary to first remove the material layer located in the gate trench through an etching process, then perform a first thermal oxidation process to form a thinner gate dielectric layer in the gate trench. After that, a portion of the thinner gate dielectric layer in the gate trench is removed through an etching process, and then a second thermal oxidation process is performed to form a thicker gate dielectric layer in this portion of the gate trench. This increases the number of thermal oxidation processes.
[0131] In this embodiment, the first gate dielectric layer 70 is formed using only one thermal oxidation process, and the first dielectric layer 31 retained in the second gate trench 14 constitutes the second gate dielectric layer 80. This eliminates the need for multiple processes such as "etching a portion of the thin gate dielectric layer + secondary thermal oxidation", reducing repetitive operations in the process, effectively shortening the production cycle of semiconductor devices, and improving the production efficiency of the production line.
[0132] Furthermore, in traditional multi-stage thermal oxidation and etching processes, each process step may introduce issues such as film thickness uniformity deviations and interface defects, which, when accumulated multiple times, exacerbate performance fluctuations in the gate dielectric layer. This solution forms the first gate dielectric layer through a single thermal oxidation step, and combines this retained first dielectric layer as the second gate dielectric layer. This reduces repeated disturbances to the dielectric layer caused by process steps, lowers the risk of interface state density and film thickness non-uniformity, ensures the insulation performance and electrical stability of the gate dielectric layer, and thus improves the yield and reliability of semiconductor devices.
[0133] In one possible implementation, prior to the step of forming the gate within the gate trench, the fabrication method further includes:
[0134] Please refer to Figure 16 A third deposition process is performed to form a fourth dielectric layer 90, which covers the top surface of the inner structure located in the gate trench.
[0135] In the first gate trench 13, a fourth dielectric layer 90 covers the top surface of the first gate dielectric layer 70. In the second gate trench 14, the fourth dielectric layer 90 covers the top surface of the shielding gate 40 and surrounds the shielding gate 40. In this embodiment, the fourth dielectric layer 90 is made of silicon oxide.
[0136] In this embodiment, the fourth dielectric layer 90 can further improve the insulation between the gate 100 and the shielding gate 40 formed subsequently, thereby improving the yield of the semiconductor device.
[0137] In one possible implementation, after the step of forming the gate within the gate trench, the fabrication method includes:
[0138] Please refer to Figure 19 This forms a fourth mask layer 120, which covers the terminal area 12.
[0139] Using the fourth mask layer 120 as a mask, a doping process is performed to form a doped region 130. The doped region 130 includes a first doped region 131 and a second doped region 132 stacked together. The conductivity type of the first doped region 131 is different from that of the second doped region 132.
[0140] For example, using the fourth mask layer 120 as the mask layer, a first doping process is performed to form an initial doped region in the substrate 10, for example, the initial doped region has a P-type conductivity. Then, a second doping process is performed to form a second doped region 132 within the initial doped region, the second doped region 132 having an N-type conductivity. Thus, the retained initial doped region constitutes the first doped region 131.
[0141] Afterwards, a cleaning process is performed to remove the fourth mask layer 120.
[0142] In one possible implementation, after the step of forming the doped region, the fabrication method further includes:
[0143] A conductive plug is formed, and the conductive plug is electrically connected to the doped region.
[0144] For example, please refer to Figure 20 An insulating layer 140 is formed on the substrate 10.
[0145] Please refer to Figure 21 A fifth mask layer 150 is formed on the insulating layer 140, and the fifth mask layer is patterned.
[0146] Please refer to Figure 22 Using a fifth mask layer as a mask, the insulating layer 140 and the substrate 10 are patterned to form a contact hole 161, which exposes the second doped region 132. It should be noted that, in order to reduce the contact resistance between the second doped region 132 and the subsequently formed conductive plug 160, the fabrication method provided in this embodiment further includes forming a heavily doped region 133, the concentration of which is greater than the concentration of the second doped region 132.
[0147] This configuration reduces the contact resistance between the conductive plug and the corresponding device, which helps improve current transmission efficiency and reduce power loss. It also improves the overall performance of the semiconductor device, including switching speed, signal transmission speed, and current drive capability.
[0148] Please refer to Figure 23 A conductive plug is formed in the contact hole 161, and the conductive plug is electrically connected to the second doped region 132.
[0149] It should be noted that the contact hole 161 can also be located on the terminal area 12. In this case, the contact hole 161 exposes the shielding grid 40, so that the conductive plug located in the terminal area 12 can be electrically connected to the shielding grid 40.
[0150] As can be clearly seen from the above embodiments, five photomasks are used in the fabrication process of semiconductor devices. Compared with the approximately eight photomasks required in related technologies, this greatly reduces the frequency of photomask usage, thereby simplifying the semiconductor device fabrication process and reducing fabrication costs.
[0151] Please refer to Figure 23 This application also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described in any of the above embodiments. The semiconductor device includes:
[0152] The substrate 10 includes interconnected cell regions 11 and terminal regions 12.
[0153] The shielding grid 40 is disposed within the base 10.
[0154] A field oxide layer 110 is disposed within the substrate 10 and surrounds the shielding gate 40. The field oxide layer 110 includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together, wherein the second dielectric layer is made of silicon nitride. It should be noted that the field oxide layer 110 is a retaining of the aforementioned dielectric layers.
[0155] The rectifier transistor is disposed within the cell region 11 of the substrate and is insulated from the shielding gate 40.
[0156] The control transistor is located within the cell region 11 of the substrate and is offset from the rectifier transistor.
[0157] In the embodiments of this application, the second gate dielectric layer of the rectifier transistor is formed simultaneously with the first dielectric layer of the field oxide layer, which can reduce the fabrication steps of the semiconductor device.
[0158] This application also provides a power device, including the semiconductor device described in any of the above embodiments. The power device provided in this application can be applied to discrete devices, AC-DC converters, or temperature sensors.
[0159] It should be noted that the beneficial effects of the power device provided in this application embodiment are the same as the beneficial effects of the semiconductor device provided in the above embodiment, and will not be elaborated further in this embodiment.
[0160] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0161] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.
[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate with a cell region and a terminal region, and patterning the substrate to form a plurality of gate trenches in the substrate; wherein the plurality of gate trenches comprises a plurality of first gate trenches and a plurality of second gate trenches; forming a dielectric layer covering at least the inner walls of the plurality of gate trenches, the dielectric layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together, the second dielectric layer being made of silicon nitride; forming a shield gate in the plurality of gate trenches, and the top surface of the shield gate located in the cell region being lower than the top surface of the substrate; removing at least the exposed third dielectric layer with the second dielectric layer as an etching stop layer; forming a first mask layer, the first mask layer exposing at least the first gate trenches located in the cell region; removing the second dielectric layer and the first dielectric layer located in the first gate trenches with the first mask layer as a mask, and removing the first mask layer; performing a first thermal oxidation process to form a first gate dielectric layer on the inner walls of the first gate trenches, the thickness of the first gate dielectric layer being greater than the thickness of the first dielectric layer; removing the second dielectric layer exposed in the second gate trenches, so that the remaining first dielectric layer constitutes a second gate dielectric layer, and the dielectric layer remaining in the gate trenches and surrounding the shield gate constitutes a field oxide layer; forming a gate in the gate trenches, the gate located in the first gate trenches and the second gate dielectric layer constituting a rectifier transistor, and the gate located in the second gate trenches and the second gate dielectric layer constituting a control transistor.
2. The method of producing a semiconductor device according to claim 1, wherein The step of forming a dielectric layer comprises: performing a second thermal oxidation process to form a first dielectric layer, the first dielectric layer covering the inner walls of the plurality of gate trenches and the top surface of the substrate, the first dielectric layer being made of silicon oxide; performing a first deposition process to form a second dielectric layer, the second dielectric layer covering the first dielectric layer; performing a second deposition process to form a third dielectric layer, the third dielectric layer covering the second dielectric layer, and the third dielectric layer being made of silicon oxide.
3. The method of producing a semiconductor device according to claim 2, wherein The step of forming a shield gate in the plurality of gate trenches comprises: forming a shield gate material layer in the plurality of gate trenches, and removing part of the thickness of the shield gate material layer; forming a second mask layer, the second mask layer exposing the gate trenches located in the cell region; removing part of the thickness of the shield gate material layer with the second mask layer as a mask to form the shield gate; removing the second mask layer.
4. The method of producing a semiconductor device according to any one of claims 1 to 3, wherein The step of taking the second dielectric layer as an etching stop layer further comprises: further removing part of the thickness of the third dielectric layer surrounding the shield gate, so that a gap is formed between the shield gate and the dielectric layer.
5. The method of producing a semiconductor device according to claim 4, wherein The step of taking the first mask layer as a mask further comprises: further removing part of the thickness of the dielectric layer surrounding the shield gate, so that the top surface of the remaining dielectric layer is lower than the top surface of the shield gate.
6. The method of producing a semiconductor device according to claim 5, wherein Before the step of forming a gate in the gate trenches, the preparation method further comprises: A third deposition process is performed to form a fourth dielectric layer covering the top surface of the inner structure of the gate trench.
7. The method of producing a semiconductor device according to any one of claims 1 to 3, wherein After the step of forming the gate in the gate trench, the preparation method comprises: A fourth mask layer is formed covering the termination region; A doping process is performed with the fourth mask layer as a mask to form a doped region, the doped region comprising a first doped region and a second doped region arranged in a stack, the first doped region having a different conductivity type from the second doped region.
8. The method of producing a semiconductor device according to Claim 7, wherein After the step of forming the doped region, the preparation method further comprises: A conductive plug is formed electrically connected with the doped region.
9. A semiconductor device, characterized by comprising: The semiconductor device is prepared by the preparation method of the semiconductor device according to any one of claims 1-8; the semiconductor device comprises: a substrate comprising a cell region and a termination region connected to each other; a shield gate disposed in the substrate; a field oxide layer disposed in the substrate and surrounding the shield gate, the field oxide layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer arranged in a stack, the second dielectric layer being made of silicon nitride; a rectifier transistor disposed in the cell region of the substrate and insulated from the shield gate; a control transistor disposed in the cell region of the substrate and misaligned with the rectifier transistor.
10. A power device, characterized by The semiconductor device according to claim 9.