Three-dimensional dynamic random access memory and manufacturing method therefor

Abstract

The present application relates to the technical field of memories. Disclosed are a three-dimensional dynamic random access memory and a manufacturing method therefor, which are used for increasing the storage density of dynamic random access memories, and increasing the contact area between a source region of a transistor and a contact structure or a capacitor as well as between a drain region of a transistor and a contact structure or a capacitor, thereby reducing contact resistance, and ameliorating electric leakage. The three-dimensional dynamic random access memory comprises a plurality of memory cells distributed in a three-dimensional array and a dielectric structure used for isolating different memory cells; each memory cell comprises a transistor and a capacitor, the transistor comprising a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of each channel region is parallel to a second direction, and two sidewalls of each channel region in the length direction are recessed inward with respect to sidewalls of a corresponding first dielectric portion, so as to form recesses; the source regions and the drain regions cover inner walls of the recesses. The manufacturing method for a three-dimensional dynamic random access memory is used for manufacturing the described three-dimensional dynamic random access memory.

Description

A three-dimensional dynamic random access memory and its manufacturing method

[0001] This application claims priority to Chinese Patent Application No. 202411482419.5, filed on October 22, 2024, entitled “A Three-Dimensional Dynamic Random Access Memory and a Method for Manufacturing the Same”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of memory technology, and in particular to a three-dimensional dynamic random access memory and its manufacturing method. Background Technology

[0003] In computer systems, memory is a crucial component for storing data and programs. Dynamic Random Access Memory (DRAM), as an important type of memory, plays a key role in modern computer architecture. DRAM includes a 1T1C memory cell structure. A memory cell in this type of DRAM consists of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor stores charge, and the transistor controls access to the capacitor. This type of DRAM also includes word lines connected to the gate of the transistor and bit lines connected to the source or drain of the transistor. When data is accessed in a memory cell, the word line connected to that memory cell is selected, and a voltage is input to that word line to turn on the transistor. The transistor turns on, and then the bit line connected to that memory cell is selected, allowing access to the charge in the capacitor. However, because the capacitor gradually leaks current, causing the stored charge to decrease, DRAM needs to be refreshed periodically (usually every few milliseconds) to maintain data validity. The refresh operation reads the data in each storage cell and rewrites it, thereby replenishing the charge lost from the capacitor.

[0004] In existing technologies, the memory cells of dynamic random access memory (DRAM) are arrayed along the horizontal direction of the wafer, which is called two-dimensional DRAM. However, the development of computer systems has placed higher demands on the density of DRAM, and the density of two-dimensional DRAM is limited by the manufacturing process and cannot meet the density requirements. Summary of the Invention

[0005] The purpose of this application is to provide a three-dimensional dynamic random access memory and a method for manufacturing the same, which can improve the storage density of the dynamic random access memory, increase the contact area between the source and drain regions of the transistor and the contact structure or capacitor, reduce the contact resistance, and improve leakage current.

[0006] To achieve the above objectives, in a first aspect, this application provides a three-dimensional dynamic random access memory (DRAM), comprising: a plurality of memory cells arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells. The plurality of memory cells arranged in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells arranged along a third direction. The first direction, the second direction, and the third direction are mutually different. Each memory cell includes: a transistor and a capacitor. The dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction. The transistor includes: a gate, a gate dielectric layer, a channel region, a source region, and a drain region. The length direction of the channel region is parallel to the second direction, and the two sidewalls of the channel region along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch. The source region and the drain region are respectively disposed on both sides along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region, and the drain region, respectively. The capacitor is electrically connected to the source or drain region of the transistor.

[0007] With the above technical solution, the three-dimensional dynamic random access memory (DRAM) provided in this application not only has multiple memory groups spaced apart along the second direction in the same layer, but also includes multiple memory layers spaced apart along the first direction, in which case the multiple memory cells are arranged in a three-dimensional array. Compared with a two-dimensional DRAM with only a single memory layer, each memory layer in this application can form a structure analogous to the existing two-dimensional DRAM. Furthermore, the multiple memory layers stacked along the first direction in this application can multiply the storage density of the three-dimensional DRAM provided in this application, effectively solving the problem of low density in two-dimensional DRAMs.

[0008] Furthermore, in the storage cell of the three-dimensional dynamic random access memory provided in this application, the two side walls of the channel region of the transistor along the length direction are recessed inward relative to the side wall of the corresponding first dielectric portion, forming a notch. The source region and drain region are respectively disposed on both sides along the length direction and cover the inner wall of the notch. In other words, the source region and drain region of the transistor are not only disposed on the inner wall of the notch along the length direction of the channel region, but also cover the inner wall of the notch along the first direction. With this configuration, compared with the prior art where the source region and drain region of the transistor only extend in size relative to the length direction of the channel region, the source region and drain region of the transistor provided in this application can also have an additional portion covering the inner wall of the notch along the first direction, that is, have a larger geometric size in the second direction, have a larger area of ​​source region and drain region, thereby increasing the contact area between the source region and drain region and the contact structure or capacitor respectively, which is beneficial to reduce the contact resistance between the source region and drain region and the contact structure or capacitor respectively, improve the speed of transistor, improve the storage performance of each storage cell, and improve leakage current.

[0009] In one possible implementation, the ratio of the height of the notch to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The height of the notch is parallel to a first direction, and the width of the notch is parallel to a second direction.

[0010] When the height and width of the notch are within the aforementioned range, the notch has a large surface area. Since the source and drain regions are respectively covered on the inner wall of the notch, compared to the prior art, the source and drain regions in this application have additional surface area in the height direction of the notch, i.e., the first direction. This increases the contact area between the source and drain regions and the contact structure or capacitor, which helps to reduce the contact resistance between the source and drain regions and the contact structure or capacitor, improves transistor speed, and reduces leakage current. Furthermore, it prevents the notch size from becoming too large, ensuring that during the manufacturing of the three-dimensional dynamic random access memory provided in this application, the lateral etching width (i.e., the width of the notch) of the first dielectric layer and the gate layer disposed on the first dielectric layer is not too large when forming the notch, reducing the difficulty of lateral etching and thus improving the yield of the manufactured three-dimensional dynamic random access memory.

[0011] In one possible implementation, the ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000. The thickness direction of the channel region is parallel to the first direction.

[0012] In the prior art, the source and drain regions extend only along the second direction from the sidewall of the channel region when the ratio of the channel region's length to width is within the aforementioned range. If the source and drain regions extend only along the second direction, their sizes are relatively small. However, simply increasing the length of the source and drain regions along the second direction can easily lead to their collapse. Therefore, in this application, the source and drain regions not only cover the inner wall of the notch along the second direction but also along the first direction. This not only increases the area of ​​the source and drain regions but also prevents the risk of collapse, further improving the yield of the three-dimensional dynamic random access memory.

[0013] In one possible implementation, the ratio of the thickness of the channel region to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The width of the notch is parallel to the second direction.

[0014] When the above technical solution is adopted, the transistor provided in this application still has the source region area and drain region area disposed at both ends of the channel region length direction in the prior art. In conjunction with the foregoing, the transistor provided in this application also includes the source region area and drain region area along the first direction. The source region area and drain region area of ​​the transistor provided in this application are larger than the source region area and drain region area of ​​the transistor in the prior art. The beneficial effects are described above and will not be repeated here.

[0015] As one possible implementation, the material of the channel region includes indium gallium zinc oxide.

[0016] With the above technical solution, indium gallium zinc oxide (IGZO) has a relatively high carrier mobility, which enables the transistors provided in this application to have faster signal transmission and switching speeds, thereby improving the operating efficiency and response speed of the three-dimensional dynamic random access memory (DRAM) provided in this application. Furthermore, transistors with IGZO as the channel material have very low current in the off-state, which helps reduce the power consumption of the three-dimensional DRAM provided in this application and improves the battery life of electronic devices using the three-dimensional DRAM provided in this application. It also reduces the need for a heat dissipation system, thereby improving the reliability and stability of electronic devices using the three-dimensional DRAM provided in this application. Simultaneously, when manufacturing the three-dimensional DRAM provided in this application, the IGZO channel region can be fabricated using a cryogenic process. Cryogenic processes reduce the need for expensive high-temperature equipment and complex process steps, thus reducing costs; they also reduce the risk of thermal damage to the three-dimensional memory, thereby improving chip yield. In addition, although the channel region has lower structural strength when the channel region material is IGZO, the channel region manufactured in this application is not suspended during the manufacturing process and will not collapse due to its lower structural strength.

[0017] As one possible implementation, the source region, drain region, and channel region are integrated and continuous.

[0018] When using the above technical solution, the source region, drain region, and channel region can be formed in the same process step when manufacturing the three-dimensional dynamic random access memory provided in this application, which can reduce process steps, reduce manufacturing costs, and increase yield.

[0019] In one possible implementation, the gate includes a first gate and a second gate disposed on both sides of the channel region along a first direction.

[0020] With the above technical solution, the transistor provided in this application is a dual-gate transistor. Traditional transistors have only one gate to control the current in the channel region, while the transistor provided in this application has two gates. The dual-gate transistor can have twice the gate control area with the same channel region area, effectively improving the gate's control capability over the channel region. This makes the gate's control over the carriers in the channel region more precise and flexible, allowing for more effective regulation of current conduction and cutoff, thereby improving the switching performance of the transistor provided in this application. It can effectively suppress short-channel effects and is conducive to further reducing the size of the transistor provided in this application, thus increasing the storage density of the three-dimensional dynamic random access memory provided in this application. For example, under low-voltage operation, the dual-gate transistor can more precisely control the current, achieving faster switching transitions, which is beneficial for reducing the power consumption of the three-dimensional dynamic random access memory provided in this application.

[0021] As one possible implementation, the three-dimensional dynamic random access memory further includes contact structures. Specifically, when the source region of a transistor is electrically connected to a capacitor, the drain region is electrically connected to the contact structure; or, when the drain region of a transistor is electrically connected to a capacitor, the source region is electrically connected to the contact structure. The dielectric structure also includes a second dielectric portion and a third dielectric portion. The second dielectric portion is located between two capacitors spaced apart along a third direction and between two contact structures spaced apart along a third direction. The third dielectric portion is located between two transistors spaced apart along a third direction.

[0022] When the above technical solution is adopted, the second medium section and the third medium section electrically isolate the multiple memory cells that are spaced apart along the second direction, so that the multiple memory cells that are spaced apart along the second direction can be accessed individually.

[0023] In one possible implementation, the capacitor includes a first electrode, a dielectric layer, and a second electrode. The dielectric layer is located between the first and second electrodes. Each first electrode fills a corresponding recess. The dielectric layer and the second electrode are disposed between two adjacent transistors spaced apart along a second direction. The dielectric layers of the different capacitors spaced apart along the first direction are integrally continuous, and the second electrodes of the different capacitors spaced apart along the first direction are integrally continuous.

[0024] With the above technical solution, the first electrode can also be reused as the source or drain electrode of the transistor provided in this application, and also as a plate of the capacitor included in the memory cell provided in this application, connecting the transistor and the capacitor to form a memory cell of a dynamic random access memory (DRAM) consisting of a transistor and a capacitor (1T1C). Furthermore, the integral and continuous second electrode and dielectric layer allow for the simultaneous formation of dielectric layers with different capacitors and second electrodes with different capacitors during the fabrication of the three-dimensional DRAM provided in this application. This reduces the process steps required to separately form dielectric layers and second electrodes with different capacitors, thereby reducing costs and increasing yield.

[0025] Secondly, this application also provides a method for manufacturing a three-dimensional dynamic random access memory (DRAM). The method includes: forming a plurality of memory cells arranged in a three-dimensional array; the plurality of memory cells arranged in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, each memory group including a plurality of memory cells arranged along a third direction; the first direction, the second direction, and the third direction are different from each other; each memory cell includes a transistor and a capacitor; forming a dielectric structure for isolating different memory cells; the dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction; the transistor includes a gate, a gate dielectric layer, a channel region, a source region, and a drain region; the length direction of the channel region is parallel to the second direction, and the two sidewalls of the channel region along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively disposed on both sides along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region, and the drain region respectively.

[0026] Compared with the prior art, the beneficial effects of the manufacturing method of the three-dimensional dynamic random access memory provided in this application are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above-mentioned technical solutions, and will not be repeated here.

[0027] In one possible implementation, forming a plurality of memory cells arranged in a three-dimensional array and forming a dielectric structure for isolating different memory cells includes: forming a stacked structure and a second dielectric portion through the stacked structure; the stacked structure includes multiple stacked cells stacked along a first direction; each stacked cell includes a first dielectric layer and a stack layer located on the first dielectric layer; the stack layer includes a stacked second dielectric layer and a gate; the material of the first dielectric layer is different from the material of the second dielectric layer; a first via group and a second via group spaced apart along a second direction are formed in the stacked structure; both the first via group and the second via group include a plurality of vias spaced apart along a third direction; the second dielectric portion is disposed between two adjacent vias in the same first via group along the first direction and between two adjacent vias in the same second via group along the first direction; the first dielectric portion includes the first dielectric layer. Next, the edge portion of each gate layer is selectively removed to form a notch. Next, the second dielectric layer is selectively etched to form a third dielectric portion; the third dielectric portion is located between two transistors spaced apart along a third direction; the dielectric structure includes the first dielectric portion, the second dielectric portion, and the third dielectric portion. Next, a gate dielectric layer is deposited to cover the outer periphery of the gate; and a channel region, a source region, and a drain region are deposited on the gate dielectric layer. Next, a contact structure is formed in each via of the first via group, and a first electrode for the capacitor is formed in the portion corresponding to the notch of each via of the second via group. Next, a dielectric layer and a second electrode are sequentially formed in each via of the second via group; the capacitor includes a first electrode, a dielectric layer, and a second electrode.

[0028] In the above technical solution, the first dielectric portion includes the entire first dielectric layer, and the second dielectric portion, which is completely removed, serves as a pre-occupying structure for the channel region. After removal, a gate dielectric layer covering the outer periphery of the gate is sequentially deposited, and the channel region, source region, and drain region are deposited on the gate dielectric layer. In the prior art, during transistor manufacturing, the sacrificial layer stacked on both sides of the channel region is first removed, and then the gate dielectric layer and gate are formed on both sides of the channel region along the first and second directions. At this time, the channel region is suspended, and the channel region is a semiconductor material with low structural strength. When the memory cell has a small geometric size, the channel region of the semiconductor material with a large aspect ratio along the second direction will collapse, causing transistor deformation, thereby reducing the performance of the memory cell or even preventing it from working properly, and reducing the yield. Based on this, in the manufacturing of three-dimensional dynamic random access memory, this application selectively etches the second dielectric layer so that the remaining second dielectric layer forms the third dielectric portion, and the gate is suspended. Compared with the channel region material, the gate material has higher structural strength and is less prone to collapse due to the large aspect ratio along the second direction when the memory cell has a small geometric size. The manufacturing method of the three-dimensional dynamic random access memory provided in this application can ensure the regularity of the transistor structure, thereby ensuring the normal operation and stable performance of the memory cell manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided in this application, thus improving the yield.

[0029] In one possible implementation, forming a stacked structure and a second dielectric portion penetrating the stacked structure includes: forming a stacked material layer; next, forming a third via group and a fourth via group penetrating the stacked material layer; the aperture pattern of the third via group is the same as the top pattern of the second dielectric layer; next, forming a second dielectric portion filling the third via group and the fourth via group.

[0030] When adopting the above technical solution, compared with the prior art, the beneficial effects of the manufacturing method of the three-dimensional dynamic random access memory provided in this application are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above technical solution, and will not be elaborated here.

[0031] As one possible implementation, the first via group includes a via diameter of 30 nm or greater and 3000 nm or less.

[0032] By adopting the above technical solution, the excessively high requirements for etching and photolithography processes due to excessively small apertures can be avoided, thus reducing costs. It also avoids the difficulty in uniformly forming contact structures on the aperture walls or the inability to form contact structures at all due to excessively small apertures. Furthermore, it avoids the excessive area occupied by excessively large apertures, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured in this application.

[0033] As one possible implementation, the second via group includes a via diameter of 50 nm or greater and 5000 nm or less.

[0034] By adopting the above technical solution, the excessively high requirements for etching and photolithography processes due to excessively small apertures can be avoided, thus reducing costs. It also avoids the reduction in capacitor retention time caused by small apertures, which would lead to higher refresh rates and increased power consumption, thereby reducing the power consumption of the three-dimensional dynamic random access memory (DRAM) manufactured in this application. Furthermore, it avoids the excessive area occupied by large apertures, thus reducing the storage density of the DRAM manufactured in this application. Furthermore, in manufacturing the first electrode and contact structure, a material layer for the first electrode and contact structure is formed by depositing material on the surface of the three-dimensional dynamic random access memory manufactured in this application, and then etching the material layer to form the first electrode and contact structure. Since the aperture of each via in the first via group is smaller than the aperture of each via in the second via group, the material layer fills each via in the first via group, but is only formed on the inner wall of each via in the second via group. During subsequent etching, only the material layer on the top of each via in the first via group and the material layer on the inner wall of each via in the second via group will be removed. In this process, the first electrode and contact structure can be formed without the use of a mask, which reduces the number of process steps, lowers the cost, and increases the yield. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0036] Figure 1 is a schematic diagram of a three-dimensional dynamic random access memory provided in an embodiment of this application;

[0037] Figure 2 is a schematic diagram of the formation of stacked material layers in an embodiment of this application;

[0038] Figure 3 is a schematic diagram of the formation of the third through-hole group and the fourth through-hole group in an embodiment of this application;

[0039] Figure 4 is a schematic diagram of the formation of the second medium section in an embodiment of this application;

[0040] Figure 5 is a schematic diagram of the formation of the first through hole group and the second through hole group in an embodiment of this application;

[0041] Figure 6 is a schematic diagram of the notch formed in an embodiment of this application;

[0042] Figure 7 is a schematic diagram of removing the second dielectric layer in an embodiment of this application;

[0043] Figure 8 is a schematic diagram of the formation of the gate dielectric layer in an embodiment of this application;

[0044] Figure 9 is a cross-sectional view of the trench layer formed along the first and second directions in an embodiment of this application;

[0045] Figure 10 is a cross-sectional view of the electrode layer formed along the first and second directions in an embodiment of this application;

[0046] Figure 11 is a cross-sectional view along the first direction and the second direction of forming the first electrode and the contact structure in an embodiment of this application;

[0047] Figure 12 is a schematic diagram of the formation of the dielectric layer and the formation of the second electrode in an embodiment of this application.

[0048] Reference numerals: 100-memory cell, 101-channel region, 102-source region, 103-drain region, 104-notch, 105-channel layer, 110-gate, 111-first gate, 112-second gate, 120-gate dielectric layer, 130-contact structure, 140-transistor; 200-capacitor, 201-first electrode, 202-dielectric layer, 203-second electrode, 204-electrode layer; 310-first dielectric portion, 311-first dielectric layer, 320-second dielectric portion, 331-second dielectric layer, 332-third dielectric portion; 410-first via group, 420-second via group, 430-third via group, 440-fourth via group. Detailed Implementation

[0049] To make the technical problems, technical solutions, and beneficial effects to be solved by the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0052] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0053] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0054] In computer systems, memory is a crucial component for storing data and programs. Dynamic Random Access Memory (DRAM), as an important type of memory, plays a key role in modern computer architecture. Common DRAM typically includes a 1T1C memory cell structure. A memory cell in this type of DRAM consists of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor stores charge, and the transistor controls access to the capacitor. This type of DRAM also includes word lines connected to the gate of the transistor, and bit lines connected to the source or drain regions of the transistor where no capacitor is connected. When data is accessed in a memory cell, the word line connected to that cell is selected, and a voltage is applied to that word line to turn on the transistor. The transistor conducts, and then the bit line connected to that memory cell is selected, allowing access to the charge in the capacitor. However, because the capacitor gradually leaks current, causing the stored charge to decrease, DRAM needs to be refreshed periodically (typically every few milliseconds) to maintain data validity. The refresh operation reads the data in each storage cell and rewrites it, thereby replenishing the charge lost from the capacitor.

[0055] In existing technologies, the memory cells of dynamic random access memory (DRAM) are arrayed along the horizontal direction of the wafer, i.e., two-dimensional DRAM. In two-dimensional DRAM, transistors are arrayed on the wafer, and capacitors can be distributed in the same plane as the transistors, or placed above or below the transistors to increase storage density. However, the development of computer systems has placed higher demands on the density of DRAM, and the density of the aforementioned two-dimensional DRAMs is limited by manufacturing processes; transistors and capacitors cannot be infinitely shrunk to meet the density requirements.

[0056] To address the aforementioned problems, in a first aspect, embodiments of this application provide a three-dimensional dynamic random access memory (DRAM). Referring to FIG1, the three-dimensional DRAM includes: a plurality of memory cells 100 arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells 100; the plurality of memory cells 100 arranged in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells 100 arranged along a third direction; the first direction, the second direction, and the third direction are mutually different. Each memory cell 100 includes: a transistor 140 and a capacitor 200; the dielectric structure includes a first dielectric portion 310 located between two transistors 140 spaced apart along the first direction. Transistor 140 includes: a gate 110, a gate dielectric layer 120, a channel region 101, a source region 102, and a drain region 103; the channel region 101 is parallel to a second direction in its length direction, and the two side walls of the channel region 101 along its length direction are recessed inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104; the source region 102 and the drain region 103 are respectively disposed on both sides along the length direction and cover the inner wall of the notch 104; the gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102, and the drain region 103 respectively. Capacitor 200 is electrically connected to the source region 102 or the drain region 103 of transistor 140.

[0057] With the above technical solution, referring to Figure 1, multiple storage cells 100 are distributed along a third direction to form a storage group, multiple storage groups are spaced apart along a second direction to form a storage layer, and multiple storage layers are spaced apart along a first direction to form multiple storage cells 100 in a three-dimensional array, constituting the three-dimensional dynamic random access memory provided in this application embodiment. Compared with the prior art, the storage layer in this application embodiment forms a structure comparable to the two-dimensional dynamic random access memory of the prior art, but the multiple storage layers are stacked in the first direction, which multiplies the storage density of the three-dimensional dynamic random access memory provided in this application embodiment, effectively solving the problem of low density in two-dimensional dynamic random access memory.

[0058] Furthermore, referring to FIG1, in the storage cell 100 of the three-dimensional dynamic random access memory provided in this embodiment, the channel region 101 of the transistor 140 has its two side walls along the length direction recessed relative to the side wall of the corresponding first dielectric portion 310, forming a notch 104; the source region 102 and the drain region 103 are respectively disposed on both sides along the length direction and cover the inner wall of the notch 104. In other words, the source region 102 and the drain region 103 of the transistor 140 are not only disposed on the inner wall of the notch 104 along the length direction of the channel region 101, but also cover the inner wall of the notch 104 along the first direction. With this configuration, compared to the prior art where the source region 102 and drain region 103 of transistor 140 only extend in the length direction relative to the channel region 101, the source region 102 and drain region 103 of transistor 140 provided in this application embodiment can additionally have portions covering the inner wall of the notch 104 along the first direction, that is, have larger geometric dimensions in the second direction, and have larger areas of source region 102 and drain region 103, thereby increasing the contact area between source region 102 and drain region 103 and contact structure 130 or capacitor 200 respectively. This is beneficial to reduce the contact resistance between source region 102 and drain region 103 and contact structure 130 or capacitor 200 respectively, improve the speed of transistor 140, and improve leakage current.

[0059] In practical applications, this application does not specifically limit the specific arrangement direction or distribution of different storage units 100, as long as the different storage units 100 are distributed in a three-dimensional array. As for the specific directions referred to by the first direction, the second direction, and the third direction, no specific limitation is made here, as long as any two of the above three directions are different.

[0060] For example, the first direction is the height direction of the three-dimensional dynamic random access memory provided in the embodiments of this application. Secondly, the second direction and the third direction can be determined according to the distribution of different storage cells 100 in the same storage layer.

[0061] For example, please refer to Figure 1. When different memory cells 100 in the same memory layer are distributed in a rectangular array, the second direction and the third direction can be the length and width directions of the rectangular array, respectively.

[0062] For example, when different memory cells 100 in the same memory layer are distributed in a parallelogram array, the second direction and the third direction can be the directions of two adjacent sides of the parallelogram array, respectively.

[0063] For example, when different memory cells 100 in the same memory layer are distributed in a concentric circle array, the second direction and the third direction can be the radial and circumferential directions of the concentric circle array, respectively.

[0064] It is understandable that when the distribution of storage cells in the same storage layer is different, the second and third directions can be changed according to their distribution.

[0065] In practical applications, this application does not impose specific limitations on the specific shape and distribution of the media structure, as long as different storage units 100 can be isolated.

[0066] Specifically, referring to Figure 1, the dielectric structure includes a first dielectric portion 310 located between two transistors 140 spaced apart along a first direction. The first dielectric portion 310 protrudes from the channel region 101 in a second direction to form a notch 104.

[0067] In practical applications, the materials of the first dielectric portion 310 are not specifically limited in this embodiment, as long as they can isolate and insulate the gates 110 of two adjacent transistors 140 along the first direction. For example, the first dielectric portion 310 can be made of silicon oxide or silicon nitride. The first dielectric layer 311 can also be a combination of multiple materials, as long as it is feasible in the manufacturing process.

[0068] Regarding the distance between two adjacent first dielectric layers 310, it is understood that it is determined by the size of the transistor located between the two adjacent first dielectric layers 310 along the first direction. For example, the distance between two adjacent first dielectric layers 310 can be 5nm to 500nm.

[0069] Regarding the thickness of the first dielectric portion 310, this embodiment does not impose specific limitations on it, as long as it can isolate and insulate the gates 110 included in two adjacent transistors 140 along the first direction. For example, the thickness of the first dielectric portion 310 can be 10nm to 1000nm.

[0070] Regarding the shape of the notch 104, please refer to Figure 1. The bottom of the notch 104 is composed of the gate 110 and the sidewall of the channel region 101 along the first direction. The sidewall of the notch 104 is composed of the opposing surfaces of the protruding portions of the first dielectric portion 310 located on both sides of the transistor 140 in the first direction, and in the third direction, it is composed of a structure that separates the two memory cells 100 along the third direction.

[0071] It is understood that the three-dimensional dynamic random access memory provided in this application embodiment further includes a plurality of contact structures 130 that can serve as data lines or bit lines, and a second medium portion 320 that isolates the contact structures 130 distributed along a third direction. Each contact structure 130 is connected along a first direction to the source region 102 or drain region 103 of the transistors 140 included in the plurality of memory cells 100, and connects the source region 102 or drain region 103 of the transistors 140 included in two adjacent memory cells 100 along a second direction. The second medium portion 320 extends through the three-dimensional dynamic random access memory provided in this application embodiment to completely isolate two adjacent contact structures 130 along a third direction.

[0072] In practical applications, the material of the contact structure 130 is not specifically limited in this application embodiment, and can be determined according to the performance and manufacturing process requirements of the three-dimensional dynamic random access memory provided in this application embodiment. For example, the material of the contact structure 130 can be at least one of copper, aluminum, chromium, and tungsten.

[0073] In practical applications, the material of the second dielectric part 320 is not specifically limited in this application embodiment. It is only necessary to meet the requirement that the second dielectric part 320 provides structural insulation in the two adjacent through holes of the first through hole group 410 on both sides of the second dielectric part 320 in the third direction, and to provide structural insulation in the two adjacent through holes of the second through hole group 420 on both sides of the second dielectric part 320 in the third direction.

[0074] It should be noted that the materials of the first dielectric part 310 and the second dielectric part 320 may be the same or different, depending on the manufacturing process.

[0075] As can be understood, referring to FIG1, along the third direction, the dielectric structure includes a third dielectric portion 332, which is located between two transistors 140 spaced apart along the third direction. The third dielectric portion 332 electrically isolates at least the channel regions 101 of the two transistors 140 spaced apart along the third direction, so as to facilitate individual access to two adjacent memory cells 100 including two adjacent transistors 140 spaced apart along the third direction. The gates 110 of the two transistors 140 spaced apart along the third direction are interconnected, forming the word lines of the three-dimensional dynamic random access memory provided in this application embodiment. Furthermore, along the third direction, the region of the gate 110 between the two spaced transistors 140 does not have a recess in the first dielectric portion 310, and together with the sidewall of the third dielectric portion 332, it forms the sidewall of the notch 104 along the third direction. The gate dielectric layer 120 is also disposed on the sidewall of the notch 104 along the third direction, thereby further increasing the contact area between the source region 102 and the drain region 103 and the capacitor 200 or the contact structure 130.

[0076] Regarding the material of the third dielectric portion 332, it is different from the material of the first dielectric portion 310 and the second dielectric portion 320. Please refer to the following content to facilitate selective etching of the third dielectric portion 332. For example, if the first dielectric portion 310 and the second dielectric portion 320 are made of the same material and are both silicon oxide, the third dielectric portion 332 can be silicon nitride.

[0077] Please refer to Figure 1. Each storage cell 100 of the three-dimensional dynamic random access memory provided in this embodiment includes a transistor 140 and a capacitor 200 to form a 1T1C dynamic random access memory structure.

[0078] In practical applications, the connection relationship between the transistor 140 and the capacitor 200 included in the storage cell 100 is not specifically limited in this embodiment. It can be determined according to the conductivity type of the transistor 140 and actual needs. For example, when the source region 102 of the transistor 140 is electrically connected to the capacitor 200, the drain region 103 is electrically connected to the contact structure 130; or, referring to FIG1, when the drain region 103 of the transistor 140 is electrically connected to the capacitor 200, the source region 102 is electrically connected to the contact structure 130.

[0079] It should be noted that the accompanying drawings provided in this application only illustrate the case where the drain region 103 is electrically connected to the capacitor 200 and the source region 102 is electrically connected to the contact structure 130, but do not represent that the connection relationship can only be as described above. For the specific connection relationships between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200, respectively, please refer to the preceding text. When the drain region 103 is electrically connected to the capacitor, the source region 102 is electrically connected to the contact structure 130.

[0080] Understandably, in the third-party direction, the second medium section 320 also isolates the capacitors 200 included in the multiple storage cells 100 to achieve isolation of the data stored in the multiple storage cells 100.

[0081] Please refer to Figure 1. Transistor 140 includes: gate 110, gate dielectric layer 120, channel region 101, source region 102 and drain region 103.

[0082] Structurally, the channel region 101 is parallel to the second direction in its length direction, and the two side walls of the channel region 101 along its length direction are recessed inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104. The source region 102 and the drain region 103 are respectively disposed on both sides along the length direction and cover the inner wall of the notch 104. The gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102, and the drain region 103. Since the channel region 101, the source region 102, and the drain region 103 are formed after the gate 110, they will not be suspended during the manufacturing of the three-dimensional dynamic random access memory provided in this application embodiment. This helps to prevent collapse due to the low structural strength of the channel region 101, the source region 102, and the drain region 103, thereby ensuring the regularity of the transistor 140 structure and ensuring the normal operation and stable performance of the memory cell 100 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided in this application, thereby improving the yield.

[0083] In practical applications, the embodiments of this application do not specifically limit the gate 110 structure of transistor 140, but can determine it according to the performance requirements of the three-dimensional dynamic random access memory in the embodiments of this application. The gate 110 structure of transistor 140 can be a conventional single-gate transistor or a dual-gate transistor, or other possible gate 110 structures.

[0084] For example, transistor 140 is a conventional single-gate transistor. Along the first direction, gate 110 is disposed on the first dielectric portion 310, gate dielectric layer 120 is disposed on gate 110, and channel region 101, source region 102 and drain region 103 are disposed on both gate 110 and the first dielectric portion 310.

[0085] For example, transistor 140 is a dual-gate transistor. Referring to FIG1, in the first direction, the gate 110 includes a first gate 111 and a second gate 112 respectively disposed on two adjacent first dielectric portions 310, and the edges of the first gate 111 and the second gate 112 are recessed into the space between the first dielectric portions 310 along the second direction, forming a notch 104. That is, the projection of the first gate 111 and the second gate 112 in the second direction is smaller than the projection of the first dielectric portion 310 in the second direction. Between the two adjacent first dielectric portions 310, a gate dielectric layer 120 covering the outer periphery of the gate 110 is disposed on the first gate 111, the second gate 112, and the inner wall of the notch 104. A channel region 101, a source region 102, and a drain region 103 covering the outer periphery of the gate dielectric layer 120 are disposed on the gate dielectric layer 120. The gate 110, the gate dielectric layer 120, the channel region 101, the source region 102, and the drain region 103 constitute transistor 140. The transistor 140 provided in this embodiment has two gates 110. A dual-gate transistor can have a larger gate control area within the same channel region 101 area, effectively improving the control capability of the gate 110 over the channel region 101. This allows for more precise and flexible control of carriers within the channel region 101 by the gate 110, enabling more effective regulation of current conduction and cutoff, thereby improving the switching performance of the transistor 140 provided in this embodiment. For example, under low-voltage operation, the dual-gate transistor can more accurately control the current, achieving faster switching transitions, which helps reduce the power consumption of the three-dimensional dynamic random access memory provided in this embodiment. Furthermore, the dual-gate transistor 140 provided in this embodiment can effectively suppress short-channel effects, which helps to further reduce the size of the transistor 140 provided in this embodiment, thereby increasing the storage density of the three-dimensional dynamic random access memory provided in this embodiment.

[0086] Regarding the connection relationship between the source region 102, the drain region 103, and the channel region 101, they can be manufactured simultaneously and continuously as a single unit; or the source region 102, the drain region 103, and the channel region 101 can be formed separately, with the source region 102 and the channel region 101 connected at the bottom of a notch 104 included in the transistor 140, and the drain region 103 and the channel region 101 connected at the bottom of another notch 104.

[0087] Optionally, the source region 102, drain region 103, and channel region 101 are integrally continuous. In this case, when manufacturing the three-dimensional dynamic random access memory provided in the embodiments of this application, the source region 102, drain region 103, and channel region 101 can be formed in the same process step, which can reduce process steps, reduce manufacturing costs, and increase yield.

[0088] In practical applications, this application does not specifically limit the material of the channel region 101, as long as the material's performance can meet the speed requirements of the three-dimensional dynamic random access memory provided in this application. The material of the channel region 101 can be common silicon, or it can be a material with high electron mobility such as germanium, silicon germanium, or indium gallium zinc oxide to reduce the resistivity of the channel region 101 and improve the speed of the transistor 140.

[0089] Optionally, the channel region 101 is made of indium gallium zinc oxide (IGZO). In this case, IGZO has a relatively high carrier mobility, meaning that electrons move faster in the material. This allows the transistor 140 provided in this embodiment to have faster signal transmission and switching speeds, thereby improving the operating efficiency and response speed of the three-dimensional dynamic random access memory (DRAM) provided in this embodiment. Furthermore, the transistor 140 with IGZO as the channel region material has very low current in the off state, which helps reduce the power consumption of the three-dimensional DRAM provided in this embodiment and improves the battery life of electronic devices using the three-dimensional DRAM provided in this embodiment. It also reduces the need for a heat dissipation system, thereby improving the reliability and stability of electronic devices using the three-dimensional DRAM provided in this embodiment. Simultaneously, when manufacturing the three-dimensional DRAM provided in this embodiment, the IGZO channel region 101 can be fabricated using a cryogenic process. Cryogenic processes reduce the need for expensive high-temperature equipment and complex process steps, thus reducing costs; they also reduce the risk of thermal damage to the three-dimensional memory, thereby improving chip yield.

[0090] In practical applications, the materials of the source region 102 and the drain region 103 can be different from or the same as those of the channel region 101. This application embodiment does not impose specific limitations, as long as the design and process requirements of the three-dimensional dynamic random access memory provided in this application embodiment are met. When the materials of the source region 102 and the drain region 103 are the same as those of the channel region 101, it is beneficial to form an integral and continuous source region 102, drain region 103, and channel region 101. Alternatively, the source region 102, drain region 103, and channel region 101 can be formed separately. When the materials of the source region 102 and the drain region 103 are different from those of the channel region 101, it is beneficial to form the source region 102, drain region 103, and channel region 101 separately.

[0091] In practical applications, this application does not specifically limit the material of the gate dielectric layer 120, as long as it can be applied to the three-dimensional dynamic random access memory provided in this application. For example, a high dielectric constant material, including hafnium dioxide, can be used to reduce the thickness of the gate dielectric layer 120, thereby reducing the floating height when manufacturing the transistor 140 provided in this application, effectively avoiding structural damage caused by floating, and thus improving yield; the thickness of the transistor 140 can also be reduced to increase the storage density.

[0092] In practical applications, this application does not impose specific limitations on the material of the gate 110, as long as the parameters of the gate 110 material meet the design and process requirements of the three-dimensional dynamic random access memory provided in this application. For example, the material of the gate 110 can be copper, aluminum, or tungsten. Optionally, the material of the gate 110 is tungsten because tungsten is stable, does not easily diffuse into other structures, and is not easily affected by the high-temperature process steps during the manufacture of the three-dimensional dynamic random access memory provided in this application, thus ensuring the performance of the three-dimensional dynamic random access memory provided in this application.

[0093] Furthermore, referring to Figure 1, regarding the notch 104, since the source region 102 and the drain region 103 are disposed on the inner wall of the notch 104, the surface area of ​​the inner wall of the notch 104 is also the contact area between the source region 102 and the drain region 103 and the contact structure or capacitor, respectively. Therefore, in order to reduce the contact resistance between the source region 102 and the drain region 103 and the contact structure or capacitor, the shape of the notch is limited as follows in this embodiment:

[0094] Specifically, referring to Figure 1, the ratio of the height to the width of the notch 104 is greater than or equal to 0.1 and less than or equal to 10. The height of the notch 104 is parallel to the first direction, and the width of the notch 104 is parallel to the second direction. In this case, when the height and width of the notch 104 are within the above range, the notch 104 has a larger surface area. Since the source region 102 and the drain region 103 are respectively covered on the inner wall of the notch 104, compared with the prior art, the source region 102 and the drain region 103 in this application have additional surface area in the height direction of the notch 104, that is, the first direction. This increases the contact area between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, which helps to reduce the contact resistance between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, improve the speed of the transistor 140, and improve the leakage current. Furthermore, it also prevents the size of the notch 104 from being too large, ensuring that during the manufacturing process of the three-dimensional dynamic random access memory provided in this application embodiment, when the notch 104 is formed, the lateral etching width of the first dielectric portion 310 and the gate 110 layer disposed on the first dielectric portion 310 (i.e., the width of the notch 104) is not too large, reducing the difficulty of lateral etching and thereby improving the yield of the manufactured three-dimensional dynamic random access memory.

[0095] Furthermore, referring to Figure 1, the ratio of the length to the thickness of the channel region 101 is greater than or equal to 10 and less than or equal to 1000. The thickness direction of the channel region 101 is parallel to the first direction. In this case, the source region 102 and the drain region 103 in the prior art extend from the sidewall of the channel region 101 along the second direction. When the ratio of the length to the width of the channel region 101 is within the above range, if the source region 102 and the drain region 103 only extend along the second direction, the size of the source region 102 and the drain region 103 is relatively small. However, if the size of the source region 102 and the drain region 103 is increased by simply increasing the extension length of the source region 102 and the drain region 103 along the second direction, it is very easy for the source region 102 and the drain region 103 to collapse. Based on this, in the embodiments of this application, the source region 102 and the drain region 103 can not only cover the inner wall of the notch 104 along the second direction, but also cover the inner wall of the notch 104 along the first direction. This not only increases the area of ​​the source region 102 and the drain region 103, but also prevents the source region 102 and the drain region 103 from collapsing, thereby further improving the yield of the three-dimensional dynamic random access memory.

[0096] Furthermore, the ratio of the thickness of the channel region 101 to the width of the notch 104 is greater than or equal to 0.1 and less than or equal to 10. The width of the notch 104 is parallel to the second direction. In this case, the transistor 140 provided in this embodiment still has the source region 102 area and drain region 103 area disposed at both ends of the channel region 101 in the length direction in the prior art. In conjunction with the foregoing, the transistor 140 provided in this embodiment also includes the source region 102 area and drain region 103 area along the first direction. The source region 102 area and drain region 103 area of ​​the transistor 140 provided in this embodiment are larger than the source region 102 area and drain region 103 area of ​​the transistor 140 in the prior art. The beneficial effects are described above and will not be repeated here.

[0097] Furthermore, each transistor 140 includes two notches 104 distributed along the second direction, with an active region 102 and a drain region 103 formed in the two notches 104 respectively, as well as other structures connected to the source region 102 or the drain region 103 respectively.

[0098] Referring to Figure 1, capacitor 200 includes a first electrode 201, a dielectric layer 202, and a second electrode 203. The dielectric layer 202 is located between the first electrode 201 and the second electrode 203; each first electrode 201 fills a corresponding recess 104. The dielectric layer 202 and the second electrode 203 are disposed between two adjacent transistors 140 spaced apart along a second direction.

[0099] Please refer to Figure 1. The drain region 103 is in electrical contact with the contact structure 130, and the source region 102 is in electrical contact with the first electrode 201.

[0100] Please refer to Figure 1. The first electrode 201 can be reused as the source electrode or drain electrode of the transistor 140 provided in the embodiments of this application, and the transistor 140 and the capacitor 200 are connected.

[0101] It is understandable that if the ratio of the height to the width of the notch 104 is large, the dielectric layer 202 and the second electrode 203 can also be disposed in the notch 104 to increase the area of ​​the capacitor 200 and thus increase the capacitance of the capacitor 200. This is beneficial to reduce the refresh frequency of the three-dimensional dynamic random access memory provided in this application, thereby reducing power consumption.

[0102] The materials of the first electrode 201 and the contact structure 130 can be different or the same, depending on the performance and manufacturing process requirements of the three-dimensional dynamic random access memory provided in this embodiment. Optionally, the materials of the first electrode 201 and the contact structure 130 can be the same, and they can be formed in the same step when manufacturing the three-dimensional dynamic random access memory provided in this embodiment, thereby reducing process steps, increasing yield, and reducing costs. Furthermore, the materials of the first electrode 201 and the contact structure 130 can be one or more of all metallic materials that can be used in semiconductor manufacturing, including copper, aluminum, and tungsten.

[0103] Furthermore, the dielectric layers 202 of the different capacitors 200 spaced apart along the first direction can be separated from each other or integrally continuous; the second electrodes 203 of the different capacitors 200 spaced apart along the first direction can be separated from each other or integrally continuous. The relationship between the dielectric layers 202 of the different capacitors 200 spaced apart along the first direction and the relationship between the second electrodes 203 of the different capacitors 200 spaced apart along the first direction can be determined according to the area requirements of the capacitors 200 and the manufacturing process, and this application does not impose specific limitations on this.

[0104] For example, referring to FIG1, the dielectric layer 202 of the different capacitors 200 spaced apart along the first direction is integrally continuous, and the second electrode 203 of the different capacitors 200 spaced apart along the first direction is integrally continuous. The second dielectric portion 320 is simultaneously disposed between the two capacitors 200 spaced apart along the third direction and between the two contact structures 130 spaced apart along the third direction. In this case, the dielectric layer 202 of the different capacitors 200 spaced apart along the first direction is integrally continuous, and the second electrode 203 of the different capacitors 200 spaced apart along the first direction is integrally continuous. There is no need to form an insulating layer for the different capacitors 200 spaced apart along the first direction, which reduces the volume occupied by the insulating layer. This is beneficial to further reduce the size of the storage unit 100 provided in this application embodiment, thereby improving the storage density of the three-dimensional dynamic random access memory provided in this application embodiment. At the same time, the integrally continuous second electrode 203 and dielectric layer 202 can make the dielectric layer 202 of different capacitors 200 and the second electrode 203 of different capacitors 200 formed simultaneously when manufacturing the three-dimensional dynamic random access memory provided in this application embodiment. This reduces the process steps of forming the dielectric layer 202 and the second electrode 203 of different capacitors 200 separately, which is beneficial to reduce costs and increase yield.

[0105] Furthermore, referring to Figure 1, the transistors 140 and capacitors 200 included in the different memory cells 100 provided in this application embodiment can have the same or different sizes, depending on the design requirements for the performance of the different memory cells 100. Optionally, the transistors 140 and capacitors 200 included in the different memory cells 100 provided in this application embodiment have the same size, so that the different memory cells 100 provided in this application embodiment have the same performance, which is beneficial for electronic systems using the three-dimensional dynamic random access memory provided in this application embodiment to perform access operations on the three-dimensional dynamic random access memory provided in this application embodiment.

[0106] Regarding the size of other parts of the three-dimensional dynamic random access memory provided in the embodiments of this application, the embodiments of this application do not impose specific limitations on the size, provided that other performance requirements, including process accuracy and insulation performance, are met.

[0107] Secondly, embodiments of this application also provide a method for manufacturing a three-dimensional dynamic random access memory (DRAM). This method is used to manufacture the three-dimensional DRAM provided in the first aspect, and includes: forming a plurality of memory cells 100 arranged in a three-dimensional array; the plurality of memory cells 100 arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, each memory group including a plurality of memory cells 100 arranged along a third direction; the first direction, the second direction, and the third direction are different from each other; each memory cell 100 includes a transistor 140 and a capacitor 200; forming a method for assembling different memory cells... A dielectric structure is 100 separated; the dielectric structure includes a first dielectric portion 310 located between two transistors 140 spaced apart along a first direction; the transistor 140 includes: a gate 110, a gate dielectric layer 120, a channel region 101, a source region 102, and a drain region 103; the length direction of the channel region 101 is parallel to a second direction, and the two side walls of the channel region 101 along the length direction are recessed inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104; the source region 102 and the drain region 103 are respectively disposed on both sides along the length direction and cover the inner wall of the notch 104; the gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102, and the drain region 103 respectively.

[0108] Specifically, in the manufacturing method provided in this application embodiment, the order in which the storage unit 100 and the medium structure are formed is not specifically limited, and the two can be formed simultaneously.

[0109] Compared with the prior art, the beneficial effects of the manufacturing method of the three-dimensional dynamic random access memory provided in this application embodiment are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above-described technical solution, and will not be repeated here.

[0110] The process of manufacturing a three-dimensional dynamic random access memory (DRAM) will be described below with reference to the schematic diagrams of the operation shown in Figures 2 to 12. Exemplarily, the method for manufacturing this three-dimensional DRAM includes the following steps:

[0111] As shown in Figure 5, a stacked structure is formed, and a second dielectric portion 320 penetrates the stacked structure. The stacked structure includes multiple stacked units stacked along a first direction. Each stacked unit includes a first dielectric layer 311 and a stack on the first dielectric layer 311. The stack includes a stacked second dielectric layer 331 and a gate 110. The material of the first dielectric layer 311 is different from the material of the second dielectric layer 331. A first via group 410 and a second via group 420 are provided in the stacked structure and are spaced apart along a second direction. Both the first via group 410 and the second via group 420 include a plurality of vias spaced apart along a third direction. The second dielectric portion 320 is disposed between two adjacent vias in the same first via group 410 along the first direction and between two adjacent vias in the same second via group 420 along the first direction. The first dielectric portion 310 includes the first dielectric layer 311.

[0112] Specifically, the first dielectric layer 311 is used to form the first dielectric portion 310, which isolates the memory cell 100 along the first direction. For information on the material and thickness of the first dielectric layer 311, please refer to the relevant description of the first dielectric portion 310, which will not be repeated here.

[0113] Regarding the stacked structure, the stack includes a second dielectric layer 331 and a gate 110. The second dielectric layer 331 serves as a sacrificial layer, pre-positioning the channel region 101 and the gate dielectric layer 120 to facilitate the subsequent formation of the channel region 101 and the gate dielectric layer 120. The second dielectric layer 331 also serves as an isolation layer, insulating and isolating the channel region 101 and the gate dielectric layer 120 of adjacent transistors 140 distributed along the third direction after the subsequent formation of the third dielectric portion 332. For details regarding the materials and beneficial effects of the second dielectric layer 331 and the gate 110, including the first gate 111 and the second gate 112, please refer to the relevant description in the first aspect; further details will not be repeated here.

[0114] For example, the stack includes a first gate 111 disposed along a first direction, a second dielectric layer 331 and a second gate 112, the first gate 111 and the second gate 112 forming a gate 110 to facilitate the subsequent formation of a dual-gate transistor structure.

[0115] It is understood that the stack may also consist of only a gate layer 110 and a second dielectric layer 331 to form a conventional transistor 140 or a back-gate transistor. The specific structure of the stack can be formed according to the requirements of the transistor 140 structure in the first aspect, and will not be elaborated here.

[0116] It should be noted that, along the first direction, the two outermost layers of the stacked structure are the first dielectric layers 311, and the thickness of the two outermost first dielectric layers 311 of the stacked structure can be greater than that of the first dielectric layer 311 located inside the stacked structure, so as to protect the stacked structure and other structures formed subsequently.

[0117] The first via group 410 includes a via for forming a contact structure 130 within the via. The second via group 420 includes a via for forming a capacitor 200 within the via.

[0118] The shape of each through hole in the first through hole group 410 can be a cylindrical hole, a prism hole, or other possible shapes. Regarding the size of each through hole in the first through hole group 410, this application embodiment does not impose specific limitations on it, as long as a contact structure 130 can be formed within the first through hole.

[0119] Optionally, the aperture of each via in the first via group 410 can be greater than or equal to 30 nm and less than or equal to 3000 nm. In this case, it can avoid the excessively high cost caused by excessively small apertures due to high requirements for etching and photolithography processes, which is beneficial to cost reduction; it can also avoid the difficulty in uniformly forming or forming the contact structure 130 on the via wall due to excessively small apertures. It can also avoid the excessive area occupied by excessively large apertures, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured in the embodiments of this application.

[0120] It should be noted that the contact structure 130 formed in each through hole of the first through hole group 410 can be disposed in a barrel shape on the inner wall of the through hole to form a barrel-shaped position line; or the contact structure 130 can be disposed in a column shape to fill each through hole of the first through hole group 410 to form a column-shaped position line.

[0121] The shape of each through hole in the second through hole group 420 can be a cylindrical hole, a prism hole, or other possible shapes. Regarding the size of each through hole in the second through hole group 420, this application embodiment does not impose specific limitations on it, as long as a capacitor 200 can be formed within the second through hole.

[0122] The second via group 420 includes vias with a diameter greater than or equal to 50 nm and less than or equal to 5000 nm. In this case, excessively small via diameters can avoid the high costs associated with etching and photolithography processes, thus reducing costs. It also avoids the reduction in capacitor 200 area due to small via diameters, which would decrease the capacitor 200's hold time and lead to higher refresh rates and increased power consumption, thereby reducing the power consumption of the three-dimensional dynamic random access memory manufactured in this embodiment. Furthermore, excessively large via diameters can also be avoided, thus reducing the storage density of the three-dimensional dynamic random access memory manufactured in this embodiment.

[0123] It should be noted that the dielectric layer 202 and the second electrode 203 formed in each through hole of the second through hole group 420 can both be disposed in a barrel shape on the inner wall of the through hole; or the dielectric layer 202 can be disposed in a barrel shape on the inner wall of the through hole, and the second electrode 203 can be disposed in a column shape to fill each through hole of the first through hole group 410.

[0124] It should be noted that the diameter of the aforementioned through hole is defined as the diameter of a cylindrical hole with the same radial cross-sectional area as the through hole.

[0125] Along a third direction, the second dielectric section 320 separates each through-hole included in the first via group 410 and also isolates the contact structure 130 formed in subsequent process steps. Along a third direction, the second dielectric section 320 separates each through-hole included in the second via group 420 and also isolates the capacitor 200 formed in subsequent process steps.

[0126] In practical applications, this embodiment does not specifically limit the diameter of each through hole in the first through hole group 410 and the diameter of each through hole in the second through hole group 420, as long as the performance requirements of the structure disposed within the through hole are met.

[0127] In practical applications, the methods for forming the stacked structure and the second medium portion 320 that penetrates the stacked structure are not specifically limited in the embodiments of this application. They can be determined based on the number of storage layers and manufacturing process of the three-dimensional dynamic random access memory provided in the embodiments of this application.

[0128] In one example, the above-described forming of the stacked structure and the second dielectric portion 320 penetrating the stacked structure may include the following steps:

[0129] The first step, referring to Figure 2, is to form a stacked material layer using a deposition or epitaxial process. The stacked material layer includes a stacked structure comprising multiple stacked units stacked along a first direction, each stacked unit including a first dielectric layer 311 and stacked layers located on the first dielectric layer 311.

[0130] The second step, referring to Figure 3, involves using photolithography and etching processes to form a third via group 430 and a fourth via group 440 that penetrate the stacked material layers. The aperture pattern of the third via group 430 is the same as the top pattern of the second dielectric layer 331 located between two adjacent vias in the first via group 410 along the first direction. The aperture pattern of the fourth via group 440 is the same as the top pattern of the second dielectric layer 331 located between two adjacent vias in the first direction in the second via group 420. The formation of the third through-hole group 430 and the fourth through-hole group 440 is for the purpose of forming the second medium section 320 in a subsequent step. The second medium section 320 is used to isolate two through holes in the same first through-hole group 410 that are adjacent along the first direction and to isolate two through holes in the same second through-hole group 420 that are adjacent along the first direction. It can be understood that the orifice patterns of the first through-hole group 410 and the third through-hole group 430 that are closest along the second direction are alternately arranged, and the orifice patterns of the second through-hole group 420 and the fourth through-hole group 440 that are closest along the second direction are alternately arranged.

[0131] Thirdly, referring to Figure 4, a second dielectric portion 320 is formed, for example, by a deposition process, to fill the third via group 430 and the fourth via group 440. The material of the second dielectric portion 320 is described in the corresponding description in the first aspect and will not be repeated here.

[0132] The fourth step, please refer to Figure 5, is to use photolithography and etching processes to form the first through-hole group 410 and the second through-hole group 420 that penetrate the stacked material layer, thus forming the stacked structure.

[0133] In another example, the method of forming the stacked structure and the second medium portion 320 through the stacked structure can also be to first form a portion of the stacked material layer and form the first through-hole group 410 and the second through-hole group 420, then form another portion of the stacked material layer and form the first through-hole group 410 and the second through-hole group 420; repeat the above process to finally form the stacked structure.

[0134] Next, referring to Figure 6, an edge portion of the first gate 111 and the second gate 112 is selectively removed using, for example, a selective etching process to form a notch 104 and a stacked structure. The dimensions of the notch 104 and its beneficial effects are described in the corresponding description in the first aspect and will not be repeated here.

[0135] Next, referring to FIG7, a process such as selective etching is used to selectively remove the second dielectric layer 331, so that the remaining second dielectric layer 331 forms the third dielectric portion 332 and forms a floating region for forming the channel region 101. The floating region is located in the first direction between two transistors 140 spaced apart along the third direction between the two third dielectric portions 332.

[0136] Next, referring to Figure 8, a thin-film deposition process is used to deposit the gate dielectric layer 120 on all surfaces of the stacked structure. The material of the gate dielectric layer 120 and its beneficial effects are described in the corresponding section of the first aspect and will not be repeated here.

[0137] Next, referring to Figure 9, a thin-film deposition process is used to deposit a channel layer 105 on the entire surface of the stacked structure. The channel layer 105 completely fills the suspended areas and forms a channel region 101. The material of the channel layer 105 and its beneficial effects are described in the corresponding description of the channel region 101 in the first aspect, and will not be repeated here.

[0138] Next, referring to Figure 10, an electrode layer 204 is deposited on all surfaces of the stacked structure using a thin-film deposition process. The electrode layer 204 is subsequently fabricated into a first electrode 201 and a contact structure 130. The material of the electrode layer 204 and its beneficial effects are described in the corresponding description of the channel region 101 in the first aspect, and will not be repeated here.

[0139] Next, referring to Figure 11, photolithography and etching processes are used to remove the channel layer 105, gate dielectric layer 120, and electrode layer 204 located in each via of the second via group 420, leaving only the portion located within the recess 104 near each via of the second via group 420. The portion of the channel layer 105 located within the recess 104 near each via of the second via group 420 forms a drain region 103, and the portion of the electrode layer 204 located within the recess 104 near each via of the second via group 420 forms a first electrode 201. The portion of the channel layer 105 located within the recess 104 near each via of the first via group 410 forms a source region 102, and the electrode layer 204 located within each via of the first via group 410 forms a contact structure 130.

[0140] It should be noted that the accompanying drawings provided in this application only illustrate the case where the drain region 103 is electrically connected to the capacitor 200 and the source region 102 is electrically connected to the contact structure 130, but do not represent that the connection relationship can only be as described above. For the specific connection relationships between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200, respectively, please refer to the preceding text; when the drain region 103 is electrically connected to the capacitor, the source region 102 is electrically connected to the contact structure.

[0141] Next, referring to Figure 12, a dielectric layer 202 is formed in each via of the second via group 420 using a thin film deposition process.

[0142] Next, referring to Figure 12, a second electrode 203 is formed in each via of the second via group 420 using a thin film deposition process. The second electrode 203 is also formed on the dielectric layer 202.

[0143] Please note that when forming the gate dielectric layer 120, channel layer 105, electrode layer 204, dielectric layer 202 and second electrode 203 using thin film deposition process, the same process, such as atomic layer deposition, can be used. This is beneficial for continuous processing using the same equipment, thereby reducing damage to the three-dimensional dynamic random access memory when transferring the three-dimensional dynamic random access memory manufactured in the embodiments of this application from equipment used for different processes, thereby improving the yield.

[0144] With the above technical solution, please refer to Figure 12. The first dielectric portion 310 includes a second dielectric layer 331, in which all of the first dielectric layer 311 is removed, serving as a pre-occupancy structure for the channel region 101. After removal, a gate dielectric layer 120 covering the outer periphery of the gate 110 is sequentially deposited, and the channel region 101, source region 102, and drain region 103 are deposited on the gate dielectric layer 120. In the prior art, during the manufacturing process of the transistor 140, the sacrificial layer stacked on both sides of the channel region 101 is first removed, and then the gate dielectric layer 120 and the gate 110 are formed on both sides of the channel region 101 along the first and second directions. At this time, the channel region 101 is suspended, and the channel region 101 is a semiconductor material with low structural strength. When the memory cell 100 has a small geometric size, the channel region 101, which is a semiconductor material with a large aspect ratio along the second direction, will collapse, causing the transistor 140 to deform, thereby reducing the performance of the memory cell 100 or even preventing it from working properly, thus reducing the yield. Based on this, in the fabrication of the three-dimensional dynamic random access memory (DRAM), after selectively etching the second dielectric layer 331 to form the third dielectric portion 332, the gate 110 is left suspended. Compared to the channel region 101 material, the gate 110 material has higher structural strength and is less prone to collapse due to a large aspect ratio along the second direction when the memory cell 100 has a relatively small geometric size. The DRAM fabrication method provided by this application ensures the structural regularity of the transistor 140, thereby ensuring the normal operation and stable performance of the memory cell 100 fabricated by the DRAM fabrication method provided by this application, thus improving the yield.

[0145] Furthermore, referring to Figure 12, after forming the second electrode 203 in each via of the second via group 420 using a thin film deposition process, a planarization process, including chemical mechanical polishing, can be used to polish the outer surface of the three-dimensional dynamic random access memory manufactured in this embodiment along the first direction, the second direction, and the third direction to remove the gate dielectric layer 120, the channel layer 105, the electrode layer 204, the dielectric layer 202, and the second electrode 203, so as to ensure that the multiple memory cells 100 distributed in a three-dimensional array provided in this embodiment are mutually insulated on the outer surface of the three-dimensional dynamic random access memory.

[0146] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0147] The above are merely specific embodiments of this application, but the protection scope of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional dynamic random access memory, wherein, include: Multiple storage cells arranged in a three-dimensional array, and a medium structure for isolating the different storage cells; The plurality of storage cells arranged in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer including a plurality of storage groups spaced apart along a second direction, and each storage group including a plurality of storage cells distributed along a third direction. The first direction, the second direction, and the third direction are all different from each other; Each of the memory cells includes a transistor and a capacitor; the dielectric structure includes a first dielectric portion located between two of the transistors spaced apart along the first direction; The transistor includes: a gate, a gate dielectric layer, a channel region, a source region, and a drain region; the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are recessed inward relative to the side walls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively disposed on both sides of the channel region along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region, and the drain region respectively; The capacitor is electrically connected to the source or drain region of the transistor.

2. The three-dimensional dynamic random access memory according to claim 1, wherein, The ratio of the height to the width of the notch is greater than or equal to 0.1 and less than or equal to 10; the height of the notch is parallel to the first direction, and the width of the notch is parallel to the second direction.

3. The three-dimensional dynamic random access memory according to claim 1, wherein, The ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000; the thickness direction of the channel region is parallel to the first direction; And / or, the ratio of the thickness of the channel region to the width of the notch is greater than or equal to 0.1 and less than or equal to 10; the width of the notch is parallel to the second direction.

4. The three-dimensional dynamic random access memory according to claim 1, wherein, The material of the channel region includes indium gallium zinc oxide; And / or, the source region, the drain region, and the channel region are integrally continuous.

5. The three-dimensional dynamic random access memory according to claim 1, wherein, The gate includes a first gate and a second gate disposed on both sides of the channel region along the first direction.

6. The three-dimensional dynamic random access memory according to claim 1, wherein, The three-dimensional dynamic random access memory also includes a contact structure; Wherein, when the source region of the transistor is electrically connected to the capacitor, the drain region is electrically connected to the contact structure; or, when the drain region of the transistor is electrically connected to the capacitor, the source region is electrically connected to the contact structure. The dielectric structure further includes a second dielectric portion and a third dielectric portion; the second dielectric portion is located between two capacitors spaced apart along the third direction and between two contact structures spaced apart along the third direction; the third dielectric portion is located between two transistors spaced apart along the third direction.

7. The three-dimensional dynamic random access memory according to claim 6, wherein, The capacitor includes a first electrode, a dielectric layer, and a second electrode; the dielectric layer is located between the first electrode and the second electrode; each first electrode is filled in a corresponding notch; the dielectric layer and the second electrode are disposed between two adjacent transistors spaced apart along the second direction; The dielectric layers of the different capacitors distributed at intervals along the first direction are integrally continuous, and the second electrodes of the different capacitors distributed at intervals along the first direction are integrally continuous.

8. A method for manufacturing a three-dimensional dynamic random access memory, wherein, include: Multiple storage cells are arranged in a three-dimensional array; the multiple storage cells arranged in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, and each storage group includes multiple storage cells arranged along a third direction. The first direction, the second direction, and the third direction are all different from each other; each memory cell includes a transistor and a capacitor; A dielectric structure is formed to isolate different memory cells; the dielectric structure includes a first dielectric portion located between two transistors spaced apart along a first direction; the transistors include: a gate, a gate dielectric layer, a channel region, a source region, and a drain region; the length direction of the channel region is parallel to the second direction, and the two sidewalls of the channel region along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively disposed on the two sidewalls along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region, and the drain region respectively.

9. The method for manufacturing a three-dimensional dynamic random access memory according to claim 8, wherein, The formation of a plurality of said memory cells arranged in a three-dimensional array, and the formation of said media structure for isolating the different said memory cells, include: A stacked structure is formed, and a second dielectric portion penetrates the stacked structure; the stacked structure includes multiple stacked units stacked along a first direction; each stacked unit includes a first dielectric layer and a stacked layer located on the first dielectric layer; the stacked layer includes a stacked second dielectric layer and a gate; the material of the first dielectric layer is different from the material of the second dielectric layer; the stacked structure has a first via group and a second via group spaced apart along the second direction; both the first via group and the second via group include a plurality of vias spaced apart along the third direction; the second dielectric portion is disposed between two adjacent vias in the same first via group along the first direction, and between two adjacent vias in the same second via group along the first direction; the first dielectric portion includes the first dielectric layer; The edge portions of each of the gate layers are selectively removed to form the notch; The second dielectric layer is selectively etched to form a third dielectric portion with the remaining second dielectric layer; the third dielectric portion is located between two transistors spaced apart along the third direction; the dielectric structure includes the first dielectric portion, the second dielectric portion, and the third dielectric portion. A gate dielectric layer is deposited to cover the outer periphery of the gate; and a channel region, a source region, and a drain region are deposited on the gate dielectric layer; A contact structure is formed in each of the through holes in the first through hole group, and a first electrode of the capacitor is formed in the portion of the notch corresponding to each of the through holes in the second through hole group. A dielectric layer and a second electrode are sequentially formed in each of the vias included in the second via group; the capacitor includes the first electrode, the dielectric layer and the second electrode.

10. The method for manufacturing a three-dimensional dynamic random access memory according to claim 9, wherein, The formation of the stacked structure and the second dielectric portion penetrating the stacked structure include: Forming stacked material layers; A third and fourth through-hole group are formed through the stacked material layer; the orifice pattern of the third through-hole group is the same as the top pattern of the second dielectric layer disposed between two adjacent through-holes in the same first through-hole group along the first direction; the orifice pattern of the fourth through-hole group is the same as the top pattern of the second dielectric layer disposed between two adjacent through-holes in the same second through-hole group along the first direction. A second medium portion is formed that fills the third and fourth through-hole groups; The first and second through-hole groups are formed through the stacked material layers.

11. The method for manufacturing a three-dimensional dynamic random access memory according to claim 9, wherein, The diameter of each through hole in the first through hole group is greater than or equal to 30 nm and less than or equal to 3000 nm; And / or, the aperture of each via in the second via group is greater than or equal to 50 nm and less than or equal to 5000 nm.

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