Image sensor

Abstract

An image sensor may include: a substrate having a first surface and a second surface opposite to each other, and including a plurality of photoelectric conversion portions; a first isolation structure disposed in the substrate to separate the photoelectric conversion portions from each other; an oxide structure on the first isolation structure; and a microlens on the oxide structure. The first isolation structure and the microlens may vertically overlap each other, and the first isolation structure may include a first isolation conductive pattern. The oxide structure may be in contact with the first isolated conductive pattern, and a bottom surface of the oxide structure may be placed between the first surface and the second surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0123169, filed with the Korean Intellectual Property Office on September 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to image sensors, and more particularly, to image sensors having improved electrical and optical properties. Background Technology

[0004] An image sensor is a semiconductor device that converts optical images into electrical signals. Image sensors are classified into two types: charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS). Typically, a CMOS image sensor is referred to as a "CIS". A CIS consists of multiple pixels arranged in a two-dimensional array. Each pixel may include a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0005] Some aspects of this disclosure provide an image sensor with reduced light loss and improved sensitivity.

[0006] According to some embodiments of this disclosure, an image sensor may include: a substrate having a first surface and a second surface opposite to each other, and including a plurality of photoelectric conversion portions; a first isolation structure disposed in the substrate to separate the photoelectric conversion portions from each other; an oxide structure on the first isolation structure; and a microlens on the oxide structure. The first isolation structure and the microlens may vertically overlap each other, and the first isolation structure may include a first isolation conductive pattern. The oxide structure may contact the first isolation conductive pattern, and the bottom surface of the oxide structure may be disposed between the first surface and the second surface of the substrate.

[0007] According to some embodiments, an image sensor may include: a substrate having a first surface and a second surface opposite to each other, and including a plurality of photoelectric conversion portions; a first isolation structure and a second isolation structure disposed in the substrate and spaced apart from each other in a first direction; an oxide structure on the first isolation structure; and a microlens on the oxide structure. The first isolation structure may vertically overlap with the microlens, and the first isolation structure may include a first isolation conductive pattern. The oxide structure may include a first portion and a second portion on the first portion, and the first portion may contact the first isolation conductive pattern. The second portion may extend on a second surface, and the height of the first portion may be greater than the height of the second portion.

[0008] According to some embodiments, an image sensor may include: a substrate including a first pixel group and a second pixel group adjacent to each other, each of the first pixel group and the second pixel group including a plurality of photoelectric conversion portions; a first isolation structure disposed in the substrate to separate the first pixel group and the second pixel group from each other; a second isolation structure disposed in the substrate to separate the photoelectric conversion portions included in each of the first pixel group and the second pixel group from each other; and an oxide structure on the second isolation structure. The first isolation structure and the second isolation structure may each include a first isolation conductive pattern and a second isolation conductive pattern. The height of the second isolation conductive pattern may be less than the height of the first isolation conductive pattern. The oxide structure may include a first portion and a second portion protruding from the first portion. The first portion may contact the first isolation conductive pattern, and the second portion may contact the second isolation conductive pattern. The height of the second portion may be in the range of 0.5 μm to 1.5 μm. Attached Figure Description

[0009] Figure 1 This is a plan view showing an example of an image sensor.

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0011] Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'.

[0012] Figure 4 It is shown Figure 2 An enlarged cross-sectional view of part “CU1”.

[0013] Figure 5 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0014] Figure 6 It is shown Figure 5 An enlarged cross-sectional view of part “CU2”.

[0015] Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a cross-sectional view illustrating an example of the process for manufacturing an image sensor.

[0016] Figure 11 This is a plan view showing an example of an image sensor. Detailed Implementation

[0017] Figure 1 This is a plan view illustrating an image sensor according to some embodiments of the present disclosure. Figure 2It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B'. Figure 4 It is shown Figure 2 An enlarged cross-sectional view of part “CU1”.

[0018] Reference Figures 1 to 4 The image sensor may include a substrate 2. The substrate 2 may include a first surface 2a and a second surface 2b opposite to each other. Light can be incident into the substrate 2 through the second surface 2b. The substrate 2 may be a single-crystal wafer, epitaxial layer, or silicon-on-insulator (SOI) wafer formed of or including silicon and / or germanium, to provide several non-limiting examples. Other types of substrates are also within the scope of this disclosure.

[0019] The substrate 2 may include a first active region ACT1 and a second active region ACT2 defined by the device isolation portion STI, which will be described below. The first active region ACT1 may be configured to surround the second active region ACT2.

[0020] In this specification, the first direction D1 can be defined as a direction parallel to the first surface 2a of the substrate 2. The second direction D2 can be defined as a direction parallel to the first surface 2a of the substrate 2 and perpendicular to the first direction D1. The third direction D3 can be perpendicular to the first surface 2a of the substrate 2. The fourth direction D4 can be defined as a direction parallel to the first surface 2a of the substrate 2 and not parallel to the first direction D1 and the second direction D2.

[0021] In some embodiments, the image sensor 1 includes a first pixel group GRP1 to a fourth pixel group GRP4 disposed on a substrate 2 in a clockwise direction. The first pixel group GRP1 and the second pixel group GRP2 may be adjacent to each other in a first direction D1. The second pixel group GRP2 and the third pixel group GRP3 may be adjacent to each other in a second direction D2. The third pixel group GRP3 and the fourth pixel group GRP4 may be adjacent to each other in the first direction D1. The first pixel group GRP1 and the fourth pixel group GRP4 may be adjacent to each other in the second direction D2. The first pixel group GRP1 to the fourth pixel group GRP4 may be separated from each other in a first isolation structure DTI, which will be described below.

[0022] Each of the first pixel group GRP1 to the fourth pixel group GRP4 may include multiple pixel regions PX and photoelectric conversion portions (or components, or regions) PD within the pixel regions PX. The photoelectric conversion portions PD may be separated from each other by a second isolation structure CDTI described below.

[0023] In at least one of the pixel regions PX, a pixel gate electrode PG may be disposed in the first interlayer insulating layer ILD1, which will be described below. The pixel gate electrode PG, combined with the source / drain regions in the first active region ACT1, can constitute a pixel transistor. In some embodiments, the pixel transistor may be one of a reset transistor, a source follower transistor, a double-conversion gain transistor, and a select transistor.

[0024] In at least one of the pixel regions PX, the pixel gate electrode PG may not be disposed in the first interlayer insulating layer ILD1. Alternatively or additionally, a ground region GND may be disposed on at least one of the pixel regions PX. The arrangement of the pixel gate electrode PG and the ground region GND can be varied in various combinations or changes.

[0025] Each of the pixel regions PX may include a transfer gate electrode TG and a floating diffusion region FD disposed on the second active region ACT2. A common floating diffusion region FDC may be disposed at the center of each of the first pixel groups GRP1 to GRP4. The common floating diffusion region FDC may be electrically connected to the floating diffusion region FD in each of the pixel groups GRP1 to GRP4.

[0026] Return to reference Figure 2 and Figure 3 The substrate 2 may be doped with a first impurity to have a first conductivity type. The first impurity may be, for example, boron. The first conductivity type may be, for example, p-type.

[0027] A first isolation structure DTI can be disposed in the substrate 2 to separate the first pixel group GRP1 to the fourth pixel group GRP4 from each other. The first isolation structure DTI can be configured to penetrate or extend through the substrate 2. The width of the first isolation structure DTI can decrease as it transitions from the first surface 2a to the second surface 2b.

[0028] The first isolation structure DTI may include a first isolation conductive pattern 10, a first isolation insulating pattern 12, and a first gap-filling insulating pattern 14. The first isolation conductive pattern 10 may be spaced apart from the substrate 2. The first isolation conductive pattern 10 may include a conductive material having a different refractive index than the substrate 2. In some embodiments, the first isolation conductive pattern 10 includes at least one of doped polycrystalline silicon and (multiple) metallic materials.

[0029] A first insulating isolation pattern 12 may be interposed between a first conductive isolation pattern 10 and a substrate 2. A first gap-filling insulating pattern 14 may be disposed below the first conductive isolation pattern 10. The first insulating isolation pattern 12 and the first gap-filling insulating pattern 14 may comprise an insulating material having a different refractive index than the substrate 2. In some embodiments, the first insulating isolation pattern 12 and the first gap-filling insulating pattern 14 are formed of or comprise silicon oxide.

[0030] A second isolation structure CDTI can be disposed in the substrate 2 to separate the photoelectric conversion portions (PDs) included in each of the first pixel groups GRP1 to the fourth pixel groups GRP4 from each other. The second isolation structure CDTI can be spaced apart from the first isolation structure DTI in the first direction D1 and the second direction D2. In some embodiments, multiple second isolation structures CDTI are disposed in the first direction D1 and the second direction D2. The second isolation structures CDTI can be configured to penetrate or extend through the substrate 2. The width of the second isolation structure CDTI can decrease as it transitions from the first surface 2a to the second surface 2b.

[0031] The second isolation structure CDTI may include a second isolation conductive pattern 11, a second isolation insulating pattern 13, and a second gap-filling insulating pattern 15. The second isolation conductive pattern 11 may be spaced apart from the substrate 2. The second isolation conductive pattern 11 may include a conductive material having a different refractive index than the substrate 2. The second isolation conductive pattern 11 may include doped polycrystalline silicon or (multiple) metal materials.

[0032] Here, the height 11H of the second insulating conductive pattern 11 (e.g., the thickness on the third-direction D3) can be smaller than the height 10H of the first insulating conductive pattern 10 (e.g., the thickness on the third-direction D3). In some embodiments, the height 11H of the second insulating conductive pattern 11 is 60% to 70% of the thickness of the substrate 2.

[0033] The second insulating pattern 13 can be interposed between the second conductive insulating pattern 11 and the substrate 2, and between the substrate 2 and the oxide structure 40 described below. The second gap-filling insulating pattern 15 can be disposed below the second conductive insulating pattern 11. The second insulating pattern 13 and the second gap-filling insulating pattern 15 can comprise insulating materials having a different refractive index than the substrate 2. As an example, the second insulating pattern 13 and the second gap-filling insulating pattern 15 can be formed of silicon oxide or comprise silicon oxide.

[0034] A negative bias voltage can be applied to the first isolation conductive pattern 10 and the second isolation conductive pattern 11. The first isolation conductive pattern 10 and the second isolation conductive pattern 11 can be used as a common bias line. Therefore, holes that may exist on the surfaces of the substrate 2 that are in contact with the first isolation structure DTI and the second isolation structure CDTI can be retained, thereby improving the dark current characteristics of the image sensor.

[0035] The oxide structure 40 can be disposed on the second insulating conductive pattern 11 of the second insulating structure CDTI. The upper portion of the second insulating pattern 13 can be configured to surround (e.g., laterally surround) the side (or lateral) surface of the oxide structure 40. Here, as... Figure 4 As shown, the bottom surface of the oxide structure 40 can be placed between the first surface 2a and the second surface 2b of the substrate 2, such that the oxide structure 40 is at least partially embedded in the substrate 2. That is, the level 40l of the bottom surface of the oxide structure 40 can be lower than the second surface 2b. For example, the oxide structure 40 can protrude from the second surface 2b of the substrate 2 into the substrate.

[0036] In some implementations, such as Figure 4 As shown, the oxide structure 40 includes a first portion 40a and a second portion 40b on the first portion 40a. The first portion 40a may have a shape that protrudes from the second portion 40b. The second portion 40b may extend on the second surface 2b.

[0037] Part 40a and Part 40b can be connected to form a single object.

[0038] The first portion 40a may contact the second insulating conductive pattern 11. The second insulating pattern 13 may surround the side (or lateral) surface of the first portion 40a. The level of the bottom surface of the first portion 40a may be lower than the level of the top surface of the first insulating structure DTI. The height 40aH of the first portion 40a may be greater than the height 40bH of the second portion 40b. In this specification, the height 40aH of the first portion 40a and the height 40bH of the second portion 40b correspond to the thickness of the first portion 40a and the thickness of the second portion 40b, respectively.

[0039] The height 40aH of the first portion 40a can be 20% to 30% of the thickness of the substrate 2. In some embodiments, the height 40aH of the first portion 40a is in the range of 0.5 μm to 1.5 μm. In some embodiments, since the height 40aH of the first portion 40a is less than 30% of the thickness of the substrate 2, the dark current improvement achieved by the second isolation conductive pattern 11 can be unaffected by the first portion 40a.

[0040] The second portion 40b may contact the second surface 2b of the substrate 2 and the top surface of the first isolation structure DTI. For example, the second portion 40b may contact the first isolation conductive pattern 10 in the first isolation structure DTI.

[0041] The oxide structure 40 may include a metal oxide. In some embodiments, the oxide structure 40 includes at least one of aluminum oxide and hafnium oxide.

[0042] The device isolation portion STI can be disposed on the first surface 2a of the substrate 2. The first isolation structure DTI and the second isolation structure CDTI can be disposed on the device isolation portion STI. In some embodiments, portions of the device isolation portion STI and the first isolation structure DTI and the second isolation structure CDTI (e.g., the first isolation insulating pattern 12, the first gap-filling insulating pattern 14, the second isolation insulating pattern 13, and / or the second gap-filling insulating pattern 15) are formed of the same material. In some embodiments, when the device isolation portion STI and portions of the first isolation structure DTI and the second isolation structure CDTI are formed of the same material, the material content in the device isolation portion STI differs from the material content in the first isolation structure DTI and the second isolation structure CDTI. For example, the material content may refer to the content of silicon oxide contained in the device isolation portion STI and the first isolation structure DTI and the second isolation structure CDTI.

[0043] The photoelectric conversion section PD can be disposed in the substrate 2. The well region PW can be disposed between the photoelectric conversion section PD and the first surface 2a. In some embodiments, the well region PW is doped with a first impurity to have a first conductivity type. The first impurity can be, for example, boron. The first conductivity type can be, for example, p-type. The concentration of the first impurity doped in the well region PW can be equal to or greater than the concentration of the impurity doped in the substrate 2.

[0044] The photoelectric conversion section PD can be doped with a second impurity different from the first impurity to have a second conductivity type. The second impurity can be, for example, phosphorus or arsenic. The second conductivity type can be, for example, n-type. The photoelectric conversion section PD in the n-type region can be combined with the well region PW in the adjacent region of the substrate 2 and / or the p-type region to form a PN junction that serves as a photodiode, and electron-hole pairs can be generated from the PN junction if light is incident on it.

[0045] The pixel gate electrode PG can be disposed on the first surface 2a of the substrate 2. The pixel gate electrode PG can be formed or include at least one of doped polysilicon, conductive metal nitride, conductive metal silicide, conductive metal oxide, and combinations thereof. The gate insulating layer PGI can be interposed between the pixel gate electrode PG and the substrate 2.

[0046] like Figure 3 As shown, a common floating diffusion region FDC can be disposed on the first surface 2a of substrate 2. A floating diffusion region FD can be a part of the common floating diffusion region FDC. Pixel regions PX in each of pixel groups GRP1 to GRP4 can be electrically connected to each other through the common floating diffusion region FDC.

[0047] In some embodiments, the first isolation structure DTI is disposed on the common floating diffusion region FDC and extends from the second surface 2b toward the first surface 2a. At least in this case, the first isolation structure DTI can be spaced apart from the common floating diffusion region FDC.

[0048] A transfer gate electrode TG may be disposed on the first surface 2a. The transfer gate electrode TG may include a protrusion inserted into the substrate 2. An insulating layer may be interposed between the transfer gate electrode TG and the substrate 2.

[0049] The first to third interlayer insulating layers ILD1, ILD2, and ILD3, and the passivation layer PL may be sequentially formed on the first surface 2a of the substrate 2. In some embodiments, each of the first to third interlayer insulating layers ILD1, ILD2, and ILD3 is formed of or includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. The passivation layer PL may be formed of, for example, silicon nitride or include, for example, silicon nitride.

[0050] The connecting contact CT can be configured to penetrate or extend through the first interlayer insulation layer ILD1. The connecting contact CT can be connected to the common floating diffusion region FDC. The first metal wire M1 and the second metal wire M2 can be disposed in the second interlayer insulation layer ILD2 and the third interlayer insulation layer ILD3, respectively. The connecting contact CT, the first metal wire M1 and the second metal wire M2 can be formed of or include at least one conductive material (e.g., a metallic material).

[0051] An anti-reflective layer 42 may be disposed on the oxide structure 40. The anti-reflective layer 42 may be in contact with the second portion 40b of the oxide structure 40. In some embodiments, the anti-reflective layer 42 is formed of or comprises silicon nitride.

[0052] A grid 45 may be disposed on the first isolation structure DTI and the anti-reflective layer 42. The grid 45 may include a first pattern 44 and a second pattern 46. The first pattern 44 may be an optically opaque material (e.g., titanium). The side surfaces of the second pattern 46 may be aligned with the side surfaces of the first pattern 44. The first pattern 44 and the second pattern 46 can prevent crosstalk between adjacent pixels within a pixel. The second pattern 46 may include an organic material. The second pattern 46 may have a refractive index of about 1.3 or lower.

[0053] Color filters CF1 to CF3 can be disposed on the antireflective layer 42. Color filters CF1 to CF3 may include a photoresist material containing dyes or pigments. Here, color filters CF1 to CF3 disposed in different pixel groups in pixel groups GRP1 to GRP4 may have different colors from each other and may be arranged to form a Bayer pattern.

[0054] In some embodiments, color filters of the same color are disposed on pixel groups GRP1 to GRP4. Here, color filters of different colors may be disposed on another pixel group comprising 16 adjacent pixel regions PX. In this case, the color filters may form a 32×32 Bayer pattern on the photoelectric conversion section PD. It will be understood that various combinations of color filters and their corresponding colors and patterns are within the scope of this disclosure.

[0055] Microlenses ML can be disposed on color filters CF1 to CF3. A second isolation structure CDTI can overlap with microlenses ML along a third direction D3. When measured from the central region of microlenses ML, the first isolation structure DTI can be farther from the central region of microlenses ML than the second isolation structure CDTI (e.g., laterally farther, parallel to surfaces 2a, 2b).

[0056] Figure 5 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 6 It is shown Figure 5 An enlarged cross-sectional view of part "CU2". (Previously referenced) Figures 2 to 4 The described elements may be identified by the same reference numerals without repeating their descriptions.

[0057] Reference Figure 5 and Figure 6An air gap AG can be placed between the second insulating conductive pattern 11 and the oxide structure 40. When viewed in a horizontal or cross-sectional view, the first portion 40a of the oxide structure 40 can be placed, for example, along a first direction D1 and / or a second direction D2 between the air gap AG and the second insulating pattern 13. When viewed in a vertical or cross-sectional view, the air gap AG can be placed, for example, along a third direction D3 between the second insulating conductive pattern 11 and the second portion 40b of the oxide structure 40. The thickness 40aT of the first portion 40a of the oxide structure 40 in the first direction D1 can be in the range of 8 nm to 12 nm. Due to the presence of the air gap AG, light passing through the microlens ML is not refracted, which allows for an increase in the amount of light incident on the photoelectric conversion section PD.

[0058] Therefore, an image sensor may include microlenses and an isolation structure that vertically overlaps the microlenses and includes a conductive pattern. Here, an oxide structure (e.g., Figures 1 to 6 and Figure 11 The oxide structure 40 can be disposed on the conductive pattern of the isolation structure. Therefore, due to the total internal reflection of the oxide structure, light incident through the microlens can enter the photoelectric conversion section in the substrate. This allows for an increase in the amount of light incident on the photoelectric conversion section, and thus, the image sensor can have improved sensitivity and improved optical properties. In some embodiments, the material of the oxide structure (e.g., hafnium oxide or aluminum oxide) can advantageously promote total internal reflection compared to other materials such as polycrystalline silicon or silicon oxide. For example, advantageous optical behavior can be based on the absorption and / or refractive index of the oxide structure.

[0059] Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a cross-sectional view illustrating a process for manufacturing an image sensor according to some embodiments of the present disclosure.

[0060] Reference Figure 1 and Figure 7 A substrate 100 may be provided having a first surface 2a and a second surface 2b opposite to each other. The substrate 100 may have a first conductivity type (e.g., p-type). A device isolation portion STI may be formed on the first surface 2a of the substrate 2. The device isolation portion STI may be formed to define a first active region ACT1 and a second active region ACT2. In some embodiments, the device isolation portion STI is formed by a shallow trench isolation (STI) process.

[0061] A first isolation structure (DTI) and a second isolation structure (CDTI) can be formed on the device isolation section (STI). Pixel groups GRP1 to GRP4 can be separated from each other through the first isolation structure (DTI). The photoelectric conversion section (PD) in each of pixel groups GRP1 to GRP4 can be separated from each other through the second isolation structure (CDTI).

[0062] The first isolation structure DTI may include a first isolation conductive pattern 10, a first isolation insulating pattern 12, and a first gap-filling insulating pattern 14. The second isolation structure CDTI may include a second isolation conductive pattern 11, a second isolation insulating pattern 13, and a second gap-filling insulating pattern 15.

[0063] A well region PW and a photoelectric conversion portion PD can be formed in the substrate 2. Forming the well region PW may include implanting a first impurity into the substrate 2. Forming the photoelectric conversion portion PD may include implanting a second impurity, different from the first impurity, into the substrate 2.

[0064] Reference Figure 8 A gate insulating layer PGI and a pixel gate electrode PG can be formed on the first surface 2a of the substrate 2. Subsequently, a first interlayer insulating layer ILD1 to a third interlayer insulating layer ILD3 and a passivation layer PL can be sequentially formed on the first surface 2a of the substrate 2. Here, a first metal line ML1 and a second metal line ML2 can be formed in the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3, respectively.

[0065] Reference Figure 4 and Figure 9 It can Figure 8 The substrate 2, the first interlayer insulating layer ILD1 to the third interlayer insulating layer ILD3, and the passivation layer PL are reversed. A polishing process can be performed on the second surface 2b of the substrate 2 to expose the top surfaces of the first isolation structure DTI and the second isolation structure CDTI. As a result of the polishing process, the thickness of the substrate 2 on the third direction D3 can be reduced.

[0066] A photoresist pattern PRP can be formed on the second surface 2b. The photoresist pattern PRP can expose the top surface of the second insulating conductive pattern 11. The photoresist pattern PRP can define the area thereon where the first portion 40a of the oxide structure 40 will be formed.

[0067] Next, an etching process can be performed to remove a portion of the second conductive isolation pattern 11. As a result of partially removing the second conductive isolation pattern 11, the height of the second conductive isolation pattern 11 can be reduced. In some embodiments, the depth of removal of the second conductive isolation pattern 11 is in the range of 0.5 μm to 1.5 μm. Afterward, the photoresist pattern PRP can be removed.

[0068] Reference Figure 10 An oxide structure 40 can be formed on the second surface 2b of the substrate 2. Here, the oxide structure 40 can fill the area formed by partially removing the second insulating conductive pattern 11. In some embodiments, the oxide structure 40 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0069] Next, refer to again Figure 2 An antireflective layer 42 can be formed on the oxide structure 40. A first pattern 44 and a second pattern 46 can be sequentially formed on the antireflective layer 42. Color filters CF1 to CF3 can be formed on the antireflective layer 42. Next, microlenses ML can be formed on the color filters CF1 to CF3, thereby enabling the fabrication of an image sensor as described herein.

[0070] Figure 11 This is a plan view illustrating an image sensor according to some embodiments. For the sake of brevity, previous references... Figure 1 The described elements may be identified by the same reference numerals without repeating their descriptions.

[0071] Reference Figure 11 Each of pixel groups GRP1 to GRP4 may not include a common floating diffusion region in its central region. That is, when viewed in a planar view, the second isolation structure CDTI can be placed in the central region of each of pixel groups GRP1 to GRP4. Because no common floating diffusion region is provided, the pixel region PX in each of pixel groups GRP1 to GRP4 can be controlled independently, and the signal generated by the incident light can be processed separately.

[0072] Therefore, an image sensor may include a microlens and an isolation structure that vertically overlaps the microlens and includes a conductive pattern. An oxide structure may be disposed on the conductive pattern of the isolation structure. Thus, due to total internal reflection by the oxide structure, light incident through the microlens can enter the photoelectric conversion section in the substrate. This allows for an increase in the amount of light incident on the photoelectric conversion section, and therefore, the image sensor can have improved sensitivity and improved optical properties.

[0073] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of any claims. Specific features described in the context of individual embodiments of this disclosure can also be implemented in combination within a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, in some cases one or more features from the combination may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0074] While various examples have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. An image sensor comprising: a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a first photoelectric conversion region and a second photoelectric conversion region; a first isolation structure disposed in the substrate between the first photoelectric conversion region and the second photoelectric conversion region; an oxide structure on the first isolation structure; and a microlens on the oxide structure, wherein the first isolation structure overlaps the microlens in a vertical direction, wherein the first isolation structure includes a first isolation conductive pattern, wherein the oxide structure is in contact with the first isolation conductive pattern, and wherein the oxide structure at least partially extends into the first isolation structure.

2. The image sensor of claim 1, wherein, the oxide structure includes at least one of hafnium oxide and aluminum oxide, and wherein the first isolation conductive pattern includes doped polysilicon.

3. The image sensor of claim 1, further comprising: a second isolation structure in the substrate and spaced apart from the first isolation structure in a first direction parallel to the first surface, wherein the second isolation structure includes a second isolation conductive pattern, and wherein a thickness of the first isolation conductive pattern in the vertical direction is less than a thickness of the second isolation conductive pattern in the vertical direction.

4. The image sensor of claim 3, wherein, a top surface of the second isolation conductive pattern is higher than a top surface of the first isolation conductive pattern in the vertical direction, and wherein the top surface of the second isolation conductive pattern is in contact with the oxide structure.

5. The image sensor of claim 3, wherein, a thickness of the first isolation conductive pattern in the vertical direction is 60% to 70% of a thickness of the substrate. 6.The image sensor according to claim 3, further comprising an opaque grid overlapping the second isolation structure in the vertical direction.

7. The image sensor of claim 1, wherein, the first isolation structure includes an isolation insulating pattern interposed between the substrate and the first isolation conductive pattern, and wherein an upper portion of the isolation insulating pattern is arranged to laterally surround the oxide structure.

8. The image sensor of claim 1, wherein, a width of the first isolation conductive pattern decreases as a distance from the microlens decreases. 9.An image sensor comprising: a substrate having a first surface and a second surface opposite to each other, wherein the substrate includes a plurality of photoelectric conversion regions; a first isolation structure and a second isolation structure spaced apart from each other in the substrate and in a first direction parallel to the first surface; an oxide structure on the first isolation structure; and a microlens on the oxide structure, wherein the first isolation structure overlaps the microlens in a vertical direction, wherein the first isolation structure includes a first isolation conductive pattern, wherein the oxide structure includes a first portion and a second portion on the first portion, wherein the first portion is in contact with the first isolation conductive pattern, wherein the second portion extends on the second surface of the substrate, and wherein a thickness of the first portion in the vertical direction is greater than a thickness of the second portion in the vertical direction.

10. The image sensor of claim 9, wherein, A thickness of the first portion of the oxide structure in the vertical direction is in a range of 0.5 pm to 1.5 pm.

11. The image sensor of claim 9, wherein, The second portion is in contact with a second surface of the substrate and a top surface of the second isolation structure.

12. The image sensor of claim 9, wherein, A thickness of the first portion in the vertical direction is in a range of 20% to 30% of a thickness of the substrate.

13. The image sensor of claim 9, wherein, The first isolation structure includes an isolation insulating pattern interposed between the substrate and the first isolation conductive pattern, and wherein the isolation insulating pattern is arranged to surround a lateral surface of the first portion of the oxide structure.

14. The image sensor according to claim 13, further comprising an air gap between the first isolation conductive pattern and the oxide structure in the vertical direction, wherein the first portion of the oxide structure is arranged between the air gap and the isolation insulating pattern in the first direction.

15. The image sensor of claim 14, wherein, A thickness of the oxide structure in the first direction is in a range of 8 nm to 12 nm.

16. An image sensor comprising: a substrate including a first pixel group and a second pixel group adjacent to each other, each of the first pixel group and the second pixel group including a plurality of photoelectric conversion regions; a first isolation structure in the substrate between the first pixel group and the second pixel group; a second isolation structure in the substrate between a first photoelectric conversion region of the first pixel group and a second photoelectric conversion region of the first pixel group and between a first photoelectric conversion region of the second pixel group and a second photoelectric conversion region of the second pixel group; and an oxide structure on the second isolation structure, wherein the first isolation structure includes a first isolation conductive pattern and the second isolation structure includes a second isolation conductive pattern, wherein a thickness of the second isolation conductive pattern in a vertical direction is less than a thickness of the first isolation conductive pattern in the vertical direction, wherein the oxide structure includes a first portion and a second portion protruding from the first portion, wherein the first portion is in contact with the first isolation conductive pattern, wherein the second portion is in contact with the second isolation conductive pattern, and wherein a thickness of the second portion in the vertical direction is in a range of 0.5 pm to 1.5 pm. The first isolation conductive pattern and the second isolation conductive pattern are configured as a common bias line.

17. The image sensor of claim 16, wherein, A bottom surface of the second portion of the oxide structure is lower than a top surface of the first isolation structure.

18. The image sensor of claim 16, wherein, 19. The image sensor according to claim 16, further comprising: an anti-reflection layer on the oxide structure; a color filter on the anti-reflection layer; and a microlens on the color filter. A lateral distance between the first isolation structure and a center of the microlens is greater than a lateral distance between the second isolation structure and the center of the microlens.

20. The image sensor of claim 19, wherein, ​

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