Check node data compression in storage system

Abstract

The invention relates to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a data block, and determines check node data indicating a likelihood value that the subset of codeword symbols is an error. A set of data bits is determined based on a combination of values of data items of the check node data to uniquely identify the combination of values among a set of selected combinations of values according to a predefined relationship. The electronic device stores, in a storage block, the set of data bits representing the data item of the check node data for the check node. Each data item requires more data bits than the data bits in the set of data bits to represent all possible values of the respective data item.

Description

[0001] Related Applications

[0002] This application is a continuation of and claims priority to U.S. Patent Application No. 18 / 221,819, filed July 13, 2023, entitled “Check Node Data Compression in Memory Systems,” U.S. Patent Application No. 18 / 236,849, filed August 22, 2023, entitled “Check Node Data Compression in Memory Systems,” and U.S. Patent Application No. 18 / 236,861, filed August 22, 2023, entitled “Data Structure Reconfiguration for Low Density Parity Checks (LDPCs) in Memory Systems,” each of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates generally to memory management, including but not limited to methods, systems, and non-transitory computer-readable storage media for compressing check node data applied in data verification in a memory system (e.g., solid state drive). BACKGROUND

[0004] Memory is used in computer systems to store instructions and data. The data is processed by one or more processors of the computer system according to the instructions stored in the memory. Multiple memory units are used in different parts of the computer system to provide different functionalities. Specifically, a computer system includes a non-volatile memory that serves as a secondary storage to hold data stored thereon in the event the computer system is decoupled from a power source. Examples of secondary storage include, but are not limited to, a hard disk drive (HDD) and a solid state drive (SSD). Min-sum is a popular algorithm used to identify and / or correct bit errors of user data stored in memory with integrity data (e.g., low density parity check (LDPC) codes). When a storage controller identifies or corrects bit errors based on the LDPC codes during an integrity check process, the storage controller generates check node data and temporarily stores it in a register. It would be beneficial to compress the check node data used in the integrity check process to reduce expensive register usage and improve memory access performance. SUMMARY

[0005] Various embodiments of the present application relate to methods, systems, devices, non-transitory computer-readable storage media for compressing check node data temporarily stored in registers during an integrity check process implemented by a storage system (e.g., an SSD). Check node data is applied to identify or correct bit errors in code symbols extracted from a storage system, and the code symbols, including integrity data, such as an LDPC code, represent a type of error correction code used to provide error correction for data storage errors in a storage system. In an example, the min-sum is a popular algorithm used to correct bit errors in code symbols stored in a storage system. LDPC decoding is typically visualized as a bipartite Tanner graph with variable nodes and check nodes, and messages are exchanged between variable nodes and check nodes on the Tanner graph during an integrity check process. In some implementations, memory (e.g., registers) is allocated for each check node to store a plurality of data items summarizing information of a set of variable nodes connected to the respective check node. Various embodiments of the present application relate to compressing check node data generated and temporarily stored during an integrity check process, thereby reducing expensive register usage and improving memory access performance.

[0006] In one aspect, a method for compressing check node data on a storage system (e.g., a solid state drive) is implemented at an electronic device. The method includes identifying a plurality of check nodes associated with a data block. Each check node corresponds to a subset of code symbols in the data block and has respective check node data indicating a likelihood value that the subset of code symbols is erroneous. The method also includes, for each check node in a subset of check nodes, identifying a set of most significant bits (MSBs) of one or more data items in the respective check node data. The method also includes determining a set of data bits based on the plurality of sets of MSBs of the subset of check nodes. The plurality of sets of MSBs includes the set of MSBs of one or more data items in the respective check node data of each check node in the subset of check nodes. The method also includes storing the set of data bits in a memory block (e.g., a register file, one or more registers) allocated to the plurality of check nodes in association with the subset of check nodes. The plurality of sets of MSBs collectively has a first number of bits, and the set of data bits has a second number of bits. The first number is greater than the second number.

[0007] In another aspect, a method for compressing check node data on a storage system (e.g., a solid state drive) is implemented at an electronic device. The method includes identifying a check node corresponding to a subset of code symbols in a data block, and determining check node data including a plurality of data items. The check node data indicates a likelihood value for the subset of code symbols being erroneous. The method also includes determining a set of data bits based on a value combination of the plurality of data items. The set of data bits uniquely identifies the value combination among a set of selected value combinations according to a predefined relationship. The method also includes storing the set of data bits representing the plurality of data items of the check node data of the check node in a storage block. Each of the plurality of data items requires at least a first number of data bits to represent all possible values of the respective data item, and the set of data bits has a second number of data bits. The second number is less than a sum of the first number of each of the plurality of data items.

[0008] In yet another aspect, a method for adaptively storing check node data on a storage system (e.g., a solid state drive) is implemented at an electronic device. The method includes obtaining a data block corresponding to a plurality of first check nodes. Each first check node corresponds to a first subset of code symbols of the data block and has respective first check node data indicating a likelihood value for the first subset of code symbols being erroneous. The method also includes identifying a storage block allocated for storing the first check node data of the plurality of first check nodes, and re-grouping data bits of the data block to form a plurality of second check nodes. Each second check node corresponds to a second subset of code symbols of the data block and has respective second check node data indicating a likelihood value for the second subset of code symbols being erroneous. The method also includes reconfiguring the storage block to store the second check node data of the plurality of second check nodes. The plurality of second check nodes has a number of check nodes different from the plurality of first check nodes.

[0009] Some embodiments of the application include an electronic device that includes one or more processors and memory storing instructions thereon that, when executed by the one or more processors, cause the processors to perform any of the above-described methods on a storage system (e.g., a solid state drive).

[0010] Some embodiments include a non-transitory computer-readable storage medium storing one or more programs. The one or more programs comprise instructions, which when executed by one or more processors, cause the processors to perform any of the above-described methods on a storage system (e.g., a solid state drive).

[0011] In some embodiments, the above-described methods for managing LDPC-based check node data, electronic devices, or non-transitory computer-readable storage media are also used for communication (e.g., wireless communication using 5G or Wi-Fi technology, satellite communication, Ethernet communication, and communication via fiber optic networks).

[0012] Reference to these illustrative embodiments and implementations is not intended to limit or define the disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the DETAILED DESCRIPTION and further description is provided. BRIEF DESCRIPTION OF DRAWINGS

[0013] For a better understanding of the various described implementations, reference should be made to the Detailed Description below, in connection with the following drawings, in which like references numerals refer to corresponding parts throughout the figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the implementations.

[0014] Figure 1 is a block diagram of example system modules in a typical electronic device according to some embodiments.

[0015] Figure 2 is a block diagram of a storage system of an example electronic device having one or more memory access queues according to some embodiments.

[0016] Figure 3 is a block diagram of an example integrity check system of a storage system for processing codewords according to some embodiments.

[0017] Figure 4A is a Tanner graph for implementing LDPC encoding using check nodes and variable nodes according to some embodiments.

[0018] Figure 4B is a simplified Tanner graph having a single check node coupled to a set of variable nodes according to some embodiments.

[0019] Figure 5A is a schematic diagram of a sequence of check node operations implemented to determine check node data for a check node during LDPC decoding according to some embodiments.

[0020] Figure 5B is a schematic diagram of a sequence of variable node operations implemented to determine variable node data for a variable node during LDPC decoding according to some embodiments.

[0021] Figure 6 is an example data structure for check node data of a set of check nodes having one or more data compression schemes according to some embodiments.

[0022] Figure 7ATwo tables are shown, showing possible combinations of two data items of the check node data for each check node, according to some embodiments. Figure 7B is an example data structure of check node data for a check node subset with an index-based compression scheme, according to some embodiments, and Figure 7A is an example data structure of check node data for a check node subset with an index-based compression scheme, according to some embodiments, and Figure 7C The original check node data of the check node subset is compared to the corresponding compressed check node data, according to some embodiments.

[0023] Figure 8A is an example data structure of check node data for a check node subset with an index-based compression scheme, according to some embodiments, and Figure 8B The original check node data of the check node subset is compared to the corresponding compressed check node data, according to some embodiments.

[0024] Figure 9 is a flowchart of an example method for compressing check node data of an electronic device, according to some embodiments.

[0025] Figure 10 is a data map showing example value combinations of two likelihood value data items of the check node data for each check node, according to some embodiments.

[0026] Figure 11 A lookup table and a formula are shown that are applied to relate value combinations of two data items of the check node data to a set of data bits, according to some embodiments.

[0027] Figure 12 is another example data map showing example value combinations of two likelihood value data items of the check node data for each check node, according to some embodiments.

[0028] Figures 13-16 is an example data map showing different lossy value combinations of two data items of the check node data for each check node, according to some embodiments.

[0029] Figure 17 is an example data structure of check node data for a check node with one or more data compression schemes, according to some embodiments.

[0030] Figure 18 is a flowchart of an example method for compressing check node data of an electronic device, according to some embodiments.

[0031] Figure 19 is a diagram showing two example data structures of check node data temporarily stored in a memory block, according to some embodiments.

[0032] Figure 20is a flowchart of an example method for adaptively storing check node data in an electronic device, according to some embodiments.

[0033] In the various views of the drawings, like reference numerals refer to corresponding parts throughout. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to specific implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description of embodiments, numerous specific details are set forth in order to provide a thorough understanding of the subject matter presented herein. However, it will be apparent to one of ordinary skill in the art that the subject matter presented can be practiced without these specific details. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented can be implemented on many types of electronic devices with digital video functionality.

[0035] This application relates to compressing check node data temporarily stored in registers during an integrity check process implemented by a storage system (e.g., an SSD). The check node data is applied to identify or correct bit errors in code symbols extracted from the storage system, and the code symbols contain integrity data, e.g., an LDPC code, which represents a type of error correcting code used to provide error correction for data storage errors in the storage system. In an example, the sum-product algorithm is a popular algorithm used to correct bit errors in an LDPC code. LDPC decoding is typically visualized as a Tanner graph with variable nodes and check nodes, and messages are exchanged between the variable nodes and check nodes on the Tanner graph during the integrity check process. In some implementations, memory (e.g., registers) is allocated for each check node to store a plurality of data items summarizing information of a set of variable nodes connected to the respective check node. The check node data generated and temporarily stored during the integrity check process is compressed, thereby reducing expensive register usage and improving memory access performance.

[0036] In an example, each check node stores a symbol, a minimum message (Minl) magnitude, a second minimum message (Min2) magnitude, an index (Minl index) identifying the variable node that provided the minimum message, and optionally a Min2 index (Min2 index) identifying the variable node that provided the second minimum message. The Minl magnitude is always less than or equal to the Min2 magnitude, resulting in a method for data compression. Furthermore, in some embodiments, the Minl index and the Min2 index are limited to a maximum check node degree (i.e., the number of variable nodes coupled to each check node) that is not a power of two, and some index values are never used, which is used for data compression. In some embodiments, the Min2 magnitude and the Min2 index are less important than the Minl magnitude and the Minl index, so some bits can be truncated without causing a significant negative impact. In some embodiments, the decoder is reused for multiple matrices. For example, a smaller matrix with a higher check node degree is reconfigured in a commutative manner to a larger matrix with a smaller check node degree. Optionally, some unused storage space in the larger matrix is used to increase the Minl index and the Min2 index size of the small matrix. Conversely, decreasing the index size of the small matrix increases the number of check nodes stored for the large matrix.

[0037] Storage system of an electronic device

[0038] Figure 1 is a block diagram of an example system module 100 in a typical electronic device in accordance with some embodiments. The system module 100 in an electronic device includes at least a processor module 102, a storage module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces such as a network interface 108, and one or more communication buses 140 for interconnecting these components. In some embodiments, the I / O controller 106 enables the processor module 102 to communicate with I / O devices (e.g., a keyboard, a mouse, or a touchpad) via a universal serial bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each of which enables the electronic device to exchange data with external sources (e.g., a server or another electronic device). In some embodiments, the communication buses 140 include circuitry (sometimes called a chipset) that interconnects and controls communications between various system components included in the system module 100.

[0039] In some embodiments, the storage module 104 includes a high-speed random access memory such as DRAM, static random access memory (SRAM), double data rate (DDR) dynamic random access memory (RAM), or other random access solid state storage devices. In some embodiments, the storage module 104 includes non-volatile memory such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. In some embodiments, the storage module 104, or alternatively a non-volatile storage device within the storage module 104, includes a non-transitory computer- readable storage medium. In some embodiments, a storage slot is reserved on the system module 100 for receiving the storage module 104. Once inserted into the storage slot, the storage module 104 is integrated into the system module 100.

[0040] In some embodiments, the system module 100 also includes one or more components selected from a storage controller 110, an SSD 112, a hard disk drive (HDD) 114, a power management integrated circuit (PMIC) 118, a graphics module 120, and a sound module 122. The storage controller 110 is configured to control communications between the processor module 102 and storage components (including the storage module 104) in the electronic device. The SSD 112 is configured as an application integrated circuit component to store data in the electronic device, and in many embodiments, is based on a NAND or NOR memory configuration. The HDD 114 is a conventional data storage device for storing and retrieving digital information based on electromechanical magnetic disks. The power connector 116 is electrically coupled to receive an external power source. The PMIC 118 is configured to modulate the received external power source to various components or circuits within the electronic device (e.g., the processor module 102) required at other desired DC voltage levels, such as 5 V, 3.3 V, or 1.8 V. The graphics module 120 is configured to generate an output image feed to one or more display devices according to a desired image / video format of the one or more display devices. The sound module 122 is configured to facilitate input and output of audio signals to and from the electronic device under control of a computer program.

[0041] It should be noted that the communication bus 140 also interconnects and controls communications between various system components including the components 110-122.

[0042] Furthermore, as is known to those skilled in the art, other non-transitory computer-readable storage media can be used in place of, or in addition to, the non-transitory computer-readable storage media in the storage module 104 and the SSD 112 as new data storage technologies are developed for storing information in non-transitory computer-readable storage media. These new non-transitory computer-readable storage media include, but are not limited to, storage media fabricated with biological materials, nanowires, carbon nanotubes, and / or with single molecules, although the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0043] Some embodiments of the present application relate to an integrity check process implemented by a storage system (e.g., SSD 112, storage module 104, hard drive 114, storage controller 110) storing code symbols containing integrity data (e.g., LDPC codes). The integrity check process is also referred to as a decoding process, and is visualized by a Tanner graph having variable nodes and check nodes. The variable nodes correspond to code symbols extracted from the storage system. Each check node corresponds to a distinct set of variable nodes, and has check node data configured to identify or correct bit errors in the code symbols corresponding to the distinct set of variable nodes. Specifically, messages are exchanged between the variable nodes and the check nodes on the Tanner graph to update the check node data until bit errors are identified and corrected in the code symbols. During the integrity check process, the check node data is generated and temporarily stored in registers or register files of the storage system. In some embodiments, the check node data of two or more check nodes is jointly compressed to save one or more bits in the registers or register files, for example, in a lossless manner. In some embodiments, two or more data items of the check node data of a single check node are jointly compressed to save one or more bits in the registers or register files, for example, in a lossless or lossy manner. In some embodiments, storage space is reconfigured to store the check node data for two sets of distinct numbers of check nodes, and the data structure of the check node data is adjusted when switching the check node data between two data structures corresponding to the two sets of distinct numbers of check nodes. In these ways, the register space allocated to the registers or register files is reduced, and the storage space of the storage system is effectively utilized with little or no impact on the performance of the data integrity check process.

[0044] Figure 2 is a block diagram of a storage system 200 of an example electronic device having one or more memory access queues according to some embodiments. The storage system 200 is coupled to a host device 220 (e.g., processor module 102 in FIG. 1), and is configured to store instructions and data for an extended period of time, for example, when the electronic device is in hibernation, inactive, or turned off. The host device 220 is configured to access the instructions and data stored in the storage system 200, and process the instructions and data to run an operating system and execute user applications. The storage system 200 further includes a controller 202 and a plurality of storage channels 204. Each storage channel 204 includes a plurality of storage units. The controller 202 is configured to execute firmware-level software to bridge the plurality of storage channels 204 to the host device 220. Figure 1

[0045] ​Each storage channel 204 is contained on one or more storage packages 206 (e.g., two storage chips, two storage dies). In an example, each storage package 206 corresponds to a storage die. Each storage package 206 contains a plurality of storage planes 208, and each storage plane 208 further contains a plurality of storage pages 210. Each storage page 210 contains an ordered set of storage cells, and each storage cell is identified by a respective physical address. In some embodiments, the storage system 200 contains single-level cell (SLC) NAND flash chips, and each storage cell stores a single data bit. In some embodiments, the storage system 200 contains multi-level cell (MLC) NAND flash chips, and each storage cell of a MLC NAND flash chip stores 2 data bits. In an example, each storage cell of a triple-level cell (TLC) NAND flash chip stores 3 data bits. In another example, each storage cell of a quad-level cell (QLC) NAND flash chip stores 4 data bits. In yet another example, each storage cell of a penta-level cell (PLC) NAND flash chip stores 5 data bits. In some embodiments, each storage cell can store any suitable number of data bits. An SSD with SLC NAND flash chips runs faster, is more reliable, and has a longer lifespan than an SSD with non-SLC NAND flash chips (e.g., MLC SSD, TLC SSD, QLC SSD, PLC SSD), but has a lower device density and is more expensive.

[0046] Each storage channel 204 is coupled to a respective channel controller 214 configured to control internal and external requests to access storage cells in the respective storage channel 204. In some embodiments, each storage package 206 (e.g., each storage die) corresponds to a respective queue 216 of memory access requests. In some embodiments, each storage channel 204 corresponds to a respective queue 216 of memory access requests. Further, in some embodiments, each storage channel 204 corresponds to a distinct and different queue 216 of memory access requests. In some embodiments, a subset (less than all) of the plurality of storage channels 204 correspond to a distinct queue 216 of memory access requests. In some embodiments, all of the plurality of storage channels 204 of the storage system 200 correspond to a single queue 216 of memory access requests. Each memory access request is optionally received from within the storage system 200 to manage the respective storage channel 204, or from outside the host device 220 to write or read data stored in the respective channel 204. Specifically, each memory access request includes one of: a system write request received from the storage system 200 to write to the respective storage channel 204, a system read request received from the storage system 200 to read from the respective storage channel 204, a host write request originating from the host device 220 to write to the respective storage channel 204, and a host read request received from the host device 220 to read from the respective storage channel 204. It is noted that system read requests (also referred to as background read requests or non-host read requests) and system write requests are sent by the storage controller to implement internal memory management functions including, but not limited to, garbage collection, wear leveling, read disturb mitigation, memory snapshot capture, memory mirroring, caching, and memory sparing.

[0047] In some embodiments, in addition to channel controller 214, controller 202 also includes local storage processor 218, host interface controller 222, SRAM buffer 224, and DRAM controller 226. Local storage processor 218 accesses multiple storage channels 204 based on one or more queues 216 of memory access requests. In some embodiments, local storage processor 218 writes to and reads from the multiple storage channels 204 on a block-by-block basis. Data from one or more storage blocks is jointly written to or read from multiple channels. Data in the same storage block is not written simultaneously through more than one operation. Each storage block optionally corresponds to one or more storage pages. In one example, each storage block to be jointly written to or read from multiple storage channels 204 has a size of 16 KB (e.g., one storage page). In another example, each storage block to be jointly written to or read from multiple storage channels 204 has a size of 64 KB (e.g., four storage pages). In some embodiments, each page has 16 Kb of user data and 2 KB of metadata. In addition, for each of the system read operation, host read operation, system write operation, and host write operation, the number of storage blocks to be accessed and the size of each storage block are configurable.

[0048] In some embodiments, the local storage processor 218 stores data to be written to or read from each storage block in the plurality of storage channels 204 in an SRAM buffer 224 of the controller 202. Alternatively, in some embodiments, the local storage processor 218 stores data to be written to or read from each storage block in the plurality of storage channels 204 in a DRAM buffer 228, which is located in the storage system 200. Alternatively, in some embodiments, the local storage processor 218 stores data to be written to or read from each storage block in the plurality of storage channels 204 in a DRAM buffer 228, which is configured by the processor module 102 (…). Figure 1 The main memory used. The local storage processor 218 of controller 202 accesses the DRAM buffer 228 via host interface controller 222.

[0049] In some embodiments, data in multiple storage channels 204 are grouped into coded blocks, and each coded block is called a codeword. Figure 3 (302). For example, each codeword contains n The units digit, among which k The units digit corresponds to the user data, and ( n – k) corresponds to integrity data of the user data, where k and n is a positive integer. In some embodiments, the storage system 200 includes an integrity engine 230 (e.g., an LDPC engine) and registers 232, which include a plurality of registers or SRAM cells or flip-flops and are coupled to the integrity engine 230. The integrity engine 230 is coupled to the storage channels 204 via the channel controllers 214 and the SRAM buffers 224. Specifically, in some embodiments, the integrity engine 230 has a data path connection to the SRAM buffers 224, which are further connected to the channel controllers 214 via a data path controlled by the local storage processor 218. The integrity engine 230 is configured to verify data integrity of each encoded block of the storage channels 204 using variable nodes and check nodes, and exchange messages between the variable nodes and the check nodes during the integrity verification process. A subset of these messages are selected and temporarily stored in the registers 232 as variable node data or check node data.

[0050] Various implementations of the present application relate to compressing check node data temporarily stored in the registers 232 during the integrity verification process implemented by the storage system 200 (e.g., an SSD). In some embodiments, the check node data of a set of check nodes is jointly compressed by the integrity engine 230 to save one or more bits in the registers or register banks or SRAM cells or flip-flops, e.g., in a lossless manner. In some embodiments, a plurality of data items of the check node data of a single check node is jointly compressed by the integrity engine 230 to save one or more bits in the registers or register banks or SRAM cells or flip-flops, e.g., in a lossless or lossy manner. In some embodiments, the storage space is reconfigured to store the check node data for two different numbers of check nodes, and the data structure of the check node data is adjusted when switching the check node data between the two different numbers of check nodes. In these ways, the storage space allocated to the registers, register banks, SRAM cells, and / or flip-flops is reduced, and the storage space of the storage system is effectively utilized with little or no impact on the performance of the data integrity verification process.

[0051] Data integrity check based on low density parity check (LDPC) codes

[0052] Figure 3 is a block diagram of an example integrity verification system 300 of the storage system 200 for processing the codeword 302 according to some embodiments. The integrity verification system 300 includes a plurality of storage channels 204, an integrity engine 230 (e.g., an LDPC engine), and registers 232. The storage in the storage system 200 (e.g., an SSD) is organized into a plurality of storage channels 204, each of which is configured to store a plurality of encoded blocks of data. Each encoded block of data is organized into a plurality of pages, each of which is organized into a plurality of sectors. Each sector is organized into a plurality of data sectors and a plurality of parity sectors. The data sectors store user data, and the parity sectors store parity data corresponding to the user data. The parity data is used to verify the integrity of the user data. Figure 2Data in the storage channel 204 is grouped into code blocks, and each code block is referred to as a codeword 302. Each codeword 302 also contains n k n k k n

[0053] In some embodiments, the integrity engine 230 also contains one or more of a compression module 304, an error-correcting code (ECC) encoder 306, a scrambler 308, a descrambler 310, an ECC decoder 312, and a decompression module 314. The compression module 304 obtains the user data 302D and processes (e.g., compresses, encrypts) the user data 302D. The ECC encoder 306 obtains the user data 302D, optionally processed by the compression module 304, and applies a parity data generator matrix G (316) to the user data 302D to encode the codeword 302. The matrix G (316) has k n rows and n columns. The systematic form of the matrix G contains an identity matrix I configured to preserve the user data 302D within the codeword 302 and a parity matrix P configured to generate the integrity data 302I from the user data 302D. In some embodiments, the matrix G (316) is not unique and contains a set of basis vectors of a vector space of valid codewords 302. The scrambler 308 obtains the codeword 302 containing n n

[0054] ​​​​​​​​​During decoding, scrambled codeword 318 is extracted from storage channel 204 of storage system 200. Descrambler 310 recovers codeword 302' from scrambled codeword 318, and ECC decoder 312 verifies the validity of the recovered codeword 302' and corrects erroneous bits in the recovered codeword 302', thereby providing a valid codeword 302 containing valid user data 302D. In some cases, bits in the recovered codeword 302' are "1", matching the corresponding bit ("1") in codeword 302. The bits in the recovered codeword 302' are correct. Conversely, in some cases, bits in the recovered codeword 302' are "1", which do not match the corresponding bit ("0") in codeword 302. The bits in the recovered codeword 302' are incorrect. In some cases, bits in the recovered codeword 302' are "0", matching the corresponding bit ("0") in codeword 302. The bits in the recovered codeword 302' are correct. Conversely, in some cases, the recovered codeword 302' has a bit "0", which does not match the corresponding bit ("1") of codeword 302. The recovered codeword 302' has an incorrect bit.

[0055] In some embodiments, the decompression module 314 obtains user data 302D and processes (e.g., decompresses, decrypts) the user data 302D. In some embodiments, for integrity verification, the ECC decoder 312 applies a parity check matrix H (320) to the recovered codeword 302' to generate a check vector. S The parity check matrix H(320) contains the corresponding parity check matrix H(320) to... n – k Parity check equations n – k Rows and corresponding to n Each code character position n The recovered codeword 302' and the check vector. S The relationship is represented as follows: S=yH T (1) in y It is the recovered codeword '302'. In some embodiments, based on the determined checksum S If the parity is equal to 0, the ECC decoder 312 determines that all parity equations associated with the parity check matrix H are satisfied, and the recovered codeword 302' is valid. Conversely, if the parity is determined to be non-zero, the ECC decoder 312 determines that at least one parity equation associated with the parity check matrix H is not satisfied, and the recovered codeword 302' is invalid. Alternatively, in some embodiments, the ECC decoder 312 is used to solve the following equations: S=eH T (2) in eThis is the error vector. The verification sub-vector. S It is the error vector e The combination with the valid codeword 302. Assume the check vector... S and parity check matrix H Given that, ECC decoder 312 solves equation (2) to obtain the error vector. e It also identifies the error bits in the recovered codeword 302'.

[0056] Figure 4A This is a Tanner diagram 400, according to some embodiments, applied to LDPC encoding using verification node 402 and variable node 404. Verification is performed based on codewords stored in storage system 200. Figure 2 The data in ) . Each codeword 302 contains n 1 data bit, of which k Each data bit is user data 302D, and n - k Each data bit is the integrity data 302I of user data 302D, in which... k and n It is a positive integer. In some embodiments, a parity check matrix H(320) is applied during integrity verification without distinguishing between user data 302D and integrity data 302I. The parity check matrix H(320) contains corresponding to n – k Parity check equations n – k Rows and corresponding to n Each code character position n Column, in which k and n It is a positive integer. Each parity check equation is combined with the corresponding... n Each codeword (also called a code character) corresponds to a string of codewords, and thus to a string connected to a code character. n A subset or all of the check nodes 402 of the variable nodes 404. In some embodiments, in the parity check matrix H (320) of the row corresponding to the check node 402, n Only in the individual code position j For each codeword bit corresponding to 1, where j It is less than n The integer, and the verification node 402 is connected to j There are 404 variable nodes. In some embodiments, each check node 402 is connected to the same number of variable nodes 404 (e.g., ...). j (Number of variable nodes 404). Alternatively, in some embodiments, each verification node 402 is connected to a corresponding number of variable nodes 404, and at least two verification nodes 402 are connected to different numbers of variable nodes 404.

[0057] Reference Figure 4A In this example, the codeword 302 has 10 code symbols (also referred to as codeword bits). Five parity equations are applied to integrity check the codeword 302, and each parity equation is applied to a set of four code symbols j 4 Thus, the Tanner graph 400 contains five check nodes 402 (f0-f4), and each check node 402 is connected to four respective variable nodes 404, each corresponding to a distinct set of four code symbols of the codeword 302.

[0058] In some embodiments, the ECC decoder 312 solves the equations (2) to obtain an error vector e and identifies one or more error bits in the codeword 302 through an iterative integrity check process. Messages are exchanged between the variable nodes 404 and the check nodes 402 on the Tanner graph 400 until one or more error bits are identified or corrected in the codeword 302. Each variable node 404 is assigned initial variable node data. In some embodiments, the initial variable node data includes log-likelihood ratios (LLRs) determined based on data measured when adjusting a read reference voltage for the storage system 200. Each check node 402 is connected to a set of variable nodes 404 and receives messages from the set of variable nodes 404 that include the initial variable node data. For each check node 402, check node data is determined based on the initial variable node data of the set of variable nodes 404 and indicates a likelihood value that the set of code symbols corresponding to the set of variable nodes 404 is erroneous. Conversely, each variable node 404 is also connected to a set of check nodes 402 on the Tanner graph 400 and receives messages from the set of check nodes 402 that include the check node data. For each variable node 404, the variable node data is updated based on the check node data of the set of variable nodes 404. In this way, messages are exchanged between the check nodes 402 and the variable nodes 404 until an integrity check requirement is satisfied and one or more error bits are identified or corrected based on the variable node data or the check node data. In some embodiments, the integrity check requirement is satisfied when the symbol 424 is 0 for all check nodes 402.

[0059] Figure 4B is a simplified Tanner graph 420 having a single check node 402 coupled to a set of variable nodes 404 according to some embodiments. The check node 402 receives variable-check node message data j from the v 1, v 2, v 3, … v j ​,in j Also known as the degree of the check node d c After performing the check node update based on the minimum sum algorithm, check node 402 sends... d c Each variable node sends a 404 checksum - variable node message data. u 1 、u 2 、u 3, ... u j .related k The detailed information of the verification node update calculation is shown below, where k It is the range [1, d c Integers within ]:

[0060] Min1 and Min2 correspond to the two variable nodes 404 with the smallest and second smallest variable-verification node message amplitudes, respectively. Verification node data 422 includes a sign bit 424, a first likelihood value data item 426 (Min1 amplitude), a second likelihood value data item 428 (Min2 amplitude), and a first index data item 430 (Min1 index). According to equation (4), based on the variable-verification node message data from the variable node set 404 (… v 1 – v m The sign bit 424 is generated by the symbol of the variable node set 404. In other words, the sign bit 424 is a combination of the signs of the corresponding likelihood value data items of the subset of code symbols corresponding to the variable node set 404. The first likelihood value data item 426 and the second likelihood value data item 428 respectively contain the magnitudes of the smallest variable-check node message data (Min1) and the second smallest variable-check node message data (Min2) of the variable node set 404. The first index data item 430 identifies a variable node in the variable node set 424 that corresponds to the first likelihood value data item 426. In some embodiments, the check node data 422 further includes a second index data item 432, which identifies a second variable node in the variable node set 424 that corresponds to the second likelihood value data item 428.

[0061] Figure 5A This is a schematic diagram of a sequence of check node operations 500 implemented according to some embodiments to determine check node data of check node 402 during LDPC decoding. LDPC decoding is performed based on a minimum sum method. Integrity engine 230 ( Figure 2Multiple arithmetic units and registers 232 are organized to implement instructions corresponding to the minimum sum method without frequent interaction with the local memory processor 218. Specifically, each check node 402 corresponds to a combination of corresponding... n The parity check equation for each code character (also called a codeword bit) is connected to... n A subset of variable nodes 404. In some embodiments, n Only in the code character symbol j The individual code character is associated with the non-zero coefficient in the parity check equation, and check node 402 is connected to j There are 404 variable nodes. For each check node 402, multiple arithmetic units include those coupled to register 232 ( Figure 2 The comparator arithmetic unit 502 in the trigger 504 of the () is connected to the check node 402. j A subset of variable nodes 404 receives variable-verification node message data and verification node data 422, and determines that they correspond to... j The first likelihood value data item 426 and the second likelihood value data item 428 of the minimum variable-verification node message data (Min1) and the second smallest variable-verification node message data (Min2) of the set of variable nodes 404. The first likelihood value data item 426 and the second likelihood value data item 428 are stored in the flip-flop 504 of register 232. In some embodiments, from j The variable-check node message data for each variable node in the set of variable nodes 404 contains an LLR determined based on data measured when adjusting the read reference voltage for the storage system 200.

[0062] Figure 5Bis a schematic diagram of check node and variable node operations 540 implemented as a sequence of operations during LDPC decoding to determine variable-check node message data from variable nodes 404 according to some embodiments. For each variable node 404, a plurality of arithmetic units organized by integrity engine 230 includes a sign operator 506, a multiplexer 508, a combiner 510, a summation operator 512, an index identifier 514, and one or more random access memories (RAMs) 516. RAMs 516 temporarily store data involved in check node and variable node operations 540. In some embodiments, registers 232 also include RAMs 516 associated with these check node and variable node operations 540. Each variable node 404 is connected to a check node set 402 and is applied in a set of parity check equations corresponding to check node set 402. One check node in check node set 402 corresponds to check node data stored in a flip-flop 504 and includes a sign bit 424, a first likelihood value data item 426, a second likelihood value data item 428, and a first index data item 430. Sign operator 506 combines a previous variable-check node message data sign stored in RAM 516A with sign bit 424 to form an LLR sign 518. Index identifier 514 compares an index of variable node 404 k (which uniquely identifies j one variable node 404 connected to one check node 402 among a plurality of variable nodes) with first index data item 430. Based on the comparison result, multiplexer 508 selects one of likelihood value data items 426 and 428 as a likelihood value data item 520, and combiner 510 generates a signed LLR data item 522 from check node 402 to variable node 404 based on LLR sign 518 and likelihood value data item 520. Specifically, in some embodiments, multiplexer 508 selects second likelihood value data item 428 as likelihood value data item 520 according to a determination that the index of variable node 404 is k equal to first index data item 430. Conversely, in some embodiments, multiplexer 508 selects first likelihood value data item 426 as likelihood value data item 520 according to a determination that the index of variable node 404 is k not equal to first index data item 430.

[0063] The summator 512 combines the intrinsic LLR data stored in RAM 516B with the LLR data item 522 of the check node set 402 to update the variable node data associated with the variable node 404. In some embodiments, the intrinsic LLR data corresponds to the initial variable node data of each variable node 404 associated with the corresponding codeword symbol of codeword 302. The intrinsic LLR data is determined based on a log-likelihood ratio (LLR) approximated as follows: (6) in p (|) represents the probability of a combination of data values. x It is the value stored for the corresponding code character, and y This is the correct value for the corresponding code symbol. The intrinsic LLR data is determined based on data measured when adjusting the read reference voltage for storage system 200.

[0064] During LDPC decoding, the integrity engine 230 relies on register 232, which contains an array of registers, to temporarily store the parity node data associated with each parity node 402. The more parity nodes 402 there are, the larger register 232 becomes. The larger the size of the parity node data for each parity node 402, the larger register 232 becomes. Register 232 operates at high speed and allows the integrity engine 230 or the local storage processor 218 to directly access and manipulate the data stored in register 232 within one or more clock cycles. Register 232 is expensive. For these reasons, it would be beneficial to compress the parity node data generated and temporarily stored during the integrity verification process (e.g., LDPC decoding) to reduce expensive register usage and improve memory access performance.

[0065] Joint compression of check node data of multiple check nodes

[0066] Figure 6 An example data structure 600 of check node data, comprising a set 402 of check nodes having one or more data compression schemes according to some embodiments, is shown. Data stored in storage system 200 is verified on a codeword basis. Each codeword 302 contains… n 1 data bit, of which k Each data bit is user data 302D, and n - k Each data bit is integrity data 302I generated based on user data 302D, where... k and n It is a positive integer. Use n - k There are 302 parity check equations. Each parity check equation combination has a total of... n Each code character position jEach of the four distinct codeword bits corresponds to a check node 402, which is coupled to... n 404 variable nodes j A set of distinct variable nodes. In some embodiments, the set of check nodes 402 includes a plurality of check nodes 402 associated with data blocks stored in the storage system 200. Each check node 402 is associated with a subset of code symbols in the data block (e.g., j Each codeword corresponds to a specific codeword and has corresponding check node data 422, indicating that the subset of codeword characters represents the likelihood value of an error.

[0067] In the example, the data block corresponds to n - k A parity check equation and n - k There are check nodes 402-1, 402-2, ..., and 402-nk. Integrity engine 230 creates check node data 422-1, 422-2, ..., and 422-nk. For each check node, the corresponding check node data 422 contains one or more data items, such as a sign bit 424, a first likelihood value data item 426, a second likelihood value data item 428, and a first index data item 430, as determined based on the minimum sum method (in equations (3)-(5)). Each data item of check node data 422 has a corresponding number of bits. For example, for each check node 402, the sign bit 424 has 1 bit. The first likelihood value data item 426 has 2-5 bits, as does the second likelihood value data item 428. The first index data item 430 has 6-7 bits, as does the second index data item 432 (if any). Each of the one or more data items has one or more corresponding most significant bits (MSBs). For example, the sign bit 424 has at most one MSB. Each of the likelihood data items 426 and 428 has one or more corresponding MSBs, for example, 1 MSB, 2 MSB, or 3 MSB. Each index data item 430 or 432 has one or more corresponding MSBs, for example, 1 MSB, 2 MSB, or 3 MSB.

[0068] n - k Each verification node 402-1, 402-2, ..., and 402-nk contains data that is compressed and jointly stored in the storage block (e.g., ...). Figure 2corresponding to a subset of check nodes (e.g., two or more check nodes 402) in the subset of check node data (e.g., in the registers 232) in the memory 230. Specifically, each check node in the subset of check nodes 402 has a set of most significant bits (MSB) 602 of one or more data items in the respective check node data 422. The multiple sets of MSBs 602 of the subset of check nodes 402 are compressed into a set of data bits 604, and each set of MSBs 602 contains the set of MSBs 602 of one or more data items in the respective check node data 422 of each check node in the subset of check nodes 402. The multiple sets of MSBs 602 collectively have a first number of bits, and the set of data bits 604 has a second number of bits. The first number is greater than the second number. In an example, each of the 3 check nodes has 1 MSB of each of the likelihood value data items 426 and 428, and the total of 6 MSBs of the 3 check nodes are jointly compressed into the set 604 of 5 data bits. Since the set of data bits 604 is stored instead of the multiple sets of MSBs 602 of the subset of check nodes 402, at least one data bit is saved for storing the check node data of the subset of 3 check nodes 402. n - k The storage block holding the check node data of the subset of 3 check nodes 402 holds at least one data bit.

[0069] Figure 7A Two tables 700 and 710 are shown, according to some embodiments, showing possible combinations of the two data items 426 and 428 of the check node data 422 of each check node 402. Figure 7B An example data structure 720 of the check node data 422 of the subset of check nodes 402 is shown, according to some embodiments, based on the table compression shown. Figure 7A An example data structure 720 of the check node data 422 of the subset of check nodes 402 is shown, according to some embodiments, based on the table compression shown. Figure 7C The original check node data 422 of the subset 402 of 3 check nodes is compared to the corresponding compressed check node data 722, according to some embodiments.

[0070] For each check node 402, the first likelihood value data item 426 and the second likelihood value data item 428 are applied in the min-sum based LDPC decoding, and each likelihood value data item 426 or 428 has a MSB. Referring to Figure 7A , the first likelihood value data item 426 is less than or equal to the second likelihood value data item 428, and the case where the MSB of the first likelihood value data item 426 is equal to 1 and the MSB of the second likelihood value data item 428 is equal to 0 never occurs. The combination of the two MSBs of the likelihood value data items 426 and 428 never equals (1, 0), and there are only three possible combinations of the two MSBs of the likelihood value data items 426 and 428 (e.g., (0, 0), (0, 1), and (1, 1)). Referring to Figure 7BIn some embodiments, the subset of check nodes 402 includes 3 check nodes 402. The first likelihood value data item 426 and the second likelihood value data item 428 of the three check nodes 402 are jointly compressed. Each likelihood value data item 426 or 408 has one MSB 602, and the three check nodes 402 collectively have six MSBs 602. The six MSBs 602 correspond to 27 (i.e., 3 x 3 x 3) value combinations, which can be represented by a set of five data bits 604. As such, the six MSBs 602 of the likelihood value data items 426 and 428 of the three check nodes 402 are compressed and jointly stored in the set of five data bits 604, saving one data bit for register 232 space (i.e., an average of one bit per check node 402).

[0071] Referring to Figure 7B In some embodiments, for each check node in the subset of check nodes 402, the respective check node data 422-1, 422-2, or 422-3 includes a first likelihood value data item 426 corresponding to a first code symbol and a second likelihood value data item 428 corresponding to a second code symbol. One or more data items of each check node 402 includes the first likelihood value data item 426 and the second likelihood value data item 428, and the set of MSBs 602 includes a third number of MSBs (e.g., one MSB) of the first likelihood value data item 426 and a fourth number of MSBs (e.g., one MSB) of the second likelihood value data item 428. The sets of MSBs 602 collectively have a first number of bits (e.g., six), and the set of data bits 604 has a second number of bits (e.g., five). The first number is greater than the second number by, for example, one, two, or another positive integer.

[0072] For each check node in the subset of check nodes 402, the set of MSBs 602 has three value combinations of MSBs of the first likelihood value data item 426 and the second likelihood value data item 428, such as (0, 0), (0, 1), and (1, 1) in Figure 7A In an example, the subset of check nodes 402 includes 3 or 4 check nodes. The first number is greater than the second number by one. On average, each check node 402 saves or one quarter of a bit of storage space. In another example, the subset of check nodes 402 includes 5, 6, or 7 check nodes. The first number is greater than the second number by two. On average, each check node 402 saves , or bits of storage space.

[0073] Referring to Figure 7CIn some embodiments, the check node subset 402 contains 3 check nodes. For each check node in the check node subset 402, each of the first and second likelihood value data items 426, 428 has 6 bits. The first and second likelihood value data items 426, 428 of the original check node data 422 of the check node subset 402 collectively have 36 bits. Each of the first and second likelihood value data items 426, 428 has only 1 MSB, and the 6 MSBs of the first and second likelihood value data items 426, 428 of the check node data 422 are compressed to 5 MSBs, i.e., “compressed_columns [4:0]”. The first and second likelihood value data items 426, 428 of the compressed check node data 722 of the check node subset 402 collectively have 35 bits. Thus, the compressed check node data 722 saves 1 bit compared to the original check node data 422 of the subset 402 of 3 check nodes.

[0074] In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of the check node subset 402 using the following logic, which is optionally loaded in the registers 232: x[3:0] = column1[1:0] + column2[1:0] 3 (using a lookup table or logic) If (x[3] == 0) compressed_columns [4:0] = {column3[1:0], x[2:0] else compressed_columns [4:0] = {2'b11, x[2], column3[1:0] In some embodiments, the integrity engine 230 is configured to decode the compressed check node data 422 of the check node subset 402 using the following logic, which is optionally loaded in the registers 232: If (compressed_columns [4:3] <3) x[2:0] = compressed_columns [2:0] column1[1:0] = x[2:0] % 3 column2[1:0] = x[2:0] / 3 column3[1:0] = compressed_columns [4:0] else x[3:0] = 8 column1[1:0] = 2 column2[1:0] = 2 column3[1:0] = compressed_columns [1:0] In some embodiments, the integrity engine 230 saves one bit of storage space in the registers 232 for each check node 402, while adding data compression and data decompression logic. Thus, the compressed MSBs of the subset of check nodes 402 help to save expensive register space, resulting in a reduced net gate count in the integrity check system 300.

[0075] Figure 8A Another example data structure 800 of check node data 422 of a subset 402 of 3 check nodes with an index-based compression scheme is shown, in accordance with some embodiments, and Figure 8B The check node data 422 of the subset 402 of 3 check nodes is compared to the compressed corresponding check node data 822, in accordance with some embodiments. For each check node (e.g., 402-1, 402-2, or 402-3) in the subset 402 of check nodes, the corresponding check node data 422 (e.g., 422-1, 422-2, or 422-3) includes a first likelihood value data item 426 and an index data item 430 identifying one of the subsets of code symbols corresponding to the first likelihood value data item 426. For example, the check node 402 is connected to 6 variable nodes 404 on the Tanner graph 400, and the index data item 430 identifies the third variable node as having the smallest magnitude among the 6 variable nodes 404. For each check node 402-1, 402-2, 402-3, a set of MSBs 602 (e.g., 2 MSBs) of the index data item 430 is identified in the corresponding check node data 422-1, 422-2, or 422-3. A set of data bits 604 is determined based on the sets of MSBs 602 of the index data items 430 of the subset 402 of check nodes. The sets of MSBs 602 include the set of MSBs 602 of the index data item 430 in the corresponding check node data 422 of each check node in the subset 402 of check nodes. The set of data bits 604 is stored in association with the subset 402 of check nodes in a memory block (e.g., the registers 232 including a register array) allocated to the plurality of check nodes 402. The sets of MSBs 602 collectively have a first number of bits, and the set of data bits 604 has a second number of bits. The first number is greater than the second number.

[0076] Alternatively, in some embodiments, the one or more data items of the compressed check node data 422 include an index data item 432 corresponding to the second likelihood value data item 428. For example, the check node 402 is connected to 6 variable nodes 404 on the Tanner graph 400, and the index data item 432 identifies that the fifth variable node has the second smallest magnitude among the 6 variable nodes 404. The set of data bits 604 is determined based on a plurality of MSB sets 602 of the index data items 430 of the check node subset 402. The plurality of MSB sets 602 includes a set of MSBs 602 of the index data item 430 in the respective check node data 422 of each check node in the check node subset 402. At least one bit is saved by compressing the set of MSBs 602 of the index data item 430. Additionally and alternatively, in some embodiments, both the sets of MSBs 602 of the index data items 430 and 432 are compressed. The set of data bits 604 is determined based on a plurality of MSB sets 602 of both the index data items 430 and 432 of the check node subset 402. The plurality of MSB sets 602 includes a set of MSBs 602 of the index data items 430 and 432 in the respective check node data 422 of each check node in the check node subset 402. At least one bit is saved by compressing the sets of MSBs 602 of the index data items 430 and 432.

[0077] Reference is made to Figure 8B In some embodiments, the check node subset 402 includes 3 check nodes. For each check node in the check node subset 402, the first index data item 430 has 6 bits. The first index data items 430 of the original check node data 422 of the check node subset 402 collectively have 18 bits. Each first index data item 430 has 2 MSBs, and the 6 MSBs of the first index data items 430 of the check node data 422 are compressed into a set of 5 MSBs, i.e., “compressed Minl Index MSB [4:0]”. The set of 5 data bits is stored jointly with a plurality of remaining sets of bits (e.g., “Minl Index [3:0]”) of the check node subset 402. The first index data items 430 of the compressed check node data 822 of the check node subset 402 collectively have 17 bits. Thus, the compressed check node data 822 saves one bit compared to the original check node data 422 of the subset 402 of 3 check nodes.

[0078] In some embodiments, the set of data bits 604 is determined based on the plurality of MSB sets 602 by identifying a lookup table 824. The combination of the plurality of MSB sets 604 of the check node subset 402 is identified in the lookup table 824. The lookup table 824 is consulted to determine the set of data bits 604 based on the combination of the plurality of MSB sets. Alternatively, in some embodiments, the set of data bits 604 is determined based on the plurality of MSB sets 602 by identifying a predefined equation 826. A plurality of input values is determined based on the plurality of MSB sets 602 of the check node subset 402. An output value is determined based on the predefined equation 826 and the plurality of input values, and converted to the set of data bits 604. The set of data bits 604 is uniquely determined based on the plurality of MSB sets 602 in the lookup table 824 or the equation 826.

[0079] In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of the check node subset 402 using the following logic, which is optionally loaded in the registers 232: x[3:0] = min_index_msb1[1:0] + min_index_msb2[1:0] 3 If (x[3] == 0) compressed_min_index_msbs [4:0] = {min_index_msb3[1:0], x[2:0]} else compressed_min_index_msbs [4:0] = {2'b11, x[2], min_index_msb3[1:0]} In some embodiments, the integrity engine 230 is configured to decode the compressed check node data 422 of the check node subset 402 using the following logic, which is optionally loaded in the registers 232: If (compressed_min_index_msbs [4:3] < 3) x[2:0] = compressed_min_index_msbs [2:0] min_index_msb1[1:0] = x[2:0] % 3 min_index_msb2[1:0] = x[2:0] / 3 min_index_msb3[1:0] = compressed_min_index_msbs [4:0] else x[3:0] = 8 min_index_msb1[1:0] = 2 min_index_msb2[1:0] = 2 min_index_msb3[1:0] = compressed_min_index_msbs[1:0] In some embodiments, the integrity engine 230 saves space in register 232 for each verification node 402. The storage space is reduced to a single digit, while data compression and decompression logic is added. Therefore, compressing the MSB of a subset of check nodes helps save expensive register space, thereby reducing the net gate count in the integrity verification system 300.

[0080] Figure 9 This is a flowchart of a method 900 for compressing verification node data 422 of an electronic device according to some embodiments. Method 900 includes a storage system 200 (…). Figure 2 This is implemented at the electronic device. In step 902, the electronic device identifies multiple check nodes 402 associated with the data block. In step 904, each check node corresponds to a subset of code symbols in the data block and has corresponding check node data 422, which indicates the likelihood that the subset of code symbols is an error. In step 906, for each check node in the subset of check nodes 402, the electronic device identifies the set 602 of the most significant bits (MSB) of one or more data items (e.g., likelihood data items 426 and 428) in the corresponding check node data 422. Figure 6 In step 908, the electronic device determines the data bit set 604 based on multiple MSB sets 602 of the verification node subset 402. Figure 6 In step 910, the plurality of MSB sets 602 comprise one or more data items from the corresponding check node data 422 of each check node in the check node subset 402. In step 912, the electronic device stores the data bit set 604 in association with the check node subset 402 in a memory block (e.g., register 232) allocated to the plurality of check nodes 402. In step 914, the plurality of MSB sets 602 have a total of a first number of bits, and the data bit set 604 has a second number of bits. The first number is greater than the second number.

[0081] In some embodiments, for each check node in the subset of check nodes 402, the respective check node data 422 includes a first likelihood value data item 426 and an index data item 430 identifying one of the code symbol subsets corresponding to the first likelihood value data item 426, and the one or more data items include the index data item 430. In some embodiments, the subset of check nodes 402 includes 3 check nodes 402, and for each check node in the subset of check nodes 402, the MSB set 604 of the one or more data items in the respective check node data 422 includes 2 MSBs of the index data item 430.

[0082] In some embodiments, for each check node in the subset of check nodes 402, the respective check node data 422 includes a first likelihood value data item 426 corresponding to a first code symbol and a second likelihood value data item 428 corresponding to a second code symbol. The one or more data items include the first likelihood value data item 426 and the second likelihood value data item 428, and the MSB set 604 includes a third number of MSBs of the first likelihood value data item 426 and a fourth number of MSBs of the second likelihood value data item 428. Further, in some embodiments, the first likelihood value data item 426 is less than or equal to the second likelihood value data item, and the third number and the fourth number equal 1. Additionally, in some embodiments, the subset of check nodes 402 includes 3 check nodes 402, and the plurality of MSB sets of the subset of check nodes 402 includes a total of 6 bits. For each check node in the subset of check nodes 402, the MSB set has 3 combinations of values of the MSBs of the first likelihood value data item 426 and the second likelihood value data item 428. The plurality of MSB sets of the subset of check nodes 402 has 3 x 3 x 3 combinations of values of the MSBs of the first likelihood value data item 426 and the second likelihood value data item 428, and the data bit set 604 has 5 bits for representing the 3 x 3 x 3 combinations of values. The first number is greater than the second number by 1. In some embodiments, the subset of check nodes 402 includes 5, 6, or 7 check nodes 402; for each check node in the subset of check nodes 402, the MSB set has 3 combinations of values of the MSBs of the first likelihood value data item and the second likelihood value data item; and the first number is greater than the second number by 2.

[0083] In some embodiments, determining the data bit set 604 based on the plurality of MSB sets further includes: identifying a lookup table; identifying a combination of the plurality of MSB sets of the subset of check nodes 402 in the lookup table; and checking the lookup table to determine the data bit set 604 based on the combination of the plurality of MSB sets.

[0084] In some embodiments, determining the set of data bits 604 based on the plurality of sets of MSBs further comprises: identifying a predefined equation; determining a plurality of input values based on the plurality of sets of MSBs of the subset of check nodes 402; determining an output value based on the predefined equation and the plurality of input values; and determining the set of data bits 604 from the output value.

[0085] In some embodiments, storing the set of data bits 604 in association with the subset of check nodes 402 further comprises: jointly storing the set of data bits 604 and a plurality of sets of remaining bits of the subset of check nodes 402, the plurality of sets of remaining bits containing a set of remaining bits of one or more data items in the check node data 422 of each check node in the subset of check nodes 402.

[0086] In some embodiments, for each check node 402, the subset of code symbols corresponds to a set of likelihood value data items. Each likelihood value data item indicates a likelihood value that a respective code symbol is erroneous. The electronic device identifies a first likelihood value data item 426 and a second likelihood value data item 428 in accordance with a determination that the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426 and less than or equal to a remaining likelihood value data item of the subset of code symbols. Further, in some embodiments, each likelihood value data item of a respective code symbol is determined based on a log-likelihood ratio (LLR) approximated by equation (6).

[0087] In some embodiments, for each check node, the check node data 422 of the check node 402 further contains a first index data item 430 that identifies one code symbol in the subset of code symbols that corresponds to the first likelihood value data item 426 of the check node data 422.

[0088] In some embodiments, each code symbol in the subset of code symbols corresponds to a respective likelihood value data item that indicates a likelihood value that the respective code symbol is erroneous, and the check node data 422 of the check node 402 further contains a syndrome bit 424 that is a combination of signs of the respective likelihood value data items of the subset of code symbols.

[0089] The memory is further used to store instructions and data associated with the method 900, and includes high-speed random access memory, such as DRAM, SRAM or other random access solid state storage devices; and optionally includes non-volatile memory, such as one or more disk storage devices, one or more optical disk storage devices, one or more flash storage devices, or one or more other non-volatile solid state storage devices. The memory optionally includes one or more storage devices remotely located from the one or more processing units. The memory, or alternatively the non-volatile memory within the memory, comprises a non-transitory computer readable storage medium. In some embodiments, the memory, or non-transitory computer readable storage medium of the memory, stores programs, modules, and data structures, or a subset or superset thereof, used to implement the method 900.

[0090] Some embodiments of the present application relate to compressing check node data in an electronic device. The electronic device identifies check nodes associated with a data block. Each check node corresponds to a subset of code symbol in the data block and has respective check node data indicating a likelihood value that the code symbol is erroneous. For each check node in a subset of check nodes, a set of most significant bits (MSBs) is identified in the respective check node data. The electronic device determines a set of data bits based on the sets of MSBs of the subset of check nodes, the sets of MSBs of the subset of check nodes including the sets of MSBs identified for each check node in the subset of check nodes. The set of data bits is stored in a memory block allocated to the subset of check nodes. The sets of MSBs collectively have a greater number of bits than the set of data bits. More specifically, some embodiments of the present application are described in the following clauses: Clause 1. A method for compressing check node data implemented at an electronic device, the method comprising: identifying a plurality of check nodes associated with a data block, each check node corresponding to a subset of code symbols in the data block and having respective check node data indicating a likelihood value that the subset of code symbols is erroneous; for each check node in a subset of check nodes, identifying a set of most significant bits (MSBs) of one or more data items in the respective check node data; determining a set of data bits based on a plurality of sets of MSBs of the subset of check nodes, the plurality of sets of MSBs including the set of MSBs of the one or more data items in the respective check node data of each check node in the subset of check nodes; and storing the set of data bits in a memory block allocated to the plurality of check nodes in association with the subset of check nodes, wherein the plurality of sets of MSBs collectively have a first number of bits, and the set of data bits has a second number of bits, the first number being greater than the second number.

[0091] Clause 2. The method of clause 1, wherein, for each check node in the subset of check nodes, the respective check node data includes a first likelihood value data item and an index data item identifying one code symbol in the subset of code symbols corresponding to the first likelihood value data item, and the one or more data items includes the index data item.

[0092] Clause 3. The method of clause 1 or 2, wherein the subset of check nodes includes 3 check nodes, and, for each check node in the subset of check nodes, the set of MSBs of the one or more data items in the respective check node data includes 2 MSBs of the index data item.

[0093] Clause 4. The method of any of clauses 1-3, wherein, for each check node in the subset of check nodes: the respective check node data includes a first likelihood value data item corresponding to a first code symbol and a second likelihood value data item corresponding to a second code symbol; the one or more data items includes the first likelihood value data item and the second likelihood value data item, and the set of MSBs includes a third number of MSBs of the first likelihood value data item and a fourth number of MSBs of the second likelihood value data item.

[0094] Clause 5. The method of clause 4, wherein the first likelihood value data item is less than or equal to the second likelihood value data item, and the third number and the fourth number equal 1.

[0095] Clause 6. The method of clause 5, wherein: the subset of check nodes includes 3 check nodes, a total of 6 bits of the multiple sets of MSBs of the subset of check nodes; for each check node in the subset of check nodes, the set of MSBs has 3 combinations of values of MSBs of the first likelihood value data item and the second likelihood value data item; and the multiple sets of MSBs of the subset of check nodes has 3x3x3 combinations of values of MSBs of the first likelihood value data item and the second likelihood value data item, and the set of data bits has 5 bits for representing the 3x3x3 combinations of values; and the first number is 1 greater than the second number.

[0096] Clause 7. The method of clause 5 or 6, wherein: the subset of check nodes includes 5, 6, or 7 check nodes; for each check node in the subset of check nodes, the set of MSBs has 3 combinations of values of MSBs of the first likelihood value data item and the second likelihood value data item; and the first number is 2 greater than the second number.

[0097] Clause 8. The method of any one of clauses 1-7, wherein determining the set of data bits based on the plurality of sets of MSBs further comprises: identifying a lookup table; identifying a combination of the plurality of sets of MSBs of the subset of check nodes in the lookup table; and checking the lookup table to determine the set of data bits based on the combination of the plurality of sets of MSBs.

[0098] Clause 9. The method of any one of clauses 1-8, wherein determining the set of data bits based on the plurality of sets of MSBs further comprises: identifying a predefined equation; determining a plurality of input values based on the plurality of sets of MSBs of the subset of check nodes; determining an output value based on the predefined equation and the plurality of input values; and determining the set of data bits from the output value.

[0099] Clause 10. The method of any one of clauses 1-9, storing the set of data bits in association with the subset of check nodes further comprises: storing a plurality of sets of remaining bits of the set of data bits and the subset of check nodes jointly, the plurality of sets of remaining bits containing a set of remaining bits of the one or more data items in the check node data of each check node in the subset of check nodes.

[0100] Clause 11. The method of any one of clauses 1-10, wherein for each check node, the subset of code symbol corresponds to a set of likelihood value data items, each likelihood value data item indicating a likelihood value that a respective code symbol is erroneous, and wherein the method further comprises: identifying a first likelihood value data item and a second likelihood value data item in accordance with a determination that the second likelihood value data item is greater than or equal to the first likelihood value data item and less than or equal to a remaining likelihood value data item of the subset of code symbols.

[0101] Clause 12. The method of clause 11, wherein each likelihood value data item of the respective code symbol is determined based on a log-likelihood ratio (LLR) approximated as follows:

[0102] wherein p (|) is a probability of a combination of data values, x is a value stored for the respective code symbol, and y is a correct value of the respective code symbol.

[0103] Clause 13. The method of any one of clauses 1-12, wherein for each check node, the check node data of the check node further contains a first index data item, the first index data item identifying one code symbol in the subset of code symbols that corresponds to a first likelihood value data item of the check node data.

[0104] Clause 14. The method of any of clauses 1-13, wherein each code symbol in the subset of code symbols corresponds to a respective likelihood value data item indicating a likelihood value that the respective code symbol is erroneous, and wherein the check node data of the check node further includes a sign bit that is a combination of signs of the respective likelihood value data items of the subset of code symbols.

[0105] Clause 15. An electronic device, comprising: one or more processors; and memory storing instructions thereon that, when executed by the one or more processors, cause the processors to perform the method of any of clauses 1-14.

[0106] Clause 16. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed by one or more processors, cause the processors to perform the method of any of clauses 1-14.

[0107] Compression of multiple data items of check node data of each check node

[0108] Figure 10 is a data map 1000 illustrating example value combinations of two likelihood value data items 426 and 428 of check node data 422 of each check node 402 according to some embodiments. The check node 402 corresponds to a subset of code symbols (e.g., 50 code word bits) in a data block. The check node data 422 includes multiple data items (e.g., likelihood value data items 426 and 428) and indicates likelihood values that the subset of code symbols is erroneous. A data bit set 1002 is determined based on value combinations of the multiple data items to uniquely identify the value combinations among a set 1006 of selected value combinations according to a predefined relationship. The data bit set 1002 is stored in a storage block (e.g., the register 232) to represent the multiple data items of the check node data 422 of the check node 402. Each of the multiple data items requires at least a first number of data bits to represent all possible values of the respective data item, and the data bit set 1002 has a second number of data bits that is less than a sum of the first numbers of each of the multiple data items. In these ways, by storing the data bit set 1002 instead of the multiple data items of the check node 402, at least one bit of register space is saved.

[0109] In some embodiments, for each check node 402, the first likelihood value data item 426 and the second likelihood value data item 428 are applied in a min-sum based LDPC decoding. The data mapping 1000 has a first number of columns and a second number of rows. Each row corresponds to a fixed value of the second likelihood value data item 428, and the first likelihood value data item 426 increases from left to right. Each column corresponds to a fixed value of the first likelihood value data item 426, and the second likelihood value data item 428 increases from top to bottom. The data mapping 1000 illustrates value combinations of the first number of discrete values of the first likelihood value data item 426 and the second number of discrete values of the second likelihood value data item 428. Referring to Figure 10 In this example, 64 value combinations are formed by 8 values of the first likelihood value data item 426 and 8 values of the second likelihood value data item 428, and are listed in the data mapping 1000. In addition, the first likelihood value data item 426 is less than or equal to the second likelihood value data item 428, and the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426 and less than or equal to the remaining likelihood value data items of the subset of code symbols corresponding to the set of variable nodes 404 of the respective check node 402. Assuming the first likelihood value data item 426 is less than the second likelihood value data item 428, the set of first eliminated value combinations 1004-1 of the likelihood value data items 426 and 428 are marked with "X" and are not present. The data mapping 1000 contains 36 remaining value combinations that are distinct from the set of first eliminated value combinations 1004-1 of the likelihood value data items 426 and 428.

[0110] In some embodiments, a subset of 36 remaining value combinations is associated with the set of data bits 1002. Each of the subset of 36 remaining value combinations is represented by a respective set of data bits 1002. For example, the subset of 36 remaining value combinations does not include the set of second value combinations 1004-2 of likelihood value data items 426 and 428, and contains 32 remaining value combinations. The set of second eliminated value combinations 1004-2 corresponds to the second likelihood value data item 428 equal to 6 and the first likelihood value data item 426 equal to any of 0-3. The 32 remaining value combinations marked with “0” 1006 are uniquely represented by the set of 5 data bits 1002. For example, the 32 remaining value combinations are represented by 00000, 00001, 00010, …, and 11111, respectively. The first likelihood value data item 426 and the second likelihood value data item 428 correspond to 36 possible value combinations, and binary data items representing the 36 possible value combinations have at least 6 bits, which is one more bit than the set of data bits 1002. In other words, the first likelihood value data item 426 and the second likelihood value data item 428 are represented by the set of data bits 1002 in a lossy manner (e.g., such that the set of second value combinations 1004-2 of likelihood value data items 426 and 428 are not available), which allows for saving 1 bit of register space for each check node 402.

[0111] Reference Figure 10 In some embodiments, the 32 remaining value combinations marked with “0” correspond to the set of selected value combinations 1006, and exclude the set of first eliminated value combinations 1004-1 and the set of second eliminated value combinations 1004-2. The set of selected value combinations 1006 is complementary to the set of eliminated value combinations 1004 that combines the first set 1004-1 and the second set 1004-2 of eliminated value combinations. In some embodiments, for each eliminated value combination in the set of eliminated value combinations 1004, the first likelihood value data item 426 is in a first elimination range, and the second likelihood value data item 428 is in a second elimination range. For example, for the set of second value combinations 1004-2, the first elimination range is [0, 3], and the second elimination range contains the value 6.

[0112] In some embodiments, during decoding, according to a determination that the value combination 1012 (e.g., (1, 6)) of the likelihood value data items 426 and 428 belongs to the set of eliminated value combinations 1004, the second likelihood value data item 428 is approximated with the closest available value (e.g., 5 or 7) while keeping the value of the first likelihood value data item 426 (e.g., 1). The value combination 1012 is updated based on the approximated value of the second likelihood value data item 428, and the data bit set 1002 is determined based on the updated value combination 1014. For example, the value combination (1, 6) is updated to (1, 7), which is associated with the data bit set 1002 of "11001." In another example, the value combination (1, 6) is updated to (1, 5).

[0113] Figure 11 A lookup table 1102 and a formula 1104 that are applied to associate the value combination 1006 of two data items of the check node data 422 with the data bit set 1002 are shown in accordance with some embodiments. The data bit set 1002 is determined based on the value combination of the plurality of data items compressed for each check node 402. The data bit set uniquely identifies the value combination among the set of selected value combinations 1006 according to a predefined relationship. In some embodiments, the predefined relationship is defined with the lookup table 1102 that (e.g., uniquely) associates the data bit set 1002 with the set of selected value combinations 1006. In an example (e.g., Figure 10 ) the selected value combinations 1006 are consecutively numbered from 0 to 31, and each selected value combination 1006 is represented with the data bit set 1002 corresponding to the respective consecutive number. Alternatively, in some embodiments, the predefined relationship is defined with the formula 1104 that (e.g., uniquely) associates the data bit set 1002 with the set of selected value combinations 1006.

[0114] The first likelihood value data item 426 corresponds to a first code symbol, and the second likelihood value data item 428 corresponds to a second code symbol. The second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426. During encoding, according to a determination that the value combination corresponding to the values of the likelihood value data items 426 and 428 is contained in the lookup table 1102, the integrity engine 230 determines the data bit set 1002 from the lookup table 1102 based on the value combination. Conversely, according to a determination that the value combination corresponding to the values of the likelihood value data items 426 and 428 is not contained in the lookup table 1102, the integrity engine 230 approximates at least one of the values of the likelihood value data items 426 and 428 based on a value approximation rule (e.g., using the closest and available value), and determines the data bit set 1002 from the lookup table 1102 based on the corresponding approximated value combination. During decoding, the integrity engine 230 determines the value combination and the corresponding values of the likelihood value data items 426 and 428 based on the data bit set 1002.

[0115] In some embodiments, during encoding, integrity engine 230 determines data bit set 1002 from equation 1104 based on a value combination of values corresponding to likelihood value data items 426 and 428 being contained in lookup table 1102. During decoding, integrity engine 230 determines a value combination and corresponding values of likelihood value data items 426 and 428 from equation 1104 based on data bit set 1002.

[0116] Figure 12 is another example data mapping 1200 showing example value combinations of two likelihood value data items 426 and 428 of check node data 422 of each check node 402 according to some embodiments. Check node data 422 contains multiple data items (e.g., likelihood value data items 426 and 428) and indicates a likelihood value of a subset of code symbol being erroneous. A data bit set 1002 is determined based on a value combination of the multiple data items to be uniquely identified among a set 1006 (e.g., 1006-1, 1006-2, and 1006-3) of selected value combinations according to a predefined relationship (e.g., lookup table 1102 and equation 1104 in Figure 11 ). Data bit set 1002 is stored in a storage block (e.g., register 232) to represent the multiple data items of check node data 422 of check node 402, saving at least one bit of register space. Data mapping 1200 has a first number of columns and a second number of rows. Each row corresponds to a fixed value of second likelihood value data item 428, and first likelihood value data item 426 increases from left to right. Each column corresponds to a fixed value of first likelihood value data item 426, and second likelihood value data item 428 increases from top to bottom. Data mapping 1200 shows value combinations of the first number of discrete values of first likelihood value data item 426 and the second number of discrete values of second likelihood value data item 428. Reference is made to Figure 12 In this example, 64 value combinations are formed by 8 values of first likelihood value data item 426 and 8 values of second likelihood value data item 428, and are listed in data mapping 1200.

[0117] Data mapping 1200 contains a set 1006 (e.g., 1006-1, 1006-2, and 1006-3) of selected value combinations and a set 1004 (e.g., 1004-1, 1004-2, and 1004-3) of eliminated value combinations complementary to set 1006 of selected value combinations. Reference is made to Figure 12In some embodiments, the second likelihood value data item 428 has a most significant bit (MSB) and a least significant bit (LSB), and the MSB and the LSB of the second likelihood value data item 428 are equal to “1” and “0”, respectively, for each eliminated value combination in the set of eliminated value combinations 1004 (e.g., 1004-2 and 1004-3), independent of the first likelihood value data item 426. In some embodiments, during encoding, the value combination 1202 (e.g., (1, 6)) of the determining likelihood value data items 426 and 428 belongs to the set of eliminated value combinations 1004, the second likelihood value data item 428 is approximated with the closest available value (e.g., 5 or 7) while keeping the value of the first likelihood value data item 426 (e.g., 1). The value combination 1202 is updated based on the approximated value of the second likelihood value data item 428, and the set of data bits 1002 is determined based on the updated value combination 1204. For example, the value combination (1, 6) is updated to (1, 7), which is associated with the set of data bits 1002 of “11001”. During decoding, the set of data bits 1002 is decoded as (1, 7) instead of modified as (1, 6), and such a data compression scheme thereby results in the loss of the value combination (1, 6) of the likelihood value data items 426 and 428.

[0118] In some embodiments, for each eliminated value combination in the set of eliminated value combinations 1004, the first likelihood value data item 426 is within a first eliminated range, and the second likelihood value data item 428 is within a second eliminated range. For example, for the second set of value combinations 1004-2 and the third set of value combinations 1004-3, the first value range is [0, 7], and the second value range contains two discrete values 4 and 6.

[0119] In some embodiments, the MSB of the second likelihood value data item 428 is identified. In accordance with a determination that the MSB of the second likelihood value data item 428 is equal to 0, the integrity engine 230 does not store the MSB of the first likelihood value data item 426, which is also equal to 0. In accordance with a determination that the MSB of the second likelihood value data item 428 is equal to 1, the integrity engine 230 does not store the LSB of the second likelihood value data item 428 and sets it to 1. In other words, the integrity engine 230 stores either the MSB of the first likelihood value data item 426 or the LSB of the second likelihood value data item 428.

[0120] In some embodiments, the integrity engine 230 saves 1 bit of storage space in the register 232 for each check node 402 while adding data compression and data decompression logic. Thus, the compression of the likelihood value data items of each check node 402 helps to save the expensive register space, resulting in a reduction in the net gate count in the compression and decompression logic of the integrity check system 300 while not causing or causing little negative impact on the BER of the data read from the storage system 200.

[0121] Figures 13-16 are example data mappings 1300, 1400, 1500, and 1600 that illustrate different lossy value combinations of the check node data 422 for each check node 402 according to some embodiments. The check node data 422 contains multiple data items (e.g., likelihood value data items 426 and 428). A data bit set 1002 is determined based on a value combination of the multiple data items to uniquely identify the value combination among a set 1006 of selected value combinations (which are labeled with "0") according to a predefined relationship (e.g., a lookup table 1102 and a formula 1104 in Figure 11 The data bit set 1002 is stored in a storage block (e.g., a register 232) to represent the multiple data items of the check node data 422 for the check node 402, thereby saving at least one bit of register space.

[0122] Each data mapping 1300, 1400, 1500, or 1600 contains value combinations of the first likelihood value data item 426 and the second likelihood value data item 428 and has a first number of columns (e.g., 32 columns) and a second number of rows (e.g., 32 rows). Each row corresponds to a fixed value of the second likelihood value data item 428, and the first likelihood value data item 426 increases from left to right (e.g., from 0 to 31). Each column corresponds to a fixed value of the first likelihood value data item 426, and the second likelihood value data item 428 increases from top to bottom (e.g., from 0 to 31). Each data mapping 1300, 1400, 1500, or 1600 illustrates value combinations of the first number of discrete values of the first likelihood value data item 426 and the second number of discrete values of the second likelihood value data item 428. Reference is made to Figures 13-16 In these examples, 32 x 32 value combinations are formed by 32 values of the first likelihood value data item 426 and 32 values of the second likelihood value data item 428 and are listed in the data mapping 1000. In some embodiments, 5 bits are used to represent each likelihood value data item 426 or 428, and 10 bits are used to represent all 32 x 32 value combinations.

[0123] Each data mapping 1300, 1400, 1500, or 1600 contains the set 1006 of selected value combinations and the set 1004 of eliminated value combinations that is complementary to the set 1006 of selected value combinations. Reference is made to Figure 13 In some embodiments, the set 1004 of eliminated value combinations encompasses value combinations in which the second likelihood value data item 428 is less than the first likelihood value data item 426 or equal to an even number between 16 and 30 (inclusive). The set 1006 of selected value combinations is completely represented by 9 bits in the data bit set 1002, thereby saving 1 single bit of register space for each check node 402. Reference is made toFigure 14 In some embodiments, the set of eliminated value combinations 1004 encompasses value combinations in which the second likelihood value data item 428 is less than the first likelihood value data item 426 or equal to a value of one of a set of numbers including 8, 10, 12, 14, 16-18, 20-22, 24-26, and 28-30. The set of selected value combinations 1006 is represented entirely by 8 bits of the set of data bits 1002, saving 2 bits of register space for each check node 402. See FIG. 10. Figure 15 In some embodiments, the set of eliminated value combinations 1004 encompasses value combinations in which the second likelihood value data item 428 is less than the first likelihood value data item 426 or in which the LSBs of the second likelihood value data item 428 greater than or equal to 16 are not equal to the MSBs of the first likelihood value data item 426. This compression scheme reduces the number of multiplexers applied in the integrity encoding. The set of selected value combinations 1006 is represented entirely by 9 bits of the set of data bits 1002, saving 1 single bit of register space for each check node 402. See FIG. 10. Figure 16 In some embodiments, the set of eliminated value combinations 1004 encompasses value combinations in which the second likelihood value data item 428 is less than the first likelihood value data item 426, or in which the LSBs of the second likelihood value data item 428 greater than or equal to 8 and less than 16 are not equal to the MSBs of the first likelihood value data item 426, or in which the two LSBs of the second likelihood value data item 428 greater than or equal to 16 are not equal to the two MSBs of the first likelihood value data item 426. This compression scheme reduces the number of multiplexers applied in the integrity encoding. The set of selected value combinations 1006 is represented entirely by 8 bits of the set of data bits 1002, saving 2 bits of register space for each check node 402.

[0124] In some embodiments, for each selected value combination in the set of selected value combinations 1006, the first likelihood value data item 426 is in a first value range and the second likelihood value data item 428 is in a second value range that is optionally dependent on the first value range. Further, in some embodiments, the first value range contains one or more non-contiguous first data sub-ranges, one or more predefined first data values, or a combination thereof, and the second value range contains one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof. See FIG. 10. Figure 13In an example, for the set of selected value combinations 1006, the first value range is between 0 and the second likelihood value data item 428, inclusive. The second value range includes the data sub-range [0-15] and 8 predefined second data values, including 17, 19, 21, 23, 25, 27, 29, and 31. In other words, in some embodiments, for each selected value combination in the set of selected value combinations 1006, the second likelihood value data item 428 in the second value range includes one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof. The first likelihood value data item 426 is not limited except to be less than or equal to the second likelihood value data item 428.

[0125] Figure 17 An example data structure of check node data 422 for a check node 402 having one or more data compression schemes is shown in accordance with some embodiments. The check node data 422 includes a sign bit 424, a first likelihood value data item 426, a second likelihood value data item 428, and a first index data item 430. The sign bit 424 is generated based on the signs of the variable-check node data from the set of variable nodes 404 in accordance with equation (4) v 1 - v m The first likelihood value data item 426 and the second likelihood value data item 428 include the magnitudes of the minimum variable-check node message data (Minl) and the second minimum variable-check node message data (Min2) of the set of variable nodes 404, respectively. The first index data item 430 identifies one variable node in the set of variable nodes 404 that corresponds to the first likelihood value data item 426. In some embodiments, the check node data 422 also includes a second index data item 432 that identifies one variable node in the set of variable nodes that corresponds to the second likelihood value data item 428.

[0126] In some embodiments, for each check node 402, the plurality of data items that are jointly compressed includes the first likelihood value data item 426 and the second likelihood value data item 428 (e.g., Figures 10-16). In some embodiments, the data bit set 1002 is determined by selecting only one of the MSB of the first likelihood value data item 426 and the LSB of the second index data item 432 to include in the data bit set 1002 based on the MSB of the second likelihood value data item 428. Further, in some embodiments, during encoding, the integrity engine 230 determines the data bit set 1002 based on the LSB of the second index data item 432 and independent of the MSB of the first likelihood value data item 426 in accordance with a determination that the MSB of the second likelihood value data item 428 is equal to "0." The integrity engine 230 determines the data bit set 1002 based on the MSB of the first likelihood value data item 426 and independent of the LSB of the second index data item 432 in accordance with a determination that the MSB of the second likelihood value data item is equal to "1."

[0127] Alternatively, in some embodiments, for each check node 402, the plurality of data items that are jointly compressed include one of the likelihood value data items 426 and 428 and one of the index data items 430 and 432. In an example, the integrity engine 230 stores one of the MSB of the first likelihood value data item 426 and the LSB of the second index data item 432. In some embodiments, the integrity engine 230 is configured to compress the check node data 422 of the subset of check nodes 402 using the following logic, which is optionally loaded in the registers 232: If (Min2 amplitude >= 8) Set LSB of Min2 index to 0 if (Min2 amplitude >= 16) Set LSB of Min2 amplitude to 1 After compression, the data bit set 1002 requires one or two fewer data bits than the sum of the data bits in the plurality of data items to represent all possible values of the data items in the set 1006 of selected value combinations. Compression of these data items for each check node 402 helps to save expensive register space and reduce gate count in the compression and decompression logic of the integrity check system 300, while not causing or causing little negative impact on the BER of data read from the storage system 200.

[0128] Figure 18 is a flowchart of a method 1800 for compressing check node data 422 of an electronic device in accordance with some embodiments. The method 1800 is performed by processing logic that can comprise hardware (e.g., circuitry, dedicated logic, etc.), software (e.g., instructions run on a general purpose computer system or a dedicated computer system), or a combination of both. The method 1800 is performed by the integrity engine 230 of the integrity check system 300 of FIG. 1, for example. Figure 2implemented at an electronic device (e.g., the electronic device 102 of FIG. 1). At steps 1802 and 1804, the electronic device identifies the check node 402 corresponding to a subset of code symbol in the data block and determines check node data 422 containing a plurality of data items. The check node data 422 indicates a likelihood value for the subset of code symbols to be erroneous. At step 1806, the electronic device determines a data bit set 1002 based on a value combination of the plurality of data items. At step 1808, the data bit set 1002 uniquely identifies the value combination among a set 1006 of selected value combinations according to a predefined relationship (e.g., a lookup table 1102 and a formula 1104 in FIG. 1). At step 1810, the electronic device stores the data bit set 1002 representing the plurality of data items of the check node data 422 of the check node 402 in a storage block. At step 1812, each of the plurality of data items requires at least a first number of data bits to represent all possible values of the respective data item, and the data bit set 1002 has a second number of data bits. At step 1814, the second number is less than a sum of the first number of each of the plurality of data items, e.g., 1 bit, 2 bits. Figure 11

[0129] In some embodiments, at step 1816, the plurality of data items corresponds to a total number of possible value combinations, and a binary data item representing the total number has more bits than the data bit set 1002, thereby indicating that the compression of the plurality of data items is lossy.

[0130] In some embodiments, at step 1818, the plurality of data items contains a first likelihood value data item 426 corresponding to a first code symbol and a second likelihood value data item 428 corresponding to a second code symbol, and the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426; and the set 1006 of selected value combinations is complementary to the set 1004 of eliminated value combinations. Further, in some embodiments, determining the data bit set 1002 further includes, in accordance with a determination that the value combination belongs to the set 1004 of eliminated value combinations: approximating the second likelihood value data item 428 with a neighboring value available while keeping the value of the first likelihood value data item 426; updating the value combination of the plurality of data items based on the approximation of the second likelihood value data item 428; and determining the data bit set 1002 based on the updated value combination.

[0131] In some embodiments, for each selected value combination in the set 1006 of selected value combinations, the first likelihood value data item 426 is within a first value range, and the second likelihood value data item 428 is within a second value range. Further, in some embodiments, the first value range contains one or more non-contiguous first data sub-ranges, one or more predefined first data values, or a combination thereof, and the second value range contains one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof.​

[0132] In some embodiments, for each selected value combination in the set of selected value combinations 1006, the second likelihood value data item 428 in the second value range includes one or more non-consecutive second data subranges, one or more predefined second data values, or a combination thereof.

[0133] In some embodiments, the second likelihood value data item 428 has a most significant bit (MSB) and a least significant bit (LSB). For each selected value combination in the set of selected value combinations 1006, the MSB and the LSB of the second likelihood value data item 428 are not equal to "1" and "0", respectively, independently of the first likelihood value data item 426.

[0134] In some embodiments, the plurality of data items include the first likelihood value data item 426 corresponding to the first code symbol, the second likelihood value data item 428 corresponding to the second code symbol, and the second index data item identifying one of the subset of code symbols corresponding to the second likelihood value data item 428 of the check node data 422; the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426; and determining the set of data bits 1002 further includes selecting only one of the MSB of the first likelihood value data item 426 and the LSB of the second index data item to include in the set of data bits 1002 based on the MSB of the second likelihood value data item 428. Moreover, in some embodiments, selecting only one of the MSB of the first likelihood value data item 426 and the LSB of the second index data item further includes determining the set of data bits 1002 based on the LSB of the second index data item and independently of the MSB of the first likelihood value data item 426 according to a determination that the MSB of the second likelihood value data item 428 is equal to "0"; and determining the set of data bits 1002 based on the MSB of the first likelihood value data item 426 and independently of the LSB of the second index data item according to a determination that the MSB of the second likelihood value data item 428 is equal to "1".

[0135] In some embodiments, the second number is one or two less than a sum of the first number of each of the plurality of data items, thereby saving one or two bits for storing the check node data 422.

[0136] In some embodiments, the subset of code symbols corresponds to a set of likelihood value data items, each indicating a likelihood value that a respective code symbol is in error. The electronic device identifies the first likelihood value data item 426 and the second likelihood value data item 428 according to a determination that the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426 and less than or equal to a remaining likelihood value data item of the subset of code symbols. Moreover, in some embodiments, each likelihood value data item of the respective code symbol is determined based on a log-likelihood ratio (LLR) approximated by equation (6).

[0137] In some embodiments, at step 1820, the plurality of data items further includes at least one of: a first index data item 430 identifying one of the code symbol subset corresponding to the first likelihood value data item 426 of the check node data 422, and a second index data item 432 identifying one of the code symbol subset corresponding to the second likelihood value data item 428 of the check node data 422.

[0138] In some embodiments, each code symbol of the code symbol subset corresponds to a respective likelihood value data item indicating a likelihood value that the respective code symbol is in error, and wherein the check node data 422 of the check node 402 further includes a syndrome bit that is a combination of the signs of the respective likelihood value data items of the code symbol subset.

[0139] The memory is further for storing instructions and data associated with the method 1800, and includes a high-speed random access memory, such as DRAM, SRAM or other random access solid state storage devices; and optionally includes non-volatile memory, such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash devices, or one or more other non-volatile solid state storage devices. The memory optionally includes one or more storage devices remotely located from the one or more processing units. The memory, or alternatively the non-volatile memory within the memory, comprises a non-transitory computer readable storage medium. In some embodiments, the memory, or non-transitory computer readable storage medium of the memory, stores programs, modules, and data structures, or a subset or superset thereof, used to implement the method 1800.

[0140] Some implementations of the present application relate to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of code symbols in a data block, and determines check node data indicating likelihood values that the subset of code symbols is in error. A set of data bits is determined based on a combination of values of data items of the check node data to uniquely identify the combination of values among a set of selected combinations of values according to a predefined relationship. The electronic device stores the set of data bits representing the data items of the check node data for the check node in a storage block. Each data item requires more data bits to represent all possible values of the respective data item than the data bits in the set of data bits. More specifically, some implementations of the present application are described in the following clauses: Clause 1. A method implemented at an electronic device for compressing check node data, the method comprising: identifying a check node corresponding to a subset of code symbol in a data block; determining check node data containing a plurality of data items, wherein the check node data indicates a likelihood value of the subset of code symbol being erroneous; determining a set of data bits based on a value combination of the plurality of data items, wherein the set of data bits uniquely identifies the value combination among a set of selected value combinations according to a predefined relationship; and storing the set of data bits representing the plurality of data items of the check node data of the check node in a storage block; wherein each of the plurality of data items requires at least a first number of data bits to represent all possible values of a respective data item, and the set of data bits has a second number of data bits, which is less than a sum of the first number of each of the plurality of data items.

[0141] Clause 2. The method of clause 1, wherein the plurality of data items corresponds to a total number of possible value combinations, and a binary data item representing the total number has more bits than the set of data bits.

[0142] Clause 3. The method of clause 1 or 2, wherein: the plurality of data items contains a first likelihood value data item corresponding to a first code symbol and a second likelihood value data item corresponding to a second code symbol, and the second likelihood value data item is greater than or equal to the first likelihood value data item; and the set of selected value combinations is complementary to a set of eliminated value combinations.

[0143] Clause 4. The method of clause 3, determining the set of data bits further comprising: in accordance with a determination that the value combination belongs to the set of eliminated value combinations: approximating the second likelihood value data item with a neighboring value available while keeping a value of the first likelihood value data item; updating the value combination of the plurality of data items based on the approximation of the second likelihood value data item; and determining the set of data bits based on the updated value combination.

[0144] Clause 5. The method of any of clauses 1-4, wherein for each selected value combination in the set of selected value combinations, the first likelihood value data item is within a first range of values, and the second likelihood value data item is within a second range of values.

[0145] Clause 6. The method of clause 5, wherein the first range of values contains one or more non-contiguous first data sub-ranges, one or more predefined first data values, or a combination thereof, and the second range of values contains one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof.

[0146] Clause 7. The method of any one of clauses 1-6, wherein, for each selected value combination of the set of selected value combinations, the second likelihood value data item in the second value range comprises one or more non-consecutive second data sub-ranges, one or more predefined second data values, or a combination thereof.

[0147] Clause 8. The method of any one of clauses 1-7, wherein the second likelihood value data item has a most significant bit (MSB) and a least significant bit (LSB), and, for each selected value combination of the set of selected value combinations, the MSB and the LSB of the second likelihood value data item are not equal to “1” and “0,” respectively, independently of the first likelihood value data item.

[0148] Clause 9. The method of any one of clauses 1-8, wherein: the plurality of data items comprise a first likelihood value data item corresponding to a first code symbol, a second likelihood value data item corresponding to a second code symbol, and a second index data item identifying one of the code symbols in the subset of code symbols corresponding to the second likelihood value data item of the check node data; the second likelihood value data item is greater than or equal to the first likelihood value data item; and determining the set of data bits further comprises: based on a MSB of the second likelihood value data item, only selecting one of a MSB of the first likelihood value data item and a LSB of the second index data item to include in the set of data bits.

[0149] Clause 10. The method of clause 9, only selecting one of the MSB of the first likelihood value data item and the LSB of the second index data item further comprises: in accordance with a determination that the MSB of the second likelihood value data item is equal to “0,” determining the set of data bits based on the LSB of the second index data item and independently of the MSB of the first likelihood value data item; and in accordance with a determination that the MSB of the second likelihood value data item is equal to “1,” determining the set of data bits based on the MSB of the first likelihood value data item and independently of the LSB of the second index data item.

[0150] Clause 11. The method of any one of clauses 1-10, wherein the second number is one or two less than a sum of the first number of each of the plurality of data items, thereby saving one or two bits for storing the check node data.

[0151] Clause 12. The method of any of clauses 1-11, wherein the subset of code symbols corresponds to a set of likelihood value data items, each likelihood value data item indicating a likelihood value that a respective code symbol is erroneous, and wherein the method further comprises: in accordance with a determination that a second likelihood value data item is greater than or equal to a first likelihood value data item and less than or equal to a remaining likelihood value data item of the subset of code symbols, identifying the first and second likelihood value data items.

[0152] Clause 13. The method of clause 12, wherein each likelihood value data item of the respective code symbol is determined based on a log likelihood ratio (LLR) approximated as follows:

[0153] wherein p (|) is a probability of a combination of data values, x is a value stored for the respective code symbol, and y is a correct value of the respective code symbol.

[0154] Clause 14. The method of any of clauses 1-13, wherein the plurality of data items further include at least one of: a first index data item identifying one code symbol of the subset of code symbols corresponding to a first likelihood value data of the check node data, and a second index data item identifying one code symbol of the subset of code symbols corresponding to a second likelihood value data of the check node data.

[0155] Clause 15. The method of any of clauses 1-14, wherein each code symbol of the subset of code symbols corresponds to a respective likelihood value data item indicating a likelihood value that the respective code symbol is erroneous, and wherein the check node data of the check node further includes a sign bit that is a combination of signs of the respective likelihood value data items of the subset of code symbols.

[0156] Clause 16. An electronic device, comprising: one or more processors; and memory storing instructions thereon that, when executed by the one or more processors, cause the processors to perform the method of any of clauses 1-15.

[0157] Clause 17. A non-transitory computer-readable storage medium having instructions stored thereon, the instructions, when executed by one or more processors, cause the processors to perform the method of any of clauses 1-15.

[0158] Reconfiguring registers for different low density parity checks

[0159] Figure 19This illustrates temporary storage in a storage block (e.g., according to some embodiments) Figure 2 The diagram illustrates two example data structures 1900 for the check node data 422 in register 232. Based on two different data structures 1900A and 1900B, the same storage block is adaptively applied to store the check node data 422. The data block corresponds to a plurality of first check nodes 402A, and each first check node 402A corresponds to a subset of the first code character symbols of the data block and has corresponding first check node data 422A, which indicates the likelihood that the first code character symbol subset is incorrect. Based on the first data structure 1900A, storage blocks are allocated to store the first check node data 422A of the plurality of first check nodes 402A. For example, via... Figure 2 The integrity engine 230 regroups the data bits of the data block to form a plurality of second check nodes 402B. Each second check node 402B (e.g., 402B-1, 402B-2, or other second check nodes not shown) corresponds to a subset of the second code characters of the data block and has corresponding second check node data 422B (e.g., 422B-1, 422B-2, or other second node data not shown), which indicates the likelihood value of the second code character subset being incorrect. According to the second data structure 1900B, the storage block is reconfigured to store the second check node data 422B of the plurality of second check nodes 402B. The plurality of second check nodes 402B has a different number of check nodes than the plurality of first check nodes 402A.

[0160] In some embodiments, the first check node 402A has a greater number of check nodes than the second check node 402B. For simplicity, in this example, the data block contains 1280 code characters and corresponds to 40 first check nodes 402A, each of which is associated with 32 code characters. For each first check node 402A, the 32 code characters are identified by a 5-bit first index data item 430 (i.e., z=4 in the first index data item 430). Check node data 422A of the 40 first check nodes 402A is organized according to a first data structure 1900A. The 1280 code characters are regrouped according to the 32 second check nodes 402B, each of which is associated with 40 code characters. For each second check node 402B, the 40 code characters are identified by a 6-bit first index data item 430, for example, requiring an additional data bit for the first index data item 430. The second data structure 1900B organizes 32 second check nodes 402B of second check node data 422B.

[0161] In some embodiments, the integrity engine 230 identifies one or more excess check nodes 402A-1 and 402A-2 of the plurality of first check nodes 402A. The excess check node data 422A of the one or more excess check nodes 402A-1 and 402A-2 forms the plurality of excess bits 1902. The plurality of excess bits 1902 is reassigned to store the second check node data 422B-1 or 422B-2 of the plurality of second check nodes 402B. Further, in some embodiments, the plurality of excess bits 1902 is reassigned by assigning a first set of excess bits 1902A of the excess check node data of the first excess check node 402A-1 to store the second check node data 422B-1 of a first subset of the plurality of second check nodes 402B, and assigning a second set of excess bits 1902B of the excess check node data of the second excess check node 402A-2 to store the second check node data 422B-1 of the first subset or a second subset of the plurality of second check nodes 402B. For example, the set of excess bits 1902A created by the first check node 402A-1 is used to add one bit to the first index data item 430 of a subset or all of the second check nodes 402B (e.g., Minl index [5]), and the set of excess bits 1902B created by the first check node 402A-1 is used to add one or more bits to a subset or all of the second index data item 432 of a subset or all of the second check nodes 402B.

[0162] In some embodiments, the plurality of excess bits 1902 contains at least one remaining bit 1904 that is not assigned to any second check node data 422B of the plurality of second check nodes 402B. In some embodiments, a set of excess check nodes (e.g., 402A-1 and 402A-2) is identified in the plurality of first check nodes 402A to provide the plurality of excess bits 1902, and a respective subset of the plurality of excess bits is assigned to the second check node data of each second check node 402B (e.g., Minl index [5]).

[0163] In other words, in some embodiments, a first subset of code symbols corresponding to each first check node 402A contains a first number of code symbols, and a second subset of code symbols corresponding to each second check node 402B contains a second number of code symbols. The first number is less than the second number. An excess check node 402A-1 or 402A-2 has excess check node data that contains a plurality of excess bits 1902. The plurality of excess bits 1902 is assigned to index data items 430 or 432 of second check node data 422B of the plurality of second check nodes 402B.

[0164] In some embodiments, the second check nodes 402B have a greater number of check nodes than the first check nodes 402A. For simplicity, in the example, the data block contains 1280 code symbols and corresponds to 32 first check nodes 402A, each of which is associated with 40 code symbols. For each first check node 402A, the 40 code symbols are identified by a 6-bit first index data item 430 (i.e., z = 5 in the first index data item 430). The check node data 422A for the 32 first check nodes 402A is organized according to the first data structure 1900A. The 1280 code symbols are re-grouped according to 40 second check nodes 402B, each of which is associated with 32 code symbols. For each second check node 402B, the 32 code symbols are identified by a 5-bit first index data item 430, for example, saving one excess data bit from each first index data item 430. The second check node data 422B for the 40 second check nodes 402B is organized according to the second data structure 1900B.

[0165] In some embodiments, the integrity engine 230 identifies one or more excess bits 1906 (e.g., the Minl index [5] of the first index data item 430) in the respective first check node data 422A of each of the plurality of first check nodes 402A. The excess bits 1906 of the respective first check node data 422A of a first subset (e.g., less than all, all) of the plurality of first check nodes 402A are grouped to store additional check node data 422B of additional check nodes 402B of the plurality of second check nodes 402B. Specifically, in some embodiments, one excess bit (e.g., the Minl index [5] of the first index data item 430) is identified in the respective first check node data 422A of each of the plurality of first check nodes 402A, and the excess bits 1906 of the respective first check node data of the plurality of first check nodes are grouped to store additional check node data of two or more additional check nodes (including additional check nodes 402B-1 or 402B-2) of the plurality of second check nodes 402B. For example, the Minl index [5] of the first index data item 430 of each of the check nodes 402A is merged and applied to store the sign bit 424, the first likelihood value data item 426, the second likelihood value data item 428, and the first index data item 430 of the additional check nodes 402B-1 or 402B-2. In another example, two or more bits 1906 of the first index data item 430 of each of the check nodes 402A are merged and applied to store the check node data of one or more additional check nodes 402B. In some embodiments, the data items 424, 426, 428, and 430 of the additional check nodes 402B-1 or 402B-2 are stored in a distributed manner in a subset of the second check node data 422B that is converted from the first check node data 422A and corresponds to the first check node data.

[0166] In some embodiments, the additional check nodes include a first additional check node 402B-1. The excess bits 1906 of the respective first check node data of a second subset (e.g., less than all, all) of the plurality of first check nodes 402A are pooled together to store additional check node data 422B of the first additional check node 402A-1 or the second additional check node 402B-2 of the plurality of second check nodes 402B. For example, the first unused excess bits 1906 of the first index data item 430 of the first 50 check nodes 402A are pooled and applied to store the check node data 422B of the check node 402B-1, and the second distinct excess bits 1906 of the first index data item 430 of the remaining 50 check nodes 402A are pooled and applied to store the check node data 422B of the check node 402B-2. In another example, the first unused excess bits 1906 of the first index data item 430 of all check nodes 402A are pooled and applied to store the check node data 422B of the check node 402B-1, and the second distinct excess bits 1906 of the first index data item 430 of all check nodes 402A are pooled and applied to store the check node data 422B of the check node 402B-2.

[0167] In some embodiments, for a third subset of the plurality of first check nodes 402A, a subset or all of the excess bits of the respective first check node data 422A are not reassigned for storing any additional check node data 422B of the plurality of second check nodes 422B.

[0168] In some embodiments, for each of the plurality of first check nodes 402A and the plurality of second check nodes 402B, the respective check node data 422 includes a first likelihood value data item 426 and an index data item 430 identifying one of the respective subset of code symbols corresponding to the first likelihood value data item 426. Further, in some embodiments, the first subset of code symbols corresponding to each first check node 402A includes a first number of code symbols, and the second subset of code symbols corresponding to each second check node 402B includes a second number of code symbols. The first number is greater than the second number. The index data item 430 of each of the plurality of first check nodes 402A includes at least one excess bit (e.g., at 1906) over the index data item 430 of each of the plurality of second check nodes 402B to address the first number of code symbols. The at least one excess bit of each of the plurality of first check nodes 402A forms a plurality of excess bits 1906 that are reconfigured to store the second check node data 422B of at least one additional second check node 402B-1 or 402B-2.

[0169] In some embodiments, integrity engine 230 includes a min-sum and decoder to implement LDPC min-sum based decoding. Referring to FIG. 4, in LDPC decoding, each check node 402 stores an index (i.e., first index data item 430) of a variable node 404 that provides a min message value (i.e., first likelihood value data item 426). The range of the index depends on the number of variable nodes 404 connected to check node 402 in Tanner graph 400. The number of variable nodes 404 connected to each check node 402 is referred to as the check node degree or row weight of the parity check H matrix. When integrity engine 230 reuses the same min-sum decoder hardware for different LDPC codes, there is a tradeoff between the number of check nodes and the number of min value index bits (e.g., of index data items 430 or 432), resulting in a lower total number of flip-flops by having fewer min value index bits when more check nodes are needed.

[0170] In some embodiments, integrity engine 230 reuses the same hardware (e.g., logic and registers) to decode different LDPC codes. Some LDPC matrices require 6 bits for first likelihood value data item 426, while some require 7 bits, depending on the row weight of the H matrix. In some cases, LDPC matrices with higher code rates have fewer check nodes and higher row weights, resulting in more bits being needed in first index data item 430. For example, integrity engine 230 uses multiplexers to use the same flip-flops for check nodes with 6-bit index data items 430 or for a small number of check nodes with more than 6-bit index data items 430. More specifically, in an example, integrity engine 230 saves 1 bit of storage space in registers 232 for each check node 402. Thus, the compression of MSBs for a subset of check nodes helps to save expensive register space for integrity check system 300.

[0171] Figure 20 FIG. 20 is a flowchart of a method 2000 for adaptively storing check node data 422 in an electronic device, according to some embodiments. Method 2000 is performed by a processor, such as processor 202, in an electronic device, such as electronic device 100. In some embodiments, method 2000 is performed by integrity engine 230. Method 2000 begins when processor 202 receives a request to decode a LDPC code (2002). For example, integrity engine 230 receives a request to decode a LDPC code from a host processor, such as processor 202. Figure 2This is implemented at an electronic device. In step 2002, the electronic device obtains data blocks corresponding to a plurality of first check nodes 402A. In step 2004, each first check node corresponds to a first code character subset of the data block and has corresponding first check node data 422A, the corresponding first check node data indicating the likelihood value of the first code character subset being incorrect. In step 2006, the electronic device identifies a storage block allocated for storing the first check node data of the plurality of first check nodes 402A. In step 2008, the electronic device regroups the data bits of the data block to form a plurality of second check nodes 402B. In step 2010, each second check node 402B corresponds to a second code character subset of the data block and has corresponding second check node data 422B, the corresponding second check node data indicating the likelihood value of the second code character subset being incorrect. In step 2012, the electronic device reconfigures the storage block to store the second check node data of the plurality of second check nodes 402B. In step 2014, the plurality of second verification nodes 402B have a different number of verification nodes than the plurality of first verification nodes 402A.

[0172] In some embodiments, in step 2016, the electronic device identifies one or more excess bits 1906 in the corresponding first check node data 422A of each of the plurality of first check nodes 402A. In step 2018, the electronic device groups the excess bits 1906 of the corresponding first check node data 422A of a first subset of the plurality of first check nodes 402A to store additional check node data of additional check nodes 402B-1 or 402B-2 of the plurality of second check nodes 402B. Furthermore, in some embodiments, the additional check node includes a first additional check node 402B-1. The electronic device groups the excess bits 1906 of the corresponding first check node data 422A of a second subset of the plurality of first check nodes 402A to store additional check node data of a second additional check node 402B-2 of the plurality of second check nodes 402B. In some embodiments, for a third subset of the plurality of first check nodes 402A, a subset or all of the excess bits of the corresponding first check node data 422A are not reassigned to store any additional check node data of the plurality of second check nodes 402B. In some embodiments, an excess bit 1906 is identified in the corresponding first check node data 422A of each of the plurality of first check nodes 402A, and the excess bits 1906 of the corresponding first check node data 422A of the plurality of first check nodes 402A are grouped to store the additional check node data of two or more additional check nodes 402B-1 or 402B-2 (containing additional check nodes) of the plurality of second check nodes 402B.

[0173] In some embodiments, at step 2020, the electronic device identifies one or more excess check nodes 402A-1 or 402A-2 in the plurality of first check nodes 402A. The excess check node data of the one or more excess check nodes 402A-1 or 402A-2 forms a plurality of excess bits 1902. At step 2022, the electronic device assigns the plurality of excess bits 1902 to the second check node data 422B of the plurality of second check nodes 402B. Further, in some embodiments, assigning the plurality of excess bits 1902 to the second check node data 422B of the plurality of second check nodes 402B also includes: (1) assigning a first set of excess bits 1902A of the excess check node data of a first excess check node to store the second check node data 422B of a first subset of the plurality of second check nodes 402B; and (2) assigning a second set of excess bits 1902B of the excess check node data of a second excess check node to store the second check node data 422B of a second subset of the plurality of second check nodes 402B. In some embodiments, the plurality of excess bits 1902 includes at least one remaining bit 1904 that is not assigned to any second check node data 422B of the plurality of second check nodes 402B. In some embodiments, one excess check node is identified in each of the plurality of first check nodes 402A to provide the plurality of excess bits, and a respective subset of the plurality of excess bits is assigned to the second check node data of each second check node.

[0174] In some embodiments, for each of the first plurality of check nodes 402A and the second plurality of check nodes 402B, the respective check node data includes a first likelihood value data item 426 and an index data item 430 that identifies one of the code symbol subset corresponding to the first likelihood value data item 426. Further, in some embodiments, the first code symbol subset includes a first number of code symbols and the second code symbol subset includes a second number of code symbols. The first number is greater than the second number. The index data item 430 of each of the first plurality of check nodes 402A includes at least one excess bit 1906 over the index data item of each of the second plurality of check nodes 402B to address the first number of code symbols. The at least one excess bit 1906 of each of the first plurality of check nodes 402A forms a plurality of excess bits 1906 that are reconfigured to store second check node data 422B of at least one additional second check node 402B-1 or 402B-2. In some embodiments, the first code symbol subset includes a first number of code symbols and the second code symbol subset includes a second number of code symbols. The first number is less than the second number. The excess check node 402A-1 or 402A-2 has excess check node data 422A that includes a plurality of excess bits 1902; and the plurality of excess bits 1902 are assigned to the index data item 430 or 432 of the second check node data 422B of the second plurality of check nodes 402B.

[0175] In some embodiments, for each of the first check node and the second check node, the subset of code symbols corresponds to a set of likelihood value data items. Each likelihood value data item indicates a likelihood value that a respective code symbol is in error. The electronic device identifies the first likelihood value data item 426 and the second likelihood value data item 428 in accordance with a determination that the second likelihood value data item 428 is greater than or equal to the first likelihood value data item 426 and less than or equal to a remaining likelihood value data item of the subset of code symbols. Further, in some embodiments, each likelihood value data item of the respective code symbol is determined based on a log likelihood ratio (LLR) approximated by equation (6).

[0176] In some embodiments, for each of the first check node and the second check node, the check node data of the respective check node further includes a first index data item that identifies one of the subset of code symbols corresponding to the first likelihood value data of the check node data 422.

[0177] In some embodiments, each code symbol of the subset of code symbols corresponds to a respective likelihood value data item that indicates a likelihood value that the respective code symbol is in error. The check node data of the check node further includes a sign bit that is a combination of the signs of the respective likelihood value data items of the subset of code symbols.

[0178] The memory is further used to store instructions and data associated with the method 2000, and includes a high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state storage devices; and optionally includes non-volatile memory, such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid state storage devices. The memory optionally includes one or more storage devices remotely located from the one or more processing units. The memory, or alternatively the non-volatile memory within the memory, comprises a non-transitory computer readable storage medium. In some embodiments, the memory, or the non-transitory computer readable storage medium of the memory, stores programs, modules, and data structures, or a subset or superset thereof, utilized by the method 2000.

[0179] Some implementations of the present application relate to adaptively storing check node data in an electronic device. The electronic device obtains data blocks corresponding to first check nodes, each of the first check nodes having respective first check node data indicating a likelihood value that a first subset of code symbols of the data blocks is erroneous. The electronic device identifies a storage block allocated to store the first check node data of the first check nodes, and re-groups data bits of the data blocks to form second check nodes. Each second check node has respective second check node data indicating a likelihood value that a second subset of code symbols of the data blocks is erroneous. The electronic device reconfigures the storage block to store the second check node data of the second check nodes. The second check nodes have a number of check nodes that is different from the first check nodes. More specifically, some implementations of the present application are described in the following clauses: Clause 1. A method for adaptively storing check node data implemented at an electronic device, the method comprising: obtaining data blocks corresponding to a plurality of first check nodes, wherein each first check node corresponds to a first subset of code symbols of the data blocks and has respective first check node data indicating a likelihood value that the first subset of code symbols is erroneous; identifying a storage block allocated to store the first check node data of the plurality of first check nodes; re-grouping data bits of the data blocks to form a plurality of second check nodes, each second check node corresponding to a second subset of code symbols of the data blocks and having respective second check node data indicating a likelihood value that the second subset of code symbols is erroneous; and reconfiguring the storage block to store second check node data of the plurality of second check nodes, the plurality of second check nodes having a number of check nodes that is different from the plurality of first check nodes.

[0180] Clause 2. The method of clause 1, further comprising: identifying one or more excess bits in the respective first check node data of each of the plurality of first check nodes; and grouping excess bits of the respective first check node data of a first subset of the plurality of first check nodes to store additional check node data of an additional check node of the plurality of second check nodes.

[0181] Clause 3. The method of clause 2, wherein the additional check node comprises a first additional check node, and the method further comprises: grouping excess bits of the respective first check node data of a second subset of the plurality of first check nodes to store additional check node data of a second additional check node of the plurality of second check nodes.

[0182] Clause 4. The method of clause 2 or 3, wherein for a third subset of the plurality of first check nodes, none of the excess bits of the respective first check node data are reassigned for storing any additional check node data of the plurality of second check nodes.

[0183] Clause 5. The method of any of clauses 2-4, wherein one excess bit is identified in the respective first check node data of each of the plurality of first check nodes, and the excess bits of the respective first check node data of the plurality of first check nodes are grouped to store the additional check node data of two or more additional check nodes of the plurality of second check nodes, including the additional check node.

[0184] Clause 6. The method of clause 1, further comprising: identifying one or more excess check nodes of the plurality of first check nodes, excess check node data of the one or more excess check nodes forming a plurality of excess bits; and assigning the plurality of excess bits to second check node data of the plurality of second check nodes.

[0185] Clause 7. The method of clause 6, assigning the plurality of excess bits to the second check node data of the plurality of second check nodes further comprising: assigning a first set of excess bits of excess check node data of a first excess check node to store the second check node data of a first subset of the plurality of second check nodes; and assigning a second set of excess bits of the excess check node data of a second excess check node to store the second check node data of a second subset of the plurality of second check nodes.

[0186] Clause 8. The method of clause 6 or 7, wherein the plurality of excess bits includes at least one remaining bit that is not assigned to any of the second check node data of the plurality of second check nodes.

[0187] Clause 9. The method of any one of clauses 6-8, wherein one excess check node is identified in each of the plurality of first check nodes to provide the plurality of excess bits, and a respective subset of the plurality of excess bits is assigned to the second check node data of each second check node.

[0188] Clause 10. The method of any one of clauses 1-9, wherein for each of the plurality of first check nodes and the plurality of second check nodes, the respective check node data includes a first likelihood value data item and an index data item identifying one code symbol of the respective subset of code symbols corresponding to the first likelihood value data item.

[0189] Clause 11. The method of clause 10, wherein: the first subset of code symbols includes a first number of code symbols and the second subset of code symbols includes a second number of code symbols, wherein the first number is greater than the second number; the index data item of each of the plurality of first check nodes includes at least one bit in excess of the index data item of each of the plurality of second check nodes to address the first number of code symbols; and the at least one excess bit of each of the plurality of first check nodes forms a plurality of excess bits that are reconfigured to store the second check node data of at least one additional second check node.

[0190] Clause 12. The method of clause 10, wherein: the first subset of code symbols includes a first number of code symbols and the second subset of code symbols includes a second number of code symbols, wherein the first number is less than the second number; an excess check node has excess check node data including a plurality of excess bits; and the plurality of excess bits are assigned to index data items of second check node data of the plurality of second check nodes.

[0191] Clause 13. The method of any one of clauses 1-12, wherein for each check node, a corresponding subset of code symbols corresponds to a set of likelihood value data items, each likelihood value data item indicating a likelihood value that a respective code symbol is erroneous, and wherein the method further comprises: identifying a first likelihood value data item and a second likelihood value data item in accordance with a determination that the second likelihood value data item is greater than or equal to the first likelihood value data item and less than or equal to a remaining likelihood value data item of the subset of code symbols.

[0192] Clause 14. The method of clause 13, wherein each likelihood value data item of the respective subset of code symbols is determined based on a log-likelihood ratio (LLR) represented as follows:

[0193] wherein p (|) is a probability of a combination of data values, x is a value stored for the respective code symbol, and y is a correct value of the respective code symbol.

[0194] Clause 15. The method of any of clauses 1-14, wherein, for each check node, the check node data of the check node further includes a first index data item that identifies one code symbol of the subset of code symbols that corresponds to the first likelihood value data of the check node data.

[0195] Clause 16. The method of any of clauses 1-15, wherein each code symbol of the subset of code symbols corresponds to a respective likelihood value data item that indicates a likelihood that the respective code symbol is erroneous, and wherein the check node data of the check node further includes a sign bit that is a combination of signs of the respective likelihood value data items of the subset of code symbols.

[0196] Clause 17. An electronic device, comprising: one or more processors; and memory having instructions stored thereon that, when executed by the one or more processors, cause the processors to perform the method of any of clauses 1-16.

[0197] Clause 18. A non-transitory computer-readable storage medium having instructions stored thereon that, when executed by one or more processors, cause the processors to perform the method of any of clauses 1-16.

[0198] Each of the above elements can be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The modules identified above, i.e., sets of instructions need not be implemented as separate software programs, procedures, modules or data structures, and thus various subsets of these modules can be combined or otherwise rearranged in various embodiments. In some embodiments, the memory optionally stores a subset of the modules and data structures identified above. Furthermore, the memory optionally stores additional modules and data structures not described above.

[0199] The terminology used in the description of the various implementations described herein is for the purpose of describing particular implementations only and is not intended to be limiting. In describing various described implementations and the accompanying drawings, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used herein, refer to and encompass any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, it is to be understood that the term "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to denote one element from another.

[0200] As used herein, the term "if' can be construed to mean "when" or "while" or "in response to the determination" or "in response to the detection" or "upon the determination" depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be construed to mean "upon the determination" or "in response to the determination" or "upon the detection [of a stated condition or event]" or "in response to the detection [of a stated condition or event]" or "upon the

[0201] The foregoing description, for purposes of explanation, has been described with reference to specific embodiments. The illustrative discussion, however, is not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teaching. The embodiments were chosen and described in order to best explain the principles of operation and their practical application, to thereby enable others skilled in the art to best utilize the embodiments.

[0202] While the various figures illustrate a number of logical stages in a particular order, stages that are not required or implicit in the specification can be reordered and other stages can be added or broken out, etc. And, while a particular ordering was described with regard to the examples, other orderings can be used. Some reorderings or other groupings can be addressed to specific reordering or other groupings will be apparent to those of ordinary skill in the art and it is intended to embrace all such orderings and groupings. Further, it will be recognized that the stages could be implemented in hardware, software, firmware, or any combination thereof, and that the order in which the stages are presented is not limiting.

Claims

1. A method implemented at an electronic device for compressing check node data, the method comprising: identifying a check node corresponding to a subset of code symbol in a data block; determining check node data containing a plurality of data items, wherein the check node data indicates a likelihood value of the subset of code symbol being erroneous; determining a set of data bits based on a value combination of the plurality of data items, wherein the set of data bits uniquely identifies the value combination among a set of selected value combinations according to a predefined relationship; and storing the set of data bits representing the plurality of data items of the check node data of the check node in a storage block; wherein each of the plurality of data items requires at least a first number of data bits to represent all possible values of a respective data item, and the set of data bits has a second number of data bits, the second number being less than a sum of the first number of each of the plurality of data items.

2. The method of claim 1, wherein the plurality of data items corresponds to a total number of possible value combinations, and a binary data item representing the total number has more bits than the set of data bits.

3. The method of claim 1 or 2, wherein: the plurality of data items contains a first likelihood value data item corresponding to a first code symbol and a second likelihood value data item corresponding to a second code symbol, and the second likelihood value data item is greater than or equal to the first likelihood value data item; and the set of selected value combinations is complementary to a set of eliminated value combinations.

4. The method of claim 3, determining the set of data bits further comprises: based on a determination that the value combination belongs to the set of eliminated value combinations: approximating the second likelihood value data item with a neighboring value available while keeping a value of the first likelihood value data item; updating the value combination of the plurality of data items based on the approximation of the second likelihood value data item; and determining the set of data bits based on the updated value combination.

5. The method of any one of claims 1 to 4, wherein for each selected value combination in the set of selected value combinations, the first likelihood value data item is within a first range of values, and the second likelihood value data item is within a second range of values.

6. The method of claim 5, wherein the first range of values contains one or more non-contiguous first data sub-ranges, one or more predefined first data values, or a combination thereof, and the second range of values contains one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof.

7. The method of any one of claims 1 to 6, wherein for each selected value combination in the set of selected value combinations, the second likelihood value data item in a second range of values contains one or more non-contiguous second data sub-ranges, one or more predefined second data values, or a combination thereof.

8. The method of any one of claims 1-7, wherein the second likelihood value data item has a most significant bit (MSB) and a least significant bit (LSB), and for each selected value combination of the set of selected value combinations, the MSB and the LSB of the second likelihood value data item are not equal to "1" and "0", respectively, independent of the first likelihood value data item.

9. The method of any one of claims 1-8, wherein: the plurality of data items include a first likelihood value data item corresponding to a first code symbol, a second likelihood value data item corresponding to a second code symbol, and a second index data item identifying one of the subset of code symbols corresponding to the second likelihood value data item of the check node data; the second likelihood value data item is greater than or equal to the first likelihood value data item; and determining the set of data bits further includes selecting only one of a MSB of the first likelihood value data item and a LSB of the second index data item for inclusion in the set of data bits based on the MSB of the second likelihood value data item.

10. The method of claim 9, selecting only one of the MSB of the first likelihood value data item and the LSB of the second index data item further includes: determining the set of data bits based on the LSB of the second index data item and independent of the MSB of the first likelihood value data item in accordance with a determination that the MSB of the second likelihood value data item is equal to "0"; or determining the set of data bits based on the MSB of the first likelihood value data item and independent of the LSB of the second index data item in accordance with a determination that the MSB of the second likelihood value data item is equal to "1".

11. The method of any one of claims 1-10, wherein the second number is one or two less than a sum of the first number of each of the plurality of data items, thereby saving one or two bits for storing the check node data.

12. The method of any one of claims 1-11, wherein the subset of code symbols corresponds to a set of likelihood value data items, each indicating a likelihood value that a respective code symbol is in error, one or more programs including instructions for: identifying the first likelihood value data item and a second likelihood value data item in accordance with a determination that the second likelihood value data item is greater than or equal to the first likelihood value data item and less than or equal to a remaining likelihood value data item of the subset of code symbols.

13. The method of claim 12, wherein each likelihood value data item of the respective code symbol is determined based on a log likelihood ratio (LLR) approximated as follows: wherein p (|) is the probability of the data value combination, x is the stored value for the respective code symbol, and y is the correct value of the respective code symbol.

14. The method of any one of claims 1-13, wherein the plurality of data items further include at least one of: a first index data item that identifies one of the subset of code symbol corresponding to the first likelihood value data of the check node data, and a second index data item that identifies one of the subset of code symbol corresponding to the second likelihood value data of the check node data.

15. The method of any one of claims 1-14, wherein each of the subset of code symbols corresponds to a respective likelihood value data item that indicates a likelihood value that the respective code symbol is in error, and wherein the check node data of the check node further includes a sign bit that is a combination of the signs of the respective likelihood value data items of the subset of code symbols.

16. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed by one or more processors, cause the processors to perform the method of any one of claims 1-15.

17. An electronic device, comprising: one or more processors; and memory having stored thereon instructions that, when executed by the one or more processors, cause the processors to perform the method of any one of claims 1-15. ​

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