Firmware configuration management method, device and equipment and readable storage medium

Abstract

The invention provides a firmware configuration management method, device and equipment and a readable storage medium, and the method comprises the steps: responding to a starting event, running an SBR file, and obtaining the state of a target GPIO pin, the target GPIO pin is connected to a corresponding GPIO pin of a management chip, and the corresponding GPIO pin of the management chip enables a firmware configuration function; obtaining an index value according to the state of the target GPIO pin; and comparing the index value corresponding to the currently running SBR file according to the index value, and keeping or replacing the SBR file according to an associated or non-associated comparison result. Through the technical scheme of the invention, the GPIO pin state dynamically selects the matched configuration, so that the single universal firmware can adapt to various port connection topologies, and the firmware reusability and the system maintenance efficiency are remarkably improved while the PCIe link performance is ensured.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a firmware configuration management method, apparatus, device, and readable storage medium. Background Technology

[0002] Currently, mainstream GPU servers generally adopt a CPU-SW-GPU interconnect architecture. The combined switching mode (SSw MODE) is a common operating mode for PCIe switching chips (PCIe SW). This mode requires firmware (FW) to drive the internal Arm processor of the chip, typically stored in external flash memory, to achieve key functions such as port allocation, speed, and bandwidth configuration of the SW chip. However, in practical applications, due to the need to control hardware link loss in single-board layout, the port allocation methods of different SW chips are often difficult to unify, resulting in a lack of uniformity in the FWs that need to be programmed into the SW chips. This situation brings many problems: when firmware upgrades are needed, multiple different FWs must be updated separately, which is not only cumbersome but also carries the risk of mismatch between the FW and the actual installation location of the SW chip during repairs; when the server topology changes, a complete set of corresponding FWs needs to be redeveloped, increasing the manpower cost of software development and extending the entire project cycle, seriously affecting product development efficiency and market responsiveness. Summary of the Invention

[0003] In view of this, this specification provides a firmware configuration management method, apparatus, device, and readable storage medium to improve the aforementioned problem of firmware lack of uniformity.

[0004] The specific technical solution is as follows: This specification provides a firmware configuration management method applied to a PCIe switching chip. The PCIe switching chip is programmed with general firmware, which is used to be programmed to several PCIe switching chips with the same or different port connection configurations. The general firmware stores several sets of SBR sequence boot record files. The SBR files include port attribute configurations. The method includes: in response to a boot event, running the SBR file, obtaining the state of a target GPIO pin, the target GPIO pin being connected to a corresponding GPIO pin of a management chip, and enabling firmware configuration functions on the corresponding GPIO pin of the management chip; obtaining an index value based on the state of the target GPIO pin, the index value being used to indicate the current port connection configuration of the PCIe switching chip; comparing the index value with the index value corresponding to the currently running SBR file, and maintaining or replacing the SBR file based on the comparison result (associative or non-associative), so that the index value corresponding to the updated SBR file is associated with the index value reflected by the state of the target GPIO pin.

[0005] As a technical solution, the general firmware stores several STATION configurations, each STATION configuration including an SBR sequence startup record file and a corresponding MFG manufacturing file; after the step of comparing the index value corresponding to the currently running SBR file according to the index value, and keeping or replacing the SBR file according to the comparison result of association or non-association, it also includes: loading the MFG file corresponding to the updated SBR file.

[0006] As a technical solution, the state of the corresponding GPIO pin is configured by the management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

[0007] As one technical solution, the port connection configuration of the PCIe switching chips is the same or different, including several PCIe switching chips with the same port connection configuration and / or different port connection configurations between the same and different chips.

[0008] This specification also provides a firmware configuration management device applied to a PCIe switching chip. The PCIe switching chip is programmed with general firmware, which is used to be programmed to several PCIe switching chips with the same or different port connection configurations. The general firmware stores several sets of SBR sequence boot record files. The SBR files include port attribute configurations. The device includes: a first module, used to run the SBR file in response to a boot event and obtain the status of a target GPIO pin, the target GPIO pin being connected to a corresponding GPIO pin of a management chip, and the corresponding GPIO pin of the management chip enabling firmware configuration functions; a second module, used to obtain an index value based on the status of the target GPIO pin, the index value being used to indicate the current port connection configuration of the PCIe switching chip; and a third module, used to compare the index value with the index value corresponding to the currently running SBR file, and maintain or replace the SBR file based on the comparison result (associative or non-associative), so that the index value corresponding to the updated SBR file is associated with the index value reflected by the status of the target GPIO pin.

[0009] As a technical solution, the general firmware stores several STATION configurations, each STATION configuration including an SBR sequence startup record file and a corresponding MFG manufacturing file; the third module is also used to load the MFG file corresponding to the updated SBR file after comparing the index value corresponding to the currently running SBR file according to the index value, and keeping or replacing the SBR file according to the comparison result of association or non-association.

[0010] As a technical solution, the state of the corresponding GPIO pin is configured by the management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

[0011] As one technical solution, the port connection configuration of the PCIe switching chips is the same or different, including several PCIe switching chips with the same port connection configuration and / or different port connection configurations between the same and different chips.

[0012] This specification also provides an electronic device, including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned firmware configuration management method.

[0013] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned firmware configuration management method.

[0014] The technical solutions provided in this specification offer at least the following beneficial effects: By dynamically selecting the matching configuration through GPIO pin states, a single general-purpose firmware can be adapted to multiple port connection topologies, significantly improving firmware reusability and system maintenance efficiency while ensuring PCIe link performance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.

[0016] Figure 1 This is a flowchart of a firmware configuration management method according to one embodiment of this specification; Figure 2 This is a structural diagram of a firmware configuration management device according to one embodiment of this specification; Figure 3 This is a hardware structure diagram of an electronic device according to one embodiment of this specification.

[0017] Reference numerals: Module 1 21, Module 22, Module 3 23. Detailed Implementation

[0018] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0019] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0020] To address the firmware (FW) normalization issue, one hardware normalization scheme, taking 8U / 10U models as an example, typically requires four PCIe switch (SW) chips. The burned SW FW contains two key components: a Serial Boot Record (SBR) and a Manufacturing File (MFG). Current mainstream FW baseline versions allow a single FW file to contain one SBR and one MFG, and the port attribute configurations in the SBR and MFG files must be consistent for the SW chips to function correctly. Therefore, this hardware normalization scheme requires completely uniform port configurations for all SW chips, achieving FW universality through standardized hardware topology layout.

[0021] However, this approach has significant drawbacks: the internal board size of a server is limited, while the SW chip itself occupies a large amount of board space. When four SW chips are deployed on a single board with a unified port configuration hardware topology, the layout and routing of the PCB (Printed Circuit Board) becomes extremely difficult, inevitably leading to an increase in the length of the traces within the board. Furthermore, the loss of high-speed PCIe signals during transmission within the board is highly correlated with the trace length; excessively long traces can easily cause signal loss to exceed the limit, severely affecting the link transmission quality. In addition, this hardware normalization method is only applicable to fixed architectures. Once the server architecture changes, the original firmware will become completely ineffective, and a firmware adapted to the new architecture must be redeveloped. This results in extremely poor application flexibility, failing to meet the architectural adjustment needs of different models and application scenarios, and making it difficult to adapt to the changing market demands for product diversification and customization.

[0022] The above-mentioned technical solutions, in the process of achieving PCIe SW chip FW normalization, are difficult to balance low hardware link loss and architectural flexibility. Either the unified hardware topology leads to excessive signal loss and layout difficulties, or the FW is strongly bound to a fixed architecture, resulting in high development and maintenance costs and limited application scenarios.

[0023] There is an urgent need for an innovative technical solution to overcome this predicament, to achieve efficient normalization of the FW while ensuring the transmission performance of the hardware link, reduce development and maintenance costs, and improve the flexibility and adaptability of the product architecture.

[0024] In view of this, this specification provides a firmware configuration management method, apparatus, device, and readable storage medium, which achieves efficient normalization of firmware while ensuring hardware link transmission performance, reduces development and maintenance costs, and improves the flexible adaptability of product architecture.

[0025] The specific technical solution is described below.

[0026] In one embodiment, this specification provides a firmware configuration management method applied to a PCIe switching chip. The PCIe switching chip is programmed with general firmware, which is used to be programmed to several PCIe switching chips with the same or different port connection configurations. The general firmware stores several sets of SBR sequence boot record files, and the SBR files include port attribute configurations. The method includes: in response to a boot event, running the SBR file, obtaining the state of a target GPIO pin, the target GPIO pin being connected to a corresponding GPIO pin of a management chip, and enabling firmware configuration functions on the corresponding GPIO pin of the management chip; obtaining an index value based on the state of the target GPIO pin, the index value being used to indicate the current port connection configuration of the PCIe switching chip; comparing the index value with the index value corresponding to the currently running SBR file, and maintaining or replacing the SBR file based on the comparison result (associative or non-associative), so that the index value corresponding to the updated SBR file is associated with the index value reflected by the state of the target GPIO pin.

[0027] In one implementation, a highly integrated and adaptive universal firmware is constructed. This universal firmware is pre-installed with several complete SBR files before leaving the factory, each SBR file corresponding to a typical port connection configuration scenario.

[0028] For example, an 8U server motherboard supporting four-way GPU interconnect might contain three typical topologies: the first is a full interconnect mode, where SW0's Port0 connects to the CPU, and Ports 1-3 connect to GPUs 0-2 respectively; the second is a grouped interconnect mode, where SW0 only connects the CPU and GPU 0, while SW1 handles the interconnect between GPUs 1-3; and the third is a hybrid storage acceleration mode, where some ports connect to NVMe SSDs instead of GPUs. For these three scenarios, the general firmware will embed three configuration files: SBR_0, SBR_1, and SBR_2. Each file not only contains port roles and speed settings but also a unique index value (e.g., Index=0, 1, 2). This index value is fixed in the metadata area of ​​the corresponding SBR during the firmware compilation stage as its identifier. These SBR files are not simply stacked but have undergone rigorous verification and compatibility testing to ensure safe coexistence within the same firmware framework and to prevent startup delays or memory overflows due to redundant configurations.

[0029] like Figure 1 This includes the following steps, the order of which can be changed depending on the needs of the actual application scenario: Step S11: In response to the startup event, run the SBR file to obtain the status of the target GPIO pin.

[0030] When the PCIe switch chip powers on and triggers a boot event (Power-On Reset or Cold Boot), its internal embedded ARM core loads and runs the current default SBR file (usually SBR_0 with the smallest index value). Simultaneously, the firmware reads the level states of a set of predefined "target GPIO pins." These GPIO pins are explicitly specified during the hardware design phase and are physically connected to the corresponding GPIO pins of the management chip (such as a CPLD or BMC) on the motherboard via PCB traces. During system power-on initialization, the management chip actively drives its corresponding GPIO pins to output specific high and low level combinations based on the actual topology location of the PCIe switch chip.

[0031] Step S12: Obtain the index value based on the state of the target GPIO pin.

[0032] For example, if SW0 is in a fully interconnected position, the BMC sets its GPIO[7:6] to "00"; if it is in a packet interconnected position, it sets it to "01"; and if it is used for hybrid storage acceleration, it sets it to "10". This encoding method essentially constitutes a hardware-level "topology ID", the number of which can be expanded according to actual needs (e.g., using 3-bit GPIO can support 8 configurations). The firmware of the PCIe switch chip can parse a binary value by reading these pin states and convert it into the aforementioned index value - for example, "00" corresponds to Index=0, "01" corresponds to Index=1, and "10" corresponds to Index=2.

[0033] Step S13: Compare the index values ​​of the currently running SBR file with the index values, and keep or replace the SBR file based on the comparison results (whether associated or not).

[0034] After obtaining the target index value, the index value associated with the currently running SBR file (i.e., Index=0 for the default loaded SBR_0) is compared with the target index value read from GPIO. If the two are consistent (e.g., both are 0), it means that the current SBR configuration is completely matched with the hardware topology, and the firmware does not need any adjustments. It can directly continue to execute the subsequent initialization process, including standard operations such as link training, port enumeration, and hot-plug enabling.

[0035] If the two are inconsistent (e.g., GPIO returns Index=2, while the currently running SBR is Index=0), the firmware determines that the current configuration is inapplicable and triggers the SBR switching mechanism. Through the internal firmware scheduler, it locates and loads the SBR file (e.g., SBR_2) corresponding to the target index value from the reserved storage area of ​​the general firmware image (usually located in a specific partition of the SPI Flash). After loading, the firmware re-parses the port attribute configuration in the new SBR and re-initializes the physical layer and link layer parameters of the PCIe ports accordingly, ensuring that the role, speed, and width of each port strictly conform to the actual requirements of the current hardware connection. The entire switching process is completed early in the chip's boot process, completely transparent to the upper-layer operating system and drivers, and is imperceptible to the user.

[0036] In one implementation, the general firmware stores several STATION configurations, each STATION configuration including an SBR sequence startup record file and a corresponding MFG manufacturing file; after the step of comparing the index value corresponding to the currently running SBR file according to the index value, and keeping or replacing the SBR file according to the comparison result of association or non-association, the system further includes: loading the MFG file corresponding to the updated SBR file.

[0037] In one implementation, the state of the corresponding GPIO pin is configured by a management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

[0038] In one embodiment, the port connection configurations of the plurality of PCIe switching chips are the same or different, including a plurality of PCIe switching chips with the same port connection configuration and / or different port connection configurations between each pair of chips.

[0039] In one implementation, such as Figure 2 This specification also provides a firmware configuration management device applied to a PCIe switching chip. The PCIe switching chip is programmed with general firmware, which is used to be programmed to several PCIe switching chips with the same or different port connection configurations. The general firmware stores several sets of SBR sequence boot record files. The SBR files include port attribute configurations. The device includes: a first module, used to run the SBR file in response to a boot event and obtain the status of a target GPIO pin, the target GPIO pin being connected to a corresponding GPIO pin of a management chip, and the corresponding GPIO pin of the management chip enabling firmware configuration functions; a second module, used to obtain an index value based on the status of the target GPIO pin, the index value being used to indicate the current port connection configuration of the PCIe switching chip; and a third module, used to compare the index value with the index value corresponding to the currently running SBR file, and maintain or replace the SBR file based on the comparison result (associative or non-associative), so that the index value corresponding to the updated SBR file is associated with the index value reflected by the status of the target GPIO pin.

[0040] In one implementation, the general firmware stores several STATION configurations, each STATION configuration including an SBR sequence startup record file and a corresponding MFG manufacturing file; the third module is further configured to load the MFG file corresponding to the updated SBR file after comparing the index value corresponding to the currently running SBR file according to the index value, and keeping or replacing the SBR file according to the comparison result of association or non-association.

[0041] In one implementation, the state of the corresponding GPIO pin is configured by a management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

[0042] In one embodiment, the port connection configurations of the plurality of PCIe switching chips are the same or different, including a plurality of PCIe switching chips with the same port connection configuration and / or different port connection configurations between each pair of chips.

[0043] In one implementation, the goal is to address industry pain points such as the difficulty in normalizing traditional switch chip firmware (FW), the inability to balance hardware link loss control and architectural flexibility, and high development and maintenance costs. This implementation uses mainstream switch chip models (such as PEX89104 and PEX89144) and management chips (CPLD and BMC) in actual application scenarios as examples for illustration. However, the above selections are for illustrative purposes only and are not the only options for the technical solution in this specification.

[0044] The SW chip is a key component for realizing PCIe signal exchange and bandwidth allocation between the CPU and GPU, and between the GPU and other peripherals. Its working mode, the composite switching mode (SSw MODE), relies on the FW driver to run the internal Arm processor to complete core functions such as port role definition (e.g., uplink port connects to the CPU, downlink port connects to the GPU), rate negotiation (e.g., PCIe 4.0 x16), and bandwidth allocation.

[0045] In this embodiment, a single firmware can be programmed into multiple switch chips with the same or different port connection configurations. The general firmware integrates several sets of sequence boot record files (SBRs), each SBR corresponding to a specific port attribute configuration (e.g., ports 0-3 are uplink ports connected to the CPU, ports 4-15 are downlink ports connected to the GPU, or ports 0-1 are uplink ports, ports 2-17 are downlink ports, etc.). By controlling the GPIO pin states through the management chip (CPLD or BMC), the SBR that matches the current switch chip port connection configuration is dynamically selected, achieving the goal of "one firmware for multiple uses" and "one board for multiple uses".

[0046] At the hardware connection level, the GPIO pin correspondence design between the SW chip and the management chip needs to be completed. In this embodiment, the management chip is preferably a complex programmable logic device (CPLD) because it has the characteristics of flexible logic configuration, fast response speed and high stability, and can directly establish a hardware connection with the GPIO pins of the SW chip; at the same time, in order to further improve the configuration flexibility, the CPLD can communicate with the baseboard management controller (BMC) through the I2C bus, and the BMC can indirectly control the GPIO pin status by writing to the internal registers of the CPLD, so as to meet the needs of remote configuration or dynamic adjustment. Taking the SW chip PEX89144 (which has abundant GPIO pin resources) as an example, this embodiment selects 3 GPIO pins as "target GPIO pins" (denoted as GPIO [2:0]), which are connected to the 3 output GPIO pins of the CPLD (denoted as CPLD_GPIO [2:0]) to form a one-to-one hardware link. Among them, the 3 GPIO pins of the CPLD need to be configured in advance by programming the firmware. That is, the high and low level states output by these pins will be used directly as the basis for the SW chip to select the SBR, rather than for other general functions (such as hardware reset, status indication).

[0047] In the initial configuration of the CPLD, the pin function of CPLD_GPIO [2:0] should be defined as "SW_FW_SBR_SELECT", and its output drive capability and level standard (such as 3.3V LVTTL) should be set to ensure that it matches the electrical characteristics of the GPIO pin of the SW chip and avoid configuration errors caused by incompatible signal levels.

[0048] This implementation integrates multiple SBR+MFG sets based on a single FW file. The MFG is the manufacturing file, and its port attribute configuration must be consistent with that of the SBR to ensure the normal operation of the SW chip. Up to 6 SBR+MFG combinations are integrated (3 GPIO pins can represent 8 binary states; considering the reserved expansion space, this implementation actually uses 6 configurations, corresponding to index values ​​0-5). Each combination corresponds to a typical port connection configuration. Secondly, a "default SBR index value" is preset in the firmware's "Persistent Area" (the data in this area is not lost after the chip is powered off and is used to save configuration parameters). This value can be set by the programming tool during firmware flashing. By default, it corresponds to the regular port configuration of a certain SW chip on the board. The firmware contains a GPIO status detection module and an SBR switching control module, which are used to obtain the target GPIO pin status at startup and to perform the SBR hold or change operation based on the index value comparison result.

[0049] Taking an 8U GPU server board (deploying 4 PEX89144 chips, denoted as SW1, SW2, SW3, and SW4) as an example, the general firmware SBR integration scheme is as follows: Index value 0 (binary 000): SBR0+MFG0, corresponding to the port configuration of SW1 - Ports 0-1 are uplink ports (connecting to the PCIe root port of CPU1), and ports 2-15 are downlink ports (connecting 4 GPUs, each GPU occupying 4 PCIe lanes), with a speed configuration of PCIe 4.0 x16. Index value 1 (binary 001): SBR1+MFG1, corresponding to the port configuration of SW2 - ports 0-1 are uplink ports (connecting to the PCIe root port of CPU2), ports 2-15 are downlink ports (connecting to 4 GPUs), and the speed configuration is the same as SW1; Index value 2 (binary 010): SBR2+MFG2, corresponding to the port configuration of SW3 - Port 0 is the uplink port (connecting to the spare PCIe root port of CPU1), and ports 1-14 are the downlink ports (connecting to 3 GPUs + 1 NIC network card), with a speed configuration of PCIe 4.0 x8; Index value 3 (binary 011): SBR3+MFG3, corresponding to the port configuration of SW4 - Port 0 is the uplink port (connecting to the spare PCIe root port of CPU2), and ports 1-14 are the downlink ports (connecting to 3 GPUs + 1 storage controller), with the speed configuration being the same as SW3; Index value 4 (binary 100): SBR4+MFG4, which corresponds to the port configuration of SW1 when this board is adapted to another 10U server - ports 0-2 are uplink ports (connecting the PCIe root ports of 3 CPUs), and ports 3-17 are downlink ports (connecting 5 GPUs). Index value 5 (binary 101): SBR5+MFG5, corresponding to the port configuration of SW2 when the board is adapted to a 10U server - ports 0-2 are uplink ports (connecting the PCIe root ports of 3 CPUs), and ports 3-17 are downlink ports (connecting 5 GPUs).

[0050] During the firmware flashing stage, a dedicated programming tool (such as the PEXConfiguration Tool provided by the SW chip manufacturer) is used to flash the aforementioned general firmware to the external flash memory of SW1, SW2, SW3, and SW4 respectively. During the flashing process, a "default SBR index value" for the persistent region needs to be set for each SW chip: the default index value for SW1 is set to 0, for SW2 to 1, for SW3 to 2, and for SW4 to 3. This ensures that the chip can load the default SBR and start without GPIO configuration, thus avoiding boot failure.

[0051] When the server powers on or the SW chip triggers a reset (e.g., the BMC sends a reset command), the startup event is triggered, and the SBR selection and configuration switch is executed.

[0052] The following details the startup process of SW1: The first step is to respond to the startup event, run the default SBR, and obtain the target GPIO pin status. After the server is powered on, the SW chip PEX89144 first performs hardware initialization (such as clock reset and port detection), and then loads the general firmware from the external flash to the internal memory. After the firmware starts, it prioritizes running the default SBR preset in the persistent area (SW1 runs SBR0 by default). In the initial stage of SBR operation, the "GPIO status detection module" inside the firmware is activated. This module reads the current level status of the target GPIO pin (GPIO [2:0]) through the GPIO controller of the SW chip. At this point, the CPLD has completed initialization, and the output CPLD_GPIO [2:0] level state has been pre-set according to the port configuration requirements of SW1 (because SW1 needs to use the configuration corresponding to SBR0, CPLD_GPIO [2:0] is configured as binary 000, that is, CPLD_GPIO2=0, CPLD_GPIO1=0, CPLD_GPIO0=0, so the state read by SW1's GPIO [2:0] is 000. It should be noted that before reading the GPIO state, the firmware will first check whether the target GPIO pin has been enabled by the firmware configuration function). This check is implemented by reading the GPIO function configuration register inside the SW chip. If the register indicates that the function of the pin is not enabled (such as being misconfigured as a normal I / O), the firmware will trigger a level one alarm (reported to BMC via an interrupt signal) and suspend the SBR selection process, waiting for the administrator to check the hardware configuration error; if it has been enabled, the subsequent steps will continue.

[0053] The second step is to obtain the index value based on the target GPIO pin status. This index value directly maps to the port connection configuration that the current SW chip needs to adapt to. In this embodiment, the level status of the three target GPIO pins is converted into index values ​​using binary encoding. The specific mapping rules are pre-defined in the firmware, as shown in the table below: In the startup instance of SW1, the target GPIO pin status is 000, and according to the above rules, the firmware calculates an index value of 0. If the SW chip is SW3 at this time, and the connected CPLD_GPIO [2:0] status is 010 (corresponding to index value 2), then after the firmware reads that the GPIO [2:0] status is 010, it calculates an index value of 2, explicitly indicating that SW3 needs to use the port configuration corresponding to SBR2 (port 0 is the uplink port, and ports 1-14 are the downlink ports). In addition, if it is necessary to remotely adjust the configuration through BMC (such as switching SW1 from an 8U server adapter to a 10U server adapter), the administrator can send commands through the BMC management interface. The BMC writes data to a specific register of the CPLD via the I2C bus (such as writing 0x04, which corresponds to binary 100). After receiving the data, the CPLD updates the output status of CPLD_GPIO [2:0] to 100. If SW1 triggers a restart at this time, the target GPIO pin status will become 100, and the calculated index value is 4, corresponding to the configuration of SBR4, thus realizing remote dynamic adjustment.

[0054] The third step involves maintaining or replacing the currently running SBR file based on the index value comparison result, ensuring that the finally loaded SBR matches the port connection configuration of the current SW chip. After the firmware obtains the "index value corresponding to the GPIO state" (denoted as Index_GPIO), it reads the preset "default SBR index value" (denoted as Index_Default) in the persistent area and compares the two, performing different operations based on the comparison result: Scenario 1: Index_GPIO and Index_Default are associated (i.e., their values ​​are equal). In this case, the currently running default SBR is already adapted to the current port configuration, and the firmware does not need to replace the SBR. It directly continues to execute the subsequent SBR process (such as resetting the Arm CPU, loading the corresponding MFG file, and issuing port configuration commands). Taking the default startup of SW1 as an example, Index_GPIO=0 and Index_Default=0, which are equal. The firmware keeps running SBR0, and then loads MFG0 (which has the same port attribute configuration as SBR0). After the Arm CPU is reset, it runs the small system. According to the configuration of SBR0 and MFG0, it configures ports 0-1 of SW1 as uplink ports and ports 2-15 as downlink ports, and negotiates the speed to PCIe 4.0 x16. Finally, it completes the normal startup of SW1, meeting the working requirements of SW1 in the 8U server.

[0055] Scenario 2: Index_GPIO and Index_Default are not associated (i.e., their values ​​are not equal). In this case, the currently running default SBR does not match the current port configuration, and the firmware needs to perform an SBR replacement operation. The specific process is as follows: First, the "SBR switching control module" inside the firmware will trigger a warning (recorded in the firmware's internal storage via log, and simultaneously reported to the BMC via the PCIe bus), indicating that "the default SBR and GPIO configuration do not match, and an SBR replacement will be performed." Then, based on the value of Index_GPIO, the module searches for the corresponding target SBR from the multiple SBRs integrated in the general firmware (e.g., searching for SBR4 when Index_GPIO=4), and loads the code and data of the target SBR into the SBR running area of ​​the SW chip (overwriting the contents of the original default SBR). Next, the module updates the "currently effective SBR index value" in the persistent area (updating Index_Default to Index_GPIO to ensure that the target SBR can be directly loaded upon the next startup without repeated comparison). Finally, the firmware restarts the SBR running process, loads the MFG file corresponding to the target SBR, and completes the configuration switch.

[0056] Taking the remote adjustment of SW1 to the 10U server configuration as an example, if CPLD_GPIO [2:0] is set to 100 through BMC, after SW1 restarts, Index_GPIO=4, while Index_Default is still 0 (before the update). The two are not equal, the firmware triggers a warning and starts to replace SBR: load SBR4 from the general firmware to the running area, update the persistent area's Index_Default to 4, then rerun SBR4, load the corresponding MFG4, configure SW1's ports 0-2 as uplink ports and ports 3-17 as downlink ports, negotiate the rate to PCIe 4.0 x16, and adapt to the port connection requirements of the 10U server. During this process, it is necessary to ensure the configuration consistency between the target SBR and MFG. Before loading the MFG, the firmware will verify the port attribute configuration information of the SBR and MFG (such as the number of ports, uplink / downlink roles, and rate levels). If there is any inconsistency (such as SBR4 being configured with 18 ports and MFG4 being configured with 16 ports), the firmware will trigger a level 2 alarm and pause the startup to avoid abnormal operation of the SW chip due to configuration conflicts.

[0057] This implementation also has good scalability. If the subsequent server architecture needs to add port configurations (such as supporting PCIe 5.0 speed or adding more downlink ports), it is only necessary to add the corresponding SBR+MFG combination in the general firmware (such as index value 6 corresponding to SBR6+MFG6, supporting PCIe 5.0 x32) and expand the number of GPIO pins (such as increasing to 4 GPIO pins, supporting 16 configurations), without the need for large-scale hardware modifications, further reducing product iteration costs.

[0058] In one embodiment, this specification provides an electronic device including a processor and a readable storage medium storing machine-executable instructions executable by the processor. The processor executes the machine-executable instructions to implement the aforementioned firmware configuration management method. From a hardware perspective, a hardware architecture diagram can be found... Figure 3 As shown.

[0059] In one embodiment, this specification provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned firmware configuration management method.

[0060] Here, a readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0061] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0062] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0063] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0064] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments thereof. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0065] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0066] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0067] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0068] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A firmware configuration management method, characterized in that, The method involves a PCIe switching chip programmed with generic firmware. This firmware is used to program several PCIe switching chips with the same or different port connection configurations. The generic firmware stores several sets of SBR sequence boot record files, each containing port attribute configurations. In response to the startup event, the SBR file is run to obtain the status of the target GPIO pin, which is connected to the corresponding GPIO pin of the management chip, and the corresponding GPIO pin of the management chip enables the firmware configuration function. Based on the state of the target GPIO pin, obtain the index value, which is used to indicate the port connection configuration of the current PCIe switching chip; The index value is compared with the index value of the currently running SBR file. The SBR file is kept or replaced according to the comparison result of association or non-association, so that the index value of the updated SBR file is associated with the index value of the target GPIO pin status response.

2. The method according to claim 1, characterized in that, The general firmware stores several STATION configurations, each STATION configuration including an SBR sequence boot record file and a corresponding MFG manufacturing file; After the step of comparing the index values ​​corresponding to the currently running SBR file based on the index values, and keeping or replacing the SBR file based on the comparison results (whether associated or not), the method further includes: Load the MFG file corresponding to the updated SBR file.

3. The method according to claim 1, characterized in that, The state of the corresponding GPIO pin is configured by the management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

4. The method according to claim 1, characterized in that, The port connection configurations of the PCIe switching chips are the same or different, including several PCIe switching chips with the same port connection configuration and / or different port connection configurations between the same and different chips.

5. A firmware configuration management device, characterized in that, An application is made to a PCIe switching chip, wherein the PCIe switching chip is programmed with universal firmware. This universal firmware is used to program several PCIe switching chips with the same or different port connection configurations. The universal firmware stores several sets of SBR sequence boot record files, each SBR file including port attribute configurations. The device includes: The first module is used to respond to a startup event, run an SBR file, obtain the status of a target GPIO pin, the target GPIO pin is connected to a corresponding GPIO pin of the management chip, and the corresponding GPIO pin of the management chip enables firmware configuration functions. The second module is used to obtain an index value based on the state of the target GPIO pin, and the index value is used to indicate the port connection configuration of the current PCIe switching chip. The third module is used to compare the index value of the currently running SBR file with the index value, and to keep or replace the SBR file based on the comparison result (whether associated or not) so that the index value of the updated SBR file is associated with the index value of the target GPIO pin's state response.

6. The apparatus according to claim 5, characterized in that, The general firmware stores several STATION configurations, each STATION configuration including an SBR sequence boot record file and a corresponding MFG manufacturing file; The third module is also used to load the MFG file corresponding to the updated SBR file after comparing the index value corresponding to the currently running SBR file with the index value, and keeping or replacing the SBR file according to the comparison result of association or non-association.

7. The apparatus according to claim 5, characterized in that, The state of the corresponding GPIO pin is configured by the management chip. The management chip configures the state of the corresponding GPIO pin according to the data written by the BMC in a specific register. The state of the corresponding GPIO pin is used to set the state of the target GPIO pin.

8. The apparatus according to claim 5, characterized in that, The port connection configurations of the PCIe switching chips are the same or different, including several PCIe switching chips with the same port connection configuration and / or different port connection configurations between the same and different chips.

9. An electronic device, characterized in that, include: A processor and a readable storage medium storing machine-executable instructions that can be executed by the processor to implement the method of any one of claims 1-4.

10. A readable storage medium, characterized in that, The readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method described in any one of claims 1-4.

Images