Quantum approximate optimization algorithm-based planned line optimization method and related device

Abstract

The embodiment of the invention discloses a planned line optimization method of a quantum approximation optimization algorithm and a related device, and the method comprises the steps: determining two multiplied Folli Z gate subitems in Hamiltonian corresponding to a target optimization problem, and taking an edge determined by two quantum bits acted by two Folli Z gates in the subitems as a target, obtaining a group of targets; and searching the group of targets on a topological structure of a real quantum chip through a breadth-first search algorithm to determine the shortest execution path of all subitems in the Hamiltonian so as to realize the planned line optimization of the quantum approximate optimization algorithm. By adopting the embodiment of the invention, hardware resources of the logic gate can be saved, and the operation speed and accuracy of the algorithm are improved.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a proposed circuit optimization method and related apparatus for a quantum approximation optimization algorithm. Background Technology

[0002] The Quantum Approximate Optimization Algorithm (QAOA) is a quantum variational algorithm that can approximate solutions to combinatorial optimization problems on quantum computers. QAOA combines parameterized quantum circuits with classical optimization methods to find approximate optimal solutions and has broad application potential in many fields, such as optimization problems, artificial intelligence, cryptography, materials science, and drug development.

[0003] While the QAOA algorithm has achieved encouraging results in solving optimization problems, its practical applications are still limited by quantum hardware, such as the error rate of qubits, connectivity limitations, and runtime. Ultimately, quantum algorithms need to be mapped to the circuitry of real quantum computers to solve real-world problems; therefore, circuit optimization of the QAOA algorithm is particularly important. Summary of the Invention

[0004] This application provides a proposed circuit optimization method and related apparatus for a quantum approximation optimization algorithm, which helps to save logic gate hardware resources and improve the running speed and accuracy of the algorithm.

[0005] The first aspect of this application provides a proposed circuit optimization method using a quantum approximation optimization algorithm, the method comprising:

[0006] By identifying the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the objective optimization problem, and taking the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the objective, a set of objectives is obtained.

[0007] The set of targets is searched on the topology of a real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian, thereby achieving the proposed path optimization of the quantum approximation optimization algorithm.

[0008] Based on the above scheme, when the two multiplicative Pauli Z-gate sub-terms in the Hamiltonian corresponding to the objective optimization problem are mapped to a real quantum chip for execution, a breadth-first search algorithm is first used to search the topology of the real quantum chip to find the shortest execution path for the sub-term. This reduces the number of swapping gates introduced by the two Pauli Z-gates in the sub-term because the two qubits they affect are not directly connected on the real quantum chip, thus saving logic gate hardware resources. At the same time, due to the reduction in quantum logic gates, the algorithm runs faster. Furthermore, the reduction in quantum logic gates can also reduce the accumulation of hardware error rates such as those related to quantum logic gates, thereby improving the accuracy of the calculation.

[0009] In conjunction with the first aspect, in some descriptions of the first aspect, the step of searching the set of targets on the topology of a real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all items in the Hamiltonian includes:

[0010] The search order of the set of targets is determined, and the set of targets is searched on the topology of the real quantum chip in accordance with the search order using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian.

[0011] In conjunction with the first aspect, in certain descriptive methods of the first aspect, determining the search order of the set of targets includes:

[0012] Randomly select one target from the set of targets as the current target;

[0013] The remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance between the remaining target and the current target is determined as the next target of the current target. The remaining target is the target in the group of targets other than the current target.

[0014] The next target is taken as the current target, and the remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance of the remaining target and the current target is determined as the next target of the current target;

[0015] If no remaining target exists, determine the search order for the set of targets.

[0016] In conjunction with the first aspect, in some descriptions of the first aspect, before determining the remaining target corresponding to the minimum sum of the edge length of the remaining target and the edge distance between the remaining target and the current target as the next target of the current target, the method further includes:

[0017] Determine a first distance between the endpoint of the current target and the starting point of the remaining targets, and a second distance between the endpoint of the current target and the starting point of the remaining targets;

[0018] The smaller of the first distance and the second distance is determined as the edge distance between the remaining target and the current target.

[0019] In conjunction with the first aspect, in some descriptions of the first aspect, the step of searching the set of targets on the topology of the real quantum chip using a breadth-first search algorithm in the order of the search to determine the shortest execution path for all items in the Hamiltonian includes:

[0020] The first target in the set of targets is determined as the search target according to the search order, and a queue and all paths are defined. The element information in the queue includes the state, which is used to record the state determined according to the link. The link is determined according to the topology of the real quantum chip. All paths are used to record the shortest execution path to achieve the sub-item corresponding to each search target.

[0021] Determine whether the queue is empty;

[0022] If it is not empty, then determine whether the state of the first element in the queue includes the state corresponding to the search target;

[0023] If the state corresponding to the search target is included, then the first element is stored in all paths;

[0024] The next search target is determined from the set of targets according to the search order, and the step of determining whether the queue is empty is performed.

[0025] If the next search target does not exist in the set of targets, the shortest execution path for all sub-items in the Hamiltonian is determined based on all elements included in all paths.

[0026] In conjunction with the first aspect, in some descriptions of the first aspect, the element information in the queue further includes path and depth, the path being used to record links, and the depth being used to record the number of times the links are traversed. The method further includes:

[0027] If the state corresponding to the search target is not included and the depth of the first element in the queue does not exceed the set depth, then each link determined according to the topology of the real quantum chip is traversed and the state is updated according to the link.

[0028] If the updated state has not been visited and the updated state does not include the state corresponding to the search target, then add a new element and add the new element to the queue.

[0029] In conjunction with the first aspect, in certain descriptive methods of the first aspect, the addition of an element includes:

[0030] The updated state is used as the state of the newly added element, the currently traversed link is used as the path, and the incremented depth is used as the depth to obtain the newly added element.

[0031] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0032] If the depth exceeds the set depth, or if all paths are not empty and the depth exceeds the depth of the elements in all paths, then the search for the search target is stopped.

[0033] In conjunction with the first aspect, in some descriptions of the first aspect, the initial state of the first element in the queue is determined based on the total number of bits of the Pauli Z-gate action in the Hamiltonian, the initial path is empty, and the initial depth is zero.

[0034] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0035] Define historical access, which refers to the state of a previously accessed site.

[0036] In conjunction with the first aspect, in some descriptions of the first aspect, when storing the first element in all paths, the method further includes:

[0037] The first element is deleted from the queue and stored in the history of access.

[0038] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0039] If the updated state is not found in the historical access, it is determined that the updated state has never been accessed, and the updated state is stored in the historical access.

[0040] A second aspect of this application provides a proposed circuit optimization apparatus for a quantum approximation optimization algorithm, the apparatus comprising:

[0041] The target determination unit is used to determine the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the target optimization problem, and to take the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the target, so as to obtain a set of targets;

[0042] The target search unit is used to search the set of targets on the topology of the real quantum chip using a breadth-first search algorithm to determine the shortest execution path of all sub-items in the Hamiltonian, thereby realizing the proposed path optimization of the quantum approximation optimization algorithm.

[0043] A third aspect of this application provides an electronic device, including: a processor and a memory;

[0044] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0045] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 An example system block diagram of a proposed circuit optimization method based on a quantum approximation optimization algorithm provided in one embodiment of this application is shown;

[0048] Figure 2 A schematic diagram of the structure of QAOA provided in one embodiment of this application is shown;

[0049] Figure 3 This paper shows a schematic diagram of the Cost layer structure of a proposed QAOA line according to an embodiment of this application;

[0050] Figure 4 A schematic flowchart of a proposed circuit optimization method based on a quantum approximation optimization algorithm provided in one embodiment of this application is shown.

[0051] Figure 5 A topological diagram of a real quantum chip provided in one embodiment of this application is shown;

[0052] Figure 6 This paper shows a schematic diagram of the proposed circuit optimization device for a quantum approximation optimization algorithm provided in one embodiment of the present application;

[0053] Figure 7A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0055] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0056] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, n quantum states can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement. The state of one qubit (whether it's 1, 0, or both) can depend on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0057] Please refer to Figure 1 This illustrates an example system block diagram of a proposed circuit optimization method for a quantum approximation optimization algorithm provided in one embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0058] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0059] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0060] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0061] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0062] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0063] QAOA is a classical-quantum hybrid algorithm that combines quantum computing and classical optimization techniques. QAOA is used to solve combinatorial optimization problems, aiming to find the optimal approximate solution. The QAOA algorithm consists of a quantum circuit part and a classical optimizer part. Its core idea is to find the optimal solution to the combinatorial optimization problem by constructing a parameterized quantum circuit.

[0064] like Figure 2 The diagram shows a schematic representation of the QAOA structure provided in one embodiment of this application. The proposed circuit consists of two unitary operators with adjustable parameters, alternating between them. Typically, these two alternating unitary operators are... and The components are the Cost layer and the Mixer layer, where H... C For the objective optimization problem, H represents the Hamiltonian. B As a mixed Hamiltonian, γ is responsible for performing random walks in the solution space. i and β i For self-tuning parameters, i represents the number of Cost layer and Mixer layer.

[0065] The construction of the Mixer layer is straightforward, using RX gates. Therefore, the Cost layer is the primary source of QAOA circuit depth. The Cost layer is constructed by using CNOT gates for accumulation, and then constructing the result on the last bit. That is, an RZ gate is applied to the last bit to construct the phase, and finally a CNOT gate is used to restore the quantum state back to the original state. For example, H C =Z1Z2+Z2Z3+Z1Z3, the corresponding Cost layer is as follows Figure 3 As shown. It can be seen that this existing practice is for H C Each sub-item in the algorithm starts from the initial state, traverses that sub-item, and then returns to the initial state. If it's possible to start from the initial state, traverse all sub-items, and return to the initial state, the number of CNOT gates between returning to the initial state from one sub-item and then moving to the next sub-item can be reduced. It's worth noting that the swap gate can also be constructed using three CNOT gates. Therefore, reducing the number of CNOT gates can save logic gate hardware resources and improve the algorithm's speed and accuracy. To address this technical problem, this application provides a proposed circuit optimization method and related apparatus for a quantum approximation optimization algorithm.

[0066] Please refer to Figure 4 This document illustrates a flowchart of a proposed circuit optimization method for a quantum approximation optimization algorithm provided in one embodiment of this application. This method can be applied to computer devices, which refer to electronic devices capable of data computation and processing. For example, the executing entity for each step could be... Figure 1 The computer device shown. The method may include the following steps:

[0067] Step 401: Determine the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the objective optimization problem, and take the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the objective, to obtain a set of objectives.

[0068] Wherein, the Hamiltonian corresponding to the objective optimization problem is... Figure 3 H in the illustrated embodiment C For example, the cost function for a polynomial unconstrained bivariate optimization problem is:

[0069]

[0070] Where, x i It is a Boolean variable, i.e., 0 or 1. For x i coefficient, It is an n-bit binary vector. For example, if f(x1, x2, x3) = mx1x2x3 + nx1x2 + px2x3 + qx3, then m = h 1，1，1 n = h 1，1，0 p = h 0,1,1 q = h 0，0,1 .

[0071] In quantum circuits, this needs to be converted into an energy function; therefore, x i Operators can be used Therefore, the Hamiltonian corresponding to this polynomial unconstrained bivariate optimization problem can be expressed as:

[0072]

[0073] because:

[0074]

[0075] In other words, for any monomial Z i Z j …Z k The eigenvalues ​​of its Hamiltonian depend on the parity of the summation of the bits at corresponding positions. When solving... When, if ∑ i∈c z i If the number is odd, then the expression contributes an e. (iγ) The phase; if it is even, then contribute an e. (-iγ) The phase of ∑. The problem can be transformed into finding ∑. i∈c Z i The parity, or rather, the parity of. The value is encoded onto a specific qubit. Therefore, the Cost layer quantum circuit can be constructed by using CNOT gates to build an accumulation, and then constructing the value on the last bit. That is, an RZ gate is applied to the last bit to construct the phase, and finally a CNOT gate is used to restore the quantum state back to the original state.

[0076] pass It can be seen that the subterms of the Hamiltonian include not only two multiplied Pauli Z-gate subterms, but also one or more Pauli Z-gate subterms. Therefore, this method also includes:

[0077] If a subterm of the Hamiltonian includes a Pauli Z-gate, then a Pauli Z-gate is directly applied to the corresponding qubit.

[0078] If the Hamiltonian sub-items include two or more Pauli Z-gates, then the two or more Pauli Z-gate sub-items are converted into multiple multiplied Pauli Z-gate sub-items, and then the shortest path is determined according to the above method.

[0079] The qubits corresponding to the Pauli Z gate are determined by their subscripts, and the subscript number is the qubit number.

[0080] The edge defined by the two qubits of the two Pauli Z-gates, for example, Z1Z3, can be represented as [1, 3]. It should be noted that since Z1Z3 and Z3Z1 represent different terms, this edge is directed. This directed edge [1, 3] can be used as a target for subsequent searches. Because H... C The sub-items included may include multiple items, thus resulting in a set of objectives. For example, H c =Z0Z3+Z1Z2, then a set of targets is [0,3] and [1,2].

[0081] Step 402: Search the set of targets on the topology of the real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian, thereby achieving the proposed path optimization of the quantum approximation optimization algorithm.

[0082] Among them, the Breadth First Search (BFS) algorithm is a graph search algorithm that starts from the root node and traverses the nodes of the tree along the width of the tree. If the target is found, the calculation terminates.

[0083] Topology describes the connections between points and lines. In a real quantum chip, the topology is obtained by abstracting qubits as points and the circuits connecting them as lines. For example, Figure 5 A topological diagram of a real quantum chip provided in one embodiment of this application is shown. Figure 5 As shown, the real quantum chip includes four qubits, which are numbered from 0 to 3. The edges between the qubits can be represented as [[0,1],[0,2],[1,3],[2,3],[1,0],[2,0],[3,1],[3,2]].

[0084] Based on the above scheme, when the two multiplicative Pauli Z-gate sub-terms in the Hamiltonian corresponding to the objective optimization problem are mapped to a real quantum chip for execution, a breadth-first search algorithm is first used to search the topology of the real quantum chip to find the shortest execution path for each sub-term. Figure 2 Compared to existing technologies, this solution, when executing all Hamiltonian-corresponding sub-items, does not return to the initial state after executing each sub-item, but instead traverses all sub-items before returning to the initial state. This saves the number of CNOT gates between returning to the initial state of one sub-item and then to the next, thereby reducing the number of swapping gates introduced by the two Pauli Z-gates of the sub-item because the two qubits they act on are not directly connected on the real quantum chip, thus saving logic gate hardware resources. At the same time, due to the reduction in quantum logic gates, the algorithm runs faster. Furthermore, the reduction in quantum logic gates can also reduce the accumulation of hardware error rates such as those caused by quantum logic gates, thereby improving the accuracy of the calculation.

[0085] In conjunction with the first aspect, in some descriptions of the first aspect, the step of searching the set of targets on the topology of a real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all items in the Hamiltonian includes:

[0086] The search order of the set of targets is determined, and the set of targets is searched on the topology of the real quantum chip in accordance with the search order using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian.

[0087] The search order of this set of targets can be determined by algorithms such as the greedy nearest neighbor algorithm, the shortest link algorithm, and the cheapest algorithm, or other algorithms can be used. No specific limit is imposed here.

[0088] Since a set of objectives may exist in multiple orders, for example, H C =Z1Z2+Z2Z3+Z1Z3, where the target set is [[1,2], [2,3], [1,3]], then there are 6 possible search orders. If a target is arbitrarily selected as the starting point using the breadth-first search algorithm, the chosen search order may not be optimal. Before using the breadth-first search algorithm, determining the shortest search order from multiple search orders helps improve the algorithm's running speed and finds the shortest execution path for all sub-items in the Hamiltonian.

[0089] In conjunction with the first aspect, in certain descriptive methods of the first aspect, determining the search order of the set of targets includes:

[0090] Randomly select one target from the set of targets as the current target;

[0091] The remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance between the remaining target and the current target is determined as the next target of the current target. The remaining target is the target in the group of targets other than the current target.

[0092] The next target is taken as the current target, and the remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance of the remaining target and the current target is determined as the next target of the current target;

[0093] If no remaining target exists, determine the search order for the set of targets.

[0094] The length of an edge is determined by the straight-line distance between its two endpoints, i.e., the straight-line distance between the physical qubits corresponding to the endpoints. The distance between edges can be determined by the distance between the endpoints of one edge and the endpoint of the other edge. For example, the distance between [0,3] and [1,2] could be the distance between the qubit with index 0 and the qubit with index 1, or the distance between the qubit with index 0 and the qubit with index 2, or the distance between the qubit with index 3 and the qubit with index 1, or the distance between the qubit with index 3 and the qubit with index 2. There is no limitation on this.

[0095] The above scheme provides a method for determining the search order of a set of targets by using the length of the remaining target's own body and the distance between the remaining target and the current target. This enables the determination of the shortest search order from multiple search orders, which helps to improve the running speed of the algorithm and find the shortest execution path for all sub-items in the Hamiltonian.

[0096] In conjunction with the first aspect, in some descriptions of the first aspect, before determining the remaining target corresponding to the minimum sum of the edge length of the remaining target and the edge distance between the remaining target and the current target as the next target of the current target, the method further includes:

[0097] Determine a first distance between the endpoint of the current target and the starting point of the remaining targets, and a second distance between the endpoint of the current target and the starting point of the remaining targets;

[0098] The smaller of the first distance and the second distance is determined as the edge distance between the remaining target and the current target.

[0099] Taking [0,3] and [1,2] as examples, the above embodiments provide four methods for determining the distance between these two targets. This embodiment further calculates the distances between the endpoint of the previous edge (the endpoint the directed edge points to) and the two endpoints of the other target, taking the smallest distance as the distance between the two targets. This results in a shorter path, reducing the number of CNOT gates between one sub-item and another. Because existing methods restore the initial quantum state to its original state via CNOT after the RZ gate in each sub-item is executed, this embodiment selects the path without returning to the initial quantum state after the RZ gate is executed, directly starting from the current quantum state to construct the next sub-item.

[0100] In conjunction with the first aspect, in some descriptions of the first aspect, the step of searching the set of targets on the topology of the real quantum chip using a breadth-first search algorithm in the order of the search to determine the shortest execution path for all items in the Hamiltonian includes:

[0101] The first target in the set of targets is determined as the search target according to the search order, and a queue and all paths are defined. The element information in the queue includes the state, which is used to record the state determined according to the link. The link is determined according to the topology of the real quantum chip. All paths are used to record the shortest execution path to achieve the sub-item corresponding to each search target.

[0102] Determine whether the queue is empty;

[0103] If it is not empty, then determine whether the state of the first element in the queue includes the state corresponding to the search target;

[0104] If the state corresponding to the search target is included, then the first element is stored in all paths;

[0105] The next search target is determined from the set of targets according to the search order, and the step of determining whether the queue is empty is performed.

[0106] If the next search target does not exist in the set of targets, the shortest execution path for all sub-items in the Hamiltonian is determined based on all elements included in all paths.

[0107] In conjunction with the first aspect, in some descriptions of the first aspect, the element information in the queue further includes path and depth, the path being used to record links, and the depth being used to record the number of times the links are traversed. The method further includes:

[0108] If the state corresponding to the search target is not included and the depth of the first element in the queue does not exceed the set depth, then each link determined according to the topology of the real quantum chip is traversed and the state is updated according to the link.

[0109] If the updated state has not been visited and the updated state does not include the state corresponding to the search target, then add a new element and add the new element to the queue.

[0110] The initial state of the first element in the queue is determined based on the total number of bits involved in the Pauli Z-gate interaction in the Hamiltonian; the initial path is empty, and the initial depth is zero. Specifically, if the total number of bits involved in the Pauli Z-gate interaction is n, then the initial state is [2]. 0 ,2 1 , ..., 2 n-1 ].

[0111] The state corresponding to the search target is determined based on the search target [i, j]. Specifically, the state corresponding to the search target is 2. j +2 i .

[0112] The depth is set in advance, for example, it can be the longest path determined by the edges in the topology of a real quantum chip. The path is composed of edges that are connected end to end, with the starting point of the current edge being the ending point of the previous edge, and the ending point of the current edge being the starting point of the next edge.

[0113] Specifically, the current state is [2 0 ,2 1 , ..., 2 n-1 The algorithm iterates through each link determined by the topology of the real quantum chip, updating the state according to the link. This includes updating the i-th element in the state to 2 if the traversed link is [i, j]. i +2 j The updated state is obtained [2] 0 ,2 1 , ...2 i +2 j …, 2 n-1 ].

[0114] In conjunction with the first aspect, in certain descriptive methods of the first aspect, the addition of an element includes:

[0115] The updated state is used as the state of the newly added element, the currently traversed link is used as the path, and the incremented depth is used as the depth to obtain the newly added element.

[0116] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0117] If the depth exceeds the set depth, or if all paths are not empty and the depth exceeds the depth of the elements in all paths, then the search for the search target is stopped.

[0118] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0119] Define historical access, which refers to the state of a previously accessed site.

[0120] Specifically, historical access can be defined as

[0121] In conjunction with the first aspect, in some descriptions of the first aspect, when storing the first element in all paths, the method further includes:

[0122] The first element is deleted from the queue and stored in the history of access.

[0123] In conjunction with the first aspect, in some descriptions of the first aspect, the method further includes:

[0124] If the updated state is not found in the historical access, it is determined that the updated state has never been accessed, and the updated state is stored in the historical access.

[0125] Specifically, the first element is removed from the queue, for example, using a pop operation. The pop operation removes and returns a specific element from the data structure. To determine whether the state of the first element in the queue includes the state corresponding to the search target, the pop operation is used to pop the first element from the queue, and then the determination is made regarding whether its state includes the state corresponding to the search target.

[0126] For example, a quantum chip on a real quantum computer consists of four qubits, and its topology is as follows: Figure 5 As shown, the topological links determined by the connected edges in this topological structure are [[0,1], [0,2], [1,3], [2,3], [1,0], [2,0], [3,1], [3,2]]. The Hamiltonian H corresponding to the current objective optimization problem is... c =Z0Z3+Z1Z2, the target is [[0,3], [1,2]], then the initial state is [1,2,4,8]. The set depth can be, for example, 4.

[0127] The first element in the queue can be represented as [[[1,2,4,8],(),0]], and the initial queue can be represented as Q = deque([[[1,2,4,8],(),0]]). The search proceeds in a predetermined order: first target [0,3], then target [1,2].

[0128] First, determine if the queue is empty. If Q = deque([[[1,2,4,8],(),0]]) contains one element and is not empty, then determine if the state of the first element in the queue includes the state corresponding to the search target. For example, the first element [[[1,2,4,8],(),0]] can be popped from Q, and its state is s = [1,2,4,8], which does not include the state 2 corresponding to the search target [0,3]. 3 +2 0 =9.

[0129] Then, it checks whether the depth of the first element in the queue exceeds the set depth. The current depth is 0, which is less than the set depth of 4. Then, it iterates through each link determined according to the topology of the real quantum chip and updates the state according to the link. The first link is [0,1], and the updated state s' = [3,2,4,8].

[0130] The state s = [1,2,4,8] has only been visited previously, so this state has not been visited. Add a new element. Use the updated state s' = [3,2,4,8] as the state of the new element s' = [3,2,4,8].

[0131] If the state s' = [3,2,4,8] still does not include state 9, then the currently traversed link [0,1] is taken as the path [0,1], and the depth after adding one (0+1) is taken as the depth 1, resulting in the newly added element [[3,2,4,8],(0,1),1].

[0132] Continuing to iterate through the second link, which is [0,2], the updated state s' = [5,2,4,8] can be obtained by performing the above operations. Similarly, after the above operations, another item is added to Q, becoming deque([[[3,2,4,8],(0,1),1],[[5,2,4,8],(0,2),1]]). This continues until, after 8 operations, 9 is no longer included. At this point, 8 new elements have been added to Q, resulting in:

[0133] 0={list:3}[[3,2,4,8],(0,1),1]

[0134] 1={list:3}[[5,2,4,8],(0,2),1]

[0135] 2={list:3}[[1,10,4,8],(1,3),1]

[0136] 3={list:3}[[1,2,12,8],(2,3),1]

[0137] 4={list:3}[[1,3,4,8],(1,0),1]

[0138] 5={list:3}[[1,2,5,8],(2,0),1]

[0139] 6={list:3}[[1,2,4,10],(3,1),1]

[0140] 7={list:3}[[1,2,4,12],(3,2),1]

[0141] Then, continue to check if the queue is empty, pop the first item [[3,2,4,8],((0,1),),1], leaving 7 items, and then proceed to the operation of 8 links. However, [1,2,4,8] is repeated in the access history, so it is not added. Add 7 extra items, so there are 14 items in Q. Then pop the current first item [[5,2,4,8],((0,2),),1]] from Q, and repeat the above process, and so on.

[0142] After popping the first 8 states and adding new states, Q has 40 states, and the path length of each state becomes 2; then, in the same way, all cases with a path length of 3 are obtained.

[0143] At this point, we'll find that some of the states already contain a value of 9. These paths will be added to all paths (all_paths). When all_paths is not an empty set (meaning at least one solution has been found), if the path length is longer than the solution length, the search will terminate.

[0144] In this way, we have found a set (more than one) of paths starting from [1,2,4,8] and finding 9 = [0,3]. Then, for each path, we find the shortest path that starts from that final state and searches for [1,2]. This determines the shortest path.

[0145] Figure 6 A schematic diagram of a proposed circuit optimization device for a quantum approximation optimization algorithm provided in one embodiment of this application is shown. The device includes:

[0146] The target determination unit 601 is used to determine the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the target optimization problem, and to take the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the target, so as to obtain a set of targets;

[0147] The target search unit 602 is used to search the set of targets on the topology of the real quantum chip using a breadth-first search algorithm to determine the shortest execution path of all sub-items in the Hamiltonian, thereby realizing the proposed path optimization of the quantum approximation optimization algorithm.

[0148] Figure 7 The diagram illustrates the structure of a computer device according to an embodiment of this application, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system for the proposed circuit optimization method of the quantum approximation optimization algorithm in any of the above embodiments.

[0149] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of a computer system for the proposed circuit optimization method of the quantum approximation optimization algorithm in any of the above embodiments.

[0150] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of a computer system for the proposed circuit optimization method of the quantum approximation optimization algorithm in any of the above embodiments.

[0151] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0152] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0153] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0154] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0155] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0156] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0157] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0158] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0159] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0160] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0161] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0162] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0163] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A proposed circuit optimization method using a quantum approximation optimization algorithm, characterized in that, The method includes: By identifying the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the objective optimization problem, and taking the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the objective, a set of objectives is obtained. The set of targets is searched on the topology of a real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian, thereby achieving the proposed path optimization of the quantum approximation optimization algorithm.

2. The method according to claim 1, characterized in that, The step of searching the set of targets on the topology of a real quantum chip using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian includes: The search order of the set of targets is determined, and the set of targets is searched on the topology of the real quantum chip in accordance with the search order using a breadth-first search algorithm to determine the shortest execution path for all sub-items in the Hamiltonian.

3. The method according to claim 2, characterized in that, Determining the search order for the set of targets includes: Randomly select one target from the set of targets as the current target; The remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance between the remaining target and the current target is determined as the next target of the current target. The remaining target is the target in the group of targets other than the current target. The next target is taken as the current target, and the remaining target corresponding to the minimum value of the sum of the edge length of the remaining target and the edge distance of the remaining target and the current target is determined as the next target of the current target; If no remaining target exists, determine the search order for the set of targets.

4. The method according to claim 3, characterized in that, Before determining the remaining target corresponding to the minimum sum of the edge length of the remaining target and the edge distance between the remaining target and the current target as the next target of the current target, the method further includes: Determine a first distance between the endpoint of the current target and the starting point of the remaining targets, and a second distance between the endpoint of the current target and the starting point of the remaining targets; The smaller of the first distance and the second distance is determined as the edge distance between the remaining target and the current target.

5. The method according to claim 2, characterized in that, The step of searching the set of targets on the topology of the real quantum chip using a breadth-first search algorithm in the order of the search to determine the shortest execution path for all items in the Hamiltonian includes: The first target in the set of targets is determined as the search target according to the search order, and a queue and all paths are defined. The element information in the queue includes the state, which is used to record the state determined according to the link. The link is determined according to the topology of the real quantum chip. All paths are used to record the shortest execution path to achieve the sub-item corresponding to each search target. Determine whether the queue is empty; If it is not empty, then determine whether the state of the first element in the queue includes the state corresponding to the search target; If the state corresponding to the search target is included, then the first element is stored in all paths; The next search target is determined from the set of targets according to the search order, and the step of determining whether the queue is empty is performed. If the next search target does not exist in the set of targets, the shortest execution path for all sub-items in the Hamiltonian is determined based on all elements included in all paths.

6. The method according to claim 5, characterized in that, The element information in the queue also includes path and depth, whereby the path is used to record links and the depth is used to record the number of times the links are traversed. The method further includes: If the state corresponding to the search target is not included and the depth of the first element in the queue does not exceed the set depth, then each link determined according to the topology of the real quantum chip is traversed and the state is updated according to the link. If the updated state has not been visited and the updated state does not include the state corresponding to the search target, then add a new element and add the new element to the queue.

7. The method according to claim 6, characterized in that, The addition of a new element includes: The updated state is used as the state of the newly added element, the currently traversed link is used as the path, and the incremented depth is used as the depth to obtain the newly added element.

8. The method according to claim 6, characterized in that, The method further includes: If the depth exceeds the set depth, or if all paths are not empty and the depth exceeds the depth of the elements in all paths, then the search for the search target is stopped.

9. The method according to claim 6, characterized in that, The initial state of the first element in the queue is determined based on the total number of bits of the Pauli Z-gate in the Hamiltonian, with an empty initial path and an initial depth of zero.

10. The method according to claim 6, characterized in that, The method further includes: Define historical access, which refers to the state of a previously accessed site.

11. The method according to claim 10, characterized in that, When storing the first element in all paths, the method further includes: The first element is deleted from the queue and stored in the history of access.

12. The method according to claim 10, characterized in that, The method further includes: If the updated state is not found in the historical access, it is determined that the updated state has never been accessed, and the updated state is stored in the historical access.

13. A proposed circuit optimization device for a quantum approximation optimization algorithm, characterized in that, The device includes: The target determination unit is used to determine the two multiplied Pauli Z-gate sub-terms in the Hamiltonian corresponding to the target optimization problem, and to take the edge determined by the two qubits of the two Pauli Z-gates in the sub-term as the target, so as to obtain a set of targets; The target search unit is used to search the set of targets on the topology of the real quantum chip using a breadth-first search algorithm to determine the shortest execution path of all sub-items in the Hamiltonian, thereby realizing the proposed path optimization of the quantum approximation optimization algorithm.

14. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-12.

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