An IC chip package detection method for realizing system-in-package and 3D package

Abstract

The application discloses an IC chip package detection method for realizing system-level package and 3D package, and relates to the technical field of chip package detection, and comprises the following steps: vertically stacking a plurality of DRAM core particles on a basic logic core particle provided with a micro-bump array on a surface through a through silicon via, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing area risk levels and generating a differentiated scanning parameter set through a targeted scanning scheduling algorithm; controlling an external X-ray source to collect multi-spectral projection data according to the differentiated scanning parameter set for each suspicious area; performing three-dimensional reconstruction on a plurality of sets of multi-spectral projection data by using an enhanced reconstruction model embedded with physical prior knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defects as detection results. The application aims to solve the problems of perspective imaging difficulty and insufficient resolution of internal defects of high-density 3D stacked chips.

Description

Technical Field

[0001] This invention relates to the field of chip packaging and testing technology, and in particular to an IC chip packaging and testing method for realizing system-level packaging and 3D packaging. Background Technology

[0002] With the integration of integrated circuits entering the post-Moore's Law era, system-in-package (SIP) and 3D packaging technologies have become key approaches to improving chip performance and integration, with high-bandwidth memory being a typical example. However, the high density, multi-layered, and heterogeneous internal structure of such chips presents a severe challenge to packaging reliability testing. Traditional non-destructive testing methods (such as single-energy X-ray imaging) face inherent limitations: insufficient penetration imaging resolution for multi-layered stacked structures, low material interface contrast, and inefficient global uniform scanning mode, making it difficult to accurately identify micron-level through-silicon via voids, interlayer delamination, and other critical defects, which have become bottlenecks restricting the yield and reliability of advanced packaging. Summary of the Invention

[0003] This invention provides an IC chip packaging inspection method for implementing system-level packaging and 3D packaging, comprising:

[0004] Multiple DRAM chips are vertically stacked on a base logic chip with a microbump array on its surface through through-silicon vias (TSVs). The self-detection circuit integrated in the base logic chip is activated to obtain a list of coordinates of suspicious areas with electrical anomalies. The TSVs include high-density signal TSV regions and low-density monitoring TSV regions.

[0005] The list of coordinates of suspicious areas is input into the targeted scanning scheduling algorithm to classify the risk levels of different areas, and a differentiated scanning parameter set is dynamically generated based on the risk level. The differentiated scanning parameter set includes: applicable energy spectrum type and scanning resolution.

[0006] For each suspicious area, the external X-ray source is controlled to switch to the corresponding type of energy spectrum, and multispectral projection data is acquired according to the corresponding scanning resolution;

[0007] An enhanced reconstruction model with embedded physical prior knowledge is used to reconstruct three-dimensional data from multiple sets of multispectral projection data, resulting in enhanced three-dimensional volume data.

[0008] Automatic defect identification is performed on the enhanced 3D volume data, and the identified defects are output as the detection results.

[0009] The aforementioned IC chip packaging inspection method for system-level packaging and 3D packaging involves vertically stacking multiple DRAM chips through through-silicon vias (TSVs) onto a base logic chip with a micro-bump array on its surface. A self-detection circuit integrated within the base logic chip is activated to obtain a list of coordinates of suspicious areas exhibiting electrical anomalies. The TSVs comprise high-density signal TSV regions and low-density monitoring TSV regions, including:

[0010] DRAM chips are stacked on a base logic chip containing a self-detection circuit and partitioned TSVs, and then packaged in a standard package to form an IC chip.

[0011] The self-test circuit of the chip under test is activated, a diagnostic electrical signal is applied by low-density monitoring TSV, electrical parameters are collected and compared to determine abnormalities, abnormal points are mapped to three-dimensional logical coordinates and a list of suspicious areas is output.

[0012] The aforementioned IC chip packaging inspection method for system-level packaging and 3D packaging includes inputting a list of suspicious region coordinates into a targeted scanning scheduling algorithm to classify different regions into risk levels, and dynamically generating a differentiated scanning parameter set based on the risk level. The differentiated scanning parameter set includes: applicable energy spectrum type and scanning resolution, including:

[0013] The list of suspicious area coordinates is analyzed to determine the three-dimensional logical coordinates of each electrical anomaly point, and the physical influence domain is analyzed to determine the list of targeted scanning areas.

[0014] The risk level of each suspicious point and its associated area in the comprehensive targeted scanning area list is dynamically calculated and classified.

[0015] The aforementioned IC chip packaging inspection method for implementing system-level packaging and 3D packaging includes, for each suspicious area, controlling the external X-ray source to switch to the corresponding type of energy spectrum, and acquiring multispectral projection data according to the corresponding scanning resolution, including:

[0016] Receive the target scan list and differentiated parameter set, dynamically configure differentiated scan parameters according to risk level, and match the corresponding exposure time and projection quantity;

[0017] After configuration, the raw projection data is acquired, calibrated, and stored according to region and energy spectrum. The system then automatically moves to the next target region until the scan is complete.

[0018] The aforementioned IC chip packaging inspection method for implementing system-level packaging and 3D packaging includes using an enhanced reconstruction model embedded with prior physical knowledge to perform three-dimensional reconstruction of multiple sets of multispectral projection data to obtain enhanced three-dimensional volume data, including:

[0019] By extracting deep features from multispectral projection data and combining them with prior physical knowledge, an enhanced reconstruction model is constructed.

[0020] Using multispectral projection data and physical prior tensors as input, the system outputs enhanced 3D volume data through an enhanced reconstruction model.

[0021] The IC chip packaging inspection method for implementing system-level packaging and 3D packaging includes automatic defect identification of enhanced three-dimensional volume data and outputting the identified defects as inspection results, comprising:

[0022] Receive enhanced 3D volume data and a list of targeted scanning regions, and output a defect segmentation mask through a 3D U-shaped network to accurately segment all defect instances;

[0023] For each segmented defect instance, extract multi-dimensional feature vectors to output the defect category and calculate the comprehensive severity level.

[0024] The beneficial effects achieved by this invention are as follows:

[0025] By combining detection guidance and imaging enhancement algorithms, high-resolution, high-contrast intelligent imaging of internal defects in high-density chip packaging is achieved, significantly improving the resolution and efficiency of defect detection. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0027] Figure 1 This is a flowchart of an IC chip packaging and testing method for implementing system-level packaging and 3D packaging, provided in Embodiment 1 of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example 1

[0030] like Figure 1 As shown, Embodiment 1 of this application provides an IC chip packaging inspection method for implementing system-level packaging and 3D packaging, including:

[0031] S1: Multiple DRAM chips are vertically stacked on a base logic chip with a microbump array on its surface through through-silicon vias (TSVs), and a self-detection circuit integrated in the base logic chip is activated to obtain a list of coordinates of suspicious areas with electrical anomalies. The TSVs include high-density signal TSV areas and low-density monitoring TSV areas.

[0032] The process involves vertically stacking multiple DRAM chips onto a base logic chip with a microbump array on its surface via through-silicon vias (TSVs), activating a self-detection circuit integrated within the base logic chip, and obtaining a list of coordinates of suspected areas with electrical anomalies. The TSVs contain high-density signal TSV regions and low-density monitoring TSV regions. The process includes the following sub-steps:

[0033] S11: DRAM chips are stacked on a basic logic chip containing a self-detection circuit and partitioned TSVs, and then packaged into an IC chip using standard packaging.

[0034] Multiple DRAM chips are sequentially stacked onto a pre-fabricated microbump array base logic chip using hybrid bonding or thermoforming bonding processes. During stacking, the TSVs of the upper DRAM chip are electrically and mechanically interconnected with the microbumps of the lower chip, ultimately forming a complete 3D stacked structure. The logic chip integrates self-detection circuitry beforehand, and the through-silicon vias (TSVs) are laid out on the layout, clearly distinguishing between high-density signal TSV areas and low-density monitoring TSV areas. After stacking, standard packaging processes such as underfill and molding are performed to form the final IC chip under test. It is important to note that the X-ray source, as an external detection device, is not integrated inside the chip. During testing, the prepared chip is placed on the stage of the X-ray detection system.

[0035] The DRAM chip refers to a memory cell that is vertically stacked on top of a basic logic chip through through-silicon vias (TSVs) and microbumps to form a 3D memory array; the TSV is a conductive channel that penetrates the silicon substrate of the chip to achieve vertical interconnection; the X-ray source is the core component of the external detection system, used to emit X-rays with switchable energy spectra to penetrate the chip and obtain multispectral projection data of its internal structure.

[0036] S12: Activate the self-test circuit of the chip under test, apply diagnostic electrical signals by low-density monitoring TSV, collect and compare electrical parameters to determine abnormalities, map abnormal points to three-dimensional logical coordinates and output a list of suspicious areas.

[0037] The chip under test (DUT) is placed in a test socket or dedicated fixture, connected to a power supply and a test bench, and its internal self-test circuit is activated. The circuit performs the following operations according to a preset program: The test excitation generator in the self-test circuit applies a series of diagnostic electrical signals (such as scan voltage, pulse signals, etc.) to the chip's vertical interconnect network through a dedicated channel in the low-density TSV monitoring area. The low-density TSV monitoring area provides physical space for test traces and sensors, and avoids mutual interference with high-speed TSV signals. The response acquisition module synchronously monitors the electrical parameters at each monitoring point, such as path resistance, capacitance, leakage current, and signal integrity. The data analysis module compares the acquired data with preset normal threshold ranges in real time. When the monitored electrical parameters exceed the threshold (e.g., abnormally high resistance in a TSV link, indicating possible microcracks or voids; or abnormal leakage between two paths, indicating possible bridging short circuits), the circuit determines that an electrical anomaly exists at that location.

[0038] After detecting an anomaly, the self-detection circuit records the anomaly data at each point to generate a structured coordinate list containing spatial semantics. Specifically, based on the chip's design layout information, the electrical anomaly points are mapped to the chip's three-dimensional logic coordinates. This coordinate system includes at least: the vertical level (which DRAM chip layer the anomaly occurs in), the planar block number (e.g., located in the A3 functional block of the logic chip), and the specific TSV column, ultimately outputting a list of coordinates for the suspected areas.

[0039] S2: Input the list of suspicious area coordinates into the targeted scanning scheduling algorithm, divide the risk level of different areas, and dynamically generate a differentiated scanning parameter set according to the risk level. The differentiated scanning parameter set includes: applicable energy spectrum type and scanning resolution.

[0040] The process involves inputting a list of suspicious area coordinates into a targeted scanning scheduling algorithm to classify different areas into risk levels, and then dynamically generating a differentiated set of scanning parameters based on the risk levels. This includes the following sub-steps:

[0041] S21: The list of suspicious area coordinates is analyzed to determine the three-dimensional logical coordinates of each electrical anomaly point, and the physical influence domain is analyzed to determine the list of targeted scanning areas.

[0042] The system receives a list of suspicious region coordinates and performs data fusion and correlation analysis with the chip's design knowledge file (containing precise TSV / bump layout and material stack-up information). Specifically, it analyzes the three-dimensional logic coordinates of each electrical anomaly point; for example, [L2,Zone_B5,TSV_Column_28]. Based on the design knowledge, it determines the DRAM chip thickness, material properties, and its Z-axis (vertical) coordinate range in the overall stack based on the layer number (L2). It also determines the precise boundary of the block in the XY plane and all internal circuit structures (logic cells, interconnects, etc.) based on the block number (Zone_B5). Finally, it determines the diameter, spacing, and alignment relationship with the microbumps above and below each TSV in the TSV column (TSV_Column_28).

[0043] Based on the above information, the physical spatial coordinates of the anomaly point are calculated, and all interconnections directly connected to it are identified. For example, [L2,Zone_B5,TSV_Column_28] is a TSV located at Z=150µm below the chip surface, with coordinates (X,Y) of (1250,780). It is connected upwards to a memory cell of the L2 layer DRAM and downwards to an input / output node of the logic chip.

[0044] After resolving the three-dimensional logical coordinates, the targeted scan scheduling algorithm further performs a physical influence domain analysis to determine the extended region where high-resolution targeted scanning needs to be implemented. Specifically, this analysis is based on at least one of the following principles:

[0045] Spatial proximity and structural association principles: Based on the chip design knowledge, identify other components that are physically adjacent to the electrical anomaly and located within the same critical structural unit. For example, when the anomaly is located at a through-silicon via (TSV), the entire high-density signal TSV array block to which the TSV belongs, or adjacent interconnect structures sharing the same microbump coupling node, are classified as high-risk influence regions to be scanned.

[0046] Electrical connectivity and network analysis principles: Access the layout netlist information of the chip design knowledge to trace the entire local network directly electrically connected to the electrical anomaly. For example, if the anomaly is a power network leakage, all wiring of that power network within the functional block where the anomaly is located, as well as the critical logic unit area powered by that network, are defined as the affected domain.

[0047] The final output includes a comprehensive list of targeted scan areas containing the original anomaly coordinates and their physical influence domains.

[0048] S22: Dynamically calculate and classify the risk level of each suspicious point and its associated area in the comprehensive targeted scanning area list.

[0049] Next, risk levels (e.g., high (H), medium (M), low (L)) are dynamically calculated and classified for each suspected point and its associated area according to assessment criteria. Assessment criteria typically include:

[0050] 1. Severity of electrical anomalies: The percentage by which parameters deviate from normal thresholds (e.g., a 200% increase in resistance is riskier than a 50% increase).

[0051] 2. Structural criticality: Whether the anomaly is located on the critical path such as clock or power supply, or in the high-density signal TSV region where stress is concentrated.

[0052] 3. Failure mode prior probability: Based on historical process data, certain locations are more prone to specific defects (such as edge bumps being prone to cracking).

[0053] Specifically, given the area to be evaluated, its comprehensive risk score is... It is calculated using the following formula:

[0054] in, The score indicates the severity of the electrical anomaly; and The first The measured and standard values ​​of each electrical parameter, where n represents the total number of electrical parameters; It is a piecewise linear scoring function. ;in, This represents the normal process fluctuation threshold, which characterizes the maximum percentage deviation of electrical parameters allowed due to inherent process fluctuations under defect-free conditions; deviations below this threshold are considered normal fluctuations and do not contribute to the risk score. It indicates the turning point of severe deviation, defining the critical point between "moderate deviation" and "severe deviation"; This represents the maximum score under normal conditions, which is when the deviation... achieve The full score assigned at that time represents the achievement of meeting the requirements. Under the given conditions, the highest risk benchmark value that electrical anomalies can contribute; The slope of the score in the moderate deviation zone determines the deviation range. Within, the rate at which the score increases with deviation; The additional scoring slope for the severely exceeding zone is defined as the slope at which the deviation exceeds the severe inflection point. The additional rating slope afterward. It is typically set to... ,For example To impose stronger risk weights on anomalies that significantly exceed the limits; For optional range normalization functions, ensure Indicates the structural criticality coefficient; This represents the upper limit of the normalized structural criticality coefficient; This is the three-dimensional logical coordinate vector of the region; The functional unit type and location attributes mapped from the design knowledge base; This is a basic risk value obtained by mapping from a chip design knowledge base; As an indicator function, when the region is adjacent Known high-risk design unit set The value is 1 if the condition is met, and 0 otherwise. This is the nearest neighbor addition factor (e.g., 0.1). This represents the prior probability coefficient of the fault; These are classified by structure type and location, respectively, mapped from historical databases; The corresponding historical statistical failure rate is used to characterize the historical failure tendency of a specific type of structure at a specific location, providing predictive prior knowledge based on real process experience for risk assessment; Normalized mapping function; contribution factor It is a configurable constant that satisfies This is used to balance the contributions of each factor.

[0055] Calculated After the value is calculated, the risk level is determined based on a preset threshold: low risk. Medium risk High risk ;in and This is an empirical threshold.

[0056] The output is a "list of targeted scanning regions" labeled with risk levels. For regions in the list with different risk levels, distinct sets of scanning parameters are automatically generated to ensure an optimal balance between efficiency and accuracy. These differentiated scanning parameter sets include: applicable energy spectrum type and scanning resolution.

[0057] S3: For each suspicious area, control the external X-ray source to switch to the corresponding type of energy spectrum, and acquire multispectral projection data according to the corresponding scanning resolution;

[0058] For each suspected area, the external X-ray source is switched to the corresponding energy spectrum, and multispectral projection data is acquired according to the corresponding scanning resolution, including the following sub-steps:

[0059] S31: Receive the target scan list and differential parameter set, dynamically configure the differential scan parameters according to the risk level, and match the corresponding exposure time and projection quantity;

[0060] The system receives a list of target scanning regions and a set of differentiated scanning parameters for each region. Following the order of the list, it drives a six-axis precision motion platform to precisely position the first target region of the chip under test within the field of view of the X-ray source and detector. Then, it analyzes the scanning parameter set of the current target region and dynamically configures the X-ray source and detector accordingly.

[0061] The choice of energy spectrum and the setting of scanning resolution are directly related to the risk level. For example, high-risk areas H use a combination of dual-energy / multi-energy spectra (such as 80kV and 150kV) and high resolution, setting long single-frame exposure times (e.g., >2 seconds) and planning dense projection acquisition paths (typically >1800 projection angles) to obtain the highest spatial detail and signal-to-noise ratio. Medium-risk areas M optimize single-energy spectra (selecting an energy that best balances penetration and contrast, such as 120kV), setting the scanning resolution to standard high-resolution mode, and appropriately reducing the number of projections (e.g., 800-1200) to significantly improve acquisition speed while ensuring defect detection capabilities, used to confirm or eliminate potential problems over a large area. Low-risk areas L or background areas utilize high-energy single spectra (e.g., above 130kV for rapid penetration) and fast scanning resolution (<500 projections, or even sparse angle scanning with the shortest exposure time) to quickly complete large-area coverage, used to confirm the overall structural integrity.

[0062] The precision motion platform is an independent, high-precision multi-axis (usually four to six axes) mechanical positioning system used to carry and fix the IC chip under test. It precisely moves the specific area on the chip that needs to be scanned to the center of the path of the X-ray beam (called the "field of view") and moves it along a preset trajectory (such as 360-degree rotation) to collect projections from various angles.

[0063] A detector is a device that records a two-dimensional image of X-rays attenuated by different parts of a chip at each angle. It consists of an array of millions of tiny pixelated sensing units (such as amorphous silicon or CMOS sensors).

[0064] The X-ray source and detector are fixed on opposite sides of the gantry, in relatively fixed positions. A precision motion platform, carrying the chip, performs precise movement and rotation within the beam path between them.

[0065] S32: After configuration, the raw projection data is acquired, calibrated, and stored according to region and energy spectrum. It then automatically moves to the next target region until the scan is complete.

[0066] After configuration, the automatic scanning sequence is initiated. The precision motion platform rotates the chip according to the planned scanning path (such as a circular or helical trajectory), and the X-ray source and detector are synchronously triggered at each preset angular position. For areas requiring multispectral scanning, at each or every few angular positions, the X-ray source rapidly switches between two tube voltages as instructed, while the detector synchronously acquires two projection images at the corresponding energy, ensuring that the two sets of projection datasets are perfectly matched geometrically. The acquired raw projection data undergoes preliminary dark-field and bright-field correction to eliminate detector noise and response inhomogeneity. Subsequently, it is stored as multispectral projection data along with metadata such as acquisition angle and energy spectrum labels, categorized by region and energy spectrum (high energy spectrum and low energy spectrum). After acquiring data for one region, the system automatically moves the chip to the next target position in the targeted scanning region list until all regions in the list have been scanned.

[0067] S4: Using an enhanced reconstruction model with embedded physical prior knowledge, multiple sets of multispectral projection data are reconstructed in three dimensions to obtain enhanced three-dimensional volume data;

[0068] The process involves using an enhanced reconstruction model embedded with prior physical knowledge to perform 3D reconstruction of multiple sets of multispectral projection data, resulting in enhanced 3D volume data. This includes the following sub-steps:

[0069] S41: By extracting deep features from multispectral projection data and combining them with prior physical knowledge, an enhanced reconstruction model is constructed.

[0070] The augmented reconstruction model is an end-to-end deep learning network whose architecture includes, in sequence: a dual-path spectral feature encoder, a physical prior knowledge fusion module, and a 3D decoder.

[0071] The dual-path spectral feature encoder consists of two identical, parameter-independent sub-encoder networks connected in parallel, one for processing high-energy spectral projection data and the other for low-energy spectral projection data. Each sub-encoder contains multiple cascaded coding units, each consisting of a 3D convolutional layer, a normalization layer, and an activation function layer connected sequentially. Feature maps are downsampled using pooling layers to extract deep abstract features from different energy spectral data. Through progressive downsampling, each encoder transforms the input projection data sequence (dimensions: `[number of angles, detector height, detector width, number of channels]`) into a series of multi-scale deep feature maps. The weights of the two encoders are independent, ensuring that they learn the unique feature patterns of different energy spectral data.

[0072] The physical prior knowledge fusion module receives feature maps from the dual-path encoder and physical prior tensors from the chip design. These physical prior tensors include at least a structural mask tensor aligned with the space to be reconstructed (a three-dimensional binary tensor, with values ​​of 1 at preset positions in key interconnect structures such as TSVs and microbumps, and 0 elsewhere) and a material composition probability tensor (a three-dimensional multi-channel tensor, where each channel represents the prior probability that a voxel belongs to a certain type of basic material, such as silicon, copper, tin alloy, polymer, etc.). This module uses conditional feature modulation technology, specifically, to use the physical prior tensors as dynamic weight parameters to scale and bias the feature maps from the encoder channel by channel. This ensures that during the learning process, the network can dynamically enhance or suppress the information flow related to known structures and materials in the feature maps based on the physical priors, thus completing the deep guidance and correction of data features by physical rules.

[0073] 3D Decoder: The decoder consists of multiple decoding levels, symmetrical to the encoder levels. Each level contains a 3D transposed convolutional layer (for upsampling), a skip connection to the corresponding encoder level feature map, and convolutional and activation layers. The skip connection combines the detailed features extracted by the encoder with the contextual features recovered by the decoder, helping to reconstruct clear structural boundaries.

[0074] Each decoding stage is followed by a 3D convolutional layer and a sigmoid activation function, outputting the final reconstruction result—enhanced 3D volumetric data, where each voxel value represents a corrected linear decay coefficient.

[0075] S42: Takes multispectral projection data and physical prior tensors as input, and outputs enhanced 3D volume data through enhanced reconstruction model.

[0076] Multispectral projection data and physical prior tensors are fed into the model in batches. An encoding-fusion-decoding process is performed through forward propagation to generate a predicted 3D volume. The composite loss function between the predicted volume and the ground truth label is calculated.

[0077] High-energy spectral projection data, low-energy spectral projection data, and physical prior tensors are input in batches into the enhanced reconstruction model. The forward propagation process is then executed, sequentially passing through:

[0078] A dual-path spectral feature encoder performs multi-layer 3D convolution and downsampling on high-energy spectral projection data and low-energy spectral projection data respectively to extract multi-scale depth feature maps. Then, the extracted feature maps are conditionally modulated with physical prior tensors to fuse structural masks and material prior information. Subsequently, high-resolution 3D volume data is reconstructed by progressively upsampling through transposed convolution and skip connections.

[0079] After the above encoding-fusion-decoding process, the model outputs the predicted 3D volume data. This involves enhancing the 3D volumetric data. Subsequently, a composite loss function is used. The difference between the predicted and true labels is calculated, and the Adam optimizer is used for backpropagation to update the model parameters. Continue until the model converges.

[0080] Among them, the composite loss function The specific formula is as follows:

[0081] Represents the overall loss function; This represents the set of all trainable parameters in the augmentation and reconstruction model (such as the weights and biases of the convolutional kernels). The optimization process involves finding the optimal set. This enables the model to accurately reconstruct three-dimensional structures from multispectral projection data; Indicates the projection of known high-energy spectrum observations Low-energy spectrum observation projection and physical prior mask tensor Under the conditions of real, flawless, ideal three-dimensional volume data The probability of occurrence; It represents an estimate of the standard deviation of data noise and is an adaptive scaling factor used to quantify the noise level in the observed data; Represents the set of all projection angles; This represents a robust loss function used to resist interference from a few serious erroneous projection data caused by hardware defects, scattering, or artifacts. The projected data representing the model's predictions are the 3D volume data reconstructed from the current model. By using the forward projection operator at the angle The two-dimensional projection image obtained from the calculation simulation; This represents the actual multispectral projection data collected;

[0082] It is a hyperparameter greater than 0, used to adjust the relative importance or strength of the physical prior constraint in the total loss; This represents all prior-defined local structural regions in the chip (such as each individual TSV, each microbump). This represents the KL divergence, used to measure the distance between the distribution predicted by the model and the physical prior distribution; Indicates that, given a physical prior mask Given a binary tensor (e.g., one labeled with the k-th TSV position), the parameter is... The three-dimensional volume data reconstructed from the model is in the region Empirical distribution of endothelial values; Represents a region defined based on a material library and physical laws. The theoretical physical prior distribution of the intrinsic voxel values; for example, for a TSV region labeled "copper", this distribution might be a narrow distribution centered on the theoretical X-ray attenuation coefficient of copper; It is a hyperparameter greater than 0, used to control the weight of the edge regularization term in the total loss; This represents the edge-aware similarity metric function, which measures the difference in cosine similarity between two gradient fields; Represents the reconstructed three-dimensional volume data Spatial gradient field; areas with large gradient values ​​correspond to edges or interfaces in the image (such as the sidewalls of TSV, chip layer boundaries). Represents the physical prior mask tensor The calculated desired edge map;

[0083] The final output is enhanced 3D volumetric data. This data systematically enhances the signal-to-noise ratio, material contrast, and edge sharpness in key areas such as electrical anomaly coordinates and high-density interconnect structures, ensuring that micron- and submicron-level defects are clearly displayed.

[0084] Additionally, using The optimizer (initial learning rate 1e-4, β1=0.9, β2=0.999) performs backpropagation to update the network weights. Training lasts approximately 300 epochs and stops when the validation set loss no longer decreases.

[0085] S5: Automatically identify defects in the enhanced 3D volume data and output the identified defects as the detection results.

[0086] The process of automatically identifying defects in the enhanced 3D volume data and outputting the identified defects as detection results includes the following sub-steps:

[0087] S51: Receives enhanced 3D volume data and a list of targeted scanning regions, outputs a defect segmentation mask through a 3D U-shaped network, and accurately segments all defect instances;

[0088] The system receives enhanced 3D volumetric data and loads a list of targeted scanning regions (including the coordinates of high-risk regions and their risk levels). Specifically, it prioritizes processing high-risk (H) and medium-risk (M) regions marked in the list. Within these regions, local visual features extracted from the 3D volumetric data (such as local grayscale anomalies and texture disturbances) are spatially correlated and verified with the coordinates of electrical anomalies. This ensures that the identification process focuses from the outset on the most likely problematic regions that have already exhibited electrical characteristics. A 3DU-Net network is then used as the segmentation core. Its input is the volumetric data block of the located region, and its output is a pixel-level labeled defect segmentation mask of the same size, accurately segmenting defect instances that deviate from the expected geometry or material uniformity. The network encoder part additionally receives the region's "design rules" as side input. For example, when processing a TSV region, the network can explicitly "know" that it should be a continuous cylindrical structure. This ensures that the network can more accurately segment parts that deviate from the expected geometry or material homogeneity (such as dark cavities, protrusions on the sidewalls, or cracks within a cylinder), improving the segmentation accuracy for small, blurry defect edges.

[0089] S52: For each segmented defect instance, extract multi-dimensional feature vectors, output the defect category, and calculate the comprehensive severity level.

[0090] For each segmented defect instance, the system extracts multi-dimensional feature vectors, including: three-dimensional morphological features (volume, surface area, aspect ratio, compactness, grayscale, etc.) and material features, contextual features, etc.

[0091] Finally, the fused feature vectors are input into a pre-trained multi-layer fully connected neural network classifier, which outputs the defect's category and confidence level. Based on the defect's 3D morphological features and location criticality (whether it is located in the power / clock path, etc.), a rule engine or lightweight evaluation network is used to calculate the defect's overall severity level (e.g., "fatal," "major," "minor"). A structured detection result is generated, including: 3D spatial coordinates (accurate to layer and XYZ position), type, quantization size, and associated electrical anomaly ID.

[0092] Corresponding to the above embodiments, the present invention provides a computer storage medium, including: at least one memory and at least one processor;

[0093] The memory is used to store one or more program instructions;

[0094] A processor is used to run one or more program instructions to execute an IC chip packaging inspection method that implements system-level packaging and 3D packaging.

[0095] Corresponding to the above embodiments, the present invention provides a computer-readable storage medium containing one or more program instructions, which are executed by a processor to provide an IC chip packaging and testing method for implementing system-level packaging and 3D packaging.

[0096] The embodiments disclosed in this invention provide a computer-readable storage medium storing computer program instructions. When the computer program instructions are executed on a computer, the computer performs the aforementioned IC chip packaging and testing method for implementing system-level packaging and 3D packaging.

[0097] In this embodiment of the invention, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0098] The various methods, steps, and logic diagrams disclosed in the embodiments of this invention can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The processor reads information from the storage medium and, in conjunction with its hardware, completes the steps of the above methods.

[0099] The storage medium can be memory, such as volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.

[0100] Among them, non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory.

[0101] Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM).

[0102] The storage media described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0103] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using a combination of hardware and software. When applied as software, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0104] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for testing IC chip packaging that implements system-level packaging and 3D packaging, characterized in that, include: Multiple DRAM chips are vertically stacked on a base logic chip with a microbump array on its surface through through-silicon vias (TSVs). The self-detection circuit integrated in the base logic chip is activated to obtain a list of coordinates of suspicious areas with electrical anomalies. The TSVs include high-density signal TSV regions and low-density monitoring TSV regions. The list of coordinates of suspicious areas is input into the targeted scanning scheduling algorithm to classify the risk levels of different areas, and a differentiated scanning parameter set is dynamically generated based on the risk level. The differentiated scanning parameter set includes: applicable energy spectrum type and scanning resolution. For each suspicious area, the external X-ray source is controlled to switch to the corresponding type of energy spectrum, and multispectral projection data is acquired according to the corresponding scanning resolution; An enhanced reconstruction model with embedded physical prior knowledge is used to reconstruct three-dimensional data from multiple sets of multispectral projection data, resulting in enhanced three-dimensional volume data. Automatic defect identification is performed on the enhanced 3D volume data, and the identified defects are output as the detection results; The algorithm inputs a list of suspicious area coordinates into a targeted scan scheduling algorithm to classify different areas into risk levels, including: The list of suspicious area coordinates is analyzed to determine the three-dimensional logical coordinates of each electrical anomaly point, and the physical influence domain is analyzed to determine the list of targeted scanning areas. The risk level of each suspicious point and its associated area in the comprehensive targeted scanning area list is dynamically calculated and classified.

2. The IC chip packaging inspection method for realizing system-level packaging and 3D packaging according to claim 1, characterized in that, Multiple DRAM chips are vertically stacked on a base logic chip with a microbump array on its surface via through-silicon vias (TSVs). A self-detection circuit integrated within the base logic chip is activated to obtain a list of coordinates of suspected areas with electrical anomalies. The TSVs contain high-density signal TSV regions and low-density monitoring TSV regions, including: DRAM chips are stacked on a base logic chip containing a self-detection circuit and partitioned TSVs, and then packaged in a standard package to form an IC chip. The self-test circuit of the chip under test is activated, a diagnostic electrical signal is applied by low-density monitoring TSV, electrical parameters are collected and compared to determine abnormalities, abnormal points are mapped to three-dimensional logical coordinates and a list of suspicious areas is output.

3. The IC chip packaging inspection method for realizing system-level packaging and 3D packaging according to claim 1, characterized in that, For each suspected area, the external X-ray source is switched to the corresponding energy spectrum, and multispectral projection data is acquired according to the corresponding scanning resolution, including: Receive the target scan list and differentiated parameter set, dynamically configure differentiated scan parameters according to risk level, and match the corresponding exposure time and projection quantity; After configuration, the raw projection data is acquired, calibrated, and stored according to region and energy spectrum. The system then automatically moves to the next target region until the scan is complete.

4. The IC chip packaging inspection method for realizing system-level packaging and 3D packaging according to claim 1, characterized in that, An enhanced reconstruction model embedding prior physical knowledge is used to reconstruct three-dimensional data from multiple sets of multispectral projection data, resulting in enhanced three-dimensional volume data, including: By extracting deep features from multispectral projection data and combining them with prior physical knowledge, an enhanced reconstruction model is constructed. Using multispectral projection data and physical prior tensors as input, the system outputs enhanced 3D volume data through an enhanced reconstruction model.

5. The IC chip packaging inspection method for realizing system-level packaging and 3D packaging according to claim 1, characterized in that, Automatic defect identification is performed on the enhanced 3D volume data, and the identified defects are output as detection results, including: Receive enhanced 3D volume data and a list of targeted scanning regions, and output a defect segmentation mask through a 3D U-shaped network to accurately segment all defect instances; For each segmented defect instance, extract multi-dimensional feature vectors to output the defect category and calculate the comprehensive severity level.

6. A computer-readable storage medium, characterized in that, It includes one or more program instructions, which are executed by a processor as described in any one of claims 1-5, to implement an IC chip packaging and testing method for system-level packaging and 3D packaging.

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