Driving circuit of display panel and display device

Abstract

The invention provides a driving circuit of a display panel and a display device.The driving circuit of the display panel comprises a plurality of signal output circuits, a plurality of first switching circuits and a plurality of first time sequence comparison circuits; the first time sequence comparison circuit receives one path of first target driving signals and controls the first switching circuits to be switched on, the first target driving signals are output to target signal ends of the display panel, and the multiple target driving signals at least comprise one path of common electrode voltage and one path of data voltage; the voltages of the two corresponding electrode ends of the display panel are equal, liquid crystals of the liquid crystal layer do not deflect and transmit light during startup, so that startup splash screen does not occur, then in the subsequent time period, the first time sequence comparison circuit sequentially controls the first switching circuit to be switched off, the multiple second target signal ends sequentially receive matched second target driving signals, and the second target driving signals are switched off. And the display panel is normally driven and displays corresponding image information.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a driving circuit and display device for a display panel. Background Technology

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main types of flat panel displays and has become an important display platform in modern IT and visual products.

[0003] like Figure 1 As shown, the display device consists of a display panel and corresponding driving circuits. The display panel is composed of an array substrate, a color filter substrate, and a liquid crystal layer disposed between the two substrates. The liquid crystal in the liquid crystal layer changes the polarization angle of the transmitted light as the pressure difference between the two ends changes, and displays different brightness under the action of the polarizer.

[0004] One end of the liquid crystal layer has a fixed common electrode voltage, while the other end uses a source drive circuit to output a data voltage to charge each sub-pixel. The input data voltage and the common electrode voltage create a voltage difference across the liquid crystal layer, controlling the display panel to show different brightness levels.

[0005] However, when the display panel is powered on, there is a problem that the output timing of the common electrode voltage and the data voltage is different, which causes a voltage difference between the two ends of the liquid crystal layer, allowing light to pass through the liquid crystal layer and causing screen flickering. Summary of the Invention

[0006] The purpose of this invention is to provide a driving method for a display panel, which aims to solve the problem of screen flickering during the startup of traditional display panels.

[0007] A first aspect of this invention provides a driving circuit for a display panel. The display panel has multiple target signal terminals, including a first target signal terminal and multiple second target signal terminals. The first target signal terminal is used to input a first target driving signal, and the multiple second target signal terminals are used to input a matching plurality of second target driving signals. The driving circuit for the display panel includes:

[0008] Multiple signal output circuits are used to output the first target driving signal and multiple second target driving signals respectively when powered on, wherein the output terminal of a matched signal output circuit is connected to the first target signal terminal of the display panel and transmits the first target driving signal, and the output timing of the first target driving signal is ahead of the output timing of the other second target driving signals; Multiple first switching circuits, the input terminals of the multiple first switching circuits are connected to the first target signal terminal, the output terminal of each first switching circuit is connected to a second target signal terminal and the output terminal of the matching signal output circuit, the first switching circuit is triggered to turn on by a first level signal and triggered to turn off by a second level signal; Multiple first timing comparison circuits are provided. The first input terminal of each first timing comparison circuit is connected to the first target signal terminal of the display panel. The second input terminal of each first timing comparison circuit is connected to the output terminal of a corresponding signal output circuit. The output terminal of each first timing comparison circuit is connected to the control terminal of a corresponding first switching circuit. The first timing comparison circuit is used to output the first level signal when receiving a first target driving signal and to output the second level signal when receiving a first target driving signal and a second target driving signal.

[0009] Optionally, the driving circuit of the display panel further includes: The second switching circuit has its input terminal connected to the output terminal of a corresponding signal output circuit, and its output terminal connected to the first target signal terminal. The second switching circuit is turned off by a third level signal and turned on by a fourth level signal. The second timing comparator circuit has its first input terminal connected to the input terminal of the second switching circuit, its second input terminal grounded, and its output terminal connected to the control terminal of the second switching circuit. The second timing comparator circuit is used to output the third level signal when the first target driving signal is not received, and to output the fourth level signal when the first target driving signal is received.

[0010] Optionally, the first timing comparison circuit includes a first logic gate, wherein the first input terminal, the second input terminal, and the output terminal of the first logic gate are respectively the first input terminal, the second input terminal, and the output terminal of the first timing comparison circuit; The second timing comparison circuit includes a second logic gate, and the first input, second input, and output of the second logic gate are respectively the first input, second input, and output of the second timing comparison circuit.

[0011] Optionally, the amplitude of the first target driving signal is smaller than that of the remaining second target driving signals; The first timing comparison circuit includes a first comparator, wherein the non-inverting input, the inverting input, and the output of the first comparator are respectively the first input, the second input, and the output of the first timing comparison circuit; The second timing comparison circuit includes a second comparator, wherein the first input terminal, the second input terminal, and the output terminal of the second comparator are respectively the first input terminal, the second input terminal, and the output terminal of the second timing comparison circuit.

[0012] Optionally, the first switching circuit includes a first electronic switch tube, and the first terminal, the second terminal, and the control terminal of the first electronic switch tube respectively constitute the input terminal, the output terminal, and the control terminal of the first switching circuit. The second switching circuit includes a second electronic switch tube, and the first terminal, the second terminal, and the control terminal of the second electronic switch tube respectively constitute the input terminal, the output terminal, and the control terminal of the second switching circuit.

[0013] Optionally, the driving circuit of the display panel further includes: A switch switching circuit, wherein multiple input terminals of the switch switching circuit are connected to the output terminals of multiple signal output circuits one by one, the output terminal of the switch switching circuit is connected to the input terminals of multiple first switch circuits and the input terminals of second switch circuits, and the output terminal of the second switch circuit is also connected to the output terminal of a matching signal output circuit. The switch switching circuit is used to select one of its input terminals and output terminals to be connected according to a switch switching signal. Multiple selection circuits are provided, with their first input terminals connected to the output terminal of the switch switching circuit, their second input terminals grounded, the output terminal of one of the multiple selection circuits connected to the first input terminal of the second timing comparison circuit, and the output terminals of the other selection circuits connected to the first input terminals of the multiple first timing comparison circuits. The selection circuits are used to output the output signal or ground signal of the switch switching circuit to the second timing comparison circuit and the first timing comparison circuit according to the selection signal. The timing detection circuit is connected to multiple signal output circuits, the switch switching circuit, and multiple selection circuits respectively. The timing detection circuit is used to determine the first target drive signal from the target drive signal with a preset amplitude received first during the initial power-on period, and output the corresponding switch switching signal and the selection signal according to the first target drive signal.

[0014] Optionally, the switching circuit includes multiple parallel switching switches; The input terminals of the multiple switching switches are connected one by one to the output terminals of the multiple signal output circuits. The output terminals of the multiple switching switches are connected together to form the output terminal of the switching circuit. The control terminal of the switching switch is connected to the signal terminal of the timing detection circuit.

[0015] Optionally, the selection circuit includes a multiplexer, wherein the first input terminal, the second input terminal, the output terminal, and the control terminal of the multiplexer constitute the first input terminal, the second input terminal, the output terminal, and the control terminal of the selection circuit, respectively.

[0016] Optionally, the driving circuit of the display panel further includes: Multiple unidirectional conduction circuits are provided, with the input terminals of the multiple unidirectional conduction circuits connected to the output terminals of the multiple signal output circuits one by one, and the output terminals of the multiple unidirectional conduction circuits connected to the input terminals of the multiple first switch circuits and the input terminals of the multiple second switch circuits one by one. The unidirectional conduction circuits are used to transmit the corresponding target driving signal unidirectionally to the corresponding switch circuit.

[0017] A second aspect of the present invention provides a display device, including a display panel and a driving circuit for the display panel as described above, wherein the driving circuit for the display panel is connected to the display panel.

[0018] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The driving circuit of the above-mentioned display panel includes multiple signal output circuits, multiple first switch circuits, and multiple first timing comparison circuits. During the initial power-on period of the display panel, the first timing comparison circuit receives a first target driving signal and controls each of the first switch circuits to be turned on. The first target driving signal is output to each target signal terminal of the display panel. The multiple target driving signals include at least one common electrode voltage and one data voltage. The voltages of the corresponding two electrodes of the display panel are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not be deflected and transmitted when the power is turned on, so there will be no power-on screen flicker. Then, in the subsequent period, the first timing comparison circuit sequentially controls the first switch circuit to be turned off, and the multiple second target signal terminals sequentially receive the matching second target driving signal. The display panel is driven normally and displays the corresponding image information. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the display device provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a first structure of a display panel provided in Embodiment 1 of the present invention; Figure 3 These are schematic diagrams of the display devices provided in Embodiments 1 and 3 of the present invention. Figure 4 This is a signal timing diagram provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of a second structure of the display panel provided in Embodiment 1 of the present invention; Figure 6This is a schematic diagram of a first module of the driving circuit for a display panel provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of a second module of the driving circuit for the display panel provided in Embodiment 1 of the present invention; Figure 8 This is a first circuit diagram of the driving circuit for the display panel provided in Embodiment 1 of the present invention; Figure 9 This is a second circuit diagram of the driving circuit for the display panel provided in Embodiment 1 of the present invention; Figure 10 This is a schematic diagram of the driving circuit for the display panel provided in Embodiment 2 of the present invention; Figure 11 This is a schematic diagram of a first type of driving circuit for a display panel provided in Embodiment 2 of the present invention; Figure 12 This is a second circuit diagram of the driving circuit for the display panel provided in Embodiment 2 of the present invention.

[0020] The figures in the diagram are labeled as follows: 100. Display panel; 200. Driving circuit for display panel; 1. Circuit board; 2. Chip-coated film; 110. Display area; 120. Non-display area; 10. Array substrate; 20. Color filter substrate; 30. Liquid crystal layer; 11. Lower polarizer; 12. First substrate; 13. Pixel electrode; 21. Upper polarizer; 22. Second substrate; 23. Filter layer; 24. First common electrode layer; 210. Signal output circuit; 220. First switching circuit; 230. First timing comparator circuit; 240. Second switching circuit; 250. Second timing comparator circuit; 260. Switching circuit; 270. Selection circuit; 280. Timing detection circuit; 290. Unidirectional conduction circuit; T1, First electronic switch transistor; T2, Second electronic switch transistor; U1, First logic gate; U2, Second logic gate; U3, First comparator; U4, Second comparator; K1, Switch; D1, Diode; Vcom1, first common electrode voltage; Vcom2, second common electrode voltage; Vcom3, third common electrode voltage; V1, corresponding endpoint of the first common electrode layer; V2, corresponding endpoint of the second common electrode layer; V3, corresponding endpoint of the third common electrode layer; Vs, corresponding endpoint of the pixel electrode. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] Example 1 like Figure 1 As shown, the driving circuit 200 of the display panel is connected to the display panel 100. The display panel 100 can be disposed in the flexible circuit board 1 and multiple flip-chip films 2. The flip-chip films 2 are connected to the circuit board 1 and bonded to the non-display area 120 of the display panel 100.

[0024] like Figure 2 As shown, the display panel 100 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 disposed between the array substrate 10 and the color filter substrate 20. The array substrate 10 includes a lower polarizer 11, a first substrate 12, and a first conductive layer stacked sequentially. The first conductive layer may include a driving circuit layer and a pixel electrode layer stacked on top of each other. The driving circuit layer is stacked on the first substrate 12 and includes multiple data lines, multiple scan lines, and an array of thin-film transistors. The thin-film transistors are connected to a corresponding data line and a scan line. The scan line is used to input a horizontal scan signal, and the data line is used to input a data voltage Data. The pixel electrode layer includes multiple pixel electrodes 13 arranged in an array. Each pixel electrode 13 is connected to a thin-film transistor. The pixel electrode 13 and the corresponding thin-film transistor are disposed in the corresponding display area 110. When the thin-film transistor receives a horizontal scan signal, it turns on and writes a data signal. The data signal is transmitted to the pixel electrode 13 through the thin-film transistor.

[0025] The color filter substrate 20 includes an upper polarizer 21, a second substrate 22, a filter layer 23, and a second conductive layer stacked sequentially. The second conductive layer includes a first common electrode layer 24. The first common electrode layer 24 and the pixel electrode 13 form a plurality of liquid crystal capacitors. The first common electrode layer 24 is used to input a first common electrode voltage Vcom1. The first common electrode voltage Vcom1 and the data voltage Data form a driving voltage to drive the liquid crystal deflection of the liquid crystal layer 30.

[0026] The first conductive layer may also include a correspondingly stacked second common electrode layer, which forms a storage capacitor with the pixel electrode 13. The second common electrode layer is used to input the second common electrode voltage Vcom2.

[0027] When the sub-pixel is set to an eight-domain structure, the sub-pixel includes a main pixel and a secondary pixel. The first conductive layer may also include a third common electrode layer stacked accordingly. The third common electrode layer is used to input the third common electrode voltage Vcom3. The third common electrode voltage Vcom3 is used to control the deflection angle of the liquid crystal of the secondary pixel, thereby improving the viewing angle.

[0028] like Figure 3 As shown, the display panel 100 is used to output different driving signals to the display panel 100, and the driving signals may include at least the corresponding common electrode voltage and driving voltage.

[0029] When the voltages of the common electrodes and the data voltage Data are not synchronized when output on the display panel 100, for example... Figure 4 As shown, the first common electrode voltage Vcom1 is output first, while the data voltage Data is not output. Figure 5 As shown, the first common electrode voltage Vcom1 input first will form a voltage difference with the pixel electrode 13 which has no voltage signal, causing the liquid crystal to deflect first and transmit light, resulting in the problem of screen flickering when the display panel 100 is turned on.

[0030] To solve this problem, such as Figure 6 As shown, a first aspect of the present invention provides a driving circuit 200 for a display panel. The display panel 100 has a plurality of target signal terminals, including a first target signal terminal and a plurality of second target signal terminals. The first target signal terminal is used to input a first target driving signal, and the plurality of second target signal terminals are used to input a plurality of matching second target driving signals. For example, the first target signal terminal includes a corresponding endpoint V1 of the first common electrode layer 24, and the second target signal terminals respectively include a corresponding endpoint V2 of the second common electrode layer, a corresponding endpoint V3 of the third common electrode layer, and a corresponding endpoint Vs of the pixel electrode 13.

[0031] In this embodiment, the driving circuit 200 of the display panel includes: Multiple signal output circuits 210 are used to output a first target driving signal and multiple second target driving signals respectively when powered on. The output terminal of a matched signal output circuit 210 is connected to the first target signal terminal of the display panel 100 and transmits the first target driving signal. The output timing of the first target driving signal is ahead of the output timing of the other second target driving signals. Multiple first switching circuits 220 are provided, with their input terminals connected to a first target signal terminal. The output terminal of each first switching circuit 220 is connected to a second target signal terminal and the output terminal of a matching signal output circuit 210. The first switching circuit 220 is turned on by a first level signal and turned off by a second level signal. Multiple first timing comparison circuits 230 are provided. The first input terminal of each first timing comparison circuit 230 is connected to the first target signal terminal of the display panel 100. The second input terminal of each first timing comparison circuit 230 is connected to the output terminal of a corresponding signal output circuit 210. The output terminal of each first timing comparison circuit 230 is connected to the control terminal of a corresponding first switch circuit 220. The first timing comparison circuit 230 is used to output a first level signal when it receives a first target driving signal, and to output a second level signal when it receives a first target driving signal and a second target driving signal.

[0032] In this embodiment, the signal output circuit 210 can be a corresponding common electrode voltage circuit, source drive circuit, etc. The common electrode voltage circuit is used to output the corresponding common electrode voltage, such as outputting the first common electrode voltage Vcom1, the second common electrode voltage Vcom2 and the third common electrode voltage Vcom3. The source drive circuit is used to output the data voltage Data.

[0033] The target driving signal may include at least one first common electrode voltage Vcom1 and one data voltage Data. Each target driving signal corresponds one-to-one with each target signal terminal of the display panel 100. Each target signal terminal may be the corresponding common electrode layer of the display panel 100 or the corresponding endpoint of the data line. For example, the first common electrode voltage Vcom1 is matched with the corresponding endpoint V1 of the first common electrode layer 24 of the display panel 100, and the data voltage Data is matched with the corresponding endpoint of the corresponding data line.

[0034] One of the matching signal output circuits 210 is connected to the first target signal terminal of the display panel 100 and transmits the first target driving signal. The output timing of the first target driving signal is ahead of the other second target driving signals. For example, the output timing of the first common electrode voltage Vcom1 is ahead of the output timing of the other common electrode voltages and data voltage Data. The first target driving signal is the first common electrode voltage Vcom1. The first common electrode voltage Vcom1 is directly connected to the corresponding terminal V1 of the first common electrode layer 24 of the display panel 100.

[0035] Taking the first common electrode voltage Vcom1 as the first target driving signal and the second common electrode voltage Vcom2 and data voltage Data as the second target driving signals as an example, the first common electrode voltage Vcom1 leads the output timing of the second common electrode voltage Vcom2 and data voltage Data.

[0036] When the display panel 100 is powered on, the first common electrode voltage Vcom1 is established and output, but the second common electrode voltage Vcom2 and the data voltage Data are not yet established. Each first timing comparison circuit 230 receives the first common electrode voltage Vcom1 but does not receive the second common electrode voltage Vcom2 and the data voltage Data. The first timing comparison circuit 230 outputs a first level signal to control the corresponding connected first switch circuit 220 to be turned on. The first common electrode voltage Vcom1 is output to the corresponding endpoint V2 of the second common electrode layer, the corresponding endpoint Vs of the pixel electrode 13, and the corresponding endpoint V1 of the first common electrode layer 24 through each first switch circuit 220. The voltages of the corresponding two electrodes of the display panel 100 are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not be deflected and transmitted when the power is turned on, so there will be no screen flickering when the power is turned on.

[0037] After the first target driving signal is output to each target signal terminal, the first common electrode voltage Vcom1 is maintained at the corresponding terminal V1 of the first common electrode layer 24. In the subsequent period, each first timing comparison circuit 230 and the first switching circuit 220 output each second target driving signal to the matching target signal terminal according to the output timing of each second target driving signal.

[0038] For example, assuming the timing of the second common electrode voltage Vcom2 lags behind the first common electrode voltage Vcom1, and the timing of the data voltage Data lags behind the second common electrode voltage Vcom2, in a subsequent period, one of the first timing comparison circuits 230 receives the second common electrode voltage Vcom2 and the first common electrode voltage Vcom1. This first timing comparison circuit 230 outputs a second level signal to the connected first switching circuit 220, and the first switching circuit 220 is turned off. At this time, the corresponding endpoint V2 of the second common electrode layer switches to input the second common electrode voltage Vcom2. Then, another first timing comparison circuit 230 receives the data voltage Data and the first common electrode voltage Vcom1. This other first timing comparison circuit 230 outputs a second level signal to the connected first switching circuit 220, and the first switching circuit 220 is turned off. At this time, the corresponding endpoint Vs of the pixel electrode 13 switches to input the data voltage Data. The data voltage Data and the first common electrode voltage Vcom1 form a driving voltage and control the liquid crystal deflection, displaying the corresponding image information.

[0039] In another optional embodiment, to avoid noise interference caused by the display panel 100 being powered off and directly inputting noise signals to the first target signal terminal, such as... Figure 7 As shown, the driving circuit 200 of the display panel also includes: The second switching circuit 240 has its input terminal connected to the output terminal of a corresponding signal output circuit 210, and its output terminal connected to the first target signal terminal. The second switching circuit 240 is turned off by a third level signal and turned on by a fourth level signal. The second timing comparison circuit 250 has its first input terminal connected to the input terminal of the second switching circuit 240, its second input terminal grounded, and its output terminal connected to the control terminal of the second switching circuit 240. The second timing comparison circuit 250 is used to output a third-level signal when the first target driving signal is not received, and to output a fourth-level signal when the first target driving signal is received.

[0040] In this embodiment, when the device is not powered on, the second timing comparison circuit 250 does not receive the first target drive signal, but receives other noise signals. When the second timing comparison circuit 250 receives other noise signals, it outputs a third level signal to control the second switch circuit 240 to turn off. At this time, no noise signals are input to the first target signal terminal.

[0041] After power-on, when the first target drive signal is output normally, the second timing comparison circuit 250 inputs the first target drive signal, controls the second switching circuit 240 to turn on and transmits the first target drive signal to the corresponding target signal terminal.

[0042] The first switching circuit 220 and the second switching circuit 240 can employ switching transistors with controlled on / off states. The timing comparison circuit can select corresponding logic gates according to the type of the switching circuit. In an optional embodiment, such as... Figure 8 As shown, the first timing comparison circuit 230 includes a first logic gate U1, and the first input terminal, the second input terminal, and the output terminal of the first logic gate U1 are the first input terminal, the second input terminal, and the output terminal of the first timing comparison circuit 230, respectively. The second timing comparator circuit 250 includes a second logic gate U2, and the first input terminal, the second input terminal, and the output terminal of the second logic gate U2 are the first input terminal, the second input terminal, and the output terminal of the second timing comparator circuit 250, respectively.

[0043] The first switching circuit 220 includes a first electronic switch transistor T1. The first terminal, the second terminal, and the control terminal of the first electronic switch transistor T1 respectively constitute the input terminal, the output terminal, and the control terminal of the first switching circuit 220. The second switching circuit 240 includes a second electronic switch transistor T2. The first terminal, the second terminal, and the control terminal of the second electronic switch transistor T2 respectively constitute the input terminal, the output terminal, and the control terminal of the second switching circuit 240.

[0044] In this embodiment, taking the first common electrode voltage Vcom1 as the first target driving signal and the second common electrode voltage Vcom2, the third common electrode voltage Vcom3 and the data voltage Data as the second target driving signals as an example, the first common electrode voltage Vcom1 leads the output timing of the second common electrode voltage Vcom2 and the data voltage Data.

[0045] When the display panel 100 is powered on, the first common electrode voltage Vcom1 is established and output. The second common electrode voltage Vcom2, the third common electrode voltage Vcom3, and the data voltage Data are not yet established. The second logic gate U2 receives the first common electrode voltage Vcom1 and controls the second electronic switch T2 to conduct. The first logic gate U1 receives the first common electrode voltage Vcom1 but does not receive the second common electrode voltage Vcom2 and the data voltage Data. The first logic gate U1 controls the corresponding first electronic switch T1 to conduct. The first common electrode voltage Vcom1 is output to the corresponding endpoint V2 of the second common electrode layer, the corresponding endpoint V3 of the third common electrode layer, the corresponding endpoint Vs of the pixel electrode 13, and the corresponding endpoint V1 of the first common electrode layer 24 through the first electronic switch T1 and the second electronic switch T2, respectively. The voltages of the corresponding two electrodes of the display panel 100 are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not deflect and transmit light when the power is turned on, so there will be no screen flickering when the power is turned on.

[0046] After the first target driving signal is output to each target signal terminal, the first common electrode voltage Vcom1 is maintained and output to the corresponding terminal V1 of the first common electrode layer 24. In the subsequent period, each first logic gate U1 and the first electronic switch T1 output each second target driving signal to the matching target signal terminal according to the output timing of each second target driving signal.

[0047] For example, suppose the timing of the second common electrode voltage Vcom2 lags behind the first common electrode voltage Vcom1, the timing of the third common electrode voltage Vcom3 lags behind the second common electrode voltage Vcom2, and the timing of the data voltage Data lags behind the third common electrode voltage Vcom3. In a subsequent time period, one of the first logic gates U1 receives both the second common electrode voltage Vcom2 and the first common electrode voltage Vcom1. This first logic gate U1 controls the connected first electronic switch T1 to turn off. At this time, the corresponding terminal V2 of the second common electrode layer switches to input the second common electrode voltage Vcom2. Then, another first logic gate U1 receives the third... The first logic gate U1 controls the first electronic switch T1 connected to the common electrode voltage Vcom3 and the first common electrode voltage Vcom1 to turn off. At this time, the corresponding terminal V3 of the third common electrode layer switches to input the second common electrode voltage Vcom2. Then, another first logic gate U1 receives the data voltage Data and the first common electrode voltage Vcom1. The first logic gate U1 controls the first electronic switch T1 connected to turn off. At this time, the corresponding terminal Vs of the pixel electrode 13 switches to input the data voltage Data. The data voltage Data and the first common electrode voltage Vcom1 form a driving voltage and control the liquid crystal deflection to display the corresponding image information.

[0048] In an optional embodiment, the first logic gate U1 and the second logic gate U2 are NAND gates, which output a high-level signal when receiving one target driving signal and a low-level signal when receiving two target driving signals. The first electronic switch T1 and the second electronic switch T2 are N-channel field-effect transistors, and correspondingly, the first level signal and the fourth level signal are high-level signals, and the second level signal and the third level signal are low-level signals.

[0049] In another alternative embodiment, such as Figure 9 As shown, the amplitude of the first target driving signal is smaller than that of the other second target driving signals.

[0050] The first timing comparison circuit 230 includes a first comparator U3, wherein the non-inverting input terminal, the inverting input terminal, and the output terminal of the first comparator U3 are respectively the first input terminal, the second input terminal, and the output terminal of the first timing comparison circuit 230. The second timing comparison circuit 250 includes a second comparator U4, the first input terminal, the second input terminal, and the output terminal of the second comparator U4 being the first input terminal, the second input terminal, and the output terminal of the second timing comparison circuit 250, respectively.

[0051] The first switching circuit 220 includes a first electronic switch transistor T1. The first terminal, the second terminal, and the control terminal of the first electronic switch transistor T1 respectively constitute the input terminal, the output terminal, and the control terminal of the first switching circuit 220. The second switching circuit 240 includes a second electronic switch transistor T2. The first terminal, the second terminal, and the control terminal of the second electronic switch transistor T2 respectively constitute the input terminal, the output terminal, and the control terminal of the second switching circuit 240.

[0052] In this embodiment, taking the first common electrode voltage Vcom1 as the first target driving signal and the second common electrode voltage Vcom2, the third common electrode voltage Vcom3 and the data voltage Data as the second target driving signals as an example, the first common electrode voltage Vcom1 leads the output timing of the second common electrode voltage Vcom2 and the data voltage Data.

[0053] When the display panel 100 is powered on, the first common electrode voltage Vcom1 is established, but the second common electrode voltage Vcom2, the third common electrode voltage Vcom3, and the data voltage Data are not yet established. The second comparator U4 receives the first common electrode voltage Vcom1 and compares it to output a high-level signal, controlling the second electronic switch T2 to turn on. The first comparator U3 receives the first common electrode voltage Vcom1 but does not receive the second common electrode voltage Vcom2 and the data voltage Data. The first comparator U3 outputs a high-level signal, controlling the corresponding first electronic switch T1 to turn on. The first common electrode voltage Vcom1 is output to the corresponding endpoint V2 of the second common electrode layer, the corresponding endpoint V3 of the third common electrode layer, the corresponding endpoint Vs of the pixel electrode 13, and the corresponding endpoint V1 of the first common electrode layer 24 through the first electronic switch T1 and the second electronic switch T2, respectively. The voltages of the corresponding two electrodes of the display panel 100 are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not deflect and transmit light when the power is turned on, thus preventing screen flickering during power-on.

[0054] After the first target driving signal is output to each target signal terminal, the first common electrode voltage Vcom1 is maintained at the corresponding terminal V1 of the first common electrode layer 24. In the subsequent period, each first comparator U3 controls the corresponding first electronic switch T1 to turn off, and the signal output circuit 210 outputs each second target driving signal to the matching target signal terminal according to the output timing of each second target driving signal.

[0055] For example, suppose the timing of the second common electrode voltage Vcom2 lags behind the first common electrode voltage Vcom1, the timing of the third common electrode voltage Vcom3 lags behind the second common electrode voltage Vcom2, and the timing of the data voltage Data lags behind the third common electrode voltage Vcom3. In a subsequent time period, one of the first comparators U3 receives both the second common electrode voltage Vcom2 and the first common electrode voltage Vcom1. This first comparator U3 compares and outputs a low-level signal, controlling the connected first electronic switch T1 to turn off. At this time, the corresponding terminal V2 of the second common electrode layer switches to input the second common electrode voltage Vcom2. Then, another first comparator U3 receives the third... The first comparator U3 compares the common electrode voltage Vcom3 and the first common electrode voltage Vcom1, outputting a low-level signal to control the connected first electronic switch T1 to turn off. At this time, the corresponding terminal V3 of the third common electrode layer switches to input the second common electrode voltage Vcom2. Then, another first comparator U3 receives the data voltage Data and the first common electrode voltage Vcom1, and controls the connected first electronic switch T1 to turn off. At this time, the corresponding terminal Vs of the pixel electrode 13 switches to input the data voltage Data. The data voltage Data and the first common electrode voltage Vcom1 form a driving voltage and control the liquid crystal deflection to display the corresponding image information.

[0056] The beneficial effects of the present invention embodiment compared with the prior art are as follows: The driving circuit 200 of the above-mentioned display panel includes multiple signal output circuits 210, multiple first switching circuits 220 and multiple first timing comparison circuits 230. During the initial power-on period of the display panel 100, the first timing comparison circuit 230 receives a first target driving signal and controls each of the first switching circuits 220 to be turned on. The first target driving signal is output to each target signal terminal of the display panel 100. The multiple target driving signals include at least one common electrode voltage and one data voltage. The voltages of the corresponding two electrodes of the display panel 100 are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not be deflected and transmitted when the power is turned on, so there will be no power-on screen flicker. Then, in the subsequent period, the first timing comparison circuit 230 sequentially controls the first switching circuits 220 to be turned off, and the multiple second target signal terminals sequentially receive the matching second target driving signals. The display panel 100 is driven normally and displays the corresponding image information.

[0057] Example 2 Furthermore, in order to identify the first target driving signal and the second target driving signal among multiple target driving signals, the driving circuit 200 of the display panel can also be equipped with corresponding detection circuits, switching circuits, etc., and when the output timing of each signal output circuit 210 changes, in order to reliably output the corresponding target driving signal with the advanced output timing to each endpoint of the display panel 100 during the initial power-on period, in an optional embodiment, such as... Figure 10 As shown, the driving circuit 200 of the display panel also includes: The switch switching circuit 260 has multiple input terminals connected to the output terminals of multiple signal output circuits 210, and the output terminal of the switch switching circuit 260 is connected to the input terminals of multiple first switch circuits 220 and the input terminal of second switch circuit 240. The output terminal of the second switch circuit 240 is also connected to the output terminal of the matched signal output circuit 210. The switch switching circuit 260 is used to select one of its input terminals and output terminals to be connected according to the switch switching signal. Multiple selection circuits 270 are provided. The first input terminal of the multiple selection circuits 270 is connected to the output terminal of the switch switching circuit 260. The second input terminal of the multiple selection circuits 270 is grounded. The output terminal of one of the multiple selection circuits 270 is connected to the first input terminal of the second timing comparison circuit 250. The output terminals of the other selection circuits 270 are connected to the first input terminals of multiple first timing comparison circuits 230. The selection circuit 270 is used to output the output signal or the ground signal of the switch switching circuit 260 to the second timing comparison circuit 250 and the first timing comparison circuit 230 according to the selection signal. The timing detection circuit 280 is connected to multiple signal output circuits 210, switch switching circuit 260 and multiple selection circuits 270 respectively. The timing detection circuit 280 is used to determine the first target drive signal from the target drive signal with the preset amplitude received first during the initial power-on period, and output the corresponding switch switching signal and selection signal according to the first target drive signal.

[0058] In this embodiment, the timing detection circuit 280 is connected to multiple signal output circuits 210, acquires each target driving signal, compares the timing of multiple target driving signals, and sets the target driving signal with the earliest output timing as the first target driving signal. For example, the first common electrode voltage Vcom1 has the earliest output timing, so the first common electrode voltage Vcom1 is the first target driving signal. The remaining target driving signals other than the first target driving signal are used as the second target driving signals. For example, the remaining second common electrode voltage Vcom2, third common electrode voltage Vcom3 and data voltage Data are set as the second target driving signals.

[0059] After determining the first target driving signal and the second target driving signal, the timing detection circuit 280 outputs a corresponding switch switching signal to the switch switching circuit 260 to output the corresponding first target driving signal to the input terminals of the first switch circuit 220 and the second switch circuit 240, and outputs the first target driving signal to the selection circuit 270. At the same time, the timing detection circuit 280 outputs a corresponding selection signal to the selection circuit 270 to control the selection circuit 270 to select the corresponding ground signal or the first target driving signal to the first timing comparison circuit 230 and the second timing comparison circuit 250. The first timing comparison circuit 230 and the second timing comparison circuit 250 perform timing comparison on the input target driving signals and output corresponding level signals to the first switch circuit 220 and the second switch circuit 240, thereby outputting the first target driving signal to each target signal terminal in the initial power-on phase, and outputting the second target driving signal to the matching second target signal terminal in the subsequent phases according to the corresponding timing sequence.

[0060] At this initial power-on stage, the timing detection circuit 280 first receives the first common electrode voltage Vcom1. Then, the timing detection circuit 280 outputs a switch switching signal to control the switch switching circuit 260 to connect the signal output circuit 210 (outputting the first common electrode voltage Vcom1), the first switch circuit 220, the second switch circuit 240, and the selection circuit 270, thus outputting the first common electrode voltage Vcom1 to the first switch circuit 220, the second switch circuit 240, and the selection circuit 270. Simultaneously, the timing detection circuit 280 outputs a selection signal to the selection circuit 270 connected to the second timing comparison circuit 250, causing it to connect its ground terminal to the first input terminal of the second timing comparison circuit 250. At the same time, the timing detection circuit 280 outputs a selection signal. The signal is sent to the selection circuit 270 connected to the first timing comparison circuit 230, so that it transmits the first common electrode voltage Vcom1 to the first input terminal of the first timing comparison circuit 230. The second timing comparison circuit 250 outputs the fourth level signal and the first timing comparison circuit 230 outputs the first level signal. The first switching circuit 220 and the second switching circuit 240 are turned on and output the first common electrode voltage Vcom1 to the corresponding terminal V2 of the second common electrode layer, the corresponding terminal Vs of the pixel electrode 13 and the corresponding terminal V1 of the first common electrode layer 24. The voltages of the corresponding two electrodes of the display panel 100 are equal and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not be deflected and transmitted when the power is turned on, so there will be no screen flickering when the power is turned on.

[0061] Alternatively, when the output timing of the signal output circuit 210 changes, the output timing of the second common electrode voltage Vcom2 is the earliest. The second common electrode voltage Vcom2 is the first target driving signal, and the other target driving signals are used as the second target driving signals. For example, the other first common electrode voltages Vcom1 and data voltage Data are set as the second target driving signals.

[0062] At this initial power-on stage, the timing detection circuit 280 first receives the second common electrode voltage Vcom2. Then, the timing detection circuit 280 outputs a switch switching signal to control the switch switching circuit 260 to connect the signal output circuit 210 (outputting the second common electrode voltage Vcom2), the first switch circuit 220, the second switch circuit 240, and the selection circuit 270, outputting the second common electrode voltage Vcom2 to the first switch circuit 220, the second switch circuit 240, and the selection circuit 270. Simultaneously, the timing detection circuit 280 outputs a selection signal to the selection circuit 270 corresponding to the second common electrode voltage Vcom2, causing it to connect its ground terminal to the first input terminal of the first timing comparison circuit 230. Also, the timing detection circuit 280 outputs a selection signal to the other first timing comparison circuits... The selection circuit 270, which is connected to the circuit 230 and the second timing comparison circuit 250, transmits the second common electrode voltage Vcom2 to the first input terminal of the remaining first timing comparison circuit 230 and the second timing comparison circuit 250. The second timing comparison circuit 250 outputs a fourth level signal and the first timing comparison circuit 230 outputs a first level signal. Each first switch circuit 220 and the second switch circuit 240 are turned on and output the second common electrode voltage Vcom2 to the corresponding terminal V2 of the second common electrode layer, the corresponding terminal Vs of the pixel electrode 13, and the corresponding terminal V1 of the first common electrode layer 24. The voltages of the corresponding two electrodes of the display panel 100 are equal, and there is no voltage difference between the corresponding electrodes. The liquid crystal of the liquid crystal layer will not be deflected and transmitted when the power is turned on, so there will be no screen flickering when the power is turned on.

[0063] The timing detection circuit 280 can be a corresponding voltage detection circuit, controller, etc., the switch switching circuit 260 can be a switching switch K1, a selection switch, etc., and the selection circuit 270 can be a multi-input single-output selector MUX1, a switch, etc.

[0064] In an alternative embodiment, such as Figure 11 As shown, the switch switching circuit 260 includes multiple parallel switching switches K1; The input terminal of the multiplexer K1 is connected to the output terminals of multiple signal output circuits 210 one by one. The output terminals of the multiplexer K1 are connected to the output terminals of the switch switching circuit 260. The control terminal of the switch K1 is connected to the signal terminal of the timing detection circuit 280.

[0065] The selection circuit 270 includes a multiplexer MUX1. The first input terminal, the second input terminal, the output terminal, and the control terminal of the multiplexer MUX1 respectively constitute the first input terminal, the second input terminal, the output terminal, and the control terminal of the selection circuit 270.

[0066] In this embodiment, taking the second common electrode voltage Vcom2 as the first target driving signal as an example, in the initial stage of power-on, the timing detection circuit 280 first receives the second common electrode voltage Vcom2. At this time, the timing detection circuit 280 outputs a switch switching signal to control one of the switches K1 in the switch switching circuit 260 to be turned on, for example... Figure 12 As shown, when the intermediate switch K1 is turned on, the second common electrode voltage Vcom2 is output to the multiplexer MUX1, the first electronic switch T1, and the second electronic switch T2. Simultaneously, the timing detection circuit 280 outputs a selection signal to multiple multiplexers MUX1. Specifically, the timing detection circuit 280 outputs a high-level signal to the intermediate multiplexer MUX1, which selects and outputs a ground signal to the intermediate first comparator U3. The output of the intermediate first comparator U3 is connected to the intermediate first switching circuit 220. Both the input and output of the intermediate first switching circuit 220 are input to the second common electrode voltage Vcom2. Simultaneously, the timing detection circuit 280 outputs a low-level signal to the multiplexer MUX1 connected to the second comparator U4. The multiplexer MUX1 selects the second common electrode voltage Vcom2... The common electrode voltage Vcom2 is selected and output to the second comparator U4, and the timing detection circuit 280 outputs a low level to another multiplexer MUX1. The other multiplexer MUX1 selects and outputs the second common electrode voltage Vcom2 to another first comparator U3. At this time, the second comparator U4 and the first comparator U3 control the connected first electronic switch T1 and second electronic switch T2 to conduct during the initial power-on period, and output the second common electrode voltage Vcom2 to each terminal of the display panel 100 through the first electronic switch T1 and the second electronic switch T2. The voltages of the corresponding two terminals of the display panel 100 are equal, both being the second common electrode voltage Vcom2. There is no voltage difference between the corresponding terminals, and the liquid crystal of the liquid crystal layer will not deflect and transmit light when the power is turned on, thus preventing screen flickering during power-on.

[0067] Then, in the subsequent period, when the first common electrode voltage Vcom1 establishes the input, the second comparator U4 compares the output to a low level and controls the second electronic switch T2 to turn off, and the first common electrode voltage Vcom1 then switches the output to the matching corresponding terminal V1.

[0068] Similarly, when the data voltage Data is established, the first comparator U3 outputs a low level and controls the connected first electronic switch T1 to turn off, and the data voltage Data is then switched to the corresponding matching terminal Vs.

[0069] Furthermore, to prevent the first target driving signal from being fed back to the corresponding signal output circuit 210 when other second target driving signals have not been established, thus causing voltage reverse flow in the signal output circuit 210, in an optional embodiment, such as Figure 12 As shown, the driving circuit 200 of the display panel also includes: Multiple unidirectional conduction circuits 290 are provided, with their input terminals connected to the output terminals of multiple signal output circuits 210, and their output terminals connected to the input terminals of multiple first switch circuits 220 and second switch circuits 240, respectively. The unidirectional conduction circuits 290 are used to transmit the corresponding target drive signal unidirectionally to the corresponding switch circuit.

[0070] In this embodiment, each first target driving signal and second target driving signal are transmitted unidirectionally to the output terminal of the corresponding switching circuit through the unidirectional conduction circuit 290 when output, thereby realizing unidirectional transmission. This reverses the first target driving signal when other second target driving signals are not established, preventing the first target driving signal from flowing back to the corresponding signal output circuit 210 and improving circuit safety.

[0071] The unidirectional conduction circuit 290 can employ a corresponding switching transistor and diode D1. In an optional embodiment, such as... Figure 12 As shown, the unidirectional conduction circuit 290 includes a diode D1. The anode and cathode of the diode D1 constitute the input and output terminals of the unidirectional conduction circuit 290. The diode D1 realizes unidirectional signal transmission and reverses to cut off the first target drive signal when other second target drive signals are not established, preventing the first target drive signal from flowing back to the corresponding signal output circuit 210 and improving circuit safety.

[0072] Example 3 A second aspect of the present invention provides a display device, such as... Figure 3 As shown, the display device includes a driving circuit 200 for the display panel and a display panel 100. The specific structure of the driving circuit 200 for the display panel is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The driving circuit 200 for the display panel is connected to the display panel 100.

[0073] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving circuit for a display panel, wherein the plurality of target signal terminals of the display panel include a first target signal terminal and a plurality of second target signal terminals, the first target signal terminal being used to input a first target driving signal, and the plurality of second target signal terminals being used to input a plurality of matched second target driving signals, characterized in that, The driving circuit of the display panel includes: Multiple signal output circuits are used to output the first target driving signal and multiple second target driving signals respectively when powered on, wherein the output terminal of a matched signal output circuit is connected to the first target signal terminal of the display panel and transmits the first target driving signal, and the output timing of the first target driving signal is ahead of the output timing of the other second target driving signals; Multiple first switching circuits, the input terminals of the multiple first switching circuits are connected to the first target signal terminal, the output terminal of each first switching circuit is connected to a second target signal terminal and the output terminal of the matching signal output circuit, the first switching circuit is triggered to turn on by a first level signal and triggered to turn off by a second level signal; Multiple first timing comparison circuits are provided. The first input terminal of each first timing comparison circuit is connected to the first target signal terminal of the display panel. The second input terminal of each first timing comparison circuit is connected to the output terminal of a corresponding signal output circuit. The output terminal of each first timing comparison circuit is connected to the control terminal of a corresponding first switching circuit. The first timing comparison circuit is used to output the first level signal when receiving a first target driving signal and to output the second level signal when receiving a first target driving signal and a second target driving signal.

2. The driving circuit for the display panel as described in claim 1, characterized in that, The driving circuit of the display panel also includes: The second switching circuit has its input terminal connected to the output terminal of a corresponding signal output circuit, and its output terminal connected to the first target signal terminal. The second switching circuit is turned off by a third level signal and turned on by a fourth level signal. The second timing comparator circuit has its first input terminal connected to the input terminal of the second switching circuit, its second input terminal grounded, and its output terminal connected to the control terminal of the second switching circuit. The second timing comparator circuit is used to output the third level signal when the first target driving signal is not received, and to output the fourth level signal when the first target driving signal is received.

3. The driving circuit for the display panel as described in claim 2, characterized in that, The first timing comparison circuit includes a first logic gate, wherein the first input terminal, the second input terminal, and the output terminal of the first logic gate are respectively the first input terminal, the second input terminal, and the output terminal of the first timing comparison circuit; The second timing comparison circuit includes a second logic gate, and the first input, second input, and output of the second logic gate are respectively the first input, second input, and output of the second timing comparison circuit.

4. The driving circuit for the display panel as described in claim 2, characterized in that, The amplitude of the first target driving signal is smaller than that of the remaining second target driving signals; The first timing comparison circuit includes a first comparator, wherein the non-inverting input, the inverting input, and the output of the first comparator are respectively the first input, the second input, and the output of the first timing comparison circuit; The second timing comparison circuit includes a second comparator, wherein the first input terminal, the second input terminal, and the output terminal of the second comparator are respectively the first input terminal, the second input terminal, and the output terminal of the second timing comparison circuit.

5. The driving circuit for the display panel as described in claim 2, characterized in that, The first switching circuit includes a first electronic switch tube, and the first terminal, the second terminal, and the control terminal of the first electronic switch tube respectively constitute the input terminal, the output terminal, and the control terminal of the first switching circuit. The second switching circuit includes a second electronic switch tube, and the first terminal, the second terminal, and the control terminal of the second electronic switch tube respectively constitute the input terminal, the output terminal, and the control terminal of the second switching circuit.

6. The driving circuit for the display panel as described in claim 2, characterized in that, The driving circuit of the display panel also includes: A switch switching circuit, wherein multiple input terminals of the switch switching circuit are connected to the output terminals of multiple signal output circuits one by one, the output terminal of the switch switching circuit is connected to the input terminals of multiple first switch circuits and the input terminals of second switch circuits, and the output terminal of the second switch circuit is also connected to the output terminal of a matching signal output circuit. The switch switching circuit is used to select one of its input terminals and output terminals to be connected according to a switch switching signal. Multiple selection circuits are provided, with their first input terminals connected to the output terminal of the switch switching circuit, their second input terminals grounded, the output terminal of one of the multiple selection circuits connected to the first input terminal of the second timing comparison circuit, and the output terminals of the other selection circuits connected to the first input terminals of the multiple first timing comparison circuits. The selection circuits are used to output the output signal or ground signal of the switch switching circuit to the second timing comparison circuit and the first timing comparison circuit according to the selection signal. The timing detection circuit is connected to multiple signal output circuits, the switch switching circuit, and multiple selection circuits respectively. The timing detection circuit is used to determine the first target drive signal from the target drive signal with a preset amplitude received first during the initial power-on period, and output the corresponding switch switching signal and the selection signal according to the first target drive signal.

7. The driving circuit for the display panel as described in claim 6, characterized in that, The switching circuit includes multiple parallel switching switches; The input terminals of the multiple switching switches are connected one by one to the output terminals of the multiple signal output circuits. The output terminals of the multiple switching switches are connected together to form the output terminal of the switching circuit. The control terminal of the switching switch is connected to the signal terminal of the timing detection circuit.

8. The driving circuit for the display panel as described in claim 6, characterized in that, The selection circuit includes a multiplexer, and the first input terminal, second input terminal, output terminal, and control terminal of the multiplexer respectively constitute the first input terminal, second input terminal, output terminal, and control terminal of the selection circuit.

9. The driving circuit for the display panel as described in claim 2, characterized in that, The driving circuit of the display panel also includes: Multiple unidirectional conduction circuits are provided, with the input terminals of the multiple unidirectional conduction circuits connected to the output terminals of the multiple signal output circuits one by one, and the output terminals of the multiple unidirectional conduction circuits connected to the input terminals of the multiple first switch circuits and the input terminals of the multiple second switch circuits one by one. The unidirectional conduction circuits are used to transmit the corresponding target driving signal unidirectionally to the corresponding switch circuit.

10. A display device, characterized in that, It includes a display panel and a driving circuit for the display panel as described in any one of claims 1 to 9, wherein the driving circuit for the display panel is connected to the display panel.

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