Time synchronization method, system, device and equipment and storage medium

Abstract

The invention relates to the technical field of electronic science, in particular to a time synchronization method, system, device and equipment and a storage medium, which are used for improving the time synchronization precision between a master system and a slave system. In the method, a master system sends a synchronization signal to each slave system according to a preset sending time, receives a feedback signal sent by each slave system and obtains a corresponding receiving time so as to judge the signal round-trip delay of each slave system. And then, the master system performs error calculation according to the sending time and the receiving time to obtain a corresponding deviation value, and adjusts the subsequent synchronization signal sending time of each slave system according to the deviation value. Therefore, targeted error compensation is carried out on each slave system through the deviation value, the time synchronization error is effectively reduced, the time synchronization between the master system and the slave system is more accurate, and the nanosecond-level or even higher-precision time synchronization requirement is met.

Description

Technical Field

[0001] This application relates to the field of electronic science and technology, and in particular to a time synchronization method, system, device, equipment and storage medium. Background Technology

[0002] Existing master-slave synchronization systems primarily rely on technologies such as real-time clock (RTC) synchronization and software timer synchronization to achieve time synchronization between multiple systems. However, due to limitations in the performance of clocks and processors, untimely interrupt service responses, and network communication latency, existing synchronization technologies have poor time synchronization accuracy and are only suitable for simple multi-system architectures with low time synchronization accuracy requirements (such as a master-slave system). Summary of the Invention

[0003] This invention provides a time synchronization method, system, device, and storage medium to improve the time synchronization accuracy between a master system and a slave system.

[0004] In a first aspect, this application provides a time synchronization method, which is applied to the main system in a time synchronization system, the method comprising:

[0005] Based on a preset transmission time, a synchronization signal is sent to at least one slave system;

[0006] Receive at least one feedback signal sent from the system, and obtain the reception time corresponding to the feedback signal;

[0007] Error calculations are performed on the receiving time and the transmitting time to obtain the deviation value corresponding to the synchronization signal;

[0008] Based on the deviation value, the transmission time of the synchronization signal is adjusted.

[0009] Secondly, this application provides a time synchronization system, the system comprising a master system and at least one slave system, wherein:

[0010] The master system is configured to send a synchronization signal to the at least one slave system and obtain a corresponding feedback signal; perform error calculation on the corresponding receiving time and sending time to obtain a deviation value corresponding to the synchronization signal; and adjust the sending time based on the deviation value.

[0011] The slave system is used to send the feedback signal to the master system.

[0012] Optionally, the main system is specifically used for:

[0013] The transmission delay is obtained based on the difference between the receiving time and the sending time;

[0014] The total latency is obtained based on the transmission latency and the processing latency of the main system.

[0015] The total delay is averaged to obtain the deviation value.

[0016] Optionally, the synchronization signal includes: a source clock signal and / or an interrupt signal.

[0017] Optionally, the main system is specifically used for:

[0018] Based on a preset reception period, acquire the life signals sent from the system.

[0019] For each life signal, determine whether the reception time exceeds the preset timeout threshold.

[0020] If the target life signal exceeds the preset timeout threshold, it is determined that the target slave system corresponding to the target life signal has malfunctioned, and the target slave system is subjected to security protection processing.

[0021] Optionally, the main system is specifically used for:

[0022] Send a prompt signal to the target from the system, so that the target from the system prompts the relevant management personnel based on the prompt signal; or;

[0023] Send a re-request signal to the target from the system to reconfirm the system status of the target from the system; or;

[0024] Stop sending synchronization signals to the slave system and disconnect the transmission path corresponding to the slave system; or;

[0025] The system stores the corresponding life signals and fault information.

[0026] Optionally, the controllers of the master system and the at least one slave system are both FPGA logic devices.

[0027] Optionally, the master system and the slave system transmit signals via hardwire.

[0028] Thirdly, this application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the time synchronization methods described in the first aspect above.

[0029] Fourthly, this application provides a computer storage medium storing computer program instructions, which are executed by a processor using any of the time synchronization methods described in the first aspect above.

[0030] Fifthly, an embodiment of this application provides a computer program product including computer program instructions, which, when executed by a processor, implement any one of the time synchronization methods described in the first aspect above.

[0031] The beneficial effects of this invention are as follows:

[0032] In this embodiment, the master system sends synchronization signals to each slave system according to a preset signal transmission time, thereby providing a unified timing reference. This ensures that each slave system uses the master system's source clock as its reference, reducing the uncertainty caused by clock differences during synchronization system initialization. The master system receives feedback signals from each slave system and obtains feedback timing parameters to determine the round-trip delay of each slave system's signal, understand the response characteristics and timing differences of each slave system, and provide an accurate data basis for subsequent error compensation. Next, the master system calculates the error of the synchronization signal's reference timing parameters based on the feedback timing parameters, obtains the corresponding deviation value, and adjusts the signal transmission time of each slave system according to the deviation value. Thus, by using the deviation value, targeted error compensation is performed on each slave system, effectively reducing time synchronization errors caused by differences in processing delays, transmission paths, and other factors. This makes time synchronization between the master and slave systems more accurate, meeting the requirements for nanosecond-level or even higher precision time synchronization. Attached Figure Description

[0033] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0034] Figure 1 This is a schematic diagram illustrating an application scenario of a time synchronization method according to an embodiment of this application;

[0035] Figure 2 An interactive flowchart of a time synchronization method provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0038] It is understood that the following specific embodiments of this application involve data such as signals. When the various embodiments of this application are applied to specific products or technologies, relevant licenses or consents are required, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, when relevant data is needed, relevant volunteers can be recruited and agreements authorizing their data can be signed, thereby enabling the use of this volunteer data for implementation; alternatively, implementation can be carried out within an authorized organization, using data from internal members to implement the following implementation methods for making relevant recommendations to internal members; or, the relevant data used in the specific implementation may be simulated data, such as simulated data generated in a virtual scene.

[0039] The design concept of the embodiments of this application will be briefly introduced below.

[0040] In the industrial sector, the mainstream time synchronization methods can be summarized as follows:

[0041] Method 1, based on RTC synchronization technology, relies on a hardware RTC module to provide the clock source. This is achieved by installing RTC modules on both the master and slave systems and periodically synchronizing the RTC time values.

[0042] Method 2, based on software timing synchronization technology, utilizes the processor's timer to generate timed interrupts through software control, and exchanges and corrects time information between the master and slave systems to maintain clock synchronization, thereby achieving time synchronization between the master and slave systems.

[0043] However, through their inventive efforts, the inventors discovered that, limited by the inherent limitations of RTC devices, the synchronization accuracy of RTC modules is only at the millisecond level, making them unsuitable for complex system architectures with high time synchronization accuracy requirements (e.g., nanosecond level) in master-slave synchronization systems. Furthermore, RTC synchronization primarily reduces errors through periodic time calibration, lacking real-time correction, resulting in low time synchronization accuracy. Software-based timing synchronization technologies are limited by multi-level data frame buffering, resulting in significant latency fluctuations, crystal oscillator frequency drift, and slow interrupt service routine response times, typically achieving only millisecond-level task synchronization and failing to achieve higher-precision time synchronization. Moreover, software timing is susceptible to limitations imposed by system load, operating system scheduling, and interrupt latency, leading to significant uncertainties at the software layer and insufficient reliability and availability of time synchronization.

[0044] In view of this, embodiments of this application provide a time synchronization method to improve the time synchronization accuracy between a master system and slave systems. The master system sends a synchronization signal to each slave system according to a preset signal transmission time, thereby providing a unified timing reference. This ensures that each slave system uses the master system's source clock as a reference, reducing the uncertainty caused by clock differences during system initialization. The master system receives feedback signals from each slave system and obtains feedback timing parameters to determine the round-trip delay of each slave system's signal, understand the response characteristics and timing differences of each slave system, and provide an accurate data basis for subsequent error compensation. Next, the master system calculates the error of the reference timing parameters of the synchronization signal based on the feedback timing parameters, obtains the corresponding deviation value, and adjusts the signal transmission time of each slave system according to the deviation value. Thus, by using the deviation value, targeted error compensation is performed on each slave system, effectively reducing time synchronization errors caused by differences in processing delays, transmission paths, and other factors, making the time synchronization between the master and slave systems more accurate and meeting the requirements for nanosecond-level or even higher precision time synchronization.

[0045] The following is a brief introduction to the application scenarios to which the technical solutions of the embodiments of this application are applicable. It should be noted that the application scenarios described below are only for illustrating the embodiments of this application and are not intended to limit the scope. In specific implementation, the technical solutions provided by the embodiments of this application can be flexibly applied according to actual needs.

[0046] The solutions provided in this application can be applied to most application scenarios with high time synchronization requirements, significantly improving system reliability and synchronization accuracy. For example, in industrial control scenarios, in industrial automated production lines, it ensures that different devices (such as robotic arms, conveyor belts, and detection devices) work collaboratively in strict accordance with a predetermined time sequence to ensure the stability and accuracy of the production process; in autonomous driving scenarios, it ensures the timing consistency between multiple sensors in autonomous vehicles; and in base station communication networks, each base station needs to maintain high-precision clock synchronization to support demanding network services such as handover and collaborative transmission.

[0047] like Figure 1 The diagram shown illustrates an application scenario of a time synchronization method provided in this application. In this scenario, a time synchronization system is included, consisting of a master system 110 and at least one slave system 120. Figure 1 (The diagram shows two slave systems).

[0048] The master system is the central control unit in the time synchronization system. It is responsible for generating and sending synchronization signals such as new source clock signals and interrupt signals, interacting with the slave system to correct errors, and receiving life signals from the slave system.

[0049] The slave system 120 is a device or subsystem that relies on the time signal of the master system for synchronization. In this embodiment, the slave system does not generate its own source clock signal, but adjusts for synchronization based on the received time signal.

[0050] It should be noted that, Figure 1 The examples shown are merely illustrative; in reality, the number of master systems 110 and slave systems 120 is unlimited, and no specific limitation is made in this embodiment. Figure 1 The components and structures shown are merely exemplary and not restrictive. In real-world scenarios, other components and structures may be used as needed.

[0051] Of course, the methods provided in the embodiments of this application are not limited to... Figure 1 The application scenarios shown can also be used in other possible scenarios, and this application does not impose any limitations. Figure 1 The functions that each device in the application scenario shown can achieve will be described in subsequent method embodiments, and will not be elaborated on here.

[0052] In one possible implementation, the embodiments of this application can be applied to autonomous driving scenarios. Autonomous vehicles need to process large amounts of data from multiple sensors such as LiDAR, cameras, and millimeter-wave radar in real time, and perform high-precision environmental perception and decision-making. To ensure the temporal consistency of sensor data, the system needs to achieve high-precision time synchronization to ensure that all sensors collect and process data at the same point in time. The solution provided by the embodiments of this application can be used to synchronize the time of the vehicle's main system and multiple sensor slave systems, synchronizing the time of multiple sensors to the nanosecond level, ensuring that the data from different sensors are aligned on the same time axis of the main system, improving the accuracy and reliability of data fusion, thereby improving the environmental perception capability of the autonomous driving system.

[0053] In one possible implementation, the embodiments of this application can be applied to security architecture scenarios, such as systems with high security requirements like aerospace, rail transportation, and nuclear power plants, where data acquisition and comparison are critical steps. The main system needs to acquire and compare communication data from multiple slave systems, such as sensors or control modules, in real time to ensure system security and stability. If the acquired data is inconsistent, the system must quickly switch to a backup system to prevent security risks caused by erroneous data. To ensure the accuracy of data comparison, the data from all acquisition points must be strictly synchronized in time. The technical solution provided by the embodiments of this application can accurately distribute the source clock signal and interrupt signal to each slave system (sensor or module), and by accurately correcting the delay of the source clock and interrupt signal, ensure that the time error of all acquired data during comparison is within an acceptable range (e.g., within 50ns). This ensures that in the event of data inconsistency, the system can switch to the backup system with minimal delay, improving security response speed.

[0054] The following describes the methods provided by exemplary embodiments of this application in conjunction with the application scenarios described above and with reference to the accompanying drawings. It should be noted that the application scenarios described above are only shown to facilitate understanding of the spirit and principles of this application, and the embodiments of this application are not limited in any way in this respect.

[0055] See Figure 2 The diagram shown is an interactive flowchart of a time synchronization method provided in an embodiment of this application. The interactive flowchart includes a time synchronization system consisting of a master system and multiple slave systems. The specific implementation flow of the method is as follows:

[0056] Step 201: The master system sends a synchronization signal to multiple slave systems based on a preset transmission time.

[0057] In this embodiment, the synchronization signal includes a source clock signal and an interrupt signal. The master system will output different types of synchronization signals according to the preset signal transmission time and the set timing requirements, thereby ensuring that multiple slave systems can receive and perform synchronization operations simultaneously.

[0058] Specifically, the source clock signal is a continuous clock pulse signal, generated by a high-precision clock source from the master system. The source clock signal serves as the time base for the entire system and can be used to coordinate the synchronous operation of each slave system. Interrupt signals are synchronization signals used to trigger specific operations performed by slave systems, including but not limited to brief high-level pulses or dedicated interrupt flag signals. Thus, while the source clock signal is continuous, the transmission of interrupt signals must maintain a relatively fixed timing relationship with the source clock signal to ensure that the slave system can correctly understand the time base upon receiving the interrupt signal. For example, the slave system will calibrate its own time based on the source clock signal and perform synchronization actions (such as triggering events or acquiring data) when the interrupt signal arrives.

[0059] In one possible implementation, the controllers for both the master system and each slave system can be implemented using FPGA logic devices, further reducing signal transmission latency between the master and slave systems and improving the response speed of each system. Furthermore, signal transmission between the master and slave systems can be performed using hardwired connections, significantly reducing signal transmission latency.

[0060] Specifically, the master system can generate a stable source clock signal through the clock management unit in the FPGA, and then send the source clock signal to each slave system through a specific output port at a preset signal transmission time. Each slave system, upon receiving the source clock signal, can use its internal clock management unit to perform phase-locked loop (PLL) and alignment operations to ensure that its internal clock is consistent with the source clock. This ensures that the source clocks of both the master and slave systems originate from the master system, guaranteeing higher system synchronization accuracy than different source clocks and reducing clock errors at their source. Furthermore, the FPGA-based master system can use timer or counter modules in the FPGA to time interrupt signals at intervals, such as generating an interrupt signal at preset times (e.g., every 5 microseconds), further reducing time errors. Signal transmission between the master and slave systems is implemented using hardwired connections, such as dedicated hardware interrupt lines or buses (e.g., SPI, I2C, or other high-speed communication interfaces), further ensuring that the signal transmission delay is no greater than 5 nanoseconds, improving the time synchronization accuracy between the master and slave systems.

[0061] Step 202: Each slave system receives and processes the synchronization signal and sends the corresponding feedback signal to the master system.

[0062] In this embodiment, each slave system receives a synchronization signal from the master system and uses the synchronization signal to adjust its own operation time to ensure synchronization with the master system. When the synchronization signal is processed, it sends a corresponding feedback signal to the master system. This feedback signal is the basis for the master system to calibrate the time deviation and assists the master system in performing accurate time calibration and error adjustment.

[0063] Specifically, the slave system will calibrate its own time based on the source clock signal sent by the master system, and will perform synchronization actions such as triggering events and collecting data when an interrupt signal arrives.

[0064] In one possible implementation, the feedback signal is the signal obtained by the slave system after receiving and processing the synchronization signal, and may include information such as timestamps and processing delays. For example, the source clock signal represents the current time base of the master system. The slave system adjusts its own clock by receiving and processing the source clock signal to keep it synchronized with the master system. Therefore, after receiving the source clock signal from the master system, the slave system processes it accordingly and feeds back the same processed source clock signal to the master system. This feedback signal typically includes the slave system's received timestamp and processing delay information, enabling the master system to calculate the round-trip time and perform clock calibration. The interrupt signal is mainly used to trigger the slave system's action or synchronization detection at a specific time point. After receiving an interrupt signal, the slave system immediately processes and responds. Its feedback signal is generally the result of the slave system's handling of the interrupt, such as the timestamp or status information after the slave system executed the interrupt. This helps the master system confirm whether the slave system's response was completed within the expected time.

[0065] Step 203: The main system obtains the reception time of each feedback signal, and calculates the error based on the reception time and transmission time to obtain the deviation value corresponding to the synchronization signal.

[0066] In this embodiment, the master system receives feedback signals from each slave system and records the arrival time of each signal, i.e., the reception time. Since signal transmission between the master and slave systems consumes time (i.e., the signal needs to propagate through cables or PCB traces), this transmission time introduces transmission delay. Furthermore, each transmission and reception process may be affected by transmission delay, processing delay, etc., leading to a discrepancy between the actual operation time and the expected time. Therefore, the time difference of the synchronization signals received by the slave systems is used by the master system to determine whether the current synchronization time is accurate and is used for subsequent error calculation.

[0067] Specifically, after receiving feedback signals from each slave system, the master system can calculate the error between the receiving time and the sending time according to the preset error compensation strategy to obtain the deviation value corresponding to the synchronization signal. This value represents the actual delay of the signal transmission and is also the value that needs to be compensated in the subsequent synchronization signal transmission process.

[0068] In one possible implementation, the present application embodiment can obtain the transmission delay based on the difference between the reception time of the feedback signal and the transmission time of the synchronization signal, and obtain the total delay based on the sum of the transmission delay and the processing delay of the main system, thereby averaging the total delay to obtain the deviation value corresponding to the synchronization signal.

[0069] Specifically, the error calculation process is shown in the following formula:

[0070]

[0071] Where t1 represents the time when the master system sends a synchronization signal to the slave system;

[0072] t3 represents the reception time of the feedback signal from the slave system received by the master system;

[0073] Δt2 represents the latency of the main system processing data.

[0074] Step 204: The master system adjusts the transmission time of the corresponding synchronization signal of each slave system based on the deviation value.

[0075] In this embodiment of the application, after obtaining the deviation value, the master system can correct the source clock signal and interrupt signal and other synchronization signals according to the latest calculated deviation value. That is, when sending the synchronization signal, the master system can adjust the corresponding sending time to compensate for the expected transmission delay and ensure high-precision time synchronization between the master and slave systems.

[0076] In one possible implementation, taking the initialization state after the master system powers on and all slave systems synchronize the source clock signal as an example, the master system generates a source clock signal as the initial time reference signal and prepares to synchronize and calibrate with each slave system. At time ta, the master system sends the source clock signal to each slave system, ensuring that all slave system clocks originate from the master clock, thus reducing clock errors at their source. Taking a slave system receiving the master system's source clock signal at time tb as an example, its controller introduces a certain processing delay when processing the received signal, recorded as ΔT1. Then, according to the protocol, the slave system feeds back the same clock signal to the master system at time tc. After receiving the clock signal from the slave system, the master system processes it accordingly, introducing a certain processing delay, i.e., the master system's own data processing delay, denoted as ΔT2. Based on error calculation, the deviation between the source clock signal transmission and reception is (tc - ta + ΔT2). The master system will adjust the source clock signal transmission time to compensate for the measured deviation value by advancing or delaying the transmission time. Each time the master system corrects the source clock signal, it applies the calculated correction time to all slave systems in the system to ensure synchronization consistency. By periodically repeating the above steps by the master system, especially during system startup, reset, or when an error deviation is detected, the source clock time of the master and slave systems is ensured to remain in high-precision synchronization.

[0077] In one possible implementation, taking the master system sending an interrupt signal as an example, the master system pre-sets the pre-transmission time of the interrupt signal to t1 = 10 μs (microseconds), and the time for the slave system to process the interrupt signal is t2, but t2 is unknown at this time. The time for the master system to receive the feedback signal from the slave system is t3 = 20 μs. Furthermore, the data processing delay of the slave system is Δt1 = 3 μs, and the data processing delay of the master system itself is Δt2 = 2 μs. According to error calculation, the deviation between the transmission and reception of the interrupt signal is 6 μs. Therefore, when the interrupt signal is transmitted again, the master system will adjust the transmission time of the synchronization signal to compensate for the measured deviation value by advancing or delaying it. For example, if the original plan was to send the synchronization signal again at t1 = 10 μs, the master system will correct the transmission time to t1 - 6 μs = 4 μs to pre-compensate for the transmission delay. In a laboratory environment, through the interrupt triggering mechanism, the master system monitors the interrupt time error between the master and slave systems and adjusts the system interrupt triggering threshold, ultimately controlling the error accuracy of the master and slave systems within 50 ns. Furthermore, based on the different physical distances between each slave system and the master system, the master system will perform distance compensation according to the time difference of the received feedback signal to ensure that the time adjustment of each slave system is based on the actual transmission path differences.

[0078] Through the above process, the embodiments of this application can accurately adjust the transmission time of the synchronization signal after multiple calibrations and corrections, minimizing the time delay error between the master and slave systems, thereby achieving more accurate clock synchronization. This dynamic adjustment and compensation process enables the system to maintain high-precision synchronization performance even when facing various time delay fluctuations, making it particularly suitable for scenarios requiring precise timing control, such as sensor fusion in autonomous driving and equipment collaboration in industrial control systems.

[0079] In one possible implementation, to further improve system reliability and reduce the risk of fault propagation, in this embodiment, each slave system will send a life signal to the master system according to a preset period. Simultaneously, the master system will periodically acquire the life signals from each slave system and determine whether each life signal exceeds a preset timeout threshold based on its latest reception time. If a target life signal exceeds the preset timeout threshold, it is determined that the corresponding slave system has failed, and security protection measures are implemented for the slave system.

[0080] Specifically, each slave system periodically sends a life signal to the master system to indicate its normal operating status. The master system can set a receiving window (e.g., 2 milliseconds) within which it continuously receives life signals from each slave system and periodically checks the life signals sent by each slave system according to a preset receiving period (e.g., once every 10 milliseconds). Then, the master system records the reception time of each life signal and compares it with the preset receiving period. If it determines that the reception time of a slave system's life signal exceeds a preset timeout threshold (e.g., 3 milliseconds), the master system will determine that the life signal has timed out and thus perform security protection procedures on the corresponding slave system.

[0081] In one possible implementation, the security protection process in this application embodiment may include, but is not limited to, a combination of one or more of the following measures: sending a prompt signal to the slave system to prompt the relevant management personnel to intervene; or sending a re-request signal to the slave system to reconfirm the system status of the slave system; or stopping the sending of synchronization signals to the slave system and disconnecting the transmission path corresponding to the slave system to prevent its erroneous data from affecting the overall system operation; or storing the life signals and fault information corresponding to the slave system to provide detailed fault information, help maintenance personnel quickly locate the source of the problem, and improve the system maintenance efficiency.

[0082] Based on the same inventive concept, this application also provides a time synchronization device 30, which includes:

[0083] The transmitting module 301 is used to send a synchronization signal to at least one slave system based on a preset transmitting time;

[0084] The receiving module 302 is used to receive at least one feedback signal sent from the system and obtain the reception time corresponding to the feedback signal;

[0085] Processing module 303 is used to calculate the error between the receiving time and the transmitting time to obtain the deviation value corresponding to the synchronization signal;

[0086] The correction module 304 is used to adjust the transmission time of the synchronization signal based on the deviation value.

[0087] For ease of description, the above sections are divided into functional units (or modules) and described separately. Of course, in implementing this application, the functions of each unit (or module) can be implemented in one or more software or hardware components. Those skilled in the art will understand that various aspects of this application can be implemented as systems, methods, or program products. Therefore, various aspects of this application can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, collectively referred to herein as "circuit," "module," or "system."

[0088] This device can be used to execute the methods shown in the various embodiments of this application. Therefore, the functions that each functional module of this device can achieve can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0089] Please see Figure 3 Based on the same technical concept, embodiments of this application also provide a computer device. In one embodiment, the computer device can be... Figure 1 The main system shown, the computer device as follows Figure 3 As shown, it includes a memory 301, a communication module 303, and one or more processors 302.

[0090] The memory 301 is used to store computer programs executed by the processor 302. The memory 301 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required to run instant messaging functions, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.

[0091] Memory 301 may be volatile memory, such as random-access memory (RAM); memory 301 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 301 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 301 may be a combination of the above-described memories.

[0092] Processor 302 may include one or more central processing units (CPUs) or digital processing units, etc. Processor 302 is used to implement the above-described time synchronization method when calling computer programs stored in memory 301.

[0093] The communication module 303 is used to communicate with other slave systems.

[0094] This application embodiment does not limit the specific connection medium between the memory 301, communication module 303, and processor 302 described above. This application embodiment... Figure 3 The memory 301 and the processor 302 are connected via a bus 304, and the bus 304 is in Figure 3The diagram uses thick lines to describe the connections between other components; these are for illustrative purposes only and should not be considered limiting. Bus 304 can be divided into address bus, data bus, control bus, etc. For ease of description, Figure 3 It is described using only a thick line, but does not indicate that there is only one bus or one type of bus.

[0095] The memory 301 stores a computer storage medium, which stores computer-executable instructions. The computer-executable instructions are used to implement the time synchronization method of the embodiments of this application, and the processor 302 is used to execute the time synchronization methods of the above embodiments.

[0096] Based on the same inventive concept, embodiments of this application also provide a storage medium storing a computer program that, when run on a computer, causes the computer to perform the steps of the time synchronization method according to various exemplary embodiments of this application described above.

[0097] In some possible implementations, various aspects of the time synchronization method provided in this application may also be implemented in the form of a computer program product, which includes a computer program that, when run on a computer device, causes the computer device to perform the steps in the time synchronization method according to the various exemplary embodiments of this application described above. For example, the computer device may perform the steps of the various embodiments.

[0098] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0099] The program product of the embodiments of this application may employ a portable compact disc read-only memory (CD-ROM) and include a computer program, and may run on a computer device. However, the program product of this application is not limited thereto. In this application, the readable storage medium may be any tangible medium that contains or stores a program, and the computer program included therein may be used by or in conjunction with a command execution system, apparatus, or device.

[0100] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a readable computer program. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting a program for use by or in conjunction with a command execution system, apparatus, or device.

[0101] Computer programs contained on readable media may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0102] Computer programs for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages.

[0103] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0104] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0105] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0107] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A time synchronization method, characterized in that, The method is applied to the main system in a time synchronization system, and the method includes: Based on a preset transmission time, a synchronization signal is sent to at least one slave system; Receive at least one feedback signal sent from the system, and obtain the reception time corresponding to the feedback signal; Error calculations are performed on the receiving time and the transmitting time to obtain the deviation value corresponding to the synchronization signal; Based on the deviation value, the transmission time of the synchronization signal is adjusted.

2. The method as described in claim 1, characterized in that, The step of calculating the error between the receiving time and the transmitting time to obtain the deviation value corresponding to the synchronization signal includes: The transmission delay is obtained based on the difference between the receiving time and the sending time; The total latency is obtained based on the sum of the transmission latency and the processing latency of the main system. The total delay is averaged to obtain the deviation value.

3. The method as described in claim 1, characterized in that, The synchronization signal includes: a source clock signal and / or an interrupt signal.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Based on a preset reception period, acquire the life signals sent from the system. For each life signal, determine whether the reception time exceeds the preset timeout threshold. If the target life signal exceeds the preset timeout threshold, it is determined that the target slave system corresponding to the target life signal has malfunctioned, and the target slave system is subjected to security protection processing.

5. The method as described in claim 4, characterized in that, The security protection process includes one or more of the following processes in combination: Send a prompt signal to the target from the system, so that the target from the system prompts the relevant management personnel based on the prompt signal; or; Send a re-request signal to the target from the system to reconfirm the system status of the target from the system; or; Stop sending synchronization signals to the slave system and disconnect the transmission path corresponding to the slave system; or; The system stores the corresponding life signals and fault information.

6. A time synchronization system, characterized in that, The system includes a master system and at least one slave system, wherein: The master system is configured to send a synchronization signal to the at least one slave system and obtain a corresponding feedback signal; perform error calculation on the corresponding receiving time and sending time to obtain a deviation value corresponding to the synchronization signal; and adjust the sending time based on the deviation value. The slave system is used to send the feedback signal to the master system.

7. The system as described in claim 6, characterized in that, The controllers of the master system and the at least one slave system are both field-programmable gate array (FPGA) logic devices.

8. The system according to any one of claims 6 to 7, characterized in that, The master system and the slave system transmit signals via hardwire.

9. A time synchronization device, characterized in that, The device includes: The transmitting module is used to send a synchronization signal to at least one slave system based on a preset transmitting time. A receiving module is configured to receive at least one feedback signal sent from the system and obtain the reception time corresponding to the feedback signal; The processing module is used to calculate the error between the receiving time and the sending time to obtain the deviation value corresponding to the synchronization signal; The correction module is used to adjust the transmission time of the synchronization signal based on the deviation value.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

11. A computer storage medium storing computer program instructions thereon, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method according to any one of claims 1 to 4.

12. A computer program product comprising computer program instructions, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method according to any one of claims 1 to 4.

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