Semiconductor device
By introducing a mesh or lattice-like gate conductive layer structure into semiconductor devices, the problem of high gate resistance is solved, switching speed and efficiency are improved, and the manufacturing process is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2026-03-13
AI Technical Summary
In existing semiconductor devices, the gate resistance is relatively high, which affects the switching speed and efficiency.
In a semiconductor device, a first conductive layer and multiple third electrodes are introduced. A fourth electrode structure, which is opposite to the semiconductor region through an insulating portion, is combined with a wide portion and a first contact portion to form a mesh or lattice-shaped gate conductive layer, thereby reducing the gate resistance.
It effectively reduces gate resistance, improves switching speed and efficiency, avoids the problem of increased feedback capacitance caused by increasing gate width, and simplifies the manufacturing process.
Smart Images
Figure CN121665631A_ABST
Abstract
Description
[0001] Related applications
[0002] This application enjoys priority based on Japanese Patent Application No. 2024-159336 (filed on September 13, 2024). This application incorporates all contents of the basic application by reference to that basic application. Technical Field
[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology
[0004] In semiconductor devices containing transistors, such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), reducing the gate resistance of the transistor can, for example, increase the switching speed. Summary of the Invention
[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer, a plurality of third electrodes, a fourth electrode, a first contact portion, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type. The second semiconductor region is disposed above the first semiconductor region. The third semiconductor region is disposed above the second semiconductor region and is electrically connected to the second electrode. The plurality of third electrodes are arranged in a unit region for the second electrode. The third electrode is opposite to the first semiconductor region through a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extension portion and a wide portion. The first extension portion is located in the unit region. The wide portion is located in the unit region and has a width greater than the width of the first extension portion. The fourth electrode is opposite to the second semiconductor region through a second insulating portion. The first contact portion is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode via the first contact portion.
[0006] According to this embodiment, a semiconductor device capable of reducing gate resistance can be provided. Attached Figure Description
[0007] Figure 1 This is a schematic top view illustrating an embodiment of a semiconductor device.
[0008] Figure 2This is a schematic diagram illustrating a semiconductor device according to an example embodiment.
[0009] Figure 3 This is a schematic diagram illustrating a semiconductor device according to an example embodiment.
[0010] Figure 4 This is a schematic cross-sectional view of a semiconductor device illustrating an embodiment.
[0011] Figure 5 This is a schematic cross-sectional view of a semiconductor device illustrating an embodiment.
[0012] Figure 6 This is a schematic diagram of a semiconductor device illustrating a variation of an embodiment.
[0013] Figure 7 This is a schematic diagram of a semiconductor device illustrating a variation of an embodiment.
[0014] Figure 8 (a) and Figure 8 (b) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.
[0015] Figure 9 (a) and Figure 9 (b) is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.
[0016] Figure 10 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.
[0017] Figure 11 This is a schematic diagram illustrating another semiconductor device in an embodiment.
[0018] Figure 12 This is a schematic diagram illustrating another semiconductor device in an embodiment.
[0019] Figure 13 This is a schematic cross-sectional view illustrating another semiconductor device in an embodiment.
[0020] Figure 14 This is a schematic cross-sectional view illustrating another semiconductor device in an embodiment. Detailed Implementation
[0021] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.
[0022] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., do not necessarily have to be the same as in reality. Even when representing the same part, there are cases where the dimensions and ratios of each other are represented differently according to the accompanying drawings.
[0023] In this application specification and figures, the same reference numerals are used for elements that are the same as those described with respect to the figures that have appeared, and detailed descriptions are omitted where appropriate.
[0024] In the following explanation, n + n － The expressions indicate the relative levels of each impurity concentration. Specifically, a "+" indicates a relatively high impurity concentration compared to an expression without either "+" or "-" markings, while a "-" indicates a relatively low impurity concentration compared to an expression without any markings. When each region contains both p-type and n-type impurities, these expressions represent the relative levels of the actual impurity concentrations after these impurities have compensated for each other.
[0025] In the following examples, the first conductivity type is n-type and the second conductivity type is p-type. However, for the embodiments described below, the p-type and n-type of each semiconductor region can also be reversed to implement the embodiments.
[0026] Figure 1 This is a schematic top view illustrating an embodiment of a semiconductor device.
[0027] In the description of the implementation method, mutually orthogonal X, Y, and Z directions are used. For example, Figure 1 As shown, when viewed from above (viewed along the Z direction), the semiconductor device 100 of the embodiment is rectangular with sides extending along the X and Y directions.
[0028] The semiconductor device 100 is, for example, a MOSFET. A source electrode 12, a gate pad 13, and a gate wiring 14 are provided on the upper surface of the semiconductor device 100. The source electrode 12, the gate pad 13, and the gate wiring 14 are arranged, for example, in the same X-Y plane.
[0029] In the semiconductor device 100, a cell region RC with a source electrode 12 is provided, and a peripheral region RE located around the cell region RC in the X-Y plane. As described later, the cell region RC is the region in the semiconductor layer where a transistor is formed. The source electrode 12 extends along the X-Y plane and completely covers the cell region RC. The gate pad 13 and the gate wiring 14 are not provided in the cell region RC. The source electrode 12 is insulated from the gate pad 13 and the gate wiring 14.
[0030] The peripheral region RE is aligned with the cell region RC in the X-Y plane. The peripheral region RE may, for example, include the termination region of the semiconductor device 100. The termination region includes the outer edge of the semiconductor layer when viewed from above, and is the region along its outer edge. Gate wiring 14 and gate pad 13 are disposed in the peripheral region RE, and may, for example, surround the source electrode 12. The gate wiring 14 extends along the X or Y direction and is electrically connected to the gate pad 13. In this example, the gate pad 13 is disposed at the corner of the rectangle of the semiconductor device 100. The source electrode 12 is not disposed in the peripheral region RE.
[0031] Figures 2-5 This is a schematic diagram illustrating a semiconductor device according to an example embodiment.
[0032] Figures 2-5 Showing the cell region RC ( Figure 1 The construction of region R1 shown. Figure 2 as well as Figure 3 The floor plan layout is shown. Figure 2 The shadow lines and Figure 4 The cross-section of line A1-A1' shown corresponds to the cross-section shown. Figure 3 The shadow lines and Figure 4 The cross-section of line A2-A2' shown corresponds to the cross-section shown. Figure 4 express Figure 2 as well as Figure 3 The cross-section of line A3-A3' shown. Figure 5 express Figure 2 as well as Figure 3 The cross-section of line A4-A4' shown.
[0033] For example, Figure 4 As shown, the semiconductor device 100 has a drain electrode 11 (first electrode), a source electrode 12 (second electrode), and a semiconductor layer 20. The semiconductor layer 20 is located between the drain electrode 11 and the source electrode 12.
[0034] Furthermore, in the description of the embodiment, the direction from the drain electrode 11 toward the source electrode 12 is defined as the Z direction. The upper and lower surfaces of the semiconductor layer 20 (semiconductor substrate) are along an X-Y plane perpendicular to the Z direction. For convenience, the direction from the drain electrode 11 toward the source electrode 12 is referred to as "up," and the opposite direction as "down." These directions are based on the relative positional relationship between the drain electrode 11 and the source electrode 12 and are independent of the direction of gravity.
[0035] The semiconductor layer 20 includes a drain region 24, a drift region 21 (first semiconductor region), a base region 22 (second semiconductor region), and a source region 23 (third semiconductor region).
[0036] Drain region 24 is of the first conductivity type (n)+ The semiconductor region is of type 11. The drain region 24 is disposed on the drain electrode 11 and is electrically connected to the drain electrode 11.
[0037] Drift region 21 is a first conductivity type (n) located above drain region 24. － The concentration of n-type impurities in drift region 21 (atoms / cm³) is shown in the figure. 3 The concentration of n-type impurities in the drain region 24 (atoms / cm²) 3 )Low.
[0038] The base region 22 is a second conductivity type (p-type) semiconductor region disposed on a portion of the drift region 21.
[0039] Source region 23 is a first conductivity type (n) disposed on a portion of base region 22. + The source region 23 is a semiconductor region of type n. The upper end of the source region 23 is located on the upper surface 20U of the semiconductor layer 20 (the surface on the side of the source electrode 12). The concentration of n-type impurities in the source region 23 (atoms / cm³) 3 The concentration of n-type impurities is higher than that in drift region 21.
[0040] For example, the drift region 21 and the drain region 24 are set throughout the cell region RC and the surrounding region RE, and the base region 22 and the source region 23 are set in the cell region RC.
[0041] For example, Figure 4 As shown, a plurality of FP trenches TR1 (first trenches) and gate trenches TR2 (second trenches) are provided on the upper surface 20U of the semiconductor layer 20.
[0042] The FP trench TR1 extends from the upper surface 20U to the drift region 21 in the Z direction. An FP insulating portion 41 (first insulating portion) and an FP electrode 31 (third electrode) are provided within the FP trench TR1. The FP insulating portion 41 covers the inner walls (side surfaces and bottom surface) of the FP trench TR1. The FP insulating portion 41 is in contact with the drift region 21 and the base region 22.
[0043] The FP electrode 31 is a field plate. The FP electrode 31 is located inside the FP insulating portion 41 within the FP trench TR1. In other words, the FP insulating portion 41 is provided between the FP electrode 31 and the semiconductor layer 20. The lower surface and side surfaces of the FP electrode 31 are in contact with the FP insulating portion 41. The FP electrode 31 is insulated from the semiconductor layer 20 by the FP insulating portion 41. The FP electrode 31 has a portion aligned with a part of the drift region 21 in the X-Y plane. That is, the FP electrode 31 is positioned opposite the drift region 21 across the FP insulating portion 41.
[0044] The gate trench TR2 comprises the portion located between two adjacent FP trenches TR1 (the closest FP trench TR1 among a plurality of FP trenches TR1). The gate trench TR2 extends in the Z direction from the upper surface 20U of the semiconductor layer 20 to the drift region 21. The gate trench TR2 is shallower than the FP trench TR1.
[0045] A gate insulating portion 42 (second insulating portion) and a gate electrode 32 (fourth electrode) are provided within the gate trench TR2. The gate insulating portion 42 covers the inner wall (side and bottom surface) of the gate trench TR2. The gate insulating portion 42 is connected to the drift region 21, the base region 22, and the source region 23.
[0046] The gate electrode 32 is located inside the gate insulating portion 42 within the gate trench TR2. In other words, the gate insulating portion 42 is provided between the gate electrode 32 and the semiconductor layer 20. The lower surface and side surface of the gate electrode 32 are in contact with the gate insulating portion 42. The gate electrode 32 is insulated from the semiconductor layer 20 by the gate insulating portion 42. The gate electrode 32 has a portion that is arranged in the X-Y plane with a portion of the drift region 21, a portion of the base region 22, and a portion of the source region 23. That is, the gate electrode 32 is opposed to the drift region 21, the base region 22, and the source region 23 through the gate insulating portion 42. The FP electrode 31 extends to a depth deeper than the gate electrode 32.
[0047] In addition, for example, Figure 4 As shown, an insulating layer 51 extending along the X-Y plane is provided on the upper surface 20U of the semiconductor layer 20. A gate conductive layer 70 (first conductive layer) and an insulating layer 52 are provided on the insulating layer 51. The gate conductive layer 70 is located between the insulating layer 51 and the insulating layer 52. The source electrode 12 is provided on the insulating layer 52.
[0048] The gate conductive layer 70 is located above the gate trench TR2 and the gate electrode 32. Within the cell region RC, a portion of the gate conductive layer 70 is located directly above the gate electrode 32. For example... Figure 5 As shown, the gate conductive layer 70 is electrically connected to the gate electrode 32 via a gate contact portion 37 (first contact portion). The gate contact portion 37 penetrates the insulating layer 51 and is located between the gate electrode 32 and the gate conductive layer 70. That is, the gate contact portion 37 is disposed within a contact hole penetrating the insulating layer 51. The gate contact portion 37 is in contact with the upper surface of the gate electrode 32 and the lower surface of the gate conductive layer 70.
[0049] The side surfaces and top surface of the gate conductive layer 70 are covered by the insulating layer 52. The gate conductive layer 70 is insulated from the source electrode 12 by the insulating layer 52.
[0050] like Figure 5As shown, a source conductive layer 35 (second conductive layer) is provided on the FP electrode 31 and the base region 22. The source conductive layer 35 electrically connects the FP electrode 31 and the source region 23. The source conductive layer 35 extends along the X-Y plane and is in contact with the upper surface of the FP electrode 31, the upper surface of the FP insulating portion 41, and the upper surface of the base region 22.
[0051] More specifically, the source conductive layer 35 has a central portion 35a located at the center of the source conductive layer 35 in the X-Y plane and an outer portion 35b located outside the central portion 35a. A source region 23 (and a portion of the base region 22) is disposed between the outer portion 35b and the gate trench TR2. The outer portion 35b is in contact with the source region 23 and the base region 22. The central portion 35a is in full contact with the entire upper surface of the FP electrode 31. The upper end portion 41a of the FP insulating portion 41 is located between the outer portion 35b and the central portion 35a. The entire upper surface of the FP insulating portion 41 (upper end portion 41a) is covered by the source conductive layer 35.
[0052] The upper surface of the source conductive layer 35 is located higher than the upper end of the gate electrode 32. The lower surface of the source conductive layer 35 is located higher than the lower end of the gate electrode 32.
[0053] The source conductive layer 35 is formed as a conductive layer different from the gate conductive layer 70 and the source electrode 12. For example, an insulating layer 51 is provided on the source conductive layer 35. That is, an insulating layer 51 is disposed between the source conductive layer 35 and the gate conductive layer 70, and the source conductive layer 35 is insulated from the gate conductive layer 70. In addition, the source conductive layer 35 is located below the insulating layer 51 and the insulating layer 52 below the source electrode 12.
[0054] A source contact portion 36 (second contact portion) is provided between the source electrode 12 and the source conductive layer 35, penetrating the insulating layer 51 and the insulating layer 52. That is, the source contact portion 36 is provided in the contact hole penetrating the insulating layer 51 and the insulating layer 52. The source contact portion 36 is in contact with the lower surface of the source electrode 12 and the center of the upper surface of the source conductive layer 35 (central portion 35a). Thus, the source contact portion 36 electrically connects the source electrode 12 and the source conductive layer 35.
[0055] The source contact 36 is located directly above the FP electrode 31. The source conductive layer 35 (central portion 35a) is located between the FP electrode 31 and the source contact 36, electrically connecting the FP electrode 31 and the source contact 36.
[0056] In addition, such as Figure 3As shown, the source region 23 (and a portion of the base region 22) surrounds and is in contact with the outer peripheral surface of the outer portion 35b of the source conductive layer 35 in the X-Y plane. The outer portion 35b surrounds and is in contact with the outer peripheral surface of the upper end portion 41a of the FP insulating portion 41 in the X-Y plane. The upper end portion 41a surrounds and is in contact with the outer peripheral surface of the central portion 35a of the source region 23.
[0057] exist Figure 2 In the diagram, dashed lines indicate the positions of the FP electrode 31, FP insulating portion 41, FP trench TR1, source conductive layer 35, and gate trench TR2 when viewed from above. For example... Figure 2 As shown, in the unit region RC, multiple FP trenches TR1 are arranged in the X-Y plane. More specifically, the multiple FP trenches TR1 are arranged along a first arrangement direction D1 and a second arrangement direction D2. The first arrangement direction D1 is the direction that connects an FP trench TR1 to the FP trench TR1 closest to that FP trench TR1 in the shortest way. In top view, the multiple FP electrodes 31 (FP trenches TR1) are located at the intersection points of the grid or mesh formed by the lines extending along the first arrangement direction D1 and the lines extending along the second arrangement direction D2. In this example, the first arrangement direction D1 is the X direction, and the second arrangement direction D2 is the Y direction. Therefore, in top view, the multiple FP electrodes 31 are located at the vertices of a square. In addition, in the embodiment, the first arrangement direction D1 and the second arrangement direction D2 do not necessarily have to be orthogonal.
[0058] For example, the planar shape of the FP electrode 31 and the FP insulating portion 41 is circular. The planar shape of the FP electrode 31 and the FP insulating portion 41 can also be a square, a regular hexagon, or other regular polygon. Furthermore, regular polygons include those with rounded corners. An FP electrode 31 is located at the center of each FP trench TR1. The source contact portion 36 is cylindrical and located at the center of the FP electrode 31.
[0059] like Figure 3 As shown, in the cell region RC, the gate trench TR2 has a first extension 61, a second extension 62, and a wide portion 65.
[0060] The first extension 61 is located between two adjacent FP grooves TR1 in the first arrangement direction D1 and extends in a direction perpendicular to the first arrangement direction D1. The first extension 61 has, for example, a certain width W61 (length in the direction perpendicular to the first arrangement direction D1).
[0061] The second extension 62 is located between two adjacent FP grooves TR1 in the second alignment direction D2, and extends in a direction perpendicular to the second alignment direction D2. The second extension 62 has, for example, a certain width W62 (length in the direction perpendicular to the second alignment direction D2). The width W62 may also be the same as the width W61.
[0062] The wide portion 65 and the first extension 61 are arranged in the Y direction (a direction perpendicular to the first alignment direction D1) and are continuous with the first extension 61. The wide portion 65 is the portion that expands the width of the gate trench TR2 from either the first extension 61 or the second extension 62. That is, the width W65 (length in the direction perpendicular to the first alignment direction D1) of the wide portion 65 is wider than the width W61 of the first extension 61. The width W65 of the wide portion 65 is wider than the width W62 of the second extension 62. The width of the wide portion 65 in the second alignment direction D2 can also be the same as the width W65 in the first alignment direction D1. The wide portion 65 and the first extension 61 are arranged alternately in the Y direction (a direction perpendicular to the first alignment direction D1).
[0063] The wide portion 65 connects the end of the first extension 61 to the end of the second extension 62. For example, the planar shape of the gate trench TR2 is a mesh. In this example, the gate trench TR2 is a lattice structure where the portions extending along the first alignment direction D1 and the portions extending along the second alignment direction D2 intersect at the wide portion 65. That is, the wide portion 65 is located at each vertex of a square, and the two first extensions 61 and the two second extensions 62 are located on the four sides of the square. An FP trench TR1 is disposed inside the square, and the FP electrode 31 is located at the center of the square.
[0064] For example, the width of the wide portion 65 gradually increases from the first extension 61 or the second extension 62. Therefore, the planar shape of the area surrounded by the first extension 61, the second extension 62 and the wide portion 65 is a polygon with rounded corners (in this example, a square).
[0065] Viewed from above, the thickness of the gate insulating portion 42 within the gate trench TR2 can be substantially constant. The gate electrode 32 includes an extension (first extension) located within the first extension 61 and extending in the same manner as the first extension 61, an extension (second extension) located within the second extension 62 and extending in the same manner as the second extension 62, and a portion located within the wide portion 65. The gate electrode 32, like the gate trench TR2, is mesh-like or lattice-like. The gate electrode 32 within the wide portion 65 can also be a wide portion having a width greater than the width of the gate electrode 32 within the first extension 61 or the second extension 62. By making the gate trench TR2 and the gate electrode 32 inside it mesh-like or lattice-like, a larger area for transistor operation can be ensured.
[0066] Furthermore, the width of the gate trench TR2 (the width W61 of the first extension 61 and the width W62 of the second extension 62) may be narrower than the width of the FP trench TR1 (the length in the first alignment direction D1 or the second alignment direction D2). Additionally, the width of the gate electrode 32 within the first extension 61 or the second extension 62 may be narrower than the width of the FP electrode 31.
[0067] like Figure 3 As shown, the gate contact portion 37 is, for example, a cylindrical shape with a circular planar shape. The gate contact portion 37 is located in the center of the wide portion 65 of the gate trench TR2. The gate contact portion 37 may also be provided only in the wide portion 65, and not in the first extension portion 61 or the second extension portion 62. The diameter of the gate contact portion 37 may also be larger than the width W61 of the first extension portion 61 or the width W62 of the second extension portion 62.
[0068] like Figure 2 As shown, the gate conductive layer 70 includes a plurality of first wiring portions 71. The first wiring portions 71 extend above the first extension 61 of the gate trench TR2 along the first extension 61. For example, the first wiring portions 71 are located above the plurality of first extensions 61 and the plurality of wide portions 65, and extend along the second arrangement direction D2. For example, the first wiring portions 71 are connected to a plurality of gate contacts 37 located directly below the first wiring portions 71.
[0069] Furthermore, the gate conductive layer 70 includes a plurality of second wiring portions 72. The second wiring portions 72 extend along the second extension 62 above the second extension 62 of the gate trench TR2. That is, in this example, the gate conductive layer 70 is a grid-like structure in which the first wiring portions 71 and the second wiring portions 72 intersect. For example, the gate conductive layer 70 overlaps entirely with the gate trench TR2 in the vertical direction. The gate contact portion 37 is connected to the intersection 75 of the first wiring portions 71 and the second wiring portions 72.
[0070] When viewed from above, an FP electrode 31 is surrounded by a square formed by two adjacent first wiring portions 71 and two adjacent second wiring portions 72, with a source contact portion 36 disposed at the center of the square.
[0071] The first wiring portion 71 and the second wiring portion 72 extend from the cell region RC to the peripheral region RE, and in the peripheral region RE, they connect with the gate wiring 14 located above the first wiring portion 71 and the second wiring portion 72 (see reference). Figure 1 Electrical connection.
[0072] An example of the materials used in the various elements of the semiconductor device 100 will be described.
[0073] Each semiconductor region of semiconductor layer 20 is made of a semiconductor material, including silicon (Si), silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. Semiconductor layer 20 is, for example, a silicon substrate or other semiconductor substrate.
[0074] The FP electrode 31 and the gate electrode 32 are made of conductive materials such as polysilicon or metal.
[0075] The FP insulating part 41, gate insulating part 42, insulating layer 51, and insulating layer 52 contain insulating materials such as silicon oxide or silicon nitride.
[0076] The gate contact 37 and the source contact 36 contain metals such as W (tungsten) and Ti (titanium).
[0077] The drain electrode 11, source electrode 12, gate wiring 14, and gate pad 13 contain metals such as Al (aluminum).
[0078] The gate conductive layer 70 comprises at least one of polysilicon, silicide, and a metallic material. The source conductive layer 35 comprises at least one of polysilicon, silicide, and a metallic material. The silicide comprises at least one selected from the group consisting of Co (cobalt), W, Ti, and Ni (nickel). Metallic silicides such as CoSi, WSi, TiSi, and NiSi are used as silicides. The metallic material comprises at least one selected from the group consisting of Ti, TiN (titanium nitride), W, Cu (copper), and Al. By using a metallic material, a conductive layer with lower resistance can be obtained. For example, the resistivity of the gate conductive layer 70 or the source conductive layer 35 can also be lower than the resistivity of the gate electrode 32 or the FP electrode 31. By using polysilicon or silicide, the formation of the gate conductive layer 70 and the source conductive layer 35 becomes easier.
[0079] The operation of the semiconductor device 100 will be explained.
[0080] With a positive voltage applied to the drain electrode 11 relative to the source electrode 12, a positive voltage is applied to the gate pad 13. This applies a voltage to the gate electrode 32 from the gate pad 13 via the gate wiring 14, the gate conductive layer 70, and the gate contact 37. If a voltage greater than a threshold is applied to the gate electrode 32, an inversion layer is formed in the base region 22, and the transistor is turned on. That is, a conduction current flows from the drain electrode 11 through the drift region 21, the base region 22, the source region 23, the source conductive layer 35, and the source contact 36 to the source electrode 12. If the voltage of the gate pad 13 decreases, and the voltage of the gate electrode 32 falls below the threshold, the transistor is turned off, and no conduction current flows.
[0081] As explained above, in the semiconductor device 100 of the embodiment, a gate conductive layer 70 electrically connected to the gate electrode 32 is provided above the gate electrode 32 within the cell region RC. This reduces the gate resistance in the semiconductor device 100.
[0082] For example, in a semiconductor device as a reference example, a configuration is considered where the gate conductive layer 70 and the gate contact portion 37 are not provided in the cell region RC, and the gate wiring 14 is connected to the gate electrode 32 in the peripheral region RE. In contrast, in the embodiment, by providing the gate conductive layer 70, for example, in the cell region RC, current flows through the path where the gate conductive layer 70 and the gate electrode 32 are connected in parallel. Therefore, according to the embodiment, the gate resistance can be reduced compared to the reference example.
[0083] In the reference example, to reduce gate resistance, the method of increasing the number of gate wirings 14 is considered in order to improve chip layout design. However, if the number of gate wirings 14 is increased, the effective device area becomes smaller and the area efficiency deteriorates for the same chip size. Alternatively, to reduce gate resistance, the method of making the gate electrode a metal gate formed of a metal material is also considered. However, in the case of a metal gate, there are concerns that damage to the gate insulating film, etc., during the manufacturing process may lead to deterioration of characteristics such as breakdown voltage, leakage current, and defect density. Furthermore, the manufacturing process can sometimes become more complex with metal gates.
[0084] In contrast, in this embodiment, by providing the gate conductive layer 70, as described above, the gate resistance can be reduced. For example, by using polysilicon as the material for the gate electrode 32 and providing the gate conductive layer 70, the gate resistance can be reduced while avoiding the characteristic degradation and manufacturing process complexity caused by metal gates. However, in this embodiment, a metal material may also be used in the gate electrode 32.
[0085] Furthermore, widening the gate electrode 32 reduces the gate resistance. However, widening the gate electrode 32 also increases the capacitance between the gate electrode 32 and the drain electrode 11, and increases the transistor's feedback capacitance. For example, in a configuration where the gate electrode 32 and the FP electrode 31 are located in different trenches, compared to a configuration where the gate electrode 32 and the FP electrode are located in the same trench, widening the gate electrode 32 tends to increase the feedback capacitance. In contrast, in a configuration where the gate electrode 32 and the FP electrode 31 are located in different trenches, by providing the gate conductive layer 70, the increase in feedback capacitance can be suppressed and the gate resistance reduced.
[0086] Such as about Figure 4 or Figure 5As explained, the source electrode 12 is disposed on the insulating layer 52 above the gate conductive layer 70. Thus, by disposing the gate conductive layer 70 and the source electrode 12 on different layers, the gate conductive layer 70 can be configured to extend wider within the cell region RC.
[0087] Furthermore, the gate contact 37 is disposed within the wide portion 65 of the gate trench TR2. Therefore, even if a positional shift occurs due to manufacturing process variations, the gate contact 37 can be reliably connected to the gate electrode 32. For example, the width W37 (diameter) of the gate contact 37 can be wider than the width W61 of the first extension 61 of the gate trench TR2. With a wider gate contact 37, resistance can be further reduced.
[0088] In addition, such as Figure 3 As shown, a wide portion 65 is surrounded by four FP trenches TR1 closest to the wide portion 65. That is, the wide portion 65 is located at an equidistant position from each of the plurality of FP electrodes 31 (or source contacts 36) surrounding it. The gate contact 37, located at the center of the wide portion 65, is located at an equidistant position from each of the plurality of FP electrodes 31 (or source contacts 36) surrounding it. That is, the gate contact 37 is positioned at the position with the greatest distance from the FP electrodes or source contacts 36. This ensures sufficient space for the wide portion 65 and the gate contact 37, and suppresses interference between the gate contact 37 and the source contact 36.
[0089] Additionally, as a layer different from the source electrode 12, a source conductive layer 35 is provided to electrically connect the source region 23 to the FP electrode 31. Using the source conductive layer 35, interference between the contact portion connecting the source region 23 to the source electrode 12 and the gate conductive layer 70 can be suppressed.
[0090] For example, Figure 4 or Figure 5 As shown, a source conductive layer 35 extending laterally from the source region 23 is provided, and a source contact portion 36 is connected directly above the FP electrode 31. This allows for electrical connection between the source region 23 and the source electrode 12, thus eliminating the need to provide the source contact portion 36 directly above the source region 23. Consequently, the source contact portion 36 can be positioned away from the gate conductive layer 70, suppressing interference between the source contact portion 36 and the gate conductive layer 70.
[0091] In this example, such as Figure 3As shown, the planar shape of the region enclosed by the gate trench TR2 is a square with rounded corners, and the planar shape of the source conductive layer 35 is also a square with rounded corners. That is, when viewed from above, the outer edge of the source conductive layer 35 extends along the gate trench TR2 (gate electrode 32) at a constant distance from it. In other words, the width of the source region 23 is approximately constant. This can suppress deviations in the in-plane transistor characteristics.
[0092] Additionally, regarding Figure 2 As explained, the gate conductive layer 70 has a first wiring portion 71 connected to a plurality of gate contacts 37 located directly below it. Using the first wiring portion 71, the gate conductive layer 70 is led out to the peripheral region RE, avoiding the source contacts 36. Furthermore, in this example, the gate conductive layer 70 is a lattice structure where the first wiring portion 71 and the second wiring portion 72 intersect along the gate trench TR2 and the gate electrode 32. This further reduces the gate resistance by leading the gate conductive layer 70 out in two directions.
[0093] For example, Figure 2 As shown, the width W71 of the first wiring portion 71 (the length in the direction perpendicular to the second arrangement direction D2) is greater than the width W61 of the first extension portion 61 of the gate trench TR2 (refer to...). Figure 3 The width W71 of the first wiring section 71 may also be wider than the width W65 of the wide section 65 (see reference). Figure 3 The width is such that, for example, the first wiring portion 71 covers the entirety of the plurality of first extension portions 61. The first wiring portion 71 (intersection portion 75) covers the entirety of the plurality of wide portions 65 from above. Thus, the gate conductive layer 70 is wider, thereby enabling the gate conductive layer 70 to be disposed on the gate contact portion 37 more reliably, even if there are deviations in the manufacturing process.
[0094] For example, the gate conductive layer 70 (the end of the first wiring portion 71 and the end of the second wiring portion 72) may overlap with the outer portion 35b of the source conductive layer 35 and the end of the FP insulating portion 41 in the vertical direction.
[0095] Figure 6 as well as Figure 7 This is a schematic diagram of a semiconductor device illustrating a variation of an embodiment.
[0096] Figure 6 and Figure 2 Similarly, a planar layout of a modified semiconductor device is shown.
[0097] Figure 7 and Figure 3 Similarly, a planar layout of a modified semiconductor device is shown.
[0098] This variation is in Figures 1-5 The configuration of the second extension 62 of the gate trench TR2, the gate electrode 32 within the second extension 62, and the gate insulating portion 42 within the second extension 62 is omitted in the semiconductor device 100 described herein.
[0099] That is, in this example, the multiple gate trenches TR2 are configured in a stripe pattern. The multiple gate trenches TR2 are arranged in a first arrangement direction D1. Each gate trench TR2 extends along a second arrangement direction D2. Each gate trench TR2 has a shape in which the first extension 61 and the wide portion 65 are arranged alternately in the second arrangement direction D2. Between two adjacent gate trenches TR2, a multiple FP electrodes 31 are arranged along the second arrangement direction D2.
[0100] Thus, when the gate trench TR2 and the gate electrode 32 are striped, compared to the lattice-shaped case, for example, the electrical capacitance between the gate electrode 32 and the drain electrode 11 can be reduced, and the feedback capacitance of the transistor can be reduced.
[0101] In this example, a gate contact 37 and a gate conductive layer 70 are also provided. For example Figure 6 As shown, in this example, the gate conductive layer 70 can also be a grid-like structure having a first wiring portion 71 and a second wiring portion. The first wiring portion 71 extends along the gate trench above the gate trench TR2. The gate contact portion 37 is connected at the intersection 75 of the first wiring portion 71 and the second wiring portion 72. Figures 1-5 The semiconductor device 100 described herein is the same, and it can suppress gate resistance. In addition, by using the source conductive layer 35, interference between the gate conductive layer 70 and the source contact portion 36 can be suppressed.
[0102] Figure 8 of (a), Figure 8 (b) Figure 9 of (a), Figure 9 (b) and Figure 10 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.
[0103] like Figure 8 As shown in (a), for example, an FP trench TR1 and a gate trench TR2 are formed on the upper surface 20U of the semiconductor layer 20 by RIE (reactive ion etching). An FP insulating portion 41 is formed in the FP trench TR1, and an FP electrode 31 is formed inside it. A gate insulating portion 42 is formed in the gate trench TR2, and a gate electrode 32 is formed inside it. In addition, before (or after) the formation of the FP trench TR1 and the gate trench TR2, a base region 22 and a source region 23 are formed by ion implantation.
[0104] After that, as Figure 8As shown in (b), a photoresist 80 is formed on the semiconductor layer 20. An opening 80e is formed in the photoresist 80 above the FP trench TR1 using photolithography. Then, using the photoresist 80 as a mask, a portion of the semiconductor layer 20 and the FP insulating portion 41 is removed on the upper surface 20U side. This exposes the upper surface of the FP electrode 31, the base region 22, and the source region 23. Afterward, the photoresist 80 is removed.
[0105] After that, as Figure 9 As shown in (a), a source conductive layer 35 is formed on the upper surface of the FP electrode 31 exposed on the upper surface 20U side, the base region 22, the source region 23, and the FP insulating portion 41. For example, a stacked film of Ti, TiN, and W is deposited on the upper surface 20U side and planarized by CMP (chemical mechanical polishing) to form the source conductive layer 35. On the upper surface 20U side, the gate insulating portion 42, the source region 23, and the upper surface of the source conductive layer 35 are exposed.
[0106] After that, as Figure 9 As shown in (b), an insulating layer 51 is formed over the gate insulating portion 42, the source region 23, and the source conductive layer 35. A gate contact portion 37 is formed directly above the gate electrode 32, penetrating the insulating layer 51 and connected to the gate electrode 32. Figure 9 (not shown in (b)). Then, a gate conductive layer 70 connected to the gate contact 37 is formed on the insulating layer 51. For example, a metal film such as W is deposited on the insulating layer 51, and a portion of the metal film is removed by RIE directly above the FP electrode 31 to form the gate conductive layer 70.
[0107] After that, as Figure 10 As shown, an insulating layer 52 is formed on the insulating layer 51 and the gate conductive layer 70. Directly above the FP electrode 31, a source contact portion 36 is formed that penetrates the insulating layer 51 and the insulating layer 52 and is connected to the source conductive layer 35. Then, a source electrode 12 connected to the source contact portion 36 is formed on the insulating layer 52.
[0108] Figures 11-14 This is a schematic diagram illustrating another semiconductor device in an embodiment.
[0109] Although the illustration is omitted, in this semiconductor device, the aforementioned Figure 1 Similarly, the cell region RC for the source electrode 12 is set and the peripheral region RE for the gate wiring 14 and the gate pad 13 is set.
[0110] Figures 11-14 This indicates the construction within the unit region RC. Figure 11 as well as Figure 12 This indicates a floor plan layout. Additionally, Figure 11 The shadow lines and Figure 13 The cross-section of line A5-A5' shown corresponds to the cross-section shown. Figure 12 The shadow lines and Figure 13 The cross-section of line A6-A6' shown corresponds to the cross-section shown. Figure 13 express Figure 11 as well as Figure 12 The cross-section of line A7-A7' shown. Figure 14 express Figure 11 as well as Figure 12 The cross-section of line A8-A8' shown.
[0111] like Figure 11 As shown, in the cell region RC, multiple FP trenches TR1 are arranged in a first alignment direction D1 and a second alignment direction D2 in the X-Y plane. In this example, the first alignment direction D1 is the X direction. The second alignment direction D2 is an inclined direction relative to the first alignment direction D1. For example, the angle between the first alignment direction D1 and the second alignment direction D2 is 60°. In this example, when viewed from above, multiple FP electrodes 31 are configured to be located at the vertices of a triangle (e.g., an equilateral triangle).
[0112] like Figure 12 As shown, the gate trench TR2 has a first extension 61, a second extension 62, and a third extension 63. The first extension 61 extends along the Y direction (a direction perpendicular to the first alignment direction D1). The second extension 62 extends along a direction perpendicular to the second alignment direction D2. The third extension 63 extends along a direction different from the first extension 61 and the second extension 62.
[0113] The planar shape of the gate trench TR2 is a mesh of hexagons (e.g., regular hexagons). Specifically, two first extensions 61, two second extensions 62, and two third extensions 63 are located along the six sides of the hexagons. The first extensions 61, second extensions 62, and third extensions 63 are connected at each vertex of the hexagon. An FP trench TR1 is disposed inside the hexagon, with the FP electrode 31 located at the center of the hexagon. Alternatively, the hexagon formed by the gate trench TR2 can also be a hexagon with rounded corners (vertices). In this case, the vertices of the hexagon (the connecting portions of the three extensions) become wide portions that expand from the width of each extension. For example, the planar shape of the region surrounded by the first extensions 61, second extensions 62, third extensions 63, and the wide portion is a regular hexagon with rounded corners.
[0114] Gate contact 37 is disposed at the connection of the first extension 61, the second extension 62, and the third extension 63. That is, gate contact 37 is located at the vertices of the hexagon. Gate electrode 32 is the same as gate trench TR2, and is a repeating hexagonal mesh.
[0115] like Figure 11 As shown, the gate conductive layer 70 includes a first wiring portion 71, a second wiring portion 72, and a third wiring portion 73. The first wiring portion 71 extends along the first extension portion 61 above the first extension portion 61 of the gate trench TR2. The second wiring portion 72 extends along the second extension portion 62 above the second extension portion 62 of the gate trench TR2. The third wiring portion 73 extends along the third extension portion 63 above the third extension portion 63 of the gate trench TR2.
[0116] That is, the planar shape of the gate conductive layer 70 is a hexagonal mesh. Two first wiring portions 71, two second wiring portions 72, and two third wiring portions 73 are located on the six sides of the hexagon. The gate contact portion 37 is connected to the intersection of the first wiring portions 71, the second wiring portions 72, and the third wiring portions 73, that is, the vertices of the hexagon.
[0117] Thus, multiple FP electrodes 31 can be arranged on a triangle. In this example, similar to the semiconductor device described above, the gate resistance can be reduced by providing the gate conductive layer 70. At this time, by providing the source conductive layer 35, a contact portion connecting the source region 23 and the source electrode 12 can be formed, avoiding the location of the gate conductive layer 70.
[0118] According to an embodiment, a semiconductor device capable of reducing gate resistance can be provided.
[0119] In this application specification, "electrical connection" includes not only the case of connection through direct contact, but also the case of connection through other conductive components.
[0120] The relative levels of impurity concentrations between different semiconductor regions can be confirmed, for example, using SCM (scanning electrostatic capacitance microscopy). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of impurities activated in that region. Therefore, the relative levels of carrier concentrations between different semiconductor regions can also be confirmed using SCM. Additionally, the impurity concentration in each semiconductor region can be determined, for example, using SIMS (secondary ion mass analysis).
[0121] The above examples illustrate several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents. Furthermore, the foregoing embodiments can be combined with each other for implementation.
Claims
1. A semiconductor device, characterized in that, have: First electrode; The second electrode is located above the first electrode; A semiconductor layer is disposed between the first electrode and the second electrode, and includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type disposed on the first semiconductor region, and a third semiconductor region of a first conductivity type disposed on the second semiconductor region and electrically connected to the second electrode. Multiple third electrodes are arranged in a unit region for the second electrodes to be disposed, and are opposite to the first semiconductor region through a first insulating portion; The fourth electrode includes a portion located between two adjacent third electrodes, comprising a first extension located in the unit region and a wide portion located in the unit region having a width greater than that of the first extension, the fourth electrode being opposed to the second semiconductor region via a second insulating portion; The first contact portion is located above the fourth electrode and is connected to the wide portion of the fourth electrode; as well as The first conductive layer is located above the fourth electrode and is connected to the fourth electrode via the first contact portion.
2. The semiconductor device according to claim 1, characterized in that, The second electrode is disposed on an insulating layer disposed above the first conductive layer.
3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an insulating layer disposed on the semiconductor layer. The semiconductor device further includes a second conductive layer that is insulated from the first conductive layer, electrically connects the third semiconductor region to the third electrode and to the second electrode, and is located below the insulating layer.
4. The semiconductor device according to claim 3, characterized in that, The outer edge of the second conductive layer extends along the fourth electrode at a fixed distance from it.
5. The semiconductor device according to claim 3, characterized in that, It also has a second contact portion located directly above the third electrode, penetrating the insulating layer, and electrically connecting the second conductive layer to the second electrode.
6. The semiconductor device according to claim 1, characterized in that, The first contact portion is located at an equidistant position from each of the plurality of third electrodes surrounding the first contact portion.
7. The semiconductor device according to claim 1, characterized in that, The plurality of the third electrodes are arranged in mutually intersecting first and second arrangement directions. The first extension is located between two adjacent third electrodes in the first arrangement direction. The fourth electrode further includes a second extension located between two adjacent third electrodes in the second arrangement direction. The wide portion connects the end of the first extension to the end of the second extension.
8. The semiconductor device according to claim 7, characterized in that, The second arrangement direction is a direction orthogonal to the first arrangement direction. The fourth electrode is configured in a lattice shape.
9. The semiconductor device according to claim 7, characterized in that, The first conductive layer includes a first wiring portion extending along the second alignment direction. The first wiring portion is connected to a plurality of first contact portions located directly below the first wiring portion.
10. The semiconductor device according to claim 8, characterized in that, The first conductive layer is a grid-like structure in which a first wiring portion extending along the first extension portion above the first extension portion intersects with a second wiring portion extending along the second extension portion above the second extension portion. The first contact portion is connected to the intersection of the first wiring portion and the second wiring portion.
11. The semiconductor device according to claim 1, characterized in that, The plurality of the fourth electrodes are configured in a striped pattern.
12. The semiconductor device according to claim 11, characterized in that, The first conductive layer includes a first wiring portion extending along the fourth electrode above the fourth electrode and a second wiring portion intersecting the first wiring portion. The first contact portion is connected to the intersection of the first wiring portion and the second wiring portion.
13. The semiconductor device according to claim 9, characterized in that, The width of the first wiring portion is wider than the width of the first extension portion of the fourth electrode.
14. The semiconductor device according to claim 3, characterized in that, A portion of the first conductive layer overlaps with a portion of the second conductive layer in the vertical direction.
15. The semiconductor device according to claim 1, characterized in that, The plurality of the third electrodes are located at the vertices of a square or an equilateral triangle.
16. The semiconductor device according to claim 1, characterized in that, The first conductive layer comprises at least one of polycrystalline silicon, silicide, and metallic material. The silicide comprises at least one selected from the group consisting of Co, W, Ti, and Ni. The metallic material comprises at least one selected from the group consisting of Ti, TiN, W, Cu, and Al.
17. The semiconductor device according to claim 3, characterized in that, The second conductive layer comprises at least one of polycrystalline silicon, silicide, and metallic material. The silicide comprises at least one selected from the group consisting of Co, W, Ti, and Ni. The metallic material comprises at least one selected from the group consisting of Ti, TiN, W, Cu, and Al.
18. The semiconductor device according to claim 3, characterized in that, The second conductive layer is connected to the second semiconductor region, the third semiconductor region, and the third electrode, respectively.
19. The semiconductor device according to claim 1, characterized in that, The second semiconductor region is located between the third electrode and the fourth electrode.
20. A semiconductor device, characterized in that, have: First electrode; The second electrode is located above the first electrode; A semiconductor layer is disposed between the first electrode and the second electrode, and includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type disposed on the first semiconductor region, and a third semiconductor region of a first conductivity type disposed on the second semiconductor region and electrically connected to the second electrode. Multiple third electrodes are arranged in a unit region for the second electrodes to be disposed, and are opposite to the first semiconductor region through a first insulating portion; The fourth electrode includes a portion located between two adjacent third electrodes and is opposed to the second semiconductor region via a second insulating portion; A first conductive layer is included in the portion of the unit region located directly above the fourth electrode, and is electrically connected to the fourth electrode via a first contact portion; The second conductive layer is insulated from the first conductive layer, electrically connecting the third semiconductor region to the third electrode and also electrically connecting it to the second electrode; as well as An insulating layer is located above the second conductive layer and below the second electrode.
Citation Information
Patent Citations
Phenolic hydroxyl group-containing resin, curable composition, cured product, prepreg, circuit board, build-up film, semiconductor sealing material and semiconductor device
JP2024159336A