Method for separating chips based on silicon-based LED device

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for separating chips based on a silicon-based LED device, and the method comprises the following steps S1 to S7. According to the method for separating the chip based on the silicon-based LED device, high-precision patterning and depth control of a wafer cutting channel are realized through collaborative design of photoetching and etching processes, so that a single chip is naturally separated along a preset path in a grinding and thinning process. Compared with a traditional mechanical splitting or laser cutting process, the technology can avoid material damage caused by appearance defects such as edge breakage and cracks and a heat effect by means of micron-level etching precision and a stress-free separation mechanism, the yield of chips is increased to 98% or above, and the technology is particularly suitable for large-scale manufacturing of high-precision photoelectric devices such as Mini / Micro LEDs. The number of chips in a single mini / microLED product ranges from tens of thousands to hundreds of thousands, and the working efficiency and the productivity are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for separating chips based on silicon-based LED devices. Background Technology

[0002] In the semiconductor device manufacturing industry, wafer dicing is one of the core processes for separating a pre-fabricated wafer into individual chips (dies). The quality and efficiency of this process directly affect chip performance, yield, and production costs. While the industry has developed various technical solutions to meet the dicing requirements of different material systems and chip structures, significant challenges remain.

[0003] Currently, the mainstream dicing techniques mainly include laser cutting and mechanical dicing (Dicing Before Grinding, DBG / SDBG or similar methods).

[0004] Laser cutting technology: As described in reference patent 1 (CN117483972A), it uses a process of "grinding and thinning + laser cutting" to separate chips. Laser cutting has advantages such as non-contact operation, high precision, and applicability to complex patterns. However, this technology has a fundamental drawback: the unavoidable thermal effect generated during laser action. Semiconductor materials (such as gallium arsenide and silicon) are extremely sensitive to temperature. Localized high temperatures from lasers can lead to lattice distortion, a significant increase in defect density, and a severe reduction in carrier mobility. For multilayer heterostructures (such as compound semiconductor devices), the mismatch in thermal expansion coefficients between different materials can introduce significant residual stress in the cutting area, threatening the long-term reliability of the device. In addition, high temperatures can easily cause the metal interconnects on the chip to melt, oxidize, or undergo electromigration, resulting in electrical failure. From a device perspective, the thermal effect can degrade the heat dissipation performance of power semiconductors (increasing thermal resistance), causing optical performance degradation or even structural burn-out of optoelectronic devices (such as LEDs and lasers). At the process level, the laser heat-affected zone (HAZ) may cause local thermal deformation of the wafer, affecting subsequent pick-up and packaging processes. When using advanced packaging (such as 2.5D / 3D IC), the thermal mismatch problem will be further aggravated, affecting the stability of the packaging structure.

[0005] Mechanical chipping technology: As represented by patent 2 (CN102104091A), this method involves first cutting trenches (partial cutting) on ​​a hard substrate (such as sapphire) and then applying mechanical force to cause the chip to break and separate along the trenches (chipping). This method is relatively low-cost and avoids thermal damage from lasers. However, its core problem lies in "chipping." Semiconductor materials (especially silicon) are hard and brittle. During mechanical chipping, the applied stress is highly concentrated at the cutting edge, which can easily induce uncontrolled crack propagation, resulting in micron-sized chipping defects at the chip edge. On silicon wafers, this chipping size can typically reach 20-50 μm. Chipping not only directly damages the effective area of ​​the chip, but also damages the critical terminal protection structure of power devices, reducing their withstand voltage capability; for optoelectronic devices (such as LEDs and VCSELs), chipping scatters light, reducing optical extraction efficiency and beam quality, and may even lead to chip structural breakage. Furthermore, edge chipping can severely affect the processing accuracy and strength of thin wafers (<100μm), and in advanced packaging (such as chip stacking and high-density interconnects), rough edges can increase stress concentration points, reduce the reliability of interconnect structures, and become a potential source of failure.

[0006] As semiconductor devices develop towards higher integration, smaller size, and higher performance, the aforementioned technological bottlenecks are becoming increasingly prominent: Thermal effects and edge chipping problems coexist: Current mainstream technologies cannot simultaneously avoid thermal damage caused by laser cutting and edge chipping defects caused by mechanical cracking, which poses a severe challenge, especially for heat-sensitive materials (such as GaAs, InP) and devices with high reliability requirements (such as power ICs, high-frequency devices, and precision optoelectronic devices).

[0007] Bottlenecks in small-size chip dicing efficiency: When the number of chips on a single wafer increases dramatically to over 100,000, neither the single-point scanning method of laser cutting nor the mechanical method requiring precise alignment and dicing operations can meet the economic requirements of large-scale mass production. The contradiction between processing speed, accuracy, and yield becomes particularly prominent in small-size chip dicing.

[0008] Therefore, there is an urgent need to develop a new chip separation technology that can effectively solve or significantly alleviate the thermal damage caused by laser cutting and the edge chipping defects caused by mechanical cleaving, while simultaneously meeting the requirements for efficient, high-precision, and high-yield separation of small-sized chips (more than 100,000 chips per wafer) to support the manufacturing of next-generation semiconductor devices. Summary of the Invention

[0009] The technical problems to be solved by this invention are: traditional laser cutting leads to thermal effects; traditional dicing methods lead to edge chipping; and the cutting efficiency of small-sized chips is not high.

[0010] The technical solution adopted by this invention to solve its technical problem is: a method for separating chips based on silicon-based LED devices, comprising the following steps: S1. Provides silicon-based LED wafers with metal lines and gallium nitride functional areas on the front side and silicon epitaxial surfaces on the back side; S2. Perform shallow cutting in the dicing area on the front side of the wafer to remove the metal layer on the dicing surface and expose the underlying silicon substrate, forming a shallow groove; S3. Spin-coat positive photoresist on the front side of the wafer, and after exposure and development, remove the photoresist in the dicing area to expose the silicon substrate of the shallow dicing groove, while other areas are covered and protected by photoresist. S4. Perform dry Bosch etching on the exposed dicing silicon substrate, with an etching depth equal to the sum of the target chip thickness and the reserved depth; S5. Remove residual photoresist and apply a polishing protective film to the front side of the wafer; S6. Grind the back of the wafer to thin it to the bottom depth of the dry etching, so that the wafer is naturally separated into individual chips along the dicing path and fixed by the grinding protective film; S7. Apply a dicing film to the back of the polished wafer, and remove the polishing protective film from the front to expose the front of the chip.

[0011] In step S2, the shallow cutting depth is determined by completely removing the metal layer on the surface of the cutting track and exposing the silicon substrate, and the depth is less than the total depth of the cutting track.

[0012] The dry Bosch etching in step S4 employs alternating etching and passivation cycles, with the etching gas containing SF6 and the passivation gas containing C4F8.

[0013] The reserved depth in step S4 is 5–20 μm, and the target thickness of the chip is 50–150 μm.

[0014] The polishing protective film in step S6 is a high-viscosity BG film, which maintains the chip position during the polishing process.

[0015] In step S7, the adhesion of the cutting film is lower than that of the grinding protective film, and the light transmittance is greater than 90%.

[0016] In step S3, the photoresist patterning uses an ultraviolet exposure wavelength of 365 nm or 405 nm, and the developing solution is tetramethylammonium hydroxide solution.

[0017] The beneficial effects of this invention are: (1) The present invention provides a method for separating chips based on silicon-based LED devices. Through the collaborative design of photolithography and etching processes, it achieves high-precision patterning and depth control of wafer dicing paths, enabling individual chips to naturally separate along a preset path during the grinding and thinning process. Compared with traditional mechanical dicing or laser cutting processes, this technology, with its micron-level etching precision and stress-free separation mechanism, can avoid appearance defects such as chipping and cracking, as well as material damage caused by thermal effects, thereby increasing the chip yield to over 98%. It is particularly suitable for the large-scale manufacturing of high-precision optoelectronic devices such as Mini / Micro LEDs. (2) This invention is designed for mini / microLED products with tens of thousands to hundreds of thousands of chips per chip, which greatly improves work efficiency and production capacity; (3) There is a metal layer in the cutting channel. Pure blade cutting affects the cutting quality. Using a combination of shallow cutting and etching greatly improves the problem of edge chipping and improves the product yield. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 This is a schematic diagram of the silicon-based LED wafer structure in this invention.

[0020] Figure 2 yes Figure 1 A schematic diagram of the internal structure in the EE direction.

[0021] Figure 3 This is a schematic diagram of the structure in step two of this invention.

[0022] Figure 4 This is a structural diagram of the third state in this invention. Figure 5 This is a schematic diagram of the structure in the fourth state of the present invention, where deep Bosch etching is performed.

[0023] Figure 6 This is a schematic diagram of the structure after the photoresist on the surface is removed in this invention.

[0024] Figure 7 This is a schematic diagram of the structure after the grinding-type BG film covers the wafer surface in this invention.

[0025] Figure 8 This is a schematic diagram of the structure before the grinding and thinning process in this invention.

[0026] Figure 9 This is a schematic diagram of the structure after grinding and thinning in this invention.

[0027] Figure 10 This is a schematic diagram of the structure of the wafer after the dicing film is attached to the back side in this invention.

[0028] Figure 11 This is a schematic diagram of the structure after the BG film on the front side of the wafer is removed in this invention.

[0029] Figure 12 This is a schematic diagram of the structure in this invention where the BG film is replaced with a glass substrate.

[0030] In the figure: 01. Silicon-based LED wafer, 02. Cut track, 03. Metal material layer, 04. Chip front side, 05. Back side, 06. Shallow groove, 07. Positive photoresist, 08. Dry Bosch etching, 09. BG film, 10. Temporary bonding material, 11. Glass, 12. Grinding, 13. Cutting film. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] Figure 1 , Figure 2 The method for separating chips based on silicon-based LED devices, as shown, includes the following steps: providing a silicon-based LED wafer 01, the front side 04 of which is provided with metal lines and gallium nitride functional areas, and the back side 05 is a silicon epitaxial surface. The front side 04 is defined as having metal lines and functional areas. The metal lines are responsible for current transmission, and the functional areas use materials such as gallium nitride to achieve light emission. The silicon epitaxial surface is defined as the back side 05, which plays a supporting and heat-conducting role. A shallow-cutting process is performed on the dicing groove 02 area on the front side of the silicon-based LED wafer 01. The groove depth is precisely controlled to a shallow groove 06 of a certain thickness using a cutting method. Figure 3 The purpose is to remove the metal layer 03 on the surface of the 02 etch path, fully exposing the underlying silicon substrate and laying the foundation for subsequent dry etching processes. The presence of the surface metal layer can severely interfere with the effective contact between reactive ions and the silicon substrate during dry etching. Shallow pre-treatment ensures that the plasma can act uniformly on the silicon substrate during dry etching, achieving precise etching of the 02 etch path area, improving sidewall etching results, and enhancing product quality. Positive photoresist 07 is spin-coated on the front side of the wafer. After exposure and development, the photoresist 07 in the dicing area 02 is removed, exposing the silicon substrate of the shallow dicing 06. Other areas are covered and protected by positive photoresist 07. This positive photoresist 07 has good film-forming properties and resolution, and can tightly adhere to the wafer surface to form a complete protective layer. Subsequently, pattern transfer is achieved using an exposure and development process: through precise positioning with a mask, the positive photoresist 07 at the corresponding position in the dicing area 02 undergoes a photochemical reaction under ultraviolet light irradiation, and the molecular structure breaks down from long chains into smaller molecules, which are selectively dissolved and removed under the action of the developer, thereby exposing the underlying silicon substrate; while the positive photoresist 07 in the unexposed areas is retained, forming a protective barrier, such as... Figure 4 The core of this process design lies in the selective retention and removal of positive photoresist 07 to create a dual-functional "etch-protection" region. This ensures that subsequent dry etching only affects the silicon substrate of dicing channel 02, effectively preventing etching gases from eroding and damaging other functional areas such as the active area and electrodes of the chip. This safeguards the integrity of the key structure and performance of the LED chip and provides process assurance for improving chip yield and consistency.

[0034] After completing the photoresist patterning process (07), the exposed silicon substrate (02 etch path) is subjected to dry Bosch etching (08), with an etching depth equal to the sum of the target chip thickness and the reserved depth; For example... Figure 5 By precisely controlling parameters such as etching gas composition, power, and time, the silicon at dicing track 02 is etched to a specific depth, which is set to the final required chip thickness plus a certain depth. This process design is technically significant: when the back side is thinned to be flush with the bottom of the dry etching, the wafer can naturally separate along the pre-etched dicing track without additional mechanical force. This significantly reduces the risk of defects such as edge chipping and cracking generated during traditional mechanical dicing, while also reducing the damage to the internal structure of the chip caused by cutting stress, improving the chip's electrical performance and luminous uniformity, and providing key technical support for achieving high-precision, high-reliability silicon-based LED chip manufacturing. After etching, the photoresist 07 on the surface is removed, as shown below. Figure 6 .

[0035] After dry etching of the 01 dicing track of the silicon-based LED wafer, a polishing protective film 09 is laminated to the front side. This tape has high adhesion and flexibility, and can tightly cover the wafer surface, providing a physical protective barrier for the chip. Figure 7 Subsequently, the back surface 05 of the silicon-based LED wafer 01 is thinned using a grinding and thinning equipment, gradually removing material until the target thickness is achieved, such as... Figure 8 and Figure 9During this process, since the dry etching process has already created a deep pre-etch along the dicing path, when the grinding step 12 reaches a specific position, the wafer naturally separates into individual chips along the dicing path. At this time, the grinding protective film 09 firmly fixes the separated chips with its adhesiveness, preventing them from scattering or shifting, and providing a stable material state for subsequent chip transfer, tape and reel packaging and other processes, effectively ensuring the integrity and yield of chip manufacturing; After the individual chips are separated by grinding and thinning, a dicing film 13 is attached to the back side 05 of the wafer, such as... Figure 10 This film material possesses stable support and moderate adhesion, enabling it to flatten and fix the wafer, providing a stable substrate for subsequent operations. After bonding, the polishing protective film 09 on the front side of the wafer is removed, fully exposing the front side 04 of the chip containing metal circuitry and functional areas, as shown below. Figure 11 This step facilitates high-precision visual inspection of the integrity of metal circuits and the morphology of functional areas on the chip surface using optical inspection equipment. It also enables tape and reel equipment to pick up chips more accurately, simplifies chip picking and arrangement processes, improves the efficiency of subsequent processes and the accuracy of yield determination, and provides reliable assurance for chip packaging and shipping.

[0036] The aforementioned BG film can be replaced by a glass substrate: the front side 04 of the wafer is temporarily bonded to the glass 11 using temporary bonding material 10, such as... Figure 12 .

[0037] This double-sided mask must meet the following characteristics: ① High temperature stability (resistance to frictional heat during the grinding process); ② Low-stress bonding (to avoid wafer warping); ③ Easy peelability (can be removed without damage after grinding). After bonding, the glass substrate provides rigid support for the wafer, replacing the flexible protective function of the BG film, keeping the wafer flat during the back-side thinning process. After grinding and thinning and chip separation are completed, the adhesion of the two films can be reduced by ultraviolet light irradiation or thermal activation, allowing the glass substrate to be safely separated from the wafer, achieving no residue exposure on the front side of the chip.

[0038] This solution offers higher flatness compared to traditional BG films, making it particularly suitable for processing large-size wafers (e.g., 8 inches and above) or ultra-thin chips. It can effectively reduce the risk of chip breakage and improve the accuracy of automated post-processing operations.

[0039] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for separating chips based on silicon-based LED devices, characterized in that, Includes the following steps: S1. Provides a silicon-based LED wafer (01), with metal lines and gallium nitride functional areas on the front side (04) and a silicon epitaxial surface on the back side (05); S2. A shallow cut is performed in the dicing channel (02) area on the front side of the wafer to remove the metal material layer (03) on the surface of the dicing channel and expose the underlying silicon substrate to form a shallow groove (06). S3. A positive photoresist (07) is spin-coated on the front side of the wafer. After exposure and development, the photoresist (07) in the dicing area (02) is removed to expose the silicon substrate of the shallow groove (06). Other areas are covered and protected by the photoresist (07). S4. Perform dry Bosch etching (08) on the exposed dicing (02) silicon substrate, with an etching depth equal to the sum of the target chip thickness and the reserved depth; S5. Remove residual photoresist (07) and apply a polishing protective film to the front side of the wafer (09); S6. Grind the back side of the wafer (05) to thin it to the depth of the dry etching bottom, so that the wafer is naturally separated into individual chips along the dicing path (02) and fixed by the grinding protective film (09); S7. Attach a dicing film (13) to the back of the wafer after grinding (12), and remove the grinding protective film (09) on the front to expose the front of the chip.

2. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: In step S2, the shallow cutting depth is determined by completely removing the surface metal layer of the cutting channel (02) and exposing the silicon substrate, and the depth is less than the total depth of the cutting channel (02).

3. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: The dry Bosch etching (08) in step S4 employs alternating etching and passivation cycles, with the etching gas containing SF6 and the passivation gas containing C4F8.

4. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: The reserved depth in step S4 is 5–20 μm, and the target thickness of the chip is 50–150 μm.

5. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: The polishing protective film (09) in step S6 is a high-viscosity BG film, which maintains the chip position during the polishing (12) process.

6. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: The adhesion of the cutting film (13) in step S7 is lower than that of the polishing protective film (09), and the light transmittance is greater than 90%.

7. The method for separating chips based on silicon-based LED devices according to claim 1, characterized in that: In step S3, the photoresist (07) is patterned using an ultraviolet exposure wavelength of 365nm or 405nm, and the developing solution is tetramethylammonium hydroxide solution.

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