Large model reasoning representation method for electrical drawing

Abstract

The invention discloses a large model reasoning representation method for an electrical drawing, and relates to the technical field of electrical engineering informatization, comprising the following steps: accessing and standardizing a multi-source drawing; carrying out multi-modal analysis and initial element extraction; unifying identification space alignment and cross-modal registration; loading a strong type mode and a constraint language; reasoning expression construction; performing uncertainty propagation and conflict grading processing; performing reasoning operator calling and task arrangement; evidence chain generation, playback and report output; and performing incremental updating. According to the method, the multi-mode content of the electrical drawing is converted into strong-type, executable and traceable reasoning representation, a unified identification space and a constraint language are established, and a combinable operator library is operated on the reasoning representation, so that automatic checking and diagnosis of the electrical drawing are realized. According to the method, complex tasks such as connectivity, dimensional consistency and protection cooperation can be completed, an accurate evidence chain can be generated for each conclusion, and the credibility and interpretability of the conclusions are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electrical engineering informatization technology, in particular to a large model reasoning representation method of electrical drawing. BACKGROUND

[0002] With the increasing digitalization of electrical engineering design, construction and operation, the data volume and complexity of electrical drawings have significantly increased. Existing technologies mostly focus on "graph element / text recognition and relationship extraction", and common methods are to use computer vision (CV) detection, OCR text recognition, and rule library or template matching to realize automatic recognition of electrical equipment and connections. Some researches introduce visual language models (VLM) or large language models (LLM) to improve recognition accuracy, but their results usually stop at the level of "element list" or "automatic configuration graph", lacking strong type reasoning representation that can support engineering-level checking and diagnosis. This leads to two main problems: first, the recognition results are difficult to directly verify the connectivity, loop completeness and protection coordination of electrical systems, and cannot meet the requirements of formal verification; second, when the drawing version is frequently iterated or cross-format input (such as DWG, PDF, scanned copy), existing technologies lack unified alignment and incremental update mechanism, leading to data redundancy, conflict resolution difficulty, and insufficient engineering traceability and maintainability. SUMMARY

[0003] In view of the deficiencies of the prior art, the present application provides a large model reasoning representation method of electrical drawing to solve the problems raised in the background art.

[0004] To achieve the above purpose, the present application provides the following technical solutions: In a first aspect, the present application provides a large model reasoning representation method of electrical drawing, comprising the following steps: S1, multi-source drawing access and standardized input; Receiving multi-source electrical drawings and uniformly converting into a standardized input buffer; S2, multi-modal analysis and initial element extraction; Converting the electrical drawings in the standardized input buffer into structured information, extracting and obtaining candidate elements; S3, unified identification space alignment and cross-modal registration; Aligning the candidate elements to the unified identification space five-tuple and using a registration strategy for cross-modal registration; S4, loading strong type patterns and constraint languages; Loading the strong type patterns of electrical objects and loading the machine-readable constraint language set; S5, reasoning representation construction; Under the joint constraints of aligned elements and patterns / constraints, constructing a multi-modal topological-semantic graph; S6, uncertainty propagation and conflict resolution; Explicitly propagate uncertainty on multi-modal topology-semantic graph, and resolve conflicts by conservative conjunction priority conflict resolution; S7, executable reasoning operator invocation and task orchestration; Orchestrate operators in the order of dependency on the multi-modal topology-semantic graph after conflict resolution; S8, evidence chain generation, playback and report output; Generate, playback and output each check / diagnosis conclusion executed by the reasoning operator; S9, incremental update; Input the as-built drawing, change order or field photo, complete the update, and generate the difference report.

[0005] Further optimize the technical solution, in step S2, multi-modal analysis and initial element extraction, comprising: Call a visual language model in parallel on a unified reasoning portal to perform geometric side analysis and extract graphic class elements; Perform layout analysis and OCR for text side analysis to extract text class elements; Call a language model for semantic side analysis to extract semantic class elements; The graphic class elements, text class elements and semantic class elements are candidate elements, each candidate element is assigned an identification confidence component, and its original picture space information is retained; The original picture space information includes page number, bounding box, coordinate system.

[0006] Further optimize the technical solution, the candidate elements include: The graphic class elements include circuit breaker, disconnecting switch, bus, grounding symbol, CT / PT, wire segment, arrow primitive; The text class elements include device name, model number, parameter table, loop number, nameplate parameter; The semantic class elements include device category, parameter meaning, and standardized name after alias aggregation.

[0007] Further optimize the technical solution, in step S3, the unified identification space five-tuple of candidate element alignment is as follows: Among them, is the device ID, is the terminal, is the wire segment ID, is the page number, is the positioning point or bounding box in the page coordinate system; The registration strategy adopts the principles of geometric constraint priority, semantic consistency evidence, and confidence fusion conservation. The geometric side takes the connection of end points-terminal adsorption and lead arrow-text box pointing as strong constraints, the semantic side takes the same pointing of device name and adjacent label / table cell as consistency conditions, and the confidence components of each candidate element are fused to form the ontology confidence label.

[0008] Further optimization of the technical solution, in step S4, the strong type mode includes entities such as Device, Terminal, Conductor, Relay, Measurement, Ground, and Loop and their field domains, including rated voltage, current, insulation level, protection curve family and setting value interval; Constraint language set Including defining unit conversion consistency, rated value interval, logic / interlocking / blocking constraint, upper / lower level protection cooperation relationship.

[0009] Further optimization of the technical solution, in step S5, the multi-modal topology-semantic graph is as follows: Among them, is a multi-modal topology-semantic graph; is a node set representing devices / terminals / measurement points / protection devices; is an edge set representing electrical connections, reference associations, and logical relationships; is a constraint language set of strong type mode; Each node / edge also saves source reference and evidence chain, and the graph Also defines executable views, including "loop_check", "selectivity", and "dimension_check", so that subsequent executable reasoning operators can be directly called.

[0010] Further optimization of the technical solution, in step S7, after the multi-modal topology-semantic graph defines the executable view, the operators are arranged in the order of dependence on the executable view, including: First, perform "connected domain and loop completeness check"; Then perform "unit / dimension consistency and rated value cross-check"; Then perform "protection selectivity cooperation check, curve family / setting value" and "short circuit / ground path reachability analysis"; Finally, perform "logic / interlocking / blocking consistency verification"; Each operator outputs structured results including conclusion label, quantitative index, affected node / edge list, and evidence chain reference set, ensuring engineering readability and automated integration.

[0011] Further optimization of the technical solution, for each check / diagnosis conclusion in step S8, generate a solidified evidence chain: including the original page number, coordinates / enclosing box, text segment and local screenshot index; support "from conclusion to original drawing" hop-by-hop playback on the front end or API side; report output is provided in the form of machine-readable and engineering-readable dual channels, all quantitative indicators and units are checked again for consistency in the export layer.

[0012] Further optimization of the technical solution, when importing as-built drawings, change orders or field photos, based on unified identification and geometric near-neighbor positioning of affected subgraphs, only the subgraphs are reconstructed and operators are recalculated, and a difference report is generated, and the difference result is written back to the multimodal topology-semantic graph and drives the necessary secondary review.

[0013] Further optimization of the technical solution, the method also exposes / import, / build_graph, / infer, / report, / diff, etc. Idempotent API, supports local / cloud hybrid deployment and GPU optional acceleration; On the performance side, the target graphing time limit and single batch inference time limit are given for complex primary graphs with more than 2000 nodes, and pixel / physical dimension dual threshold values are set for "alarm positioning error".

[0014] In a second aspect, the present application provides a computer device comprising a memory and a processor, the memory storing a computer program, wherein: the computer program instructions are executed by the processor to realize the steps of the electrical drawing large model reasoning representation method according to the first aspect of the present application.

[0015] In a third aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein: the computer program instructions are executed by the processor to realize the steps of the electrical drawing large model reasoning representation method according to the first aspect of the present application.

[0016] Compared with the prior art, the present application provides an electrical drawing large model reasoning representation method, which has the following advantages: The electrical drawing large model reasoning representation method converts the multimodal content of the electrical drawing into a strongly typed, executable and traceable reasoning representation, establishes a unified identification space and constraint language, and runs a combinable operator library on the reasoning representation, thereby realizing automatic checking and diagnosis of the electrical drawing. This method not only can complete complex tasks such as connectivity, dimensional consistency, and protection coordination, but also can generate accurate evidence chains for each conclusion, significantly improving the credibility and explainability of the conclusions. At the same time, the system supports cross-format alignment and incremental updating, can effectively adapt to the iteration and changes of the drawing, reduce the engineering checking cost, and improve the efficiency and reliability of electrical design and operation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a large-scale model reasoning representation method for electrical drawings proposed in this invention. Detailed Implementation

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0021] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0022] Example 1: Reference Figure 1 This is the first embodiment of the present invention, which provides a method for large-scale model reasoning representation of electrical drawings, including the following steps: S1. Multi-source drawing access and standardized input; Electrical drawings from different sources and in different formats need to be uniformly accessed and standardized to ensure that subsequent multimodal analysis and inference modeling can be carried out in a unified basic environment. Input drawings may include CAD files from the design phase (common formats such as DWG and DXF), PDF documents output during completion or review (which may be in vector or bitmap format), and image data obtained on-site through scanning or photography during maintenance or renovation. Because these materials vary significantly in terms of accuracy, resolution, scale, and completeness, without prior standardization, it will be difficult to achieve consistent alignment results in the subsequent analysis phase, and the reusability and verifiability of the final inference representation cannot be guaranteed.

[0023] Therefore, first of all, all input drawings are uniformly converted into a standardized input buffer, and a unique identifier UID is established for each original drawing. The UID is generated by hashing multiple-dimensional information such as project number, file number, page number, coordinate range, and timestamp, ensuring accurate positioning to a specific drawing page during subsequent version management and tracing. At the same time, the system also records metadata related to the drawing, including file format category, drawing resolution (such as DPI or vector scale), graphic scale, time of acquisition or generation, source path, and environment parameters at the time of import. Through these information, a strict one-to-one mapping relationship can be established between different formats and versions, laying the foundation for cross-drawing alignment and incremental update.

[0024] It is important to note that this step only performs "lossless import" and "basic geometry calibration" during processing. By "lossless import", it means that during the parsing and format conversion of input drawings, all geometric features and text annotations are preserved as they are, without compression, filtering or cropping, thereby avoiding introducing additional recognition bias. By "basic geometry calibration", it means that through the operations of unified coordinate system, standardized scale factor, correction of page rotation and flipping, etc., the comparability of different drawings in spatial geometry is ensured. It is worth noting that the system will not perform any form of semantic inference at this stage, nor will it classify or label the graph elements. The purpose of this design is to ensure the complete traceability and replaceability of the subsequent reasoning link.

[0025] S2, multi-modal analysis and initial element extraction; Convert the electrical drawings in the standardized input buffer into structured information, extract and obtain candidate elements.

[0026] After completing the standardization of input drawings, enter the multi-modal analysis stage. The goal of this stage is to strip out the original geometric figures, text annotations, and semantic information layer by layer, forming a set of candidate element collections, providing data basis for subsequent identification space alignment and strong type reasoning. Since electrical drawings are a typical multi-modal information carrier, they contain not only symbolic electrical element graph elements, but also geometric structures such as lines and arrows, and embed rich text annotations, parameter tables, and explanatory text, so a single recognition method cannot complete comprehensive analysis. A multi-channel fusion strategy of "visual language model (VLM) + optical character recognition (OCR) + layout analysis + language model (LLM)" is adopted to ensure efficient capture of different types of information.

[0027] Multi-modal analysis and initial element extraction, including: Call the visual language model in parallel for geometric side analysis on the unified reasoning entrance, extracting graphic elements.

[0028] The text side is analyzed by layout analysis and OCR to extract text elements.

[0029] The semantic side is analyzed by calling a language model to extract semantic elements.

[0030] The graphic elements, text elements, and semantic elements are candidate elements, each of which is assigned a recognition confidence component and retains original image space information.

[0031] The original image space information includes page numbers, bounding boxes, and coordinate systems.

[0032] The candidate elements include: The graphic elements include circuit breakers, disconnectors, busbars, grounding symbols, CT / PT, wire segments, and arrowhead primitives. The text elements include device names, model markings, parameter tables, circuit numbers, and nameplates. The semantic elements include device categories, parameter meanings, and aggregated standardized names.

[0033] The visual language model first detects electrical primitives such as circuit breakers, disconnectors, grounding switches, busbar symbols, transformers (CT / PT), protection relays, and their contact symbols. Then it identifies the connection structure and its endpoint positions, extracts arrow direction information to determine the geometric relationship between the connection and the device, and accurately locates the terminal positions and primitive bounding boxes. During this process, the VLM not only outputs the category label of each candidate primitive but also assigns a confidence score to represent the reliability of the recognition.

[0034] On the text side, the system extracts the text information in the drawing by combining OCR with layout analysis techniques. These texts include not only label information such as device names, model specifications, and circuit numbers but also tabular parameter data (such as rated current, voltage level, and short-circuit capacity). Layout analysis can identify the text and its corresponding bounding box and lead relationship, thereby establishing a "text-graph" mapping at the geometric level. For complex engineering drawings, it can also distinguish between the main graph part and the supplementary explanation part to avoid mixing different levels of text information.

[0035] On the semantic side, the role of the LLM is to further transform the raw text extracted by OCR into structured semantic elements, such as parsing "10kV / 630A" into fields "rated voltage = 10kV" and "rated current = 630A"; aggregating "CB1", "Breaker-1", and "Breaker-1" into aliases of the same device instance; and identifying logical relationships based on context, such as a certain protection device corresponding to a lower-level circuit. For ambiguous or ambiguous labels, the LLM will normalize them in combination with a domain knowledge base and output a semantic confidence score for subsequent fusion.

[0036] S3, uniform identification space alignment and cross-modal registration; After the preliminary analysis and extraction of candidate elements, the uniform identification space alignment phase is entered. The multi-modal candidate elements from the geometry side, the text side and the semantic side in the previous step are mapped into a unified identification system to eliminate inconsistencies between different drawings, different formats and different recognition modules, and to ensure that the subsequent reasoning representation can run on consistent and unambiguous data.

[0037] The uniform identification space five tuple of candidate element alignment is as follows: Among them, is the device ID, is the terminal, is the wire segment ID, is the page number, is the positioning point or bounding box in the page coordinate system. Through this identification space, any candidate element can be uniquely bound to a specific drawing page, spatial location and semantic category, thereby realizing cross-modal instance alignment.

[0038] The registration strategy adopts the principles of geometric constraint priority, semantic consistency evidence and confidence fusion conservation: The geometry side takes the line end point-terminal adsorption and the lead arrow-text box pointing as strong constraints, and the semantic side takes the same pointing of the device name and the adjacent label / table cell as the consistency condition. The confidence components of each candidate element are fused to form the ontology confidence label.

[0039] Specifically, at the geometric constraint level, first, the spatial matching between candidate elements is established by using geometric features such as line end point adsorption, lead arrow pointing, bus direction consistency, etc. For example, when the end point of a line is detected to be exactly overlapped with the terminal area of a circuit breaker symbol, the system will bind them as an "electrical connection" relationship; when the arrow points directly to a text box, the system will establish semantic association between the text and the corresponding device symbol. These geometric rules usually have high certainty, so they are the highest priority hard constraints in the registration process.

[0040] At the semantic constraint level, the semantic consistency of text information such as device name, loop number, and nameplate parameters is compared to assist in solving the cases that cannot be covered by geometric constraints or have ambiguities. For example, if the "circuit breaker QF1" extracted by OCR is close to a certain symbol in space, but does not meet the strict geometric overlap relationship, the system will use the semantic matching mechanism to determine whether the "QF1" text should be bound to the circuit breaker graph element. If they are highly consistent in semantics, even if there is a deviation in geometric relationship, an effective binding can be established through semantic constraints, thereby enhancing the robustness of the system in complex drawings.

[0041] At the confidence level fusion level, the method normalizes and fuses the confidence from the geometric side, the text side, and the semantic side to obtain a unified confidence label. At the output level, this step reorganizes all candidate elements into consistent alignment results across pages and formats, and generates a candidate conflict list. The alignment result is stored in the form of a unified identification space five-tuple, ensuring that the subsequent reasoning representation can be directly invoked; the conflict list records the ambiguities or contradictions between the recognition results for further processing in the subsequent uncertainty propagation and conflict handling steps.

[0042] S4, load strong type mode and constraint language; Load the strong type mode of electrical objects and load the machine-readable constraint language set. Establish a strict type system and attribute domain for each type of object involved in the electrical drawing, and combine it with the machine-readable constraint language, thereby providing a solid semantic and logical foundation for the construction and automatic checking of subsequent reasoning representations.

[0043] The strong type mode includes entities such as Device, Terminal, Conductor, Relay, Measurement, Ground, and Loop, as well as their field domains, including rated voltage, current, insulation level, protection curve family, and setting value interval. For example, the Device entity contains attributes such as device model, nameplate voltage, nameplate current, and rated capacity; the Terminal entity contains attributes such as polarity, direction, and number; the Conductor entity contains attributes such as cross-sectional number, insulation level, and current-carrying capacity; the Relay entity contains parameters such as protection curve family (e.g. IEC_SI, IEC_VI, ANSI_I2T, etc.), setting current, and time delay; the Measurement entity stores measured quantities such as voltage, current, and power; the Ground entity records information such as grounding method and grounding resistance; and the Loop entity defines the loop category and its relationship with upstream and downstream devices.

[0044] Constraint language set including the definition of unit conversion consistency, rated value range, logic / interlock / lockout constraints, upper / lower level protection matching relationship. Specifically, the constraint language not only includes the unit conversion and consistency check of physical quantities (such as ensuring that the rated voltage of the device matches the insulation level of the conductor), but also includes the rationality of the rated value range (such as the rated current of the circuit breaker must be within a certain range), and the complex logical relationship (such as the selective cooperation between upper and lower level protection devices, the conflict-free of interlocking conditions, and the integrity of the lockout rules). All constraints are described in the form of machine-readable rules or expressions, facilitating subsequent reasoning operator calls and automatic checking execution.

[0045] S5, reasoning representation construction; Under the common constraints of aligned elements and patterns / constraints, a multi-modal topology-semantic graph is constructed, which can not only express the physical connectivity of electrical drawings, but also carry out subsequent operator execution. In other words, this step is to transform the "object set after alignment and semantic enhancement" into "graph structure with computable semantics", truly realizing the leap from drawing data to reasoning model.

[0046] The multi-modal topology-semantic graph is as follows: wherein, is a multi-modal topology-semantic graph; is a node set representing devices / terminals / measurement points / protection devices; is an edge set representing electrical connections, reference associations and logical relationships; is a constraint language set of strongly typed patterns.

[0047] Specifically, the node set Based on the aligned strongly typed objects, devices, terminals, conductor segments, protection devices, measurement points, grounding points and loop units are all regarded as nodes of the graph. Each node not only has a unique identifier UID, but also has a type field and parameter constraints inherited from Schema. For example, the circuit breaker node contains rated voltage, current and protection characteristic parameters; the conductor node contains cross-sectional area, insulation level and current capacity; the protection relay node records the curve family and setting value. The attribute values of the nodes have been standardized through the dimension mapping mechanism in the loading stage, so as to ensure that they can be directly involved in logical judgment and operator call in the reasoning process.

[0048] Specifically, the edge set The geometric and semantic constraints between candidate elements are converted into explicit relationship edges. Mainly include electrical connection edges (representing the connection relationship between terminals and wire segments), reference edges (representing the corresponding relationship between devices and text boxes, page numbers), logical edges (representing the interlocking, locking or dependency relationship between devices), and topological edges (representing the upstream and downstream electrical relationship). Each edge carries a confidence weight, which is inherited from the multi-modal confidence fusion result in step S3, and is normalized in the graph layer to ensure the consistency of the global confidence distribution.

[0049] Each node / edge also saves the source reference and evidence chain, the graph Executable views are also defined, including "loop_check" (generated for loop completeness checking, which only retains nodes and edges related to loops), "selectivity" (generated for protection selectivity matching checking, which focuses on the relationship between protection devices and upstream and downstream), and "dimension_check" (generated for dimension consistency checking), so that subsequent executable inference operators can be directly called.

[0050] S6, uncertainty propagation and conflict classification and disposal; Uncertainty is explicitly propagated on the multi-modal topological-semantic graph, and conflict resolution is performed using conservative conjunction priority conflict classification and disposal.

[0051] The recognition confidence differences, cross-modal information contradictions and constraint conflicts left over by the multi-modal analysis stage are explicitly managed and resolved, so as to ensure that the operation of the subsequent inference operator has controllable reliability. Because the source of the electrical drawing is diverse, it may come from clear CAD vector files, or from low-resolution scans or on-site photos, so the recognition result often has certain uncertainty. Through mathematical propagation and hierarchical processing, this uncertainty is quantified and systematized, avoiding its being ignored or misused in subsequent reasoning.

[0052] Explicit propagation is used to realize the transmission of local uncertainty to global topological reasoning, so that the conclusions of subsequent loop completeness checking, short circuit path analysis, etc. have quantitative reliability indicators.

[0053] In terms of conflict resolution, the method adopts the principle of "conservative conjunction priority". Specifically, when multiple sources of analysis results or constraint conditions give mutually contradictory conclusions for the same object, the system will first take the minimum value of the confidence level in all constraints as the lower bound of the conservative conclusion to ensure that there is no over-optimistic inference in the electrical review with higher safety requirements. At the same time, the method also introduces a relaxation solution mechanism, that is, on the basis of conservative conjunction, a tolerance parameter ε is set, when the conflict is in a state of slight contradiction or on the edge, the output of "gray alert" is allowed. This gray alert is neither completely wrong nor directly ignored, but prompts the engineering personnel or the upper system for manual review or secondary calculation.

[0054] In order to facilitate engineering application, conflicts are divided into three levels: local conflict, cross-page conflict and global conflict. Local conflict mainly occurs in the contradiction between device symbols and labels within the same page, such as inconsistent rated current units; cross-page conflict involves the same device or circuit between different drawings, such as mismatched parameters between as-built drawing and construction drawing; global conflict is manifested as contradiction in the constraint system level, such as incompatible protection setting and superior device rating. For local conflicts, the system prioritizes recalculation and alignment within the subgraph; for cross-page conflicts, the system marks the conflict to the difference list for re-computation in the incremental update stage; for global conflicts, it directly triggers high-level alerts, prompting the design or operation and maintenance link to re-examine.

[0055] S7, executable reasoning operator calling and task arrangement; On the multi-modal topology-semantics graph after conflict resolution, arrange operators in the order of dependence, and on the graph Execute the predefined reasoning operator library in an orderly manner, thereby completing the automatic checking and diagnosis of electrical drawings. Unlike traditional "result visualization or static display", this step emphasizes executability, that is, all reasoning logic runs in the form of operators on the graph, outputting quantifiable, traceable and reviewable conclusions.

[0056] After defining the executable view on the multi-modal topology-semantics graph, arrange operators in the order of dependence, including: First, perform "connected domain and loop completeness check"; Then, perform "unit / dimension consistency and rated value cross-check"; Then, perform "protection selectivity matching check, curve family / set value" and "short circuit / ground path reachability analysis"; Finally, perform "logic / interlock / block consistency verification".

[0057] Each operator outputs structured results including conclusion label, quantitative index, affected node / edge list and evidence chain reference set, ensuring engineering readability and automated integration.

[0058] In this embodiment, at the operator execution level, specialized operator modules are provided for different checking tasks. For example, a loop completeness checking operator traverses the terminal-conductor-device nodes to confirm whether a closed electrical loop is formed; a dimension and rated value consistency operator compares the matching relationship between the rated voltage of a device and the insulation class of a conductor, and the setting value of a protection device and the rated value of a superior device; a protection selectivity matching operator checks whether the upstream and downstream protection actions have time margins by calling the curve family and setting value of the relay, and generates an alarm if the curves overlap and the margin is insufficient; a short-circuit and ground path analysis operator performs reachability search on the weighted graph to identify potential fault current paths and calculate their reliability; and a logic and interlocking consistency operator verifies the completeness and conflict-free of interlocking conditions in the logic relationship subgraph. These operators are all based on defined executable views, thereby avoiding repeated traversal on large-scale graphs and significantly improving reasoning efficiency.

[0059] S8, evidence chain generation, playback, and report output; Each checking / diagnosis conclusion executed by the reasoning operator is generated, played back, and output. A traceable evidence chain is established for each reasoning conclusion, and these evidences are solidified and output in a structured and visualized manner. The significance lies in that engineering applications not only require “conclusions”, but also require “the source and reason of the conclusions”. Without evidence chains, even if the operator gives a conclusion, it is difficult to be adopted in engineering review, project review, or compliance audit. Therefore, this step provides explainability and compliance assurance for the entire method.

[0060] For each checking / diagnosis conclusion, an evidence chain is generated and solidified: including the original drawing page number, coordinates / bounding box, text segment, and local screenshot index. For example, when the system determines that a loop is missing a grounding knife switch, its evidence chain not only indicates the page number of the missing point, but also marks the coordinates and adjacent marked text in that area, so that engineers can intuitively verify on the original drawing.

[0061] The “hop-by-hop playback from conclusion to original drawing” is supported on the front end or API side. For example, if the system outputs the conclusion “the upper and lower level protection action curves overlap at t=2.5s”, the playback function can show the specific curve image of the overlap interval, the involved protection device parameters, and the original annotations of both in the drawing. Through this playback mechanism, not only static evidence is provided, but also dynamic reasoning process visualization is provided, thereby greatly enhancing the transparency of the conclusion.

[0062] The report output is provided in a dual-channel form of machine-readable and engineering-readable, and all quantitative indicators and units are checked for consistency again at the export layer. On the one hand, the system generates machine-readable output files such as JSON, GraphML or CSV, and these results can be directly connected to third-party simulation software, monitoring platforms or operation and maintenance systems to realize automatic linkage; on the other hand, the system also generates engineering-readable reports such as PDF reports with text descriptions, charts and screenshot indexes or web interfaces. In these reports, each conclusion is accompanied by index information of the evidence chain, and users can quickly locate the relevant area of the original drawing by clicking or jumping, realizing seamless tracking from “conclusion” to “evidence”.

[0063] S9, incremental updating is performed; The input is the completion drawing, change order or field photo, the update is completed, and the difference report is generated to adapt to the frequent design modification, completion drawing supplement, operation field photo collection or change order revision and the like in the electrical engineering project.

[0064] When the completion drawing, change order or field photo is imported, the affected subgraph is located based on the unified identifier and geometric proximity, and only the representation reconstruction and operator recalculation of the subgraph are performed, the difference report is generated, and the difference result is written back to the multi-modal topology-semantic graph and drives the necessary secondary review.

[0065] Specifically, the UID (generated by multiple information such as project number, drawing number, page number, coordinate and timestamp) in the unified identifier space is used to compare new and old drawing data. Through the hash comparison of UID, the system can quickly identify which nodes or edges have been added, deleted or modified. For example, when a tie-in switch is added in the completion drawing, its UID does not exist in the set of old version drawings, so it is automatically determined as a new element. Similarly, when the nameplate parameter of a device is modified from 400A to 630A, the system will mark it as “modified” through the difference identification of the attribute domain. Through this mechanism, the system can quickly lock the difference area and avoid full graph recalculation.

[0066] At the subgraph reconstruction level, the strategy of “local positioning-local reconstruction” is adopted. That is, for the difference area identified to have changed, the system will extract the local subgraph in which it is located, including the devices, terminals, wires and logical relationships directly related to the area. Re-run the analysis, alignment and reasoning operators in this subgraph range to get the updated conclusions without global reconstruction of the entire topology graph. This not only significantly reduces the calculation cost, but also reduces the potential secondary conflicts caused by global reconstruction.

[0067] At the level of difference analysis and report, an automatic difference report is generated, detailing the added, deleted and modified nodes and edges, and explaining the impact of these differences on existing reasoning conclusions. For example, when an additional contact switch causes two circuits to be in parallel, the system will mark the change in the difference report that causes the selectivity of the protection to decrease, and give the corresponding evidence chain reference, so as to facilitate the review and decision of the engineering personnel. For minor differences that do not affect the global safety, the report will be marked as "low-risk update"; while for differences that may affect the integrity of the circuit or the logic of the protection, it will be marked as "high-risk update", and the output priority in the engineering report will be raised.

[0068] The method also exposes / import, / build_graph, / infer, / report, / diff and other idempotent APIs, supporting local / cloud hybrid deployment and GPU optional acceleration.

[0069] Among them, the / import interface is used for drawing import and standardized buffer processing, supporting multiple formats such as DWG, DXF, PDF, and scans; the / build_graph interface is responsible for calling multi-modal analysis, spatial alignment and mode loading, and finally generating a topology-semantic graph; the / infer interface triggers the execution of the reasoning operator library, and returns the review and diagnosis results; the / report interface outputs traceable evidence chains and engineering reports; the / diff interface is specifically used for difference analysis and version update. All interfaces adopt idempotent design to ensure that repeated calls will not introduce conflicts, and support seamless integration with existing CAD systems, engineering management platforms, and relay protection simulation software.

[0070] On the performance side, the target graphing time limit and single batch reasoning time limit are given for complex primary graphs with more than 2000 nodes, and pixel / physical dimension double threshold values are set for "alarm positioning error".

[0071] Specifically, in the graphing phase, the system parallelizes the calling of OCR, VLM and LLM, and introduces a graph partitioning mechanism, so that the overall graphing time is controlled within 120 seconds; in the reasoning execution phase, relying on the operator visualization mechanism, the execution time of typical tasks (such as circuit completeness review and protection selectivity coordination analysis) is controlled within 10 seconds; finally, in the alarm and report output phase, the evidence chain index and screenshot generation are optimized, so that the average response delay is controlled within sub-second, meeting the needs of interactive review.

[0072] At the same time, the pixel / physical dimensional double threshold of alarm positioning error is defined: the pixel error of the conclusion positioning on the drawing is less than 5 pixels, or less than 0.5 mm in actual size conversion. At the same time, the system will perform a global unit and dimensional consistency review when exporting the report to ensure that there is no numerical ambiguity. For example, whether the rated current field is “630A” or “0.63kA” in the original annotation, it will be uniformly converted and annotated during export to avoid misjudgment due to symbol confusion.

[0073] Embodiment two: Actual scene application example, automatic checking of city substation as-built drawing.

[0074] In a newly built 220kV substation project in a city, the design party provides a set of CAD format construction drawings. After the construction is completed, the supervision unit requires the submission of as-built drawings for consistency checking and acceptance. Since the as-built drawings come from multiple sources, including the DWG format primary wiring diagram, the PDF format construction change order, and the on-site photographed and uploaded grounding layout, if only relying on manual review, it not only takes a long time, but also is easy to miss and misjudge.

[0075] In the application process, first, all drawing files are accessed through step S1, and a unique UID is generated for each drawing to ensure version traceability; then in step S2, the VLM automatically detects the circuit breaker, disconnecting switch, CT / PT and other device symbols in the drawing, the OCR extracts the nameplate parameters and table data, and the LLM standardizes the parameter fields to form a candidate element set; then in step S3, the system uses constraints to align the contents of drawings from different sources to a unified identification space, realizing the multi-modal fusion of “symbol-text-parameter”.

[0076] In steps S4 and S5, the system gives each device node a strong type attribute, such as rated current, rated voltage, and protection curve family, and constructs a connected relationship in the topology-semantic graph. In step S6, due to the insufficient clarity of some scanned copies, the confidence of some parameters recognized by OCR is low, and the system propagates these uncertainties and marks the related alarms as gray-scale alarms to avoid false positives. In step S7, the reasoning operator library runs in turn: the loop completeness check finds that a certain outgoing line loop is missing the grounding knife switch interlocking logic; the dimensional consistency check detects that the nameplate current of a certain CT and the rated value unit of the upper circuit breaker are mixed (A and kA), and triggers a consistency alarm; the protection selectivity coordination analysis shows that the curves of two levels of relays overlap in a short period of time, and the time margin is less than 0.3 seconds, which has a coordination risk.

[0077] At step S8, the system generates an evidence chain for the above-mentioned alarm and directly attaches the original drawing fragment coordinates and annotated screenshots in the report. The supervisor can quickly jump to the corresponding drawing position for review by clicking the alarm item. At this time, the construction party submits a new change order, adding a contact switch. The system updates the incremental mechanism through step S9, only reconstructs and reasons the local subgraph where the contact switch is located, outputs the difference report, and points out that the added switch causes two loops in parallel, thereby reducing the protection selectivity.

[0078] Finally, the system exports a PDF engineering report and a JSON data file through the interface. The former is directly used as the supervision audit material, and the latter is imported into the power relay simulation software for further dynamic simulation analysis. The entire process from drawing import to report generation takes less than 5 minutes, which is more than 90% shorter than the traditional manual review, and significantly reduces the risk of missed detection.

[0079] Through the above actual application scenario, it can be seen that the present application can not only cope with multi-source drawing input and frequent version changes, but also provide quantifiable reasoning results and traceable evidence chains, greatly improving the automation level and engineering reliability of substation completion drawing checking and acceptance.

[0080] Embodiment Three The embodiment also provides a computer device suitable for the case of the large model reasoning representation method of the electrical drawing, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the large model reasoning representation method of the electrical drawing proposed in the above-mentioned embodiment.

[0081] The embodiment also provides a storage medium having a computer program stored thereon, and the program is executed by the processor to realize the large model reasoning representation method of the electrical drawing proposed in the above-mentioned embodiment.

[0082] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved by WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or can be a key, a trackball or a touchpad arranged on the shell of the computer device, or can be an external keyboard, a touchpad or a mouse, etc.

[0083] If the functions are implemented in the form of software function units and sold or used as independent products, the functions can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0084] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, which can be specifically embodied in any computer readable medium for use by or in conjunction with an instruction execution system, device or apparatus, such as a computer-based system, a system including a processor or other system that can fetch and execute instructions from the instruction execution system, device or apparatus. For the purpose of this specification, the "computer readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by or in conjunction with the instruction execution system, device or apparatus, or in conjunction with these instruction execution systems, devices or apparatus.

[0085] More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can also be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via an optical scanner, then compiled, interpreted, or otherwise processed, as necessary, and stored in a computer memory.

[0086] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the embodiments described above, various steps or methods can be implemented, for example, in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, and in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0087] It should be noted that the above examples are merely intended to illustrate the technical solutions of the present application and not to limit the same. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and all such modifications or replacements should be included in the scope of the claims of the present application.

Claims

1. A method of large model inference representation of electrical drawings, characterized by, Includes the following steps: S1. Multi-source drawing access and standardized input; Receive multi-source electrical drawings and transfer them uniformly into a standardized input buffer; S2, Multimodal analysis and initial feature extraction; The electrical drawings in the standardized input buffer are converted into structured information, and candidate elements are extracted and obtained. S3, Unified identifier spatial alignment and cross-modal registration; Align candidate elements to a unified identifier space quintuple and use a registration strategy for cross-modal registration. S4, loading strongly typed patterns and constrained languages; Load the strongly typed pattern of the electrical object and load the set of machine-readable constraint languages; S5. Construction of reasoning representation; A multimodal topology-semantic graph is constructed under the common constraints of aligned elements and patterns / constraints. S6. Uncertainty propagation and conflict classification and handling; Uncertainty is explicitly propagated on a multimodal topological-semantic graph, and conflict resolution is achieved by adopting a conservative conjunctive priority conflict classification approach. S7. Executable inference operator invocation and task orchestration; Operators are arranged in dependency order on the multimodal topological-semantic graph after conflict resolution; S8. Evidence chain generation, playback, and report output; Generate, replay, and output each verification / diagnosis conclusion generated by the inference operator; S9. Perform incremental update; Enter as-built drawings, change orders, or site photos to complete the update and generate a discrepancy report.

2. The method of claim 1, wherein, In step S2, multimodal analysis and initial feature extraction include: The visual language model is invoked in parallel at the unified inference entry point to perform geometric side analysis and extract graphic elements. Text-side analysis is performed using layout parsing and OCR to extract text-related elements; The language model is invoked to perform semantic parsing and extract semantic class elements. Graphical elements, textual elements, and semantic elements are considered as candidate elements. Each candidate element is assigned a recognition confidence component, and its original spatial information is preserved. The spatial information of the original image includes page numbers, bounding boxes, and coordinate systems.

3. The method of claim 2, wherein, The candidate elements include: Graphical elements include circuit breakers, disconnectors, busbars, grounding symbols, CTs / PTs, conductor segments, and arrows. Text-based elements include equipment name, model designation, parameter table, circuit number, and nameplate parameters; Semantic elements include device category, parameter meaning, and standardized name after alias aggregation.

4. The method of claim 1, wherein, In step S3, the unified identifier space quintuple for candidate feature alignment is shown below: in, for a device ID, for a terminal, for a wire segment ID, for a page number, for a position point or a bounding box in the page coordinate system; The registration strategy adopts the principles of prioritizing geometric constraints, corroborating semantic consistency, and conserving confidence through fusion: Geometrically, strong constraints are imposed on the connection endpoints—terminal adsorption and the lead arrow—text box pointing. Semantically, consistency is determined by the same pointing of the device name and adjacent label / table unit. The confidence components of each candidate element are integrated to form an ontology confidence label.

5. The method of claim 1, wherein, In step S4, the strong type mode includes entities and their field fields including Device, Terminal, Conductor, Relay, Measurement, Ground, and Loop, including rated voltage, current, insulation class, protection curve family and setting value range. Constraint language set Including the definition of unit conversion consistency, rated value interval, logic / interlock / lock constraint, upper / lower level protection matching relationship.

6. The method of claim 1, wherein, In step S5, the multimodal topology-semantic graph is shown below: wherein, is a multi-modal topology - semantic graph; is a set of nodes representing the set of devices / terminals / measurement points / protection devices; is a set of edges representing electrical connections, reference associations and logical relationships; is a set of constraint languages of strong typed patterns; Each node / edge also holds provenance references and evidence chains, graphs Executable views are also defined, including "loop_check", "selectivity", "dimension_check", so that subsequent executable inference operators can be called directly.

7. The method of claim 1, wherein, In step S7, after defining the executable view in the multi-modal topology-semantic graph, the operators are arranged in the executable view in the order of dependence, including: First, perform the "connected domain and loop completeness check"; Then, perform the "unit / dimension consistency and rated value cross-check"; After that, perform the "protection selection matching check, curve family / setpoint value" and "short circuit / ground path reachability analysis"; Finally, perform the "logic / interlocking / blocking consistency verification"; Each operator output structured results including conclusion labels, quantitative indicators, affected node / edge lists, and evidence chain reference sets to ensure engineering readability and automated integration.

8. The method of claim 1, wherein, In step S8, for each check / diagnostic conclusion, generate and solidify the evidence chain, including original drawing page number, coordinate / bounding box, text segment, and local screenshot index; support "from conclusion to original drawing" hop-by-hop playback on the front end or API side; report output is provided in the form of machine-readable and engineering-readable dual channels, and all quantitative indicators and units are checked again for consistency at the export layer.

9. The method of claim 1, wherein, In step S9, when importing the as-built drawing, change order, or field photo, based on the unified identification and geometric proximity, the affected subgraph is located, and only the subgraph is reconstructed and recalculated, a difference report is generated, and the difference result is written back to the multi-modal topology-semantic graph and driven to the necessary secondary check.

10. The method of claim 1, wherein, The method also exposes / import, / build_graph, / infer, / report, / diff, and other idempotent APIs, supports local / cloud hybrid deployment, and GPU optional acceleration; On the performance side, the target graphing time limit and single batch inference time limit are given for complex primary graphs with >2000 nodes, and pixel / physical dimension dual threshold values are set for "alarm positioning error".

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