A power amplifier with high dynamic linearity

Abstract

The application belongs to the field of radio frequency integrated circuits, and particularly relates to a high dynamic linearity power amplifier, which comprises a power amplifier tube HBT0, an input matching network, an output matching network, a radio frequency choke network and an active bias circuit, the base of the power amplifier tube HBT0 is connected with the input matching network and the active bias circuit, a radio frequency signal flows into the power amplifier tube HBT0 through the input matching network, the collector of the power amplifier tube HBT0 is connected with the radio frequency choke network and the output matching network, the other end of the radio frequency choke network is connected with a power supply VCC, the other end of the output matching network is connected with a radio frequency output port, and the active bias circuit is connected with the base of the power amplifier tube HBT0. The application can provide a compensation current to stabilize the bias offset of the power amplifier tube HBT0 under high power and improve the linearity under high power.

Description

Technical Field

[0001] This application belongs to the field of radio frequency integrated circuits, and specifically relates to a high dynamic linearity power amplifier. Background Technology

[0002] Power amplifiers are typically used in the output stage of radio frequency (RF) transceivers to amplify RF signals to a certain power before transmitting them via an antenna. With the development of communication systems, the modulation order of RF signals is constantly increasing to meet the demands of improved channel capacity. Higher modulation orders place greater demands on the linearity of power amplifiers. Power amplifiers are generally not continuously on during operation; instead, they operate intermittently according to the transmission / reception mode, and the operating time varies depending on the size of the transmitted data packets. Frequent switching on and off can lead to dynamic temperature variations and deterioration of the power amplifier's linearity, thus requiring more stringent control over its turn-on and temperature responses. Summary of the Invention

[0003] This application provides a power amplifier with high dynamic linearity, which solves the problems of insufficient thermal stability and deteriorated linearity of existing power amplifiers.

[0004] A high dynamic linearity power amplifier according to an embodiment of this application includes: a power amplifier transistor HBT0, an input matching network, an output matching network, an RF choke network, and an active bias circuit, wherein:

[0005] The base of the power amplifier transistor HBT0 is connected to the input matching network and the active bias circuit. The radio frequency signal flows into the power amplifier transistor HBT0 through the input matching network. The collector of the power amplifier transistor HBT0 is connected to the radio frequency choke network and the output matching network.

[0006] The other end of the RF choke network is connected to the power supply VCC;

[0007] The other end of the output matching network is connected to the RF output port to convert the port impedance to the load impedance required by the power amplifier tube HBT0.

[0008] The active bias circuit is connected to the base of the power amplifier transistor HBT0 to provide the bias current required by the power amplifier transistor HBT0.

[0009] Furthermore, a base resistor R0 is provided between the base of the power amplifier transistor HBT0 and the input matching network and active bias circuit. One end of the base resistor R0 is connected to the base of the power amplifier transistor HBT0, and the other end of the base resistor R0 is connected to the input matching network and active bias circuit.

[0010] Furthermore, the active bias circuit includes:

[0011] Transistor HBT1, whose collector is connected to power supply VCC, and the collectors of transistors HBT2 and HBT5, whose base is connected to the emitter of transistor HBT2, the collector of transistor HBT3, and the first end of resistor R1, whose other end is connected to the base of HBT3, whose emitter is connected to the emitter of transistor HBT1, and then connected together between the base resistor R0 and the input matching network;

[0012] Transistor HBT4, the base and collector of transistor HBT4 are connected to the base of transistor HBT2 and one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0013] Transistor HBT6, the collector of transistor HBT6 and one end of resistor R4, the emitter of transistor HBT4 is connected to the base of transistor HBT5, and the other end of resistor R4 is connected to the operating voltage VEN.

[0014] Transistor HBT5 has its emitter connected to one end of resistor R2, the other end of resistor R2 connected to the base of transistor HBT6 and one end of resistor R3, the other end of resistor R3 connected to ground. Transistor HBT6 has its emitter connected to ground.

[0015] Furthermore, the transistor HBT6 is positioned close to the power amplifier transistor HBT0.

[0016] Furthermore, as the temperature of power amplifier transistor HBT0 increases, the collector current of transistor HBT6 increases.

[0017] Furthermore, the transistor HBT3 is positioned close to the power amplifier transistor HBT0.

[0018] Compared with the prior art, the advantages of this application are as follows:

[0019] This application can provide a compensation current to stabilize the bias offset of the power amplifier tube HBT0 under high power conditions, thereby improving the linearity under high power. The base resistor R0 can greatly improve the thermal stability problem of the power amplifier tube HBT0 under high power due to the self-heating effect.

[0020] This application can compensate for the decrease in current and gain caused by the heat generated by the power amplifier tube HBT0 due to long-term high-power operation, and improve the dynamic linearity of the power amplifier tube when processing large data packets.

[0021] This application improves the response speed of the bias circuit to provide a stable current to the power amplifier transistor after the operating voltage VEN is given, thereby improving the dynamic linearity of the power amplifier transistor HBT0 when it is in a sudden on and off state. Attached Figure Description

[0022] Figure 1 A circuit schematic diagram of a high dynamic linearity power amplifier provided in an embodiment of this application;

[0023] Figure 2 The circuit schematic of the equivalent transistor circuit provided in the embodiments of this application;

[0024] Figure 3 The circuit schematic of the matching network provided in the embodiments of this application;

[0025] Figure 4 This application provides the gain change within 10ms relative to 5ms in the embodiments of the present application;

[0026] Figure 5 The gain change within 200µs relative to 200µs provided in this application embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] See Figure 1 As shown, this embodiment of the invention provides a high dynamic linearity power amplifier, including a power amplifier transistor HBT0, an input matching network, an output matching network, an RF choke network, a base resistor R0, and an active bias circuit, wherein:

[0029] The base of power amplifier transistor HBT0 is connected to base resistor R0. The other end of resistor R0 is connected to the input matching network and the active bias circuit. The RF signal flows into power amplifier transistor HBT0 through the input matching network. The collector of power amplifier transistor HBT0 is connected to the RF choke network and the output matching network.

[0030] The other end of the RF choke network is connected to the power supply VCC to provide a clean operating voltage to the collector of the power amplifier transistor HBT0 and to prevent RF signals from leaking into the power supply.

[0031] The other end of the output matching network is connected to the RF output port to convert the port impedance to the load impedance required by the power amplifier tube HBT0.

[0032] The active bias circuit is connected to the base of the power amplifier transistor HBT0 to provide the bias current required by the power amplifier transistor.

[0033] The active bias circuit includes transistors HBT1, HBT2, and HBT3, resistor R1, capacitor C1, transistors HBT4 and HBT5, resistors R2, R3, and R4, and transistor HBT6. The collector of transistor HBT1 is connected to the power supply VCC, and to the collectors of transistors HBT2 and HBT5. The base of transistor HBT1 is connected to the emitter of transistor HBT2, the collector of transistor HBT3, and one end of resistor R1. The other end of resistor R1 is connected to the base of HBT3. The emitter of transistor HBT3 is connected to the emitter of transistor HBT1, and then both are connected between resistor R0 and the input matching network. The base and collector of transistor HBT4 are connected to the base of transistor HBT2 and one end of capacitor C1. The other end of capacitor C1 is grounded. The collector of transistor HBT6 is connected to one end of resistor R4. The emitter of transistor HBT4 is connected to the base of transistor HBT5. The other end of resistor R4 is connected to the operating voltage VEN. The emitter of transistor HBT5 is connected to one end of resistor R2. The other end of resistor R2 is connected to the base of transistor HBT6 and one end of resistor R3. The other end of resistor R3 is connected to ground. The emitter of transistor HBT6 is connected to ground.

[0034] The following is combined with Figure 1 The working principle of the circuit of this invention will be described as follows:

[0035] The input matching network transforms the input impedance of the transistor, allowing the RF signal to flow into the power amplifier transistor HBT0. The output matching network converts the impedance of the RF output load port to the impedance value required for the power amplifier transistor HBT0 to output a certain power. After being amplified by the power amplifier transistor HBT0, the RF signal flows into the load port through the output matching network. The RF choke network ensures the voltage required for the normal amplification of the RF amplifier transistor HBT0 while preventing the RF signal from flowing into the power supply VCC.

[0036] When the input signal increases, the signal flowing into the active bias circuit also increases. Due to the rectification effect of the base-collector diodes of transistors HBT1 and HBT3, the collector currents of transistors HBT1 and HBT3 increase, thereby compensating for the base current required by power amplifier transistor HBT0 when outputting high power. This effectively solves the gain compression problem of power amplifier transistor HBT0 under large signal operating conditions and improves the linearity under large signal conditions. Capacitor C1 in the active bias circuit reduces the impedance of the active bias circuit, increasing the RF signal flowing into transistor HBT1 and further enhancing the current compensation capability of the active bias circuit.

[0037] When the operating temperature of a power amplifier increases, or when the power amplifier heats up due to heat dissipation limitations, the large current generated by the power amplifier transistor HBT0 causes its own temperature to rise rapidly. The increased ambient temperature further increases the current in HBT0, leading to transistor instability. In the active bias circuit, transistor HBT6 is placed near HBT0; "near" refers to a range of a few micrometers to tens of micrometers from HBT0, and this distance affects the intensity of thermal induction. The heating of HBT0 causes an increase in the collector current of HBT6. This increase in collector current, under the influence of resistor R4, leads to a decrease in the base voltage of transistors HBT2 and HBT4, thereby reducing the collector current of HBT2, HBT4, and HBT5. The decrease in the current of HBT2 leads to a decrease in the current of transistors HBT1 and HBT3, thus mitigating the thermal instability problem of HBT0 due to self-heating at high temperatures.

[0038] When the area of ​​power amplifier transistor HBT0 is particularly large or multiple transistors are connected in parallel, the thermal change of transistor HBT6 may differ significantly from that of power amplifier transistor HBT0. This can lead to insufficient temperature compensation in the active bias circuit. The decrease in current of transistor HBT5, under the influence of resistor R3, will lower the base-emitter voltage of transistor HBT6, enhancing the thermal-electric feedback and further improving the compensation effect of the active bias circuit under different temperatures.

[0039] When the power amplifier is switched on and off frequently, the thermal induction of transistor HBT6 may not keep up with the temperature changes of power amplifier transistor HBT0, resulting in untimely temperature compensation of the active bias circuit. The circuit structure of this application enables rapid compensation, employing methods such as... Figure 2 The equivalent transistor circuit shown is used to illustrate the effects of this application. In the active bias circuit, transistors HBT1, HBT2, and HBT3, and resistor R1 can be equivalent to a single transistor. The base B of the equivalent transistor is the base of transistor HBT2, the collector C is the collector of both transistors HBT2 and HBT1, and the emitter E is the emitter of both transistors HBT1 and HBT3. This is the equivalent base resistance. This is the equivalent base-collector capacitance. This is the equivalent base-emitter parallel resistance. The equivalent output resistance, This is the equivalent base input capacitor. This represents the equivalent transconductance. The emitter of transistor HBT2 and the base of transistor HBT1 are connected in series, which effectively reduces the equivalent base input capacitance of the three transistors. This significantly reduces the carrier transit time and simultaneously decreases the capacitance. The capacitor charging and discharging delay caused by this, and the current amplification capability of the equivalent transistor is greatly enhanced, so that the electro-thermal changes sensed by transistor HBT6 are transmitted to power amplifier transistor HBT0 more quickly, improving the response speed of the power amplifier, thereby improving the dynamic linearity of the power amplifier during rapid turn-on and turn-off.

[0040] When a power amplifier transmits large data packets, its on-time is relatively long. The continuous heat buildup causes a decrease in the current output from the active bias circuit to the power amplifier transistor HBT0. This leads to a change in the power amplifier's gain over time, thus deteriorating its linearity during prolonged operation. In the active bias circuit, transistor HBT3 is placed near power amplifier transistor HBT0. When the power amplifier operates for extended periods and generates heat, transistor HBT3 is affected by the high temperature, increasing its current. This compensates for the base current of power amplifier transistor HBT0 during long-term operation, mitigating the decrease in power amplifier gain over time and improving the dynamic linearity of the power amplifier during extended operation.

[0041] Figure 3 This is a circuit schematic of a specific example of the RF choke network, input matching network, and output matching network described in this application. When the power amplifier transistor HBT0 is a multi-stage amplifier, an inter-stage matching network is also required, which serves as the output matching network of the previous stage and the input matching network of the next stage. In one example, the input matching network includes an inductor L1, a capacitor C11, and a harmonic control network composed of an inductor Lf1 and a capacitor Cf1. The first end of the inductor L1 is connected to the first end of the capacitor C11, and the second end of the inductor L1 is grounded. The inductor Lf1 and the capacitor Cf1 are connected in series, with one end grounded and the other end connected to the first end of the capacitor C1. The values ​​of the inductor Lf1 and the capacitor Cf1 are chosen to ensure that the network resonates at the second harmonic frequency, so that the series connection of the inductor Lf1 and the capacitor Cf1 leads to ground, resulting in low impedance at the second harmonic frequency, thus filtering out the second harmonic. Inductor L1 and capacitor C11 form an LC matching network to match the impedance to the source impedance point required by the power amplifier transistor HBT0. The second end of capacitor C11 is connected to the base of the power amplifier transistor T1 in the previous stage.

[0042] In one example, the interstage matching network includes capacitors C12 and C13, and the harmonic suppression network consists of inductor Lf2 and capacitor Cf2 connected in series to ground. The first terminal of capacitor C12 is connected to the collector of the power amplifier transistor T1 in the preceding stage. The second terminal of capacitor C12 is connected to one end of the series-connected inductor Lf2 and capacitor Cf2, and also to the first terminal of capacitor C13. When the power amplifier transistor HBT0 consists of multiple transistors connected in parallel, capacitor C13 can be a capacitor connected from the junction of capacitor C12 and the harmonic suppression branch to the base of each transistor. The path of inductor Lf1 and capacitor Cf1 to ground resonates at the second harmonic, resulting in low impedance and filtering out the second harmonic. Capacitors C12 and C13 form a matching network to match the required load impedance of the power amplifier transistor T1 in the pre-amplifier stage and the required source impedance of the power amplifier transistor T2 in the post-amplifier stage. They also act as DC blocking capacitors. The power amplifier transistors T1 and T2 in the pre-amplifier stage form power amplifier transistor HBT0. The second terminal of capacitor C13 is connected to the base of the power amplifier transistor T2. The emitters of both power amplifier transistors T1 and T2 are grounded.

[0043] In one example, the output matching network includes a ground capacitor C14, a DC blocking capacitor C15, and a ground inductor L2. The first terminal of the ground capacitor C14 is connected to the collector of the power amplifier transistor T2 in the subsequent stage, and the second terminal of the ground capacitor C14 is grounded. The first terminal of the DC blocking capacitor C15 is connected to the collector of the power amplifier transistor T2 in the subsequent stage. The inductor Lf3 and capacitor Cf3 connected in series to ground form branch one of the harmonic suppression network. One end of branch one is grounded, and the other end is connected to the collector of the power amplifier transistor T2 in the subsequent stage. The inductor Lf4 and capacitor Cf4 connected in parallel form branch two of the harmonic suppression network. The first terminal of branch two is connected to the second terminal of the DC blocking capacitor C15, and the second terminal of branch two is connected to the RF output. The inductor Lf3 and capacitor Cf3, connected to ground, resonate in series at the second harmonic, resulting in low impedance and filtering out the second harmonic. The inductor Lf4 and capacitor Cf4 are connected in parallel to ground at the second harmonic, which resonates as a high impedance, blocking the second harmonic component in the RF signal from being output to the RF output port, thus further filtering out the second harmonic.

[0044] The RF choke network is connected in the form of an inductor between the collector of the power amplifier transistor HBT0 and the power supply VCC.

[0045] like Figure 4 As shown, this application shows the gain change within 10ms relative to 5ms. Figure 5 The figure shows the gain change within 200µs relative to 200µs in this application. It can be seen that the high dynamic linearity power amplifier of this embodiment maintains stable gain in both 10ms and 200µs operating states.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A power amplifier with high dynamic linearity, characterized in that, include: The power amplifier transistor HBT0, input matching network, output matching network, RF choke network, and active bias circuit include: The base of the power amplifier transistor HBT0 is connected to the input matching network and the active bias circuit. The radio frequency signal flows into the power amplifier transistor HBT0 through the input matching network. The collector of the power amplifier transistor HBT0 is connected to the radio frequency choke network and the output matching network. The other end of the RF choke network is connected to the power supply VCC; The other end of the output matching network is connected to the RF output port to convert the port impedance to the load impedance required by the power amplifier tube HBT0. The active bias circuit is connected to the base of the power amplifier transistor HBT0 to provide the bias current required by the power amplifier transistor HBT0. A base resistor R0 is set between the base of the power amplifier transistor HBT0 and the input matching network and active bias circuit. One end of the base resistor R0 is connected to the base of the power amplifier transistor HBT0, and the other end of the base resistor R0 is connected to the input matching network and active bias circuit. The active bias circuit includes: Transistor HBT1 has its collector connected to power supply VCC, the collectors of transistors HBT2 and HBT5, and its base connected to the emitter of transistor HBT2, the collector of transistor HBT3, and the first end of resistor R1. The other end of resistor R1 is connected to the base of HBT3, and the emitter of transistor HBT3 is connected to the emitter of transistor HBT1. They are then connected together between the base resistor R0 and the input matching network. Transistor HBT4, the base and collector of transistor HBT4 are connected to the base of transistor HBT2 and one end of capacitor C1, and the other end of capacitor C1 is grounded. Transistor HBT6, the collector of transistor HBT6 is connected to one end of resistor R4, the emitter of transistor HBT4 is connected to the base of transistor HBT5, and the other end of resistor R4 is connected to the operating voltage VEN. Transistor HBT5, the emitter of transistor HBT5 is connected to one end of resistor R2, the other end of resistor R2 is connected to the base of transistor HBT6 and one end of resistor R3, the other end of resistor R3 is connected to ground, and the emitter of transistor HBT6 is connected to ground.

2. The power amplifier with high dynamic linearity according to claim 1, characterized in that, The transistor HBT6 is placed close to the power amplifier transistor HBT0.

3. A power amplifier with high dynamic linearity according to claim 2, characterized in that, When the temperature of power amplifier transistor HBT0 increases, the collector current of transistor HBT6 increases.

4. A power amplifier with high dynamic linearity according to claim 1, characterized in that, The transistor HBT3 is placed close to the power amplifier transistor HBT0.

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