Wiring methods, devices, storage media and chips
By employing a differentiated trace widening strategy, excessively long and narrow traces in integrated circuit chips are widened in a targeted manner, solving the problem of low power supply voltage in some voltage domains and improving the voltage domain voltage value and overall performance of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-30
AI Technical Summary
In integrated circuit chip design, if the supply voltage of some voltage domains is lower than the threshold required for normal circuit operation, it will lead to unstable performance of components and abnormal power consumption, affecting the overall performance of the chip.
A differentiated trace widening strategy is adopted. Based on the voltage value differences in different voltage domains, excessively long and narrow traces are widened in a targeted manner. By obtaining the preset routing layout, trace widening rules and routing layout constraint rules, iterative verification is carried out to ensure that the widened traces meet the process design requirements.
By widening the traces through differentiation, the resistance of excessively long and narrow traces was reduced, voltage drop loss and heat generation issues were corrected, the actual voltage value in the voltage domain was increased, and the overall performance of the chip was improved.
Smart Images
Figure CN121706718B_ABST
Abstract
Description
Technical Field
[0001] The embodiments in this application relate to the field of chip design and manufacturing technology, specifically to a wiring method, apparatus, storage medium, and chip. Background Technology
[0002] In integrated circuit chip design, power networks provide stable voltages to areas or modules within the chip, such as logic components, memory modules, and input / output interfaces, via traces. Specifically, to improve overall chip performance, these areas or modules within the chip may be divided into multiple voltage domains, and the power network supplies power to one or more voltage domains through multiple stacked conductive layers with distributed traces.
[0003] As integrated circuit process nodes continue to shrink, it has been found in the actual chip design process that the voltage value of the voltage domain powered by some traces is lower than the threshold required for normal circuit operation. Summary of the Invention
[0004] In view of this, several embodiments of this application provide a wiring method, apparatus, device, medium, program product, and chip to improve the voltage of a voltage domain powered by a portion of the traces.
[0005] In one aspect, an embodiment of this application provides a routing method, the routing method comprising: obtaining a preset routing layout corresponding to each voltage domain, a trace widening rule, and a routing layout constraint rule; wherein, the trace widening rule includes a trace widening width; the trace widening width increases with the increase of the voltage value of the voltage domain corresponding to the trace widening rule; if there is a target trace in the preset routing layout that satisfies the trace screening conditions corresponding to the voltage domain corresponding to the preset routing layout, the target trace is widened according to the trace widening rule corresponding to the voltage domain corresponding to the preset routing layout to obtain a widened routing layout; wherein, the trace screening conditions include a trace length greater than a length threshold and a trace width less than a width threshold; the widened routing layout is iteratively verified based on the routing layout constraint rule, and the widened routing layout that passes the verification is taken as the target routing layout.
[0006] Optionally, the wiring method is used to configure a chip; the chip includes at least two conductive layers that are electrically connected; obtaining a preset wiring layout corresponding to each voltage domain includes: identifying all voltage domains in the chip based on voltage domain labels; and determining the preset wiring layout on all conductive layers belonging to any voltage domain based on line connection relationships.
[0007] Optionally, the step of iteratively verifying the widened routing layout based on the routing layout constraint rules and using the verified widened routing layout as the target routing layout includes: determining the routing layout constraint rules corresponding to the conductive layer corresponding to the widened routing layout according to the minimum trace width requirement, minimum trace spacing requirement, and trace density requirement of the conductive layer corresponding to the widened routing layout; verifying the widened routing layout based on the routing layout constraint rules; and using the widened routing layout as the target routing layout if the widened routing layout passes the verification.
[0008] Optionally, the step of iteratively verifying the widened routing layout based on the routing layout constraint rules and using the verified widened routing layout as the target routing layout further includes: if the widened routing layout fails verification, repeating the following sub-steps until the widened routing layout passes verification; the sub-steps include: obtaining the routing back-off rules corresponding to the conductive layer corresponding to the widened routing layout; determining abnormal routings in the widened routing layout that do not conform to the routing layout constraint rules based on the routing layout constraint rules; performing back-off processing on the abnormal routings based on the routing back-off rules; updating the widened routing layout, and verifying the updated widened routing layout based on the routing layout constraint rules.
[0009] Optionally, obtaining the trace widening rules for each voltage domain includes: for any voltage domain, determining the category of the voltage domain according to the voltage domain classification rules; wherein the voltage domain classification rules are used to indicate the voltage value range corresponding to different categories of voltage domains; and determining the trace widening reference and the trace widening width corresponding to the voltage domain according to the category of the voltage domain, thereby obtaining the trace widening rules corresponding to the voltage domain.
[0010] Optionally, the voltage domain categories include low-voltage domain, medium-voltage domain, and high-voltage domain; the trace width widening range corresponding to the low-voltage domain is not less than 0.5 times the reference width widening range and less than 1.5 times the reference width widening range; the trace width widening range corresponding to the medium-voltage domain is not less than 1.5 times the reference width widening range and less than 2.5 times the reference width widening range; the trace width widening range corresponding to the high-voltage domain is not less than 2.5 times the reference width widening range and less than 3.5 times the reference width widening range.
[0011] Optionally, in addition to the first screening sub-condition that the trace length is greater than a length threshold and the trace width is less than a width threshold, the trace screening condition also includes a second screening sub-condition determined according to the minimum trace width requirement and minimum trace spacing requirement of the voltage domain corresponding to the preset routing layout; the routing method further includes: screening the traces in the preset routing layout based on the first screening sub-condition corresponding to the voltage domain corresponding to the preset routing layout, and determining the traces that meet the first screening sub-condition as candidate traces; screening the candidate traces based on the second screening sub-condition corresponding to the voltage domain corresponding to the preset routing layout, and determining the traces that meet the second screening sub-condition as target traces.
[0012] In another aspect, one embodiment of this application provides a routing apparatus, the routing apparatus comprising: an acquisition module, configured to acquire a preset routing layout, trace widening rules, and routing layout constraint rules corresponding to each voltage domain; wherein the trace widening rule includes a trace widening width; the trace widening width increases with the increase of the voltage value of the voltage domain corresponding to the trace widening rule; a widening processing module, configured to, when there is a target trace in the preset routing layout that satisfies the trace screening conditions corresponding to the voltage domain corresponding to the preset routing layout, widen the target trace according to the trace widening rules corresponding to the voltage domain corresponding to the preset routing layout to obtain a widened routing layout; wherein the trace screening conditions include a trace length greater than a length threshold and a trace width less than a width threshold; and a verification module, configured to iteratively verify the widened routing layout based on the routing layout constraint rules, and take the widened routing layout that passes the verification as the target routing layout.
[0013] In another aspect, one embodiment of this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the wiring method as described in the above embodiments.
[0014] In another aspect, one embodiment of this application provides a chip whose wiring is configured according to the wiring method described in the above embodiments or according to a target wiring layout provided by the wiring apparatus described in the above embodiments.
[0015] In several embodiments provided in this application, by obtaining preset routing layouts, trace widening rules, and routing layout constraint rules corresponding to each voltage domain, wherein the trace widening rule includes a trace widening width, the trace widening width increases with the increase of the voltage value of the voltage domain, and when there is a target trace in the preset routing layout that satisfies the condition that the trace length is greater than the length threshold and the trace width is less than the width threshold, the target trace is widened according to the trace widening rule corresponding to the voltage domain to obtain a widened routing layout, and then the widened routing layout is iteratively verified based on the routing layout constraint rules, and the widened routing layout that passes the verification is output as the target routing layout, the unexpected effects achieved include: widening and adjusting excessively long and narrow traces by using differentiated trace widening rules corresponding to different voltage domains, and making the target routing layout meet the process design requirements of the routing layout through iterative verification, thereby correcting the voltage drop loss caused by the excessive resistance of excessively long and narrow traces, and improving the actual voltage value of the voltage domain powered by excessively long and narrow traces. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic diagram of excessively long and narrow traces provided for related technologies.
[0018] Figure 2 This is a flowchart illustrating the wiring method provided in an embodiment of this application.
[0019] Figure 3 This is a schematic diagram illustrating the process of obtaining preset wiring layouts corresponding to each voltage domain, as provided in an embodiment of this application.
[0020] Figure 4 This is a flowchart illustrating the process of obtaining trace widening rules for each voltage domain, as provided in an embodiment of this application.
[0021] Figure 5 This is a schematic diagram illustrating the iterative verification of a widened routing layout based on routing layout constraint rules, as provided in an embodiment of this application. Figure 5 (a) is a schematic diagram showing the relative positional relationship between the target trace and other traces in the preset routing layout provided in the embodiments of this application; Figure 5 (b) is a schematic diagram of widening the target trace according to an embodiment of this application; Figure 5 (c) is a schematic diagram of the process of returning abnormal traces provided in the embodiment of this application.
[0022] Figure 6 This is a schematic diagram of a wiring device provided in an embodiment of this application. Detailed Implementation
[0023] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0024] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.
[0025] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.
[0026] To adapt to the increasing complexity of integrated circuits and the trend towards more refined power management, the need for coordinated design of power networks, power domains, and voltage domains within chips is becoming increasingly significant. The power network is responsible for providing power to various functional modules within the chip; the power domain manages power distribution, circuit switching, and voltage adjustment; and the voltage domain translates the logical functional requirements of different modules into specific voltage management strategies, defining the supply voltage level for specific circuit regions. Voltage supply paths are formed between the power network, power domain, and voltage domain through wiring. However, researchers, during testing of chips using related technologies, discovered that the supply voltage to some voltage domains is lower than the threshold voltage required for normal circuit operation. This leads to unstable component performance and abnormal power consumption, ultimately affecting the overall chip performance.
[0027] An investigation into the reasons for the low supply voltage in certain voltage domains of chips provided by related technologies reveals that these chips typically employ static routing rules to design traces corresponding to different voltage domains. Taking a wireless communication chip as an example, the operating voltage of the digital baseband module may be as low as 0.8V, while the voltage domain of the RF front-end module needs to be maintained at around 1.8V. In wireless communication chips designed using static routing rules, the trace widths for supplying power to the digital baseband module voltage domain and the RF front-end module voltage domain are the same.
[0028] Please see Figure 1 The traces are connected to the positive power supply (Voltage Drain, VDD) and supply power to different voltage domains through the traces. When the traces are too long and too narrow, their resistance is high, leading to a high resistive voltage drop (IR Drop). This causes the actual voltage value of the voltage domain supplied by the trace to fall below the operating voltage threshold of the voltage domain, resulting in performance degradation of various functional devices or modules within that voltage domain. Furthermore, high trace resistance can also cause excessive heat generation, leading to a decrease in chip reliability.
[0029] To address the issue of insufficient supply voltage for certain voltage domains in chips provided by related technologies, researchers attempted to employ a uniform trace widening strategy to widen excessively long and narrow traces. Specifically, the width of excessively long traces across all voltage domains was increased by the same amount. However, this uniform trace widening strategy, without distinguishing voltage gradients across different voltage domains, may lead to resource waste and signal degradation in lower voltage domains, while potentially exacerbating resistor voltage drops in higher voltage domains. This could pose reliability risks to some components and cause system-level imbalances in the power network.
[0030] Therefore, it is necessary to provide a routing method that, after widening excessively long and narrow traces corresponding to different voltage domains, improves the overall chip performance while ensuring that the supply voltage for all voltage domains reaches the operating voltage of the voltage domain.
[0031] Please see Figure 2 One embodiment of this application provides a wiring method for configuring a chip. The chip may include at least two electrically connected conductive layers. Each conductive layer and the traces distributed on the conductive layers may be made of a conductive metal such as aluminum (Al) or copper (Cu). The wiring method may include steps S110, S120, and S130.
[0032] S110: Obtain the preset routing layout, trace widening rules, and routing layout constraint rules for each voltage domain.
[0033] Since the current carrying capacity, design power consumption, and conductive layer thickness of the trace distribution may differ for voltage domains with different operating voltage values, in order to solve the problem caused by using a uniform trace widening strategy to widen excessively long and narrow traces in related technologies, the R&D personnel adopted a differentiated trace widening strategy for voltage domains with different operating voltage values. They obtained the preset routing layout and trace widening rules for each voltage domain, so as to perform targeted widening of excessively long and narrow traces according to the operating voltage value of the voltage domain, thereby reducing the trace resistance of excessively long and narrow traces.
[0034] In this embodiment, a voltage domain can be a logic functional area within the chip that has the same supply voltage. Specifically, the division of voltage domains can be based on functional module requirements, thereby realizing a multi-voltage domain architecture for the chip and optimizing chip power consumption and performance. Differences in the supply voltage values of different voltage domains may directly affect the routing strategy and electrical characteristics of the power network.
[0035] In this embodiment, the preset routing layout can be a completed physical layout design of the traces. Specifically, the preset routing layout can be used to define the position, shape, size of the traces on the conductive layers in the chip, as well as the components or other conductive layers connected by the traces. For example, the preset routing layout can be stored in the standard binary file (Graphic Data System, GDS) format used for integrated circuit layout design.
[0036] In this embodiment, trace widening rules can be used to determine the trace width adjustment specifications for each voltage domain. Specifically, trace widening rules can include trace widening width. The trace widening width can define the range within which the trace is widened. The trace widening width can increase as the required supply voltage value of the voltage domain corresponding to the trace increases, to adapt to the current carrying capacity requirements of different voltage domains and compensate for the higher current density and resistance voltage drop risks in higher voltage domains.
[0037] In this embodiment, routing layout constraints can be used to verify the physical feasibility and electrical reliability of the routing layout. Specifically, routing layout constraints can correspond to each conductive layer in each voltage domain. Routing layout constraints can be a combination of Design Rule Check (DRC) and Electrical Rule Check (ERC). Routing layout constraints can be determined based on design and process requirements such as minimum trace width requirements, minimum trace spacing requirements, maximum resistance voltage drop tolerance, and electromigration safety threshold at different process nodes. For example, at the 28nm process node, routing layout constraints may require a minimum trace width of no less than 0.18μm and a minimum trace spacing of greater than 0.25μm to reduce short circuits and noise interference during signal transmission.
[0038] In this embodiment, the preset routing layout, trace widening rules, and routing layout constraint rules corresponding to each voltage domain are obtained by extracting data containing preset routing layout information, trace widening rule information, and routing layout constraint rule information from an integrated circuit design database, and establishing the association between this data and each voltage domain or conductive layer in the voltage domain. For example, electronic design automation (EDA) tools can be used to read the preset routing layout file, trace widening rule data, and routing layout constraint rule data stored in a computer-readable medium, and identify and load the dependency relationship between the preset routing layout file and the conductive layer in each voltage domain, the correspondence between the trace widening rule data and each voltage domain, and the correspondence between the routing layout constraint rule data and each conductive layer in each voltage domain.
[0039] Please see Figure 3 To simplify the process of obtaining preset wiring layout information, in some embodiments, obtaining the preset wiring layout corresponding to each voltage domain may include sub-steps S111 and S112.
[0040] S111: Identifies all voltage domains in the chip based on voltage domain tags.
[0041] In this embodiment, voltage domain labels can be used to identify voltage domains. Specifically, in electronic design automation tools, voltage domain labels can be predefined string identifiers, and a unique voltage domain label can be assigned to each voltage domain using the "Label" command.
[0042] In this embodiment, identifying all voltage domains in the chip can be achieved by scanning the chip to locate all mutually isolated voltage domains. Specifically, voltage domain identification can be achieved by relying on the hierarchical structure of voltage domain labels to reduce the omission of voltage domains.
[0043] S112: Determine the preset wiring layout on all conductive layers belonging to any voltage domain based on the line connection relationship.
[0044] In this embodiment, the line connection relationship can include node connections and stacked paths in the line network topology. Specifically, in electronic design automation tools, the coordinates of the trace endpoints in each conductive layer and the stacking continuity between different conductive layers can be verified using the "Connect" command, achieving open circuits at voltage domain boundaries.
[0045] Since the preset wiring layouts on different conductive layers may be different, in this embodiment, the preset wiring layouts on all conductive layers belonging to any voltage domain can be determined by first analyzing the electrical connectivity between different conductive layers to determine the physical coverage of a voltage domain, and then determining all preset wiring layouts corresponding to a voltage domain based on the dependency relationship between the preset wiring layouts and the conductive layers in each voltage domain.
[0046] Please see Figure 4 To simplify the process of obtaining trace widening rule information, in some embodiments, obtaining trace widening rules corresponding to each voltage domain may include sub-steps S113 and S114.
[0047] S113: For any voltage domain, determine the category of the voltage domain according to the voltage domain classification rules.
[0048] In this embodiment, voltage domain classification rules can be used to indicate the voltage value range corresponding to different categories of voltage domains. Specifically, voltage domain classification rules can be determined based on process node requirements and the power supply needs of different functional modules in the chip. For example, voltage domain classification rules can be determined based on the difference in the voltage value range of the required supply voltage or operating voltage for different voltage domains. The categories of voltage domains can include low-voltage domains, medium-voltage domains, and high-voltage domains. Taking the 28nm process node as an example, the voltage value range of the low-voltage domain can be less than or equal to 0.8V, the voltage value range of the medium-voltage domain can be greater than 0.8V and less than or equal to 1.2V, and the voltage value range of the high-voltage domain can be greater than 1.2V.
[0049] S114: Based on the voltage domain category, determine the trace widening reference and trace widening width corresponding to the voltage domain, and obtain the trace widening rules corresponding to the voltage domain.
[0050] In this embodiment, the trace widening reference can be defined as a baseline for widening the trace. Specifically, the trace widening reference can be the same for traces corresponding to different voltage domains. For example, when the trace widening reference is the trace centerline, the trace widening can be performed along the direction from the trace centerline to the trace edge.
[0051] To save chip area and conductive layer resources while reducing trace resistance, in this embodiment, the trace widening width range corresponding to different voltage domains can be different multiples of the reference widening width. Specifically, the reference widening width can be a standardized width increment value. More specifically, the reference widening width can be set based on the minimum trace width corresponding to the process node. For example, at a 28nm process node, the reference widening width can be 0.1μm.
[0052] In this embodiment, the trace width widening range corresponding to the low-voltage domain can be no less than 0.5 times the reference widening width and no more than 1.5 times the reference widening width. For example, the trace width widening range corresponding to the low-voltage domain can be 0.5 times, 1 time, or 1.4 times the reference widening width. The trace width widening range corresponding to the medium-voltage domain can be no less than 1.5 times the reference widening width and no more than 2.5 times the reference widening width. For example, the trace width widening range corresponding to the medium-voltage domain can be 1.5 times, 2 times, or 2.4 times the reference widening width. The trace width widening range corresponding to the high-voltage domain can be no less than 2.5 times the reference widening width and no more than 3.5 times the reference widening width. For example, the trace width widening range corresponding to the high-voltage domain can be 2.5 times, 3 times, or 3.4 times the reference widening width.
[0053] S120: If there is a target trace in the preset routing layout that meets the trace selection conditions corresponding to the voltage domain of the preset routing layout, the target trace is widened according to the trace widening rules corresponding to the voltage domain of the preset routing layout to obtain a widened routing layout.
[0054] To improve the targeting of trace widening processing, trace selection conditions can correspond to voltage domains. This allows for differentiated widening processing of traces in different voltage domains based on preset routing layouts and the correspondence between trace selection conditions and voltage domains.
[0055] In this embodiment, the routing screening conditions can be used to identify target routings that need to be widened from a preset routing layout. Specifically, to reduce the negative impact of widening the target routings on the functionality of other routings, the routing screening conditions can include a first screening sub-condition and a second screening sub-condition. The first and second screening sub-conditions can correspond to voltage domains, respectively. The first screening sub-condition can be that the routing length is greater than a length threshold and the routing width is less than a width threshold, thereby screening out routings that may generate large resistance voltage drops based on the geometric characteristics of the routings. The length and width thresholds can be determined according to the process node and voltage domain characteristics. For example, at a 28nm process node, the length threshold for the high-voltage domain can be 100μm, and the width threshold can be 0.5μm. The second screening sub-condition can be determined according to the minimum routing width requirement and minimum routing spacing requirement of the voltage domain corresponding to the preset routing layout, so as to perform refined screening of routings that meet the first screening sub-condition based on process constraints, reducing routing failures caused by widening. The minimum routing width requirement can be the minimum allowable routing width of the voltage domain corresponding to the preset routing layout. The minimum trace width requirement can be determined by both the electromigration safety threshold and the process resolution. The minimum trace spacing requirement can be defined as the minimum isolation distance that must be maintained between adjacent traces. The minimum trace spacing requirement can be used to control parasitic capacitance and short-circuit risk.
[0056] In this embodiment, the widened routing layout can be a transitional routing layout generated through widening processing. Specifically, the widened routing layout retains the topology structure in the preset routing layout and optimizes the width parameters of some traces.
[0057] Accordingly, in some embodiments, the routing method may further include: filtering the traces in the preset routing layout based on a first screening sub-condition corresponding to the voltage domain corresponding to the preset routing layout, and determining the traces that meet the first screening sub-condition as candidate traces; filtering the candidate traces based on a second screening sub-condition corresponding to the voltage domain corresponding to the preset routing layout, and determining the traces that meet the second screening sub-condition as target traces.
[0058] In this embodiment, candidate traces can be a set of traces that need to be optimized through widening processing, initially identified using the first screening sub-condition. Specifically, candidate traces can be traces that pose electrical performance risks but whose physical feasibility of the routing layout has not yet been verified. If the traces in the preset routing layout have trace identifiers, candidate traces can be determined by these identifiers. If the traces in the preset routing layout do not have trace identifiers, a two-dimensional coordinate system can be established in the preset routing layout, and candidate traces can be determined by the coordinates of the trace endpoints and multiple trace midpoints in this two-dimensional coordinate system. Taking the high-voltage domain under the 28nm process node as an example, all traces in this voltage domain with a length greater than 100μm and a width less than 0.5μm can be considered as candidate traces.
[0059] In this embodiment, the target trace can be a set of traces that require widening, as confirmed by the second screening sub-condition. Specifically, the target trace needs to simultaneously meet electrical optimization requirements and physical manufacturing constraints. The target trace can be a complete trace or a portion of a complete trace that meets the second screening sub-condition. When candidate traces are determined by trace identifiers, if the target trace is a complete trace, it can continue to be determined by trace identifiers; if the target trace is a partial trace, it can be determined by the trace identifiers and the coordinates of the endpoints of the portion that meets the second screening sub-conditions in a two-dimensional coordinate system. When candidate traces are determined by coordinates in a two-dimensional coordinate system, the target trace can continue to be determined by coordinates in a two-dimensional coordinate system. Taking the high-voltage domain under the 28nm process node as an example, candidate traces that meet the minimum trace width and minimum trace spacing requirements of this voltage domain can be determined as target traces.
[0060] In this embodiment, candidate traces are selected based on the first screening sub-condition. A layout analysis tool can be used to traverse all traces in a preset routing layout, adding candidate identifiers to traces that meet the first screening sub-condition. Traces with candidate identifiers are then designated as candidate traces. It should be noted that these candidate identifiers are only used to mark traces that meet the first screening sub-condition; they are different from trace identifiers and are not directly related to the method used to determine candidate traces.
[0061] In this embodiment, target routes are selected from candidate routes based on the second screening sub-condition. A layout analysis tool can be used to traverse all candidate routes, adding target identifiers to routes that meet the second screening sub-condition. Routes with target identifiers are then designated as target routes. It should be noted that this target identifier is only used to mark complete or partial routes that meet the second screening sub-condition. This target identifier is different from the route identifier and has little correlation with the method used to determine the target route.
[0062] Please see Figure 5 For details, please refer to the comparison. Figure 5 (a) and Figure 5 (b) Based on the routing screening criteria, Figure 5 After determining the middle trace among the three traces connected to the positive terminal of the power supply in (a) as the target trace, it can be determined according to... Figure 5 The routing layout shown in (a) uses the routing widthening rule corresponding to the voltage domain to widen the intermediate traces, resulting in... Figure 5 The widened wiring layout shown in (b) is shown in the middle.
[0063] S130: Iteratively verify the widened routing layout based on routing layout constraint rules, and use the widened routing layout that passes the verification as the target routing layout.
[0064] To ensure that the final output target routing layout meets the physical and electrical design rules of routing layout, the widened routing layout obtained by widening the traces can be iteratively verified based on the routing layout constraint rules. If the widened routing layout passes the verification, it is used as the target routing layout. If the widened routing layout fails the verification, it is further optimized.
[0065] In this embodiment, the step of iteratively verifying the widened routing layout based on routing layout constraint rules and using the verified widened routing layout as the target routing layout may include: determining the routing layout constraint rules corresponding to the conductive layer corresponding to the widened routing layout based on the minimum trace width requirement, minimum trace spacing requirement, and trace density requirement of the conductive layer corresponding to the widened routing layout; verifying the widened routing layout based on the routing layout constraint rules; and using the widened routing layout as the target routing layout if the widened routing layout passes the verification.
[0066] In this embodiment, the minimum trace width requirement and the minimum trace spacing requirement are similar to those in the above embodiments, and will not be repeated here.
[0067] In this embodiment, the trace density requirement can be defined as the percentage of traces allowed to fill a unit area of the conductive layer. Specifically, the trace density requirement can be used to balance the distribution of thermal stress and the uniformity of the planarization process.
[0068] In this embodiment, the widened routing layout is verified based on routing layout constraints. Layout analysis tools can be used to compare the widened routing layout with the routing layout constraints of the corresponding conductive layers. If all traces in the widened routing layout conform to the routing layout constraints, the widened routing layout is considered to have passed verification. If any trace in the widened routing layout does not conform to the routing layout constraints, the widened routing layout is considered to have failed verification.
[0069] In some embodiments, the step of iteratively verifying a widened routing layout based on routing layout constraint rules and using the verified widened routing layout as the target routing layout may further include: if the widened routing layout fails verification, repeating the following sub-steps until the widened routing layout passes verification; the sub-steps may include: obtaining the routing back-off rules corresponding to the conductive layer corresponding to the widened routing layout; determining abnormal routings in the widened routing layout that do not conform to the routing layout constraint rules based on the routing layout constraint rules; performing back-off processing on the abnormal routings based on the routing back-off rules; updating the widened routing layout, and verifying the updated widened routing layout based on the routing layout constraint rules.
[0070] In this embodiment, the trace rollback rule can be used to reduce the width of widened traces when the widened wiring layout fails verification. Specifically, the trace rollback rule can be a set of trace width rollback parameters set for a specific conductive layer. The trace rollback rule can include a rollback step size. For example, if the widened wiring layout belongs to the third conductive layer (Metal-3), and the widened wiring layout fails verification because some trace spacing does not meet the minimum trace spacing requirement, the trace rollback rule can be set to a rollback step size of 0.03 μm.
[0071] In this embodiment, abnormal traces can be a set of traces that, after being widened, do not meet the routing layout constraints. Specifically, similar to the target traces described in the above embodiments, abnormal traces can be complete traces or portions of complete traces that do not meet the routing layout constraints. Abnormal traces can be identified by trace identifiers or coordinates established in a two-dimensional coordinate system of the widened routing layout.
[0072] In this embodiment, the rollback process can be a width reduction process performed on abnormal traces, so that the widened routing layout passes the verification based on routing layout constraint rules and maintains the electrical performance of the traces. Specifically, the rollback process can reduce the width of abnormal traces by a corresponding rollback step size each time according to the parameter constraints in the routing rollback rules, and perform width detection on the abnormal traces after width reduction to ensure that the trace width meets the minimum trace width requirement after width reduction, thereby reducing the degradation of trace electrical performance caused by excessive rollback.
[0073] Please compare and refer to the following: Figure 5 (b) and Figure 5 (c) In the context of routing layout constraints, Figure 5 After the middle trace in (b) that has been widened is identified as an abnormal trace, it can be determined according to... Figure 5 The trace return rule corresponding to the conductive layer of the widened wiring layout shown in (b) performs a return process on the intermediate traces, resulting in... Figure 5 The target routing layout is shown in (c).
[0074] In this embodiment, updating the widened routing layout can be achieved by synchronously reflecting the rolled-back routing data in the routing layout data. Specifically, updating the widened routing layout can be achieved through the incremental modification function of the layout editing tool, that is, only updating abnormal routing and its associated layout area.
[0075] In this embodiment, the updated widened routing layout is verified based on routing layout constraint rules, and only the modified layout areas in the updated widened routing layout can be verified.
[0076] Please see Figure 6 Another embodiment of this application provides a cabling device. The cabling device may include an acquisition module, a widening processing module, and a verification module.
[0077] In this embodiment, the acquisition module can be used to acquire preset routing layouts, trace widening rules, and routing layout constraint rules corresponding to each voltage domain. The trace widening rule can include a trace widening width. The trace widening width can increase as the voltage value of the voltage domain corresponding to the trace widening rule increases.
[0078] In this embodiment, the widening processing module can be used to widen a target trace according to the trace widening rules corresponding to the voltage domain of the preset routing layout when a target trace exists in the preset routing layout and meets the trace screening conditions corresponding to the voltage domain of the preset routing layout, thereby obtaining a widened routing layout. The trace screening conditions may include a trace length greater than a length threshold and a trace width less than a width threshold.
[0079] In this embodiment, the verification module can be used to iteratively verify the widened routing layout based on routing layout constraint rules, and use the widened routing layout that passes the verification as the target routing layout.
[0080] Another embodiment of this application provides a computer-readable storage medium on which a computer program can be stored, which, when executed by a processor, can implement the wiring method as described in the above embodiments.
[0081] Another embodiment of this application provides a chip whose routing can be configured according to the routing method described in the above embodiments or according to the target routing layout provided by the routing apparatus described in the above embodiments.
[0082] For other technical effects of the wiring device, electronic device, computer-readable storage medium, computer program product, and chip described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.
[0083] In the routing method and related apparatus provided in this application embodiment, a preset routing layout, trace widening rules, and routing layout constraint rules corresponding to each voltage domain are obtained. The trace widening rules include a trace widening width, which increases with the increase of the voltage value in the voltage domain. If a target trace exists in the preset routing layout that satisfies the condition that its length is greater than a length threshold and its width is less than a width threshold, the target trace is widened according to the trace widening rules corresponding to the voltage domain to obtain a widened routing layout. Then, the widened trace is further widened based on the routing layout constraint rules. The layout is iteratively verified, and the widened routing layout that passes the verification is output as the target routing layout. Unexpected effects include: widening and adjusting excessively long and narrow traces by using differentiated trace widening rules corresponding to different voltage domains, and through iterative verification, ensuring that the output target routing layout meets the process design requirements of the routing layout. This reduces the trace resistance of excessively long and narrow traces, corrects the voltage drop loss and heat generation caused by excessive trace resistance, improves the actual voltage value of the voltage domain powered by excessively long and narrow traces, and enhances the overall chip performance.
[0084] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.
[0085] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.
[0086] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.
[0087] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0088] In the several embodiments provided in this application, it should be understood that the disclosed wiring devices, computer-readable storage media, and chips can be implemented in other ways. For example, the embodiments of wiring devices, computer-readable storage media, and chips described above are merely illustrative.
[0089] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A wiring method, characterized in that, The wiring method includes: Obtain the preset routing layout, trace widening rules, and routing layout constraint rules for each voltage domain; wherein, the trace widening rule includes a trace widening width for defining the range of trace widening; the trace widening width increases as the voltage value of the voltage domain corresponding to the trace widening rule increases; If there is a target trace in the preset routing layout that meets the trace selection criteria corresponding to the voltage domain of the preset routing layout, the target trace is widened according to the trace widening rule corresponding to the voltage domain of the preset routing layout to obtain a widened routing layout; wherein, the trace selection criteria include trace length greater than a length threshold and trace width less than a width threshold. The widened routing layout is iteratively verified based on the routing layout constraint rules, and the widened routing layout that passes the verification is taken as the target routing layout. The steps to obtain the trace widening rules for each voltage domain include: For any voltage domain, the category of the voltage domain is determined according to the voltage domain classification rules; wherein, the voltage domain classification rules are used to indicate the voltage value range corresponding to different categories of voltage domains; Based on the category of the voltage domain, the trace widening reference and the trace widening width corresponding to the voltage domain are determined, and the trace widening rule corresponding to the voltage domain is obtained.
2. The wiring method according to claim 1, characterized in that, The wiring method is used to configure a chip; the chip includes at least two conductive layers that are electrically connected. Obtain the preset routing layout for each voltage domain, including: Identify all voltage domains in the chip based on voltage domain labels; Based on the line connection relationships, a preset wiring layout is determined on all conductive layers belonging to any voltage domain.
3. The wiring method according to claim 2, characterized in that, The step of iteratively verifying the widened routing layout based on the routing layout constraint rules, and using the verified widened routing layout as the target routing layout, includes: Based on the minimum trace width requirement, minimum trace spacing requirement, and trace density requirement of the conductive layer corresponding to the widened wiring layout, determine the wiring layout constraint rules corresponding to the conductive layer of the widened wiring layout. The widened routing layout is verified based on the routing layout constraint rules. If the widened routing layout passes the verification, it is used as the target routing layout.
4. The wiring method according to claim 3, characterized in that, The step of iteratively verifying the widened routing layout based on the routing layout constraint rules and using the verified widened routing layout as the target routing layout further includes: If the widened routing layout fails verification, repeat the following sub-steps until the widened routing layout passes verification; the sub-steps include: Obtain the trace return rule corresponding to the conductive layer corresponding to the widened wiring layout; wherein, the trace return rule is used to reduce the width of the target trace after widening if the widened wiring layout fails to pass verification; Based on the routing layout constraint rules, abnormal traces in the widened routing layout that do not conform to the routing layout constraint rules are identified; The abnormal routing is returned based on the routing return rules; Update the widened routing layout and verify the updated widened routing layout based on the routing layout constraint rules.
5. The wiring method according to claim 1, characterized in that, The voltage domains are categorized into low-voltage, medium-voltage, and high-voltage domains. The trace width widening range for the low-voltage domain is no less than 0.5 times the reference width widening and no more than 1.5 times the reference width widening. The trace width widening range for the medium-voltage domain is no less than 1.5 times the reference width widening and no more than 2.5 times the reference width widening. The trace width widening range for the high-voltage domain is no less than 2.5 times the reference width widening and no more than 3.5 times the reference width widening. The voltage range of the low voltage domain is less than or equal to 0.8V, the voltage range of the medium voltage domain is greater than 0.8V and less than or equal to 1.2V, and the voltage range of the high voltage domain is greater than 1.2V.
6. The wiring method according to claim 1, characterized in that, In addition to the first screening sub-condition that the trace length is greater than the length threshold and the trace width is less than the width threshold, the trace screening condition also includes a second screening sub-condition determined according to the minimum trace width requirement and the minimum trace spacing requirement of the voltage domain corresponding to the preset wiring layout. The wiring method further includes: Based on the first screening sub-condition corresponding to the voltage domain of the preset routing layout, the traces in the preset routing layout are screened, and the traces that meet the first screening sub-condition are determined as candidate traces. The candidate traces are screened based on the second screening sub-condition corresponding to the voltage domain of the preset routing layout, and the traces that meet the second screening sub-condition are determined as target traces.
7. A wiring device, characterized in that, The wiring device includes: The acquisition module is used to acquire the preset routing layout, trace widening rules, and routing layout constraint rules corresponding to each voltage domain; wherein, the trace widening rule includes the trace widening width; the trace widening width increases as the voltage value of the voltage domain corresponding to the trace widening rule increases; The widening processing module is used to widen the target trace according to the trace widening rule corresponding to the voltage domain of the preset routing layout when there is a target trace in the preset routing layout that meets the trace screening conditions corresponding to the voltage domain of the preset routing layout, so as to obtain a widened routing layout; wherein, the trace screening conditions include the trace length being greater than the length threshold and the trace width being less than the width threshold. The verification module is used to iteratively verify the widened routing layout based on the routing layout constraint rules, and take the widened routing layout that passes the verification as the target routing layout. The acquisition module is further configured to determine the category of any voltage domain according to a voltage domain classification rule; wherein the voltage domain classification rule is used to indicate the voltage value range corresponding to different categories of voltage domains; and to determine the trace widening reference and the trace widening width corresponding to the voltage domain according to the category of the voltage domain, thereby obtaining the trace widening rule corresponding to the voltage domain.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the wiring method as described in any one of claims 1 to 6.
9. A chip, characterized in that, The chip's routing is configured according to the routing method as described in any one of claims 1 to 6 or according to the target routing layout provided by the routing apparatus as described in claim 7.