A flow generating device

Abstract

The application discloses a traffic generation device. A traffic model is encapsulated into a first data packet by a software processor, and a routing network table is encapsulated into a second data packet, which are respectively stored into corresponding first and second storage modules by a packet distribution circuit in a hardware processor. A traffic generation circuit parses the traffic model in the first data packet from the first storage module, and independently generates an initial message and corresponding index information. A routing processing circuit quickly obtains corresponding routing entries from the second storage module according to the index information and returns in real time, so that the routing access operation and the data packet generation operation are decoupled and executed in parallel at the hardware level. The routing processing circuit and the traffic generation circuit realize accurate cooperation through the index information, so that the real-time query process of the routing network table no longer blocks the message generation pipeline, thereby effectively solving the problems of message loss and traffic distortion caused by external storage access delay.

Description

Technical Field

[0001] This application relates to the field of network testing, and in particular to a traffic generation device. Background Technology

[0002] As network device port speeds increase to 800G and even 1.6T, testing systems must be able to accurately and in real-time fill large-scale routing information into the rapidly generated traffic in order to effectively verify the performance of network devices in real network environments. Currently, to address the issue of insufficient routing netlist capacity, using FPGAs (field-programmable gate arrays) with external high-capacity DDR (double data rate) storage is a common solution. However, the inherent microsecond-level random access latency of DDR cannot meet the timing requirements for real-time routing information filling during traffic generation, potentially leading to packet loss and traffic distortion.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application discloses a traffic generation device, which is used to solve at least the problems of packet loss and traffic distortion caused by external storage access delay.

[0005] This application provides a traffic generation device, comprising: a software processor for encapsulating a traffic model into a first data packet and encapsulating a routing netlist into a second data packet; the routing netlist includes multiple routing entries; and a hardware processor, comprising a packet distribution circuit, a traffic generation circuit, and a routing processing circuit; the packet distribution circuit for storing the first data packet in a first storage module and the second data packet in a second storage module; and the traffic generation circuit for parsing the first data packet in the first storage module to obtain a traffic model, generating an initial message and corresponding index information based on the traffic model, and sending the index information to the routing processing circuit. The circuit; the routing processing circuit is used to obtain routing entries from the second storage module according to the index information to obtain routing data corresponding to the index information, and return them to the traffic generation circuit; the traffic generation circuit is also used to generate target packets according to the initial packet and the routing entries returned by the routing processing circuit, realizing the decoupling and parallel execution of routing access operations and packet generation operations at the hardware level. The routing processing circuit and the traffic generation circuit achieve precise coordination through the index information, so that the real-time query process of the routing netlist no longer blocks the packet generation pipeline, thereby effectively solving the problem of packet loss and traffic distortion caused by external storage access delay.

[0006] In one possible implementation, when the packet distribution circuit stores the second data packet in the second storage module, it specifically splits the data of the value field in the second data packet into multiple first sub-data segments and stores the multiple first sub-data segments in the second storage module; wherein, the first sub-data segment is the routing data, and each first sub-data segment is stored in at least one storage address of the second storage module; when the routing processing circuit obtains a routing entry from the second storage module based on the index information, it specifically determines at least one target storage address based on the index information, reads the stored first sub-data segment from each target storage address, parses the read at least one first sub-data segment to obtain a routing entry, and returns it to the traffic generation circuit. By moving the data parsing to the routing processing circuit, the storage logic of the packet distribution circuit is simplified, and the routing data storage speed is improved.

[0007] In one possible implementation, when the packet distribution circuit stores the second data packet in the second storage module, it specifically parses the data in the value field of the second data packet to obtain at least one routing entry, and stores the parsed at least one routing entry in the second storage module; wherein, the routing entry is the routing data, and each routing entry is stored in a storage address of the second storage module; when the routing processing circuit obtains the routing entry from the second storage module according to the index information, it specifically determines at least one target storage address according to the index information, reads the stored routing entry from each target storage address, and returns it to the traffic generation circuit. By completing the data parsing in the storage stage of the packet distribution circuit, the routing processing circuit can directly read and use the routing entry, reducing the query latency.

[0008] In one possible implementation, when the packet distribution circuit stores the second data packet into the second storage module, it specifically splits the routing data in the second data packet into multiple second sub-data segments, and stores the multiple second sub-data segments sequentially into multiple consecutive storage addresses of the second storage module; the length of the second sub-data segment is less than or equal to the storage bit width of the second storage module. By splitting the routing data and storing it consecutively, the utilization of storage bit width and access timing are optimized, and the effective utilization rate of storage bandwidth is improved.

[0009] In one possible implementation, the second storage module includes multiple memories. When the packet distribution circuit stores the second data packet in the second storage module, it specifically writes multiple routing data of the second data packet sequentially and cyclically into the multiple memories according to the division order. By writing to multiple memories in a cyclic manner, the storage load is balanced, and the overall read / write bandwidth and concurrent access capability of the second storage module are improved.

[0010] In one possible implementation, the hardware processor includes multiple storage interfaces for connecting the multiple external memories. By providing external storage interfaces, the use of large-capacity off-chip memory is supported, thereby enabling the support of ultra-large-scale routing netlists.

[0011] In one possible implementation, the storage space of the memory is divided into a first storage area and a second storage area; when the packet distribution circuit is used to sequentially and cyclically write multiple routing data of the second data packet into multiple memories according to the division order, it is specifically used to sequentially and cyclically write multiple routing data of the second data packet received in the first configuration stage into the first storage area of ​​the multiple memories according to the division order, and sequentially and cyclically write multiple routing data of the second data packet received in the second configuration stage into the second storage area of ​​the multiple memories according to the division order; the second configuration stage is the configuration stage after the first configuration stage. By dividing the storage area and binding it with the configuration stage, seamless dynamic updating of the routing netlist during the testing process is realized, ensuring the continuity of the test.

[0012] In one possible implementation, the first data packet and the second data packet are TLV packets. The self-describing characteristics of the TLV packet format simplify the hardware parsing logic and enhance the data format expansion capability of the traffic generation device.

[0013] In one possible implementation, the traffic generation circuit is further configured to generate a query instruction upon receiving a traffic generation trigger instruction and send the query instruction to the packet distribution circuit; the packet distribution circuit is further configured to generate corresponding return information based on whether the first storage module is empty upon receiving the query instruction; specifically, when the traffic generation circuit parses the first data packet of the first storage module to obtain the traffic model, it is configured to parse the first data packet of the first storage module to obtain the traffic model after receiving the return information corresponding to the first storage module being non-empty, ensuring that the traffic generation circuit is only started after the configuration data is ready, thereby improving the reliability of packet generation.

[0014] In one possible implementation, the traffic generation circuit is further configured to acquire packet configuration information, which includes the number of packets and the number of routing entry insertion points for each packet, as well as the mapping relationship between each routing entry insertion point and a routing entry. When the traffic generation circuit generates an initial packet and corresponding index information based on the traffic model, it specifically generates an initial packet based on the traffic model and the packet configuration information, and generates corresponding index information based on the traffic model. When the traffic generation circuit generates a target packet based on the initial packet and the routing entries returned by the routing processing circuit, it specifically adds the routing entries returned by the routing processing circuit to the routing entry insertion point corresponding to the initial packet according to the mapping relationship, thereby obtaining the target packet. This introduces the packet configuration information, achieving precise control over the packet structure and routing backfilling rules, and improving the flexibility and accuracy of traffic simulation. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a flow generation device provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of a dual-memory parallel cross-access routing netlist provided in an embodiment of this application.

[0018] Explanation of reference numerals in the attached figures:

[0019] 10 - Software processor;

[0020] 20 - Hardware processor;

[0021] 201 - Packet distribution circuit; 202 - Traffic generation circuit; 203 - Routing processing circuit;

[0022] 30 - First storage module;

[0023] 40 - Second storage module. Detailed Implementation

[0024] When verifying the extreme performance of network devices such as routers and switches under real traffic conditions, it is necessary to accurately simulate the full table simulation of Internet-level discrete routing netlists and random address access in a real network environment. To overcome the limitations of routing netlist capacity and reduce latency response, this application provides a traffic generation device.

[0025] Combination Figure 1 The traffic generation device in this application embodiment includes:

[0026] The software processor 10 is used to encapsulate the traffic model into a first data packet and the routing netlist into a second data packet; the routing netlist includes multiple routing entries.

[0027] Hardware processor 20 includes packet distribution circuit 201, traffic generation circuit 202 and routing processing circuit 203;

[0028] The packet distribution circuit 201 is used to store the first data packet in the first storage module 30 and the second data packet in the second storage module 40;

[0029] The traffic generation circuit 202 is used to parse the first data packet of the first storage module 30 to obtain the traffic model, generate an initial message and corresponding index information based on the traffic model, and send the index information to the routing processing circuit 203.

[0030] The routing processing circuit 203 is used to obtain routing entries from the second storage module 40 according to the index information, and return them to the traffic generation circuit 202.

[0031] The traffic generation circuit 202 is also used to generate a target message based on the initial message and the routing entry returned by the routing processing circuit 203.

[0032] The software processor 10 in this application can be a CPU (Central Processing Unit), DSP (Digital Signal Processor), or other processor used to run computer program code. The hardware processor 20 in this application can include an ASIC (Application-Specific Integrated Circuit) or a PLD (Programmable Logic Device), used to implement customized hardware functional circuits; the PLD can include FPGA, CPLD (Complex Programmable Logic Device), etc. Generally, hardware processors have a faster processing speed than software processors, but software processors can execute various functions and tasks more flexibly, offering greater flexibility.

[0033] In this embodiment, the software processor 10 is used to receive and process the user's configuration data, which includes at least a traffic model and a routing netlist.

[0034] As an optional implementation, the software processor 10 can receive different types of configuration commands through two independent configuration interfaces. The user defines and generates a traffic model through the first configuration interface in the first user interface. In response to the user's command to generate a flow triggered in the first user interface, the software processor 10 generates a unique flow identifier for the created data flow, serving as the independent identification information for that flow. The user configures the required routing information for the generated flow in the second user interface through the second configuration interface. In response to the user's configuration operations in the second user interface, the software processor 10 establishes and maintains the correspondence between the flow identifier and one or more routing entries based on the routing entries configured by the user for a specific flow identifier.

[0035] As an alternative implementation, the software processor 10 can receive all configuration commands through a unified configuration interface and manage them through different views in an integrated user interface. Specifically, in the traffic model view of the user interface, the user defines and creates data flows by clicking operations such as generating flows. The software processor 10 responds to the user's command to generate a flow in the traffic model view by generating a unique flow identifier for this data flow as its independent identification information. The user can enter the routing configuration view in the flow list of the same user interface by double-clicking a flow identifier or clicking related operations such as configuring routes to set specific routing entries for the data flow. The software processor 10 responds to the user's editing operations in the routing configuration view by establishing and maintaining the correspondence between the flow identifier and the configured routing entries.

[0036] After configuration is completed using any of the above methods, the software processor 10 integrates the flow identifiers of all data flows to form a complete traffic model, and encapsulates this traffic model into at least one first data packet. Simultaneously, the software processor 10 summarizes all routing entries corresponding to all flow identifiers to form a complete routing netlist, and encapsulates this routing netlist into at least one second data packet. Each routing entry contains at least key forwarding fields such as source address and destination address. Subsequently, the software processor 10 sequentially sends the encapsulated at least one first data packet and at least one second data packet to the hardware processor 20. Both the first and second data packets contain a type identifier field indicating the data type and a value field carrying the actual configuration data. For example, in the first data packet, its type identifier field is assigned a first preset value A to indicate that the configuration data carried by the value field of this data packet is a traffic model; in the second data packet, its type identifier field is assigned a second preset value B to indicate that the configuration data carried by the value field of this data packet is a routing netlist.

[0037] The traffic generation device also includes a first storage module 30 and a second storage module 40, which are used to store two different types of configuration data in a one-to-one correspondence. The packet distribution circuit 201 in the hardware processor 20 has a receiving end, a first distribution end, and a second distribution end. The receiving end of the packet distribution circuit 201 is connected to the software processor 10 and is used to receive the first data packet and the second data packet sequentially sent by the software processor 10. The first distribution end of the packet distribution circuit 201 is connected to the first storage module 30, and the second distribution end of the packet distribution circuit 201 is connected to the second storage module 40.

[0038] When packet distribution circuit 201 receives a data packet (first data packet or second data packet) through its receiving end, it parses the type identifier field in each data packet and, based on the parsing result, distributes the data to the corresponding storage module through the corresponding distribution end. Specifically, packet distribution circuit 201 writes the first data packet with a type identifier field of a first preset value A into the first storage module 30 through its first distribution end; and writes the second data packet with a type identifier field of a second preset value B into the second storage module 40 through its second distribution end. As an optional implementation, when performing storage operations, packet distribution circuit 201 can extract only the configuration data carried by the value field in each data packet for storage, thereby saving physical space in the storage module and allowing the limited storage space to accommodate more effective configuration information.

[0039] This embodiment achieves separate storage of the traffic model and routing netlist at the hardware level through the aforementioned distribution and storage operations of the packet distribution circuit 201. The traffic model is independently stored in the first storage module 30 for use by the traffic generation circuit 202; the routing netlist is independently stored in the second storage module 40 for use by the routing processing circuit 203. Based on this, the traffic generation circuit 202 and the routing processing circuit 203 in the hardware processor 20 can simultaneously and independently access their respective storage modules in subsequent operations, thereby achieving high-speed parallel processing of the configuration data required by the traffic generation circuit 202 and the routing processing circuit 203.

[0040] The traffic generation circuit 202 includes at least a first terminal, a second terminal, and a third terminal. The first terminal of the traffic generation circuit 202 is connected to the first storage module 30, the second terminal of the traffic generation circuit 202 is connected to the second terminal of the routing processing circuit 203, and the third terminal of the traffic generation circuit 202 is connected to the third terminal of the routing processing circuit 203.

[0041] Once the traffic generation circuit 202 confirms that at least one first data packet has been stored in the first storage module 30, it reads the first data packet from the first storage module 30 through its first terminal and parses it to obtain a traffic model. Subsequently, the traffic generation circuit 202 generates an initial message and corresponding index information based on this traffic model, and sends the index information to the routing processing circuit 203 through its second terminal. Specifically, the traffic generation circuit 202 generates corresponding index information and at least one initial message based on each flow identifier in the traffic model. Each initial message contains routing entry insertion points for subsequent filling; these routing entry insertion points are empty in the initial message and do not contain any specific routing entries. It can be understood that the index information is generated based on the flow identifier. As an optional implementation, for ease of matching, the flow identifier itself can be used directly as index information.

[0042] The routing processing circuit 203 includes a first terminal, a second terminal, and a third terminal. The first terminal of the routing processing circuit 203 is connected to the second storage module 40, the second terminal of the routing processing circuit 203 is connected to the second terminal of the traffic generation circuit 202, and is used to receive index information sent by the traffic generation circuit 202. The third terminal of the routing processing circuit 203 is connected to the third terminal of the traffic generation circuit 202, and is used to return routing entries to the traffic generation circuit 202.

[0043] It should be noted that during the configuration phase, the software processor 10 generates a mapping between flow identifiers and routing entries. This mapping includes two parts: firstly, the logical association between the flow identifier and the specific routing entry content; secondly, to achieve efficient storage and retrieval, the mapping also specifies the storage location information (e.g., starting address and length range) of the routing data corresponding to each flow identifier in the second storage module 40. This mapping is encapsulated and sent to the hardware processor 20. First, the packet distribution circuit 201 uses the storage location information in this mapping to write the routing data in the second data packet to a predetermined address in the second storage module 40. The packet distribution circuit 201 then forwards this mapping to the routing processing circuit 203 for use during the query phase.

[0044] When the routing processing circuit 203 receives an index information (e.g., a flow identifier) ​​from the traffic generation circuit 202 via its second terminal, it immediately queries its corresponding relationship to determine the specific storage location of the routing entry associated with the index information in the second storage module 40. The routing processing circuit 203 then directly accesses the second storage module 40 via its first terminal, based on the storage location information, reads the corresponding routing data stored therein, and obtains the complete routing entry. Finally, the routing processing circuit 203 sends the obtained routing entry back to the traffic generation circuit 202 via its third terminal.

[0045] After receiving the routing entry returned by the routing processing circuit 203 through its third terminal, the traffic generation circuit 202 inserts it into the routing entry insertion point of the corresponding initial packet, thereby generating the final target packet. At this time, the specific routing entry has been filled into the routing entry insertion point of the target packet.

[0046] It is understood that in this embodiment, the traffic generation circuit 202 sends the corresponding index information to the routing processing circuit 203 simultaneously with the generation of the initial packet. Upon receiving the index information, the routing processing circuit 203 immediately begins parallel execution of the route entry retrieval operation. Since the generation of the initial packet is a continuous process involving the sequential processing of multiple fields, and in this embodiment, the packet generation process and the route entry retrieval process are performed synchronously in hardware. Specifically, the entire process of the traffic generation circuit 202 generating the initial packet can be divided into multiple clock cycles, where the route entry insertion point can be located in the middle or later part of the initial packet. When the traffic generation circuit 202 begins generating the packet header fields, the routing processing circuit 203 has synchronously started the route query operation. Since the traffic generation circuit 202 needs a certain amount of time to generate the preamble fields, this provides a time window for the routing processing circuit 203 to execute the query and return the route entry. Therefore, when the traffic generation circuit 202 completes the generation of the preamble fields and reaches the route entry insertion point in time, the route entry returned by the routing processing circuit 203 also arrives precisely at that point. The traffic generation circuit 202 can insert the received routing entries into the routing entry insertion point of the initial message in real time, thereby completing the final assembly of the target message.

[0047] This embodiment eliminates idle waiting time caused by waiting for route query results by aligning and parallelizing the message generation process of the traffic generation circuit 202 with the data query process of the routing processing circuit 203 in time. This enables the traffic generation device of this embodiment to maintain line-rate traffic generation under high bandwidth conditions exceeding 800Gbps and achieve low-latency dynamic acquisition of large-scale routing netlists.

[0048] In some implementations, when the packet distribution circuit 201 stores the second data packet in the second storage module 40, it is specifically used to split the data of the value field in the second data packet into multiple first sub-data segments and store the multiple first sub-data segments in the second storage module 40; wherein, the first sub-data segment is routing data, and each first sub-data segment is stored in at least one storage address in the second storage module 40.

[0049] When the routing processing circuit 203 obtains routing entries by retrieving routing data corresponding to the index information from the second storage module 40 based on the index information, it specifically determines at least one target storage address based on the index information, reads the first sub-data segment stored from each target storage address, parses the read at least one first sub-data segment to obtain routing entries, and returns them to the traffic generation circuit 202.

[0050] It is understood that the routing netlist in this embodiment contains all routing entries corresponding to all flow identifiers, and the contents of the routing entries corresponding to different flow identifiers are not all the same. During the process of encapsulating the routing netlist into a second data packet, the value field of the second data packet can adopt various data organization forms, such as: encapsulating all routing entries corresponding to one flow identifier in the same second data packet; encapsulating routing entries corresponding to multiple flow identifiers (which may be part or all of the routing entries for a certain flow identifier) ​​together in the same second data packet; or splitting the routing entries corresponding to the same flow identifier and encapsulating them in multiple different second data packets.

[0051] For example, suppose all routing entries corresponding to the first flow identifier ID1 include the first routing entry List1 (List 1), the second routing entry List2, and the third routing entry List3, and all routing entries corresponding to the second flow identifier ID2 include the fourth routing entry List4 and the fifth routing entry List5. Based on the above organization, encapsulation examples include, but are not limited to, the following: all three routing entries corresponding to the first flow identifier ID1 (List 1), the second routing entry List2, and the third routing entry List3 are encapsulated in the same second data packet; or, the three routing entries corresponding to the first flow identifier ID1 and the fourth routing entry List4 corresponding to the second flow identifier ID2 are encapsulated in the same second data packet; or, the first routing entry List1 is encapsulated in the first second data packet, while the second routing entries List2 and the third routing entry List3 are encapsulated in another second data packet.

[0052] After receiving the second data packet, the packet distribution circuit 201 parses the data carried in the value field of the second data packet and directly divides the data carried in the value field into multiple first sub-data segments. These first sub-data segments are the routing data to be stored in the second storage module 40. Each first sub-data segment contains data of a routing entry belonging to the same flow identifier. This data can be the entire content of one or more complete routing entries, or a part of the content of a routing entry. Based on the correspondence issued from the software processor 10, the packet distribution circuit 201 determines the target address range corresponding to the flow identifier of the current first sub-data segment in the second storage module 40, and stores the first sub-data segment (i.e., the routing data) in one or more specific target storage addresses within this target address range. It can be understood that any storage address within the target address range can be used as a target storage address, ensuring that first sub-data segments belonging to the same flow identifier are centrally stored within their corresponding target address range.

[0053] When the routing processing circuit 203 needs to retrieve the corresponding routing data from the second storage module 40 based on the index information to obtain a routing entry, the routing processing circuit 203 determines the target address range of the routing data pointed to by the index information in the second storage module 40 according to the index information and the same correspondence issued by the packet distribution circuit 201. This correspondence defines the storage base address or address mapping rule for each flow identifier in the second storage module 40, and the routing processing circuit 203 maps the precise target address range accordingly. Next, the routing processing circuit 203 accesses the second storage module 40 and reads the stored first sub-data segment (i.e., routing data) from each relevant target storage address within the determined target address range. After reading all the required first sub-data segments, the routing processing circuit 203 combines and parses these first sub-data segments to reconstruct at least one complete and accurate routing entry corresponding to the index information, and returns the reconstructed routing entry to the traffic generation circuit 202.

[0054] In this embodiment, the packet distribution circuit 201 only needs to divide the value field of the second data packet into multiple first sub-data segments according to preset rules and store them in the second storage module 40. It does not need to parse the specific format of each routing entry, simplifying the internal logic of the packet distribution circuit 201 and allowing it to focus on high-speed data transfer. This enables it to store a large amount of routing data in the second storage module 40 at a higher rate, shortening the overall preparation time. Furthermore, since the stored data is the unparsed first sub-data segment, the storage process is independent of the specific structure of the routing entry. If the routing entry format changes or requires support for more complex encoding, only the parsing logic in the routing processing circuit 203 needs to be updated, improving the adaptability of this traffic generation device to more data formats.

[0055] In some implementations, when the packet distribution circuit 201 stores the second data packet in the second storage module 40, it is specifically used to parse the data of the value field in the second data packet to obtain at least one routing entry, and store the parsed at least one routing entry in the second storage module 40; wherein, the routing entry is routing data, and each routing entry is stored in a storage address of the second storage module 40;

[0056] When the routing processing circuit 203 obtains routing entries from the second storage module 40 based on the index information, it specifically determines at least one target storage address based on the index information, reads the stored routing entries from each target storage address, and returns them to the traffic generation circuit 202.

[0057] In this embodiment, after receiving the second data packet, the packet distribution circuit 201 parses the data carried in the value field of the second data packet to extract all complete routing entries included in the data carried in the value field. These parsed routing entries are the routing data to be stored in the second storage module 40. Based on the correspondence issued by the software processor 10, the packet distribution circuit 201 determines the target address range corresponding to the flow identifier of the routing entry in the second storage module 40, and stores the routing entry (i.e., the routing data) in a specific target storage address within this target address range. It can be understood that any storage address within the target address range can be used as the target storage address, ensuring that routing entries belonging to the same flow identifier are centrally stored within their corresponding target address range.

[0058] When the routing processing circuit 203 needs to retrieve the corresponding routing data from the second storage module 40 based on the index information to obtain a routing entry, the routing processing circuit 203 determines the target address range of the routing data pointed to by the index information in the second storage module 40 according to the index information and the same correspondence issued by the packet distribution circuit 201. This correspondence defines the storage base address or address mapping rule for each flow identifier in the second storage module 40, and the routing processing circuit 203 maps the precise target address range accordingly. Then, the routing processing circuit 203 accesses the second storage module 40, directly reads the stored routing entry from each relevant target storage address within the determined target address range, and returns at least one read routing entry to the traffic generation circuit 202.

[0059] In this embodiment, the packet distribution circuit 201 has completely parsed the value field of the second data packet into a directly usable routing entry before storage. Therefore, after receiving the index information from the traffic generation circuit 202, the routing processing circuit 203 only needs to query the corresponding relationship to obtain the target address range, and directly read the stored routing entry from each relevant target storage address within the determined target address range and return it. Since this embodiment avoids data combination or format parsing during the query process, the response latency of the routing processing circuit 203 is minimized and the timing is fixed. This allows the traffic generation circuit 202 to receive the required routing entry in a timely manner when the packet pipeline progresses to the point where a routing entry needs to be inserted, thereby ensuring the stability and continuity of traffic generation at bandwidths of 800Gbps and even higher.

[0060] In some implementations, when the packet distribution circuit 201 stores the second data packet in the second storage module 40, it is specifically used to split the routing data in the second data packet into multiple second sub-data segments, and store the multiple second sub-data segments sequentially into multiple consecutive storage addresses of the second storage module 40; the length of the second sub-data segment is less than or equal to the storage bit width of the second storage module 40.

[0061] When the routing data is a routing entry, considering that the length of the routing entry may exceed the storage width of the second storage module 40 (the storage width is the maximum data length that each storage address in the second storage module 40 can store), this embodiment divides each routing entry into multiple second sub-data segments to facilitate storage access. When the routing data is a first sub-data segment, considering that the length of the first sub-data segment may exceed the storage width of the second storage module 40, this embodiment divides each first sub-data segment into multiple second sub-data segments to facilitate storage access. This embodiment does not specifically limit the number of second sub-data segments or the length of each second sub-data segment, as long as the length of each second sub-data segment after division is less than or equal to the storage width.

[0062] During storage, the packet distribution circuit 201 stores multiple second sub-data segments, which are split from the same routing data, into multiple consecutive, unwritten storage addresses within the destination address range corresponding to the flow identifier to which the routing data belongs. For example, if a routing data is split into two second sub-data segments, d1 and d2, d1 is written to storage address k within the destination address range, and d2 is written to storage address k+1 within the destination address range.

[0063] For the storage operation of the packet distribution circuit 201, the multiple split second sub-data segments are written to consecutive storage addresses. The packet distribution circuit 201 only needs to determine the starting storage address, and subsequent addresses can be obtained by sequential incrementing. This eliminates the need for complex free address lookups or non-contiguous address mapping calculations, thus improving the storage efficiency of the packet distribution circuit 201. For the reading operation of the routing processing circuit 203, since it knows the starting address of the target address range and the number of second sub-data segments corresponding to each routing data, it can directly start from this starting address and read multiple storage addresses sequentially and consecutively. This sequential access mode is highly compatible with the optimal access characteristics of the second storage module 40 (e.g., a high-speed memory), maximizing the utilization of storage bandwidth and enabling the acquisition of complete routing data in a single continuous burst read. This significantly reduces read latency and improves the determinism and efficiency of the read operation.

[0064] In some implementations, the second storage module 40 includes multiple memories, and the packet distribution circuit 201 is used to store the second data packet in the second storage module 40, specifically to write multiple routing data of the second data packet into the multiple memories in a sequential and cyclic manner according to the division order.

[0065] In this embodiment, the second storage module 40 consists of multiple independent memories, and the packet distribution circuit 201 is connected to all of these memories. The packet distribution circuit 201 divides or parses multiple routing data (such as the first sub-data segment or routing entry) based on the data carried in the value field of the second data packet, and then writes these routing data into different memories in a cyclical manner according to the order in which they were generated, that is, two adjacent routing data will be stored in different memories.

[0066] For example, suppose the second storage module 40 includes two memories, a first memory and a second memory. When the packet distribution circuit 201 processes the first second data packet, its value field is divided into three first sub-data segments, D1, D2, and D3. The packet distribution circuit 201 writes D1 to the first memory, then writes D2 to the second memory, and then writes D3 to the first memory, and so on in a cycle. The routing data for subsequent second data packets and other data packets are also written in this cyclical order. Of course, the routing distribution circuit can also, after receiving all second data packets, parse all the routing data from all the second data packets and then store them cyclically in the division order.

[0067] This embodiment employs a parallel architecture with multiple memories and uses a cyclic, interleaved storage method for routing data. For the packet distribution circuit 201, the cyclic write strategy balances the write operations across multiple memories, preventing the bandwidth of a single memory from becoming a bottleneck for data writing, thereby accelerating the configuration and storage speed of large-scale routing netlists. For the routing processing circuit 203, when multiple consecutive routing data need to be read for a data stream, since these routing data are likely to be evenly distributed across different memories, the routing processing circuit 203 can initiate parallel read operations on multiple memories simultaneously, or use a pipelined approach to alternately access different memories to hide access latency. This embodiment utilizes the parallelism between multiple memories, enabling it to better meet the high bandwidth and low latency access requirements for routing information generated at traffic speeds of 800Gbps and even higher, even with a fixed access cycle for a single memory.

[0068] For example, such as Figure 2As shown, the second storage module 40 includes a first memory and a second memory. After parsing the received at least one second data packet, the packet distribution circuit 201 obtains multiple routing data as list_data_0[N-1:0], list_data_1[N-1:0], list_data_2[N-1:0], list_data_3[N-1:0], list_data_m[N-1:0], and list_data_q[N-1:0]. In list_data_x, x (such as 0, 1, m, q) represents the sequence number of the data, and [N-1:0] indicates that the data has N bits. Then, the packet distribution circuit 201 first divides the above routing data into two second sub-data segments. Taking the first four segments as an example, list_data_0[N-1:0] is divided into list_data_0[N / 2-1:0] and list_data_0[N-1:N / 2], list_data_1[N-1:0] is divided into list_data_1[N / 2-1:0] and list_data_1[N-1:N / 2], list_data_2[N-1:0] is divided into list_data_2[N / 2-1:0] and list_data_2[N-1:N / 2], and so on. t_data_3[N-1:0] is divided into list_data_3[N / 2-1:0] and list_data_3[N-1:N / 2]. list_data_0[N / 2-1:0], list_data_0[N-1:N / 2], list_data_2[N / 2-1:0] and list_data_2[N-1:N / 2] are written to the first memory. list_data_1[N / 2-1:0], list_data_1[N-1:N / 2], list_data_3[N / 2-1:0] and list_data_3[N-1:N / 2] are written to the second memory.

[0069] Taking list_data_0[N / 2-1:0] and list_data_0[N-1:N / 2] as examples, list_data_0[N / 2-1:0] is written to the storage address k in the target storage range corresponding to the flow identifier of the route data, and list_data_0[N / 2-1:0] is written to the storage address k+1.

[0070] When the routing processing circuit 203 reads data, referring to Table 1, at time T0, the upper half of list_data_0[N-1:0] is read from the first memory, and at time T1, the upper half of list_data_1[N-1:0] is read from the second memory, and at the same time, the lower half of list_data_0[N-1:0] is read from the first memory, and at time T2, the lower half of list_data_1[N-1:0] is read from the second memory, and at the same time, the upper half of list_data_2[N / 2-1:0] is read from the first memory, and so on.

[0071] Table 1. Pipeline Cross-Parallel Reading Table

[0072]

[0073] Referring to Table 1, at time T1, the routing processing circuit 203 can combine list_data_0[N / 2-1:0] and list_data_0[N-1:N / 2] into complete routing data list_data_0[N-1:0], and at time T2, it can combine list_data_1[N / 2-1:0] and list_data_1[N-1:N / 2] into complete routing data list_data_1[N-1:0]. That is, starting from time T1, in each clock cycle, the routing processing circuit 203 can obtain a complete routing data. When the routing data is a routing entry, it can achieve an average access of one routing entry per clock cycle.

[0074] In another embodiment, the first storage module 30 includes a separate memory in which the packet distribution circuit 201 stores all received first data packets.

[0075] It is understandable that the first storage module 30 consists of a physically independent memory. After receiving the first data packet sent by the software processor 10, the packet distribution circuit 201 directly stores it in this single memory. All configuration data related to the traffic model is centrally accessed here, reducing the complexity of the peripheral circuits and the number of components of the hardware processor 20, thereby effectively saving the overall material and manufacturing costs of the traffic generation device. Specifically, considering that traffic model data is usually written once during the configuration phase and is mainly read sequentially or randomly by the traffic generation circuit 202 during the traffic generation phase, its access frequency and bandwidth requirements are lower than those of the second storage module 40 (routing netlist), which needs to support real-time, parallel, and high-concurrency queries. Therefore, under the premise of meeting the data access performance requirements of the traffic generation circuit 202, a lower-cost single-memory solution is adopted for the first storage module 30, achieving a balance between performance and cost in the traffic generation device.

[0076] In some implementations, the hardware processor 20 includes multiple storage interfaces for connecting external memory.

[0077] The hardware processor 20 in this embodiment has multiple storage interfaces for connecting to off-chip memory located outside the hardware processor 20. The larger storage capacity of the off-chip memory enables the traffic generation device to support larger routing netlists, thereby meeting the needs of ultra-large-scale network testing scenarios.

[0078] Of course, depending on the specific application requirements for capacity, cost, and access speed, on-chip memory integrated on the hardware processor 20 can also be selected. On-chip memory offers faster access speeds and lower latency, but its capacity is relatively limited. Therefore, in scenarios with a moderate routing netlist size and extremely low latency requirements, an on-chip memory solution can be chosen to optimize performance; in scenarios that need to support ultra-large-scale routing netlists, an external high-capacity off-chip memory solution can be selected.

[0079] As a preferred implementation, random access memory (RAM) can be used, which has a larger storage space than the FPGA's on-chip RAM (Random-Access Memory). This overcomes the latency and random access bottlenecks of DDR and avoids the high cost of TCAM (Ternary Content-Addressable Memory), thus reducing costs. By using parallel and interleaved access of dual random access memories, the utilization rate of storage space is greatly improved.

[0080] In some implementations, the storage space of each memory is divided into a first storage area and a second storage area;

[0081] When the packet distribution circuit 201 writes multiple routing data points of the second data packet into the memory in a sequential and cyclical manner according to the partitioning order, it specifically writes multiple routing data points of the second data packet received in the first configuration phase into the first storage area of ​​the memory in a sequential and cyclical manner, and writes multiple routing data points of the second data packet received in the second configuration phase into the second storage area of ​​the memory in a sequential and cyclical manner according to the partitioning order; the second configuration phase is the configuration phase following the first configuration phase. If there are multiple memories, each memory can write data into two different memories of that memory in the two configuration phases respectively, using the above method.

[0082] In this embodiment, the complete storage space of each memory is first divided into two independent storage areas: a first storage area and a second storage area. These two storage areas correspond one-to-one with two configuration stages. When the traffic generation device is initially used, both the first and second storage areas of all memories are empty. When testing the network device, the user completes the initial configuration of the routing netlist using the method described above, at which point the traffic generation device enters the first configuration stage. The software processor 10 encapsulates the initially configured routing netlist into at least one second data packet and sends it down. The packet distribution circuit 201 then writes the routing data contained in the second data packet from the first configuration stage into the first storage area of ​​each memory. Afterward, the traffic generation device can perform traffic generation and testing based on the routing netlist in the first storage area.

[0083] During the aforementioned test, if the user reconfigures the routing netlist, the traffic generation device enters the second configuration phase. The software processor 10 encapsulates the reconfigured routing netlist into at least one new second data packet and sends it out. The packet distribution circuit 201 then writes the routing data contained in the second data packet from the second configuration phase into the second storage area of ​​each memory. This writing process is completely independent and does not affect the traffic generation and testing continued by the traffic generation circuit 202 based on the first storage area. Once all the new routing netlist data in the second storage area is ready to be written, the packet distribution circuit 201 can use a hardware control signal to instruct the routing processing circuit 203 to switch its query address range from the first storage area to the second storage area, thereby achieving dynamic and seamless updating of the routing netlist without interrupting the current line-rate traffic generation.

[0084] This embodiment achieves temporal and spatial decoupling between routing netlist configuration and traffic generation testing by dividing each memory into independent storage areas and binding them to the configuration phase. It employs a hardware-level ping-pong operation mechanism, which allows the traffic generation device to securely write new routing configurations to another storage area (e.g., the second storage area) in the background while simultaneously supporting real-time traffic generation using one storage area (e.g., the first storage area). This not only eliminates test interruptions and traffic gaps caused by routing netlist updates but also ensures test continuity. When off-chip random access memory is used, the routing netlist size can support 12M static routing entries (using only one storage area of ​​the memory), and can be expanded to 24M (using two storage areas of the memory) for dynamic applications.

[0085] In some implementations, the first data packet and the second data packet are TLV packets.

[0086] In this embodiment, both the first and second data packets are encapsulated using the TLV (Type-Length-Value) format. The TLV format includes a type identifier field, a length field, and a value field. The type identifier field explicitly identifies the data type carried by the data packet. For example, the type identifier field of the first data packet (carrying a traffic model) is assigned the value A, and the type identifier field of the second data packet (carrying a routing table) is assigned the value B. The length field records the total length of the value field that follows. The value field carries the actual configuration data itself. For the first data packet, its value field contains complete traffic model data; for the second data packet, its value field contains complete routing table data.

[0087] The traffic model and routing netlist are encapsulated in TLV format. After receiving a data packet, the packet distribution circuit 201 in the hardware processor 20 first reads the type identifier field at a fixed location to determine whether the data packet should be sent to the first storage module 30 (traffic model data) or the second storage module 40 (routing netlist data). Subsequently, based on the length field, the complete value field can be accurately extracted from the data stream, effectively preventing configuration errors caused by data misalignment or truncation. This deterministic parsing method simplifies the hardware design of the packet distribution circuit 201, enabling it to complete data classification and storage with extremely low latency and extremely high reliability, eliminating the need for complex boundary lookups or protocol parsing.

[0088] In some implementations, the traffic generation circuit 202 is also used to generate a query instruction when a traffic generation trigger instruction is received, and send the query instruction to the packet distribution circuit 201.

[0089] The packet distribution circuit 201 is also used to generate corresponding return information based on whether the first storage module 30 is empty when a query command is received;

[0090] When the traffic generation circuit 202 is used to parse the first data packet of the first storage module 30 to obtain the traffic model, it is specifically used to parse the first data packet of the first storage module 30 to obtain the traffic model after receiving the return information corresponding to the non-empty first storage module 30.

[0091] In this embodiment, when it is necessary to start the traffic generation device to test the network equipment, the user can click the start trigger or a similar button on the user interface through a separate configuration interface. The software processor 10 responds to the click operation, generates a traffic generation trigger command, and sends it to the packet distribution circuit 201 in the hardware processor 20. The traffic generation circuit 202 in this embodiment also includes a fourth terminal for connecting to the packet distribution circuit to receive the traffic generation trigger command. After receiving the traffic generation trigger command, the traffic generation circuit 202 does not start working immediately, but first sends a query command to the packet distribution circuit 201 to confirm the required data, i.e., whether the traffic model is ready.

[0092] After receiving a query command, the packet distribution circuit 201 checks the status of the first storage module 30. Based on the check result, the packet distribution circuit 201 generates corresponding return information and feeds it back to the traffic generation circuit 202. If the first storage module 30 is empty, a first return information is generated; if the first storage module 30 is not empty (i.e., at least one first data packet has been stored), a second return information is generated.

[0093] After receiving the second return information (i.e., confirmation that the data is ready), the traffic generation circuit 202 will access the first storage module 30 through its first end to obtain the first data packet stored therein, and parse it to obtain the traffic model, thereby starting the subsequent message generation process.

[0094] This embodiment ensures that the traffic generation circuit 202 will only start the message generation pipeline after confirming that its necessary configuration data (traffic model) has been successfully written to the first storage module 30 on the hardware side. This prevents the traffic generation circuit 202 from running idle, starting erroneously, or generating invalid messages due to incomplete software configuration or data transmission delays, thereby improving the reliability and automation level of the entire testing process and ensuring accurate and reliable test results.

[0095] In some implementations, the traffic generation circuit 202 is also used to obtain packet configuration information, which includes the number of packets and the number of routing entry insertion points for each packet, as well as the mapping relationship between each routing entry insertion point and the routing entry.

[0096] When the traffic generation circuit 202 is used to generate an initial message and corresponding index information based on the traffic model, it is specifically used to generate an initial message based on the traffic model and message configuration information, and to generate corresponding index information based on the traffic model.

[0097] When the traffic generation circuit 202 generates a target message based on the initial message and the routing entry returned by the routing processing circuit 203, it specifically adds the routing entry returned by the routing processing circuit 203 to the routing entry insertion point corresponding to the initial message according to the mapping relationship to obtain the target message.

[0098] The software processor 10 receives packet-related configuration commands input by the user through a separate configuration interface. In the user interface corresponding to this configuration interface, the user can define the packet characteristics for each flow identifier (e.g., flow identifier ID0, flow identifier ID1). The packet configuration information specifically includes: the number of packets to be generated for the data flow, the number of routing entry insertion points within each packet, and the mapping relationship between each routing entry insertion point and a specific routing entry. In response to the user's configuration commands, the software processor 10 creates and maintains a complete set of packet configuration information for each flow identifier, forming a correspondence between flow identifiers and packet configuration information.

[0099] The software processor 10 sends the mapping relationship between flow identifiers and packet configuration information to the hardware processor 20. Upon receiving this mapping relationship, the packet distribution circuit 201 forwards it to the traffic generation circuit 202. When the traffic generation circuit 202 parses the traffic model and prepares to generate a packet for a certain flow identifier (e.g., flow identifier ID0), it queries the already obtained mapping relationship between flow identifiers and packet configuration information to obtain the packet configuration information for that flow identifier. Based on the packet configuration information, the traffic generation circuit 202 can determine how many initial packets need to be generated for that flow identifier, how many routing entry insertion points should be set in each initial packet and their positions, and which routing entry(s) each routing entry insertion point should be associated with. Based on the packet configuration information, the traffic generation circuit 202 generates a specified number of initial packets, reserving a routing entry insertion point at a specified position in each packet. Simultaneously, the traffic generation circuit 202 generates index information based on the flow identifier and sends it to the routing processing circuit 203 to request routing entries. After the traffic generation circuit 202 receives the returned routing entries from the routing processing circuit 203, it precisely inserts each routing entry into the designated routing entry insertion point of the corresponding initial packet according to the preset mapping relationship in the packet configuration information, thereby assembling the final target packet. In this embodiment, the user can flexibly plan the number of packets in each data stream, the insertion position of routing information within each packet (routing entry insertion point), and the specific routing entry content and its variation sequence to be filled at different insertion points. Based on the user configuration, the traffic generation circuit 202 performs high-speed and accurate assembly of batch packets at the hardware level. This enables a single test to simulate real network traffic scenarios containing complex sequences, intersecting or cyclically changing routing entries, improving the flexibility, coverage, and accuracy of the simulation of the real network environment.

[0100] The above-described preferred embodiments have further detailed the purpose, technical solutions, and advantages of this application. It should be understood that the above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A flow generation device, characterized in that, include: The software processor is used to encapsulate the traffic model into a first data packet and the routing table into a second data packet; the routing table includes multiple routing entries. The hardware processor includes a packet distribution circuit, a traffic generation circuit, and a routing processing circuit. The packet distribution circuit is used to store the first data packet in the first storage module and the second data packet in the second storage module; The traffic generation circuit is used to parse the first data packet of the first storage module to obtain a traffic model, and while generating an initial message based on the traffic model, it sends the corresponding index information to the routing processing circuit. The routing processing circuit is used to obtain routing entries from the second storage module according to the index information, and return them to the traffic generation circuit so that the traffic generation circuit receives the routing entries when generating the routing entry insertion point of the initial message. The traffic generation circuit is also used to generate a target message based on the initial message and the routing entry returned by the routing processing circuit.

2. The flow generation device according to claim 1, characterized in that, When the packet distribution circuit is used to store the second data packet in the second storage module, it is specifically used to split the data of the value field in the second data packet into multiple first sub-data segments, and store the multiple first sub-data segments in the second storage module; wherein, the first sub-data segment is the routing data, and each first sub-data segment is stored in at least one storage address of the second storage module; When the routing processing circuit obtains routing entries from the second storage module based on the index information, it specifically determines at least one target storage address based on the index information, reads the first sub-data segment stored at each target storage address, parses the read at least one first sub-data segment to obtain routing entries, and returns them to the traffic generation circuit.

3. The flow generation device according to claim 1, characterized in that, When the packet distribution circuit stores the second data packet into the second storage module, it is specifically used to parse the data of the value field in the second data packet to obtain at least one routing entry, and store the parsed at least one routing entry into the second storage module; wherein, the routing entry is the routing data, and each routing entry is stored in a storage address of the second storage module; When the routing processing circuit obtains routing entries from the second storage module based on the index information, it specifically determines at least one target storage address based on the index information, reads the stored routing entries from each target storage address, and returns them to the traffic generation circuit.

4. The flow generation device according to claim 1, characterized in that, When the packet distribution circuit stores the second data packet into the second storage module, it specifically splits the routing data in the second data packet into multiple second sub-data segments, and stores the multiple second sub-data segments sequentially into multiple consecutive storage addresses of the second storage module; the length of the second sub-data segment is less than or equal to the storage bit width of the second storage module.

5. The flow generation device according to claim 1, characterized in that, The second storage module includes multiple memories. When the packet distribution circuit stores the second data packet into the second storage module, it specifically writes multiple routing data of the second data packet into the multiple memories in a sequential and cyclic manner according to the division order.

6. The flow generation device according to claim 5, characterized in that, The hardware processor includes multiple storage interfaces for connecting the multiple external memories.

7. The flow generation device according to claim 5, characterized in that, The memory space is divided into a first storage area and a second storage area; When the packet distribution circuit is used to sequentially and cyclically write multiple routing data of the second data packet into the memory according to the partitioning order, it is specifically used to sequentially and cyclically write multiple routing data of the second data packet received in the first configuration stage into the first storage area of ​​the memory according to the partitioning order, and to sequentially and cyclically write multiple routing data of the second data packet received in the second configuration stage into the second storage area of ​​the memory according to the partitioning order; the second configuration stage is the configuration stage after the first configuration stage.

8. The flow generation device according to any one of claims 1-7, characterized in that, The first data packet and the second data packet are TLV packets.

9. The flow generation device according to any one of claims 1-7, characterized in that, The traffic generation circuit is also used to generate a query instruction when a traffic generation trigger instruction is received, and to send the query instruction to the packet distribution circuit. The packet distribution circuit is also used to generate corresponding return information based on whether the first storage module is empty when the query instruction is received. When the traffic generation circuit is used to parse the first data packet of the first storage module to obtain the traffic model, it is specifically used to parse the first data packet of the first storage module to obtain the traffic model after receiving the return information corresponding to the non-empty first storage module.

10. The flow generation device according to claim 9, characterized in that, The traffic generation circuit is also used to obtain packet configuration information, which includes the number of packets and the number of routing entry insertion points for each packet, as well as the mapping relationship between each routing entry insertion point and a routing entry. The traffic generation circuit is used to generate an initial packet based on the traffic model and send the corresponding index information to the routing processing circuit. Specifically, it is used to generate an initial packet based on the traffic model and the packet configuration information, generate the corresponding index information based on the traffic model, and send the corresponding index information to the routing processing circuit. When the traffic generation circuit generates a target message based on the initial message and the routing entry returned by the routing processing circuit, it specifically adds the routing entry returned by the routing processing circuit to the routing entry insertion point corresponding to the initial message according to the mapping relationship to obtain the target message.

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