Method for determining critical threshold value of data retention capability and storage device

Abstract

The invention discloses a method for determining a critical threshold value of data retention capability and storage equipment. The method comprises the steps that the time consumed when a first storage block is baked at the first temperature and data cannot be decoded successfully is obtained and recorded as the first duration, and the first temperature is the temperature at which a flash memory storage medium can work normally; subtracting the reserved duration from the first duration to obtain a second duration; and after the first storage block is baked at the first temperature for a second duration, recording a first bias voltage and a first error bit proportion adopted by successful data decoding in the state. According to the method, buffer time is reserved, and the security level of data migration is higher.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method for determining a critical threshold for data retention capability and a storage device. Background Technology

[0002] Currently, many storage devices, such as USB flash drives, SD cards, CF cards, SSDs, eMMC embedded storage cards, and UFS devices, use flash memory as their primary storage medium, especially NAND flash memory, which is gradually becoming the mainstream form. Compared to traditional magnetic media storage, this represents a qualitative leap in performance.

[0003] Flash memory storage media comprises multiple flash memory chips, each flash memory chip consists of multiple memory blocks, each memory block consists of multiple memory cells, and each memory cell consists of at least one floating gate transistor. Over time and with the increase in the refresh rate of each memory block, the charge stored in the floating gate stage of the transistor changes, leading to a decrease in the data retention capability of the corresponding memory block. Therefore, it is necessary to move the data on the memory block to another location when the data retention capability of the memory block decreases to a critical threshold. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method for determining a critical threshold for data retention capability and a storage device, wherein when the data retention capability of a storage block decreases to a critical point, the data on the storage block is moved to another location.

[0005] According to a first aspect of this disclosure, a method for determining a critical threshold for data retention capability is provided. The method is used to determine the critical threshold for data retention capability of each storage block in a flash memory chip, wherein the flash memory storage medium includes multiple storage blocks. The method includes the following steps:

[0006] The time taken for the first storage block to be baked at the first temperature until the data cannot be successfully decoded is recorded as the first duration, where the first temperature is the temperature at which the flash memory storage medium can work normally.

[0007] The second duration is obtained by subtracting the reserved duration from the first duration;

[0008] After the first storage block is baked at the first temperature for a second duration, the first bias voltage and the percentage of first error bits used for successful data decoding in this state are recorded.

[0009] In some embodiments, multiple sample blocks are selected from the storage medium, and multiple durations are tested for the multiple sample blocks to be baked at a first temperature and reach the point where their respective data cannot be successfully decoded. The minimum value among the multiple durations is taken as the first duration, and the sample block corresponding to the minimum value is taken as the first storage block.

[0010] In some embodiments, the reserved duration is the predefined user power-off duration, the time consumed by the inspection interval, and the data migration duration.

[0011] In some embodiments, the decryption is hardware decoding.

[0012] In some embodiments, the method further includes: replacing the first temperature with a second temperature and performing the determination method of claim 1 to obtain a second bias voltage and a second error bit percentage.

[0013] In some embodiments, the reservation time of the corresponding storage block is updated according to the refresh count of each storage block of the flash memory chip.

[0014] According to a second aspect of this disclosure, a method for processing data retention capability is provided, the method being used in a storage device, the storage device including a flash memory storage medium and a controller, the flash memory storage medium comprising flash memory chips, the flash memory chips including a plurality of storage blocks, the method comprising:

[0015] The first bias voltage is obtained using the above determination method, and one or more memory blocks of the flash memory storage medium are scanned.

[0016] For each storage block, if the percentage of error bits obtained by scanning is equal to or exceeds the first percentage of error bits obtained by the determination method described above, then the data in that storage block is moved to another location.

[0017] According to a third aspect of this disclosure, a method for processing data retention capability is provided, the method being used in a storage device, the storage device including a flash memory storage medium and a controller, the flash memory storage medium comprising flash memory chips divided into multiple storage blocks, the method comprising:

[0018] One or more memory blocks of the flash memory storage medium are scanned using the first bias voltage and the second bias voltage, respectively.

[0019] For each storage block, if the percentage of error bits obtained from two scans exceeds the minimum of the first and second percentage of error bits determined by the above method, then the data in that storage block is moved to another location.

[0020] The first bias voltage and the first error bit percentage are obtained by the above determination method based on the first temperature, and the second bias voltage and the second error bit percentage are obtained by the above determination method based on the second temperature.

[0021] According to a fourth aspect of this disclosure, a storage device is provided, comprising: a controller coupled to a storage medium, the controller performing the method as described in any of the preceding claims.

[0022] According to a fifth aspect of this disclosure, a controller for a storage device is provided, the controller being coupled to a flash memory storage medium, the controller performing the method as described in any of the preceding claims.

[0023] The method for determining the critical threshold of data retention capability provided in this embodiment of the invention can obtain a more accurate critical threshold of data retention capability. By using this threshold, it is helpful to improve the efficiency of inspection. In addition, the method reserves enough time as a buffer, so the security level of data transfer is higher. Attached Figure Description

[0024] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic block diagram of an exemplary host system is shown;

[0026] Figure 2 This is a schematic diagram of an exemplary flash memory storage medium;

[0027] Figure 3 This is a flowchart of a method for determining the critical threshold for data retention capability provided in an embodiment of this disclosure;

[0028] Figure 4 An exemplary timeline for maintaining data accuracy in storage blocks is provided;

[0029] Figure 5 and Figure 6 Flowcharts of methods for processing data retention capabilities under two embodiments of this disclosure are shown respectively. Detailed Implementation

[0030] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0031] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0032] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0033] Figure 1 A schematic block diagram of an exemplary host system 100 is shown. The host system 100 is, for example, a personal computer, a laptop computer, or a server.

[0034] Host system 100 includes host device 110 (e.g., a computer system including a main processor and memory) and storage devices. Host device 110 can issue host commands to the storage device, causing the storage device to manage host data stored on the storage device according to the commands. For example, host device 110 can communicatively connect to the storage device (e.g., via host interface 121) and issue various commands to the storage device (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.). The storage device can store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once a command is executed, the storage device can transmit a response to host device 110, indicating that the command has been successfully completed.

[0035] The storage device comprises a controller 120 and a storage medium 130. The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a storage medium interface 128. The host interface 121 of the control system 120 is connected to the host device 110 and is used to buffer and transmit host commands and host data. The processor 123 is connected to the host interface 121, the cache unit 124, and the storage medium interface 128. The processor 123 parses host commands and executes corresponding operations. The cache unit 124, for example, is SRAM and / or DRAM, and can be used to store the mapping relationship between logical addresses and physical addresses, as well as some configuration data. The storage medium interface 128 includes interface circuitry for data transmission between the controller 120 and the storage medium 130.

[0036] The controller 120 also has a core software layer consisting of several programs executed by the processor 123 to perform management functions, including, for example, data read / write, bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques. The core software layer is typically formed as firmware.

[0037] Storage medium 130 stores host data. Multiple channels exist between storage medium 130 and storage medium interface 128 for transmitting host data. In this embodiment of the invention, storage medium 130 is defined as a flash memory storage medium composed of flash memory chips, particularly NAND flash memory mentioned in the background art.

[0038] Figure 2 This is a schematic diagram of an exemplary flash memory storage medium. Storage medium 130 has two flash memory dies, labeled die 0 to die 1 in the diagram. Based on the physical characteristics of the dies, each die includes four planes, labeled plane 0 to plane 3 in the diagram. Each plane includes several blocks, and each block is labeled 8N + X in the diagram, exemplarily grouped into groups of eight. Each block consists of several word lines, each word line includes several memory pages, and each block can store 16KB of valid data.

[0039] The connection channels between storage medium interface 128 and storage medium 130 are channel 0 and channel 1. Chip die 0 uses channel 0. Therefore, storage medium interface 128 accesses the various storage blocks on planes 0 to 3 of chip die 0 through channel 0, and accesses the various storage blocks on planes 0 to 3 of chip die 1 through channel 1. Relying on channels 0 to 1, storage medium interface 128 can access the corresponding storage blocks on storage medium 130 in parallel. For example, storage medium interface 128 writes or reads data to or from the corresponding storage blocks on storage medium 130 in parallel through channels 0 and 1.

[0040] To maintain data retention across all storage blocks, it is necessary to periodically perform operations such as... Figure 2The storage blocks of the storage medium 130 shown are scanned. This disclosure provides two inspection strategies: the first strategy scans only a portion of the storage blocks or pages, while the second strategy scans all storage blocks. Regardless of the inspection strategy used, it is necessary to determine the critical threshold for data retention capability of the storage blocks. The critical threshold refers to the point at which the data retention capability of a storage block drops to a critical threshold, indicating that the data in the storage block is in a dangerous state and data migration is necessary.

[0041] Figure 3 This is a flowchart of a method for determining a critical threshold for data retention capability provided in an embodiment of this disclosure. This method is used to determine, for example... Figure 2 The data retention capability critical threshold of each storage block on the flash memory storage medium 130 shown. Specifically, the following steps are included:

[0042] In step S301, the time taken for the first storage block to bake at the first temperature and reach the point where data cannot be successfully decoded is obtained.

[0043] Since the data retention capability of a storage block is strongly correlated with temperature, the core idea of ​​this embodiment transforms the data retention capability of a storage block into the question of how long the data in the storage block can remain correct at a given temperature. Based on this, this step first bakes the first storage block at a first temperature and records the start time. At regular intervals, it tests whether the data on the first storage block can be correctly decoded, until a certain moment when the data on the first storage block can no longer be correctly decoded. This moment is recorded as the end time. The end time minus the start time is the duration for which the data in the first storage block can remain correct at the first temperature.

[0044] The first storage block can be as follows: Figure 2 The flash memory storage medium 130 shown is an optional storage block; however, in some embodiments, it starts from, for example... Figure 2 Multiple sample blocks of varying quality are selected on the flash memory storage medium 130 shown. The time taken for the multiple sample blocks to bake at a first temperature and reach the point where their respective data cannot be successfully decoded is measured. The minimum value among the multiple time durations is recorded as the first time duration, and the sample block corresponding to the minimum value is recorded as the first storage block. However, in some embodiments, the first storage block is a storage block determined based on statistics and / or the physical characteristics of the flash memory chip, and the first storage block is preferably a storage block whose charge count is prone to change.

[0045] Decoding involves both hardware and software decoding. During a data read operation, a detection voltage is first applied to each memory cell on the memory block. Then, the voltage level of each memory cell is obtained, and it is determined whether the voltage level of each memory cell is higher or lower than a threshold voltage. Based on this determination, the bit data stored in each memory cell is determined, and this bit data is stored as hard information in a cache unit (e.g.,...). Figure 1 (In cache unit 124). Hard decoding uses a hard decoding algorithm to verify and correct the hard information in the cache. If the data verification and correction of some storage units fail, a new detection voltage is applied to the failed storage units to obtain new hard information. Then, the hard decoding algorithm is used to verify and correct the new hard information, and so on. When the number of verification and correction attempts for a storage unit exceeds the threshold, the verification and correction process for that storage unit is stopped. Soft decoding is usually for storage units that fail hard decoding. Specifically, when some storage units cannot be successfully decoded by hard decoding, the bias voltage is adjusted symmetrically left and right based on the optimal detection voltage for hard decoding to obtain multiple detection voltages. These multiple detection voltages are applied to the storage units that fail hard decoding to obtain soft information. The soft decoding algorithm is then used in combination with the hard information to continue decoding. The decoding referred to in step S301 is usually hard decoding, but this embodiment of the present disclosure does not limit this.

[0046] In step S302, the reserved duration is subtracted from the first duration to obtain the second duration.

[0047] If step S301 determines the duration for which the data in the first storage block can be maintained correctly at the first temperature, then this step subtracts the reserved buffering time from the first duration. The size of the reserved time can be defined in advance, generally considering three aspects: data transfer time, device power-off time, and the time consumed by the inspection interval.

[0048] 1) Data Migration Duration. Data migration requires time, so it cannot be delayed until the last minute. Data migration needs to be triggered in advance to allow sufficient time. Since the migration is performed while the device is running, let's assume, for example, that the migration takes 41 hours at 85°C to complete, corresponding to 0.5 seconds at 40°C. The specific migration time is determined by the program. Based on actual customer needs and ensuring no impact on user experience, the program conducts a full-device migration test using maximum bandwidth. The time taken in this test is the theoretical time required for data migration. The theoretical time can also be obtained through pure calculation, combined with the actual time obtained from testing. A suitable time is then determined by considering both. An example is given below. The formula for calculating the theoretical time is as follows:

[0049] (tRead * (Retry_Times + 1) + tProgram + IO_Speed ​​*Page_Size * (2 +Retry_Times) * Plane_Num) * Page_Num * Block_Num * CE_NUM,

[0050] Where tRead represents the time required to read data from the flash memory;

[0051] tProgram represents the time required to write data to the flash memory;

[0052] IO_Speed ​​indicates the I / O transfer speed between the flash memory and the controller;

[0053] Page_Size: Indicates the size of a storage page, typically around 18KByte;

[0054] Plane_NUM represents the number of planes in each die (flash memory chip);

[0055] Block_NUM represents the number of storage blocks in each plane;

[0056] Page_NUM: Represents the number of pages in each storage block;

[0057] CE_NUM represents the number of CE (Chip Enable) pins connected to the SSD device;

[0058] Retry_Times represents the average number of times the bias voltage needs to be reread when each memory block (Page) is moved.

[0059] Taking a 232-layer QLC (Quad-Level Cell, 4-bit data unit) NAND flash memory chip as an example, its NAND Read Latency is 46us, and its NAND Program Latency is 620us. Regarding controller I / O, assuming the controller can guarantee DDR400 bandwidth, the calculation is as follows: (89us + 480us + 400MTs * 18KB * 2 * 4) * 5544 * 430 * 8 = 18.6h + 6.1h * Retry_Times. Retry_times is the number of retries performed for each memory page. Due to the existence of two scanning strategies, this value is generally between 3 and 4. For this example, depending on the batch of flash memory chips, a theoretical time of 36h to 43h is reasonable. The actual time obtained in the test is the time consumed by performing a full disk relocation test after baking the flash memory chips.

[0060] 2) User Power-Off Duration. Since inspection strategies and data migration can only be performed with the device powered on, the retention effect when the device is not powered on needs to be accounted for. This requires a sufficiently long time. For example, if the user is required to power off for a maximum of six months, 41 hours of power-on time must be guaranteed. Since the power-off state is at room temperature, the data health consumption during six months of power-off is 40°C + 0.5Y. This can be set according to the warranty, such as a 2-year warranty, and can be weighed according to the actual needs of the product.

[0061] 3) Time consumed during the inspection interval. Inspections are not performed continuously, but at intervals, so this time also needs to be added. If the inspection plan is to perform an inspection every 6 hours, then the reserved time for the inspection interval is 12 hours. Since the inspection is carried out while the equipment is running, the time consumed for the inspection interval is 85°C + 12 hours (40°C + 0.15°Y).

[0062] Figure 4 An exemplary timeline for maintaining data accuracy in a memory block is provided. As shown in the figure, the final output of this example is: 40C 3Y - 0.5Y - 0.5Y - 0.15Y = 40C 1.85Y. This means that for the same batch of chip chips, each memory block needs to remove data when it reaches 40C 1.85Y.

[0063] In step S303, after the first storage block has been baked at the first temperature for a second duration, the first bias voltage and the percentage of first error bits used for successful data decoding in this state are recorded. The decoding in this step can be hardware decoding and / or software decoding, as described above.

[0064] This step converts the duration output in step S302 into a bias voltage and error bit percentage that the program can recognize, so that data can be moved by judging the offset voltage and error bit percentage in inspection or other scenarios.

[0065] In some embodiments, the reservation time used in step S302 is proportional to the number of refreshes of the flash memory chip. As the number of refreshes increases, the data retention capability of the flash memory chip will gradually decrease, and the reservation time may be insufficient. Therefore, it is necessary to incorporate the number of refreshes into the process. For example, a proportional relationship can be established between the number of refreshes and the reservation time. Each time an inspection is performed, the reservation time is calculated based on the current number of refreshes, and the first bias voltage and the first error bit percentage are recalculated based on the new reservation time.

[0066] Accordingly, embodiments of this disclosure also provide a method for processing data retention capabilities, wherein the storage device used in the method has and Figure 2Similar storage media. Furthermore, this method can also be formulated as a computer program, by... Figure 1 The controller 120 in the processor 123 processes the data, and the resulting computer program can be formed as follows: Figure 1 The firmware of the controller 120 in the memory is used to start and run the computer program when the storage device is powered on. Figure 5 and Figure 6 Flowcharts for two implementations of the method are shown respectively.

[0067] In step S501, one or more memory blocks of the flash memory storage medium are scanned based on a first bias voltage. Here, the first bias voltage is as follows: Figure 3 The first bias voltage output by the embodiment shown.

[0068] In step S502, for each storage block, if the percentage of error bits obtained from the scan is equal to or exceeds the first percentage of error bits, the data in that storage block is moved to another location. Here, the first percentage of error bits is as follows: Figure 3 The percentage of the first error bits output in the illustrated embodiment.

[0069] According to this embodiment, during the scanning process using the first inspection strategy or the second inspection strategy, a detection voltage equal to the reference voltage plus the first bias voltage is applied to each storage cell of one or more storage blocks of the flash memory storage medium and information is read. For each storage block, the read information is decoded by hardware decoding and / or software decoding. If it is determined that the percentage of error bits in each storage block is equal to or exceeds the first percentage of error bits, the data of that storage block is moved to another location.

[0070] In step S601, one or more memory blocks of the flash memory storage medium are scanned based on the first bias voltage.

[0071] In step S602, one or more memory blocks of the flash memory storage medium are scanned based on the second bias voltage.

[0072] In step S603, for each storage block, if the percentage of error bits obtained from two scans is equal to or exceeds the minimum of the first and second error bit percentages, then the data in that storage block is moved to another location. Here, the first bias voltage and the first error bit percentage are based on a first temperature as follows: Figure 3 The embodiment shown obtains that the second bias voltage and the second error bit ratio are based on the second temperature as follows: Figure 3 The example shown is obtained.

[0073] According to this embodiment, during the scanning process using the first inspection strategy or the second inspection strategy, two detection voltages are obtained by adding the reference voltage to the first bias voltage and the second bias voltage respectively, and the information is read from one or more memory blocks of the flash memory storage medium. For each memory block, the read information is decoded by hardware decoding and / or software decoding. If it is determined that the error bit ratio of each memory block is equal to or exceeds the minimum value of the first error bit ratio and the second error bit ratio, the data of the memory block is moved to another location.

[0074] In summary, the method for determining the critical threshold of data retention capability provided in this embodiment of the invention can obtain a relatively accurate critical threshold of data retention capability. By using the critical threshold, it is helpful to improve the efficiency of inspection. Furthermore, the method reserves sufficient time as a buffer, thus achieving a higher level of security for data transfer.

[0075] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for determining a critical threshold for data retention capability, the method being used to determine a critical threshold for data retention capability of each storage block of a flash memory chip, the flash memory chip comprising multiple storage blocks, the method comprising the following steps: The time taken for the first storage block to bake at the first temperature until the data cannot be successfully decoded is recorded as the first duration, and the first temperature is the temperature at which the flash memory chip can work normally. The second duration is obtained by subtracting the reserved duration from the first duration; After the first storage block has been baked at the first temperature for a second duration, the first bias voltage and the percentage of first error bits used for successful data decoding in this state are recorded.

2. The determination method according to claim 1, wherein, Multiple sample blocks are selected from the flash memory chip, and the multiple time intervals taken for the multiple sample blocks to bake at the first temperature and reach the point where their respective data cannot be successfully decoded are measured. The minimum value among the multiple time intervals is taken as the first time interval, and the sample block corresponding to the minimum value is taken as the first storage block.

3. The determination method according to claim 1, wherein, The reserved time is the predefined user power-off time, the time consumed by the inspection interval, and the data migration time.

4. The determination method according to claim 1, wherein, The decoding is hardware decoding.

5. The determining method according to claim 1, further comprising: The determination method of claim 1 is performed based on the second temperature to obtain the second bias voltage and the second error bit percentage.

6. The determining method according to claim 1, wherein, The reserved time for each storage block is updated according to the refresh count of each storage block of the flash memory chip.

7. A method for processing data retention capability, the method being used in a storage device, the storage device including a flash memory storage medium and a controller, the flash memory storage medium comprising flash memory chips, the flash memory chips comprising a plurality of storage blocks, the method comprising: The first bias voltage obtained by the determination method as described in any one of claims 1 to 4 and 6 is used to scan one or more memory blocks of the flash memory storage medium; For each storage block, if the percentage of error bits obtained by the scan is equal to or exceeds the first percentage of error bits obtained by the determination method as described in any one of claims 1 to 4 and 6, then the data in that storage block is moved to another location.

8. A method for processing data retention capability, the method being used in a storage device, the storage device including a flash memory storage medium and a controller, the flash memory storage medium comprising flash memory chips divided into multiple storage blocks, the method comprising: One or more memory blocks of the flash memory storage medium are scanned using the first bias voltage and the second bias voltage, respectively. For each storage block, if the percentage of error bits obtained from two scans exceeds the minimum of the first and second error bit percentages obtained by the determination method described in claim 5, then the data in that storage block is moved to another location. Wherein, the first bias voltage and the first error bit percentage are obtained based on a first temperature by the determination method according to any one of claims 1 to 4 and 6, and the second bias voltage and the second error bit percentage are obtained based on a second temperature by the determination method according to claim 5.

9. A storage device, comprising: A coupled controller and a flash memory storage medium, the controller performing the method as described in any one of claims 7 to 8.

10. A controller for a storage device coupled to a flash memory storage medium, the controller performing the method as described in any one of claims 7 to 8.

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