Cross-ISA mapping method for unified atomic electricity calculation semantic layer

Abstract

The invention discloses a cross-ISA mapping method for a unified atomic electricity calculation semantic layer, and relates to the field of electricity calculation fusion index measurement, and the method comprises the steps: 1, obtaining an instruction sequence of a to-be-evaluated or to-be-analyzed application on a target ISA; 2, according to a predefined UACES abstract instruction set, translating each instruction of the target ISA into one or more UACES atomic instructions according to an instruction set conversion translation rule; 3, performing bit width normalization metering on the obtained UACES atomic instruction according to a bit width scaling rule to obtain arithmetic, logic, memory access and control flow indexes based on 64 bits; and step 4, aggregating and analyzing normalized UACES instruction statistical results for scenes between different ISA, and providing a unified representation and measurement basis for semantic alignment and statistics in cross-ISA performance evaluation and reference comparison and instruction coding optimization.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of algorithmic electricity fusion index measurement, and particularly relates to a cross-ISA mapping method for unifying an atomic algorithmic electricity semantic layer. BACKGROUND

[0002] An application program written by a high-level language (such as a program written in C language) is usually different in assembly language generated by compiling under different ISAs (instruction set architectures). In order to measure the performance of the same application program under different ISAs, the instruction implementation of cross-ISA needs to be uniformly expressed. At present, the performance measurement of the application program under different ISAs is usually based on the measurement of the number of instructions, but there are significant differences in instruction complexity, addressing mode, use of condition code / flag, and coverage of composite instructions between RISC and CISC, so that the differences between instructions and addressing modes are easily ignored by directly measuring the number of instruction entries or addressing modes, thereby causing measurement deviation.

[0003] ARM supports conditional execution for a long time, has both pre-indexing / post-indexing and optional write-back in addressing, and includes the "load-update" type of composite operation in the semantic level; the RISC-V instruction encoding is mainly of fixed length, the addressing mode is relatively simple, and the conditional semantics is embodied by explicit comparison and branch instructions; the x86 adopts variable-length encoding, includes a prefix, a ModR / M and a SIB substructure, the prefix is used to modify the default behavior of the instruction, such as the number of operand bits and the number of address bits; the ModR / M is used to specify the operand type and the addressing mode (register or memory); the SIB is used for complex memory addressing (base + index + scale factor). The addressing can be combined as base+index*scale+displacement, wherein the base is a register providing a base value; the index is a register providing an index value; the scale is a scale factor used to match the width of different data types; and the displacement is a fixed offset for address calculation.

[0004] The flag FLAGS (such as the zero flag ZF, the carry / borrow flag CF, and the overflow flag OF) participates in comparison and jump, and the REP type of string instruction is compressed in the syntax level and is used for repeated execution.

[0005] The above differences result in that the same application program presents completely different instruction numbers and instruction structures under different ISAs, and it is difficult to accurately measure the real differences in underlying arithmetic, logic, memory and control flow if the instruction count or the addressing mode is directly compared.

[0006] Furthermore, because the same application exhibits drastically different instruction counts, instruction structures, and bit width distributions on different ISAs, existing cross-ISA performance evaluation and modeling methods based on instruction entries or simple memory access counts are unable to eliminate the differences between RISC / CISC in terms of instruction complexity, addressing modes, and conditional execution mechanisms, and cannot accurately reflect the true strength and semantic correspondence of arithmetic, logic, memory, and control flow. Summary of the Invention

[0007] The purpose of this invention is to provide a cross-ISA mapping method for a unified atomic computing-electrical semantic layer, and to construct a unified atomic computing-electrical semantic layer UACES (Unified Atomic Compute-Electric Semantics), which is an architecture-independent abstract instruction set "below the assembly layer".

[0008] UACES represents arithmetic, logic, memory access, and control flow under different ISAs using atomic instruction semantics and bit-width constraints as basic units. It processes complex addressing as "atomic instruction combination to synthesize address + unified LOAD / STORE memory access" and abstracts conditional semantics as "compare with zero (zero equivalence), signed / unsigned atomic instructions, etc." This enables cross-ISA semantic alignment without relying on specific ISA syntax details and different microarchitecture implementations. It also provides a unified representation and measurement basis for semantic alignment and statistics in cross-ISA performance evaluation and benchmarking, instruction-level simulation / performance analyzer, and instruction coding optimization.

[0009] To achieve the above objectives, the technical solution adopted by this invention is: a cross-ISA mapping method for a unified atomic computing semantic layer, comprising the following steps:

[0010] Step 1: Obtain the instruction sequence to be evaluated or analyzed on the target ISA;

[0011] Step 2: Based on the predefined UACES abstract instruction set, translate each instruction of the target ISA into one or more UACES atomic instructions according to the instruction set conversion and translation rules;

[0012] Step 3: Perform bit-width normalization measurement on the obtained UACES atomic instructions according to the bit-width scaling rules to obtain arithmetic, logic, memory access and control flow indicators based on 64 bits;

[0013] Step 4: Aggregate and analyze the normalized UACES instruction statistics for use in scenarios involving different ISAs.

[0014] In a preferred embodiment of the present invention, the definition rules of the abstract instruction set in step two include:

[0015] General bit width and ring semantics: The default bit width is 64 bits; the arithmetic results adopt the ring semantics of "mod 2^64", that is, the calculation results are uniformly processed modulo 2^64 within the range of (0, 2^64);

[0016] Bit width normalization measurement: using 64 bits as the default base, converting different bit widths to this base equivalently;

[0017] Operand and register conventions: rd is the result register, rs1 / rs2 are the source operands, and ra is the address / destination register; register namespaces are R0 to R63;

[0018] Immediate values ​​and register operands: The operands of atomic instructions are either registers or immediate values;

[0019] Addressing and memory access constraints: Memory access is only performed through a unified LOAD / STORE; complex addressing is first synthesized into an address register ra by atomic instructions, and then used by LOAD / STORE;

[0020] Control flow semantics: Conditions and branches are uniformly abstracted into control flow atomic instructions, which do not depend on ISA-specific condition codes / predicate syntax;

[0021] Combinatorial constructivism and functional singularity: Each atomic instruction has a single semantic meaning and can be combined to form complex operations.

[0022] In a preferred embodiment of the present invention, the specific content of the abstract instruction set in step two includes:

[0023] Arithmetic and logical atomic instructions:

[0024] ADD rd, rs1, rs2: Calculates rd ← (rs1 + rs2) mod 2^64, a 64-bit atomic addition instruction. Overflow is wrapped in two's complement. No condition code or flags are set.

[0025] SUB rd, rs1, rs2: rd ← (rs1 − rs2)mod 2^64, a 64-bit atomic subtraction instruction. Overflow is wrapped in two's complement. No condition code or flags are set.

[0026] MUL rd, rs1, rs2: rd ← (rs1 × rs2) mod 2^64, a 64-bit multiplication atomic instruction that returns the lower 64 bits;

[0027] DIV rd, rs1, rs2: rd ← (rs1 / rs2) mod 2^64, a 64-bit division atomic instruction;

[0028] AND rd, rs1, rs2: rd ← (rs1 & rs2) mod 2^64, a 64-bit bitwise AND atomic instruction;

[0029] OR rd, rs1, rs2: rd ← (rs1 | rs2) mod 2^64, a 64-bit bitwise OR atomic instruction;

[0030] XOR rd, rs1, rs2: rd ← (rs1 ^ rs2) mod 2^64, a 64-bit XOR atomic instruction;

[0031] NOT rd, rs1: rd ← (~ rs1) mod 2^64, a 64-bit non-atomic instruction that inverts each bit of rs1;

[0032] Memory access atomic instructions:

[0033] LOAD rd, [ra]: Loads 64 bits from the absolute memory address specified by ra into rd. Only supports addressing where the address is given by a register. Complex addressing is achieved by combining atomic instructions to synthesize the address first.

[0034] STORE rs, [ra]: Writes the 64-bit data in register rs to the absolute address given in register ra;

[0035] Control flow atomic instructions:

[0036] JMP ra: Jump unconditionally to the absolute address given by register ra;

[0037] BRZ ra, rs: If register rs is zero, i.e. all bits are zero, then jump to the absolute address given by ra;

[0038] BRNZ ra, rs: If register rs is not zero, jump to the absolute address given by ra;

[0039] CALL ra: Procedure call and return, with ra as the return address;

[0040] Other atomic instructions:

[0041] MOV rd, rs: Copies the value of register rs to rd.

[0042] In a preferred embodiment of the present invention, the instruction set conversion translation rules in step two include:

[0043] (1) Arithmetic and logical operation instruction translation rules:

[0044] For the x86-64 architecture: the first source operand is copied to the destination register using a single MOV instruction before the operation is performed;

[0045] For the ARM64 architecture: arithmetic logic instructions are directly mapped one-to-one to UACES atomic instructions;

[0046] (2) Memory access instruction translation rules:

[0047] For the x86-64 architecture: the load instruction mov rD, [rA] is translated as LOAD rD, [rA], and the store instruction mov[rA], rS is translated as STORE rS, [rA]. When x86-64 uses complex addressing mode, the address register must first be synthesized by combining atomic instructions before performing a unified memory access.

[0048] For the ARM64 architecture: the load instruction ldr xD, [xA] is translated as LOAD rD, [rA], and the store instruction strxS, [xA] is translated as STORE rS, [rA]; the ARM64 base address plus offset addressing ldr xD, [xN, #disp] is translated as: ADD rA, rN, disp; LOAD rD, [rA];

[0049] (3) Control flow instruction translation rules:

[0050] For the x86-64 architecture: the unconditional jump instruction jmp rA is translated to JMP rA; conditional jumps are implemented using the TEST instruction in conjunction with conditional jumps.

[0051] For the ARM64 architecture: the unconditional jump instruction br xA is translated as JMP rA; the conditional jump instruction cbz xS,label is translated as BRZ label, rS, cbnz xS,label is translated as BRNZ label, rS; and the function call blr xA is translated as CALL rA.

[0052] (4) Register mapping convention:

[0053] The x86-64 general-purpose registers rAX, rBX, rCX, rDX, rSI, rDI, rBP, and rSP are mapped to UACES registers R0 to R7, respectively. The ARM64 general-purpose registers x0 to x30 are mapped to UACES registers R0 to R30, respectively. Zero register mapping is achieved through the XOR operation, that is, XOR Rd, Rd, Rd sets the target register to zero.

[0054] (5) Bit width normalization processing:

[0055] When the operand width of the target ISA instruction is not 64 bits, normalization is performed according to the bit width scaling rules.

[0056] (6) Rules for decomposing complex instructions:

[0057] For compound instructions containing multiple atomic operations, they are semantically decomposed into multiple UACES atomic instruction sequences.

[0058] As a preferred embodiment of the present invention, in step three, the weight is calculated linearly by bit width as follows: weight(w bits) = w / 64, where w represents the bit width of the instruction operand, in bits.

[0059] In a preferred embodiment of the present invention, the atomic combination specification for address synthesis in the addressing and memory access constraints is as follows:

[0060] Objective: To unify complex addressing into a single register ra, followed by memory access using LOAD rd, [ra] or STORE rs, [ra], where base represents the base address register, disp represents the offset, index represents the index register, and scale represents the scaling factor, including:

[0061] Case 1: Base address + offset (base + disp) ra ← base + disp: ADD ra, base, disp;

[0062] Case 2: Index × Scale (index × scale, scale∈{1,2,4,8,…}) ra ← index × scale:

[0063] MUL ra, index, scale;

[0064] Case 3: Base address + index × scale factor (base + index × scale) ra ← base + index × scale:

[0065] MUL ra, index, scale;

[0066] ADD ra, ra, base;

[0067] Case 4: Base address + Index × Scale factor + Shift (base + index × scale + disp)ra ← base + index × scale + disp, two additions are sufficient to preserve order:

[0068] MUL ra, index, scale;

[0069] ADD ra, ra, base;

[0070] ADD ra, ra, disp.

[0071] In a preferred embodiment of the present invention, step four, specifically includes:

[0072] S41: Instruction Classification Statistics:

[0073] Based on the functional types of UACES atomic instructions, the translated instruction sequences are divided into four categories for statistical analysis: arithmetic operations, logical operations, memory access operations, and control flow operations. For each category of instructions, the number of executions is counted, and the equivalent 64-bit instruction count is calculated according to the bit width normalization rule. The specific statistical formula is: Ni' = Σ(wj / 64) × nij, where Ni' represents the normalized statistical result of the i-th instruction, wj represents the bit width of the j-th instruction, and nij represents the number of executions of the j-th instruction.

[0074] S42: Strength Index Calculation:

[0075] Based on the classification statistics, four strength indicators are calculated: Arithmetic Strength AI, Logical Strength LI, Memory Access Strength MI, and Control Flow Strength CI. Arithmetic Strength AI is defined as the ratio of the normalized total number of arithmetic operation instructions to the total number of instructions, i.e., AI = NA / Ntotal, where NA is the normalized count of arithmetic operation instructions and Ntotal is the sum of the normalized counts of all instructions. Similarly, Logical Strength LI = NL / Ntotal, Memory Access Strength MI = NM / Ntotal, and Control Flow Strength CI = NC / Ntotal.

[0076] S43: Cross-ISA Comparison Analysis:

[0077] For the execution of the same application on different ISAs, the instruction sequences of each ISA are translated into UACES atomic instructions and statistically analyzed to compare the differences in their strength indicators. By calculating similarity, the similarity of execution behavior between different ISAs is quantified. Specifically, the similarity between ISA1 and ISA2 is defined as Sim(ISA1,ISA2) = (AI1×AI2 + LI1×LI2 + MI1×MI2 + CI1×CI2) / √(AI1²+LI1²+MI1²+CI1²) × √(AI2²+LI2²+MI2²+CI2²). The closer the similarity value is to 1, the more similar the execution behavior of the two ISAs is.

[0078] S44: Performance Efficiency Assessment:

[0079] Combining the normalized index based on 64-bit obtained in step three, the computing power output efficiency per unit power consumption is calculated; the computing power efficiency index CEI is defined as Ntotal / P, where Ntotal is the total number of normalized UACES instructions and P is the power consumption during execution; by comparing the CEI values ​​of different ISAs, their energy efficiency performance in the same application scenario is evaluated, providing a basis for decision-making on hardware selection, compilation optimization and system scheduling.

[0080] Compared with the prior art, the technical solution proposed in this invention has the following technical effects:

[0081] 1. Design of Unified Atomic Arithmetic Semantic Layer (UACES) and its Abstract Instruction Set: Under the "assembly layer", a small number of semantically singular and composable atomic instructions are used to uniformly represent the arithmetic, logic, memory access, and control flow behaviors of different ISAs (including address synthesis + unified LOAD / STORE and control flow atomic instructions such as BRZ / BRNZ / JMP / CALL), achieving consistent semantic representation and alignment across ISAs and reducing comparison bias caused by differences in instruction encoding and condition code mechanisms.

[0082] 2. Bit width normalization measurement rule based on 64-bit benchmark: Using 64-bit as a unified benchmark, different bit widths such as 8 / 16 / 32 / 64 / 128-bit are linearly converted according to w / 64, so as to uniformly measure the operation and memory access intensity under different ISAs, reduce the statistical bias caused by the difference in data bit width, and improve the comparability and stability of cross-ISA performance evaluation and cost modeling.

[0083] 3. Semantic mapping and unified measurement method across ISAs from specific ISAs to UACES: The mapping rules and implementation examples of typical ISAs such as x86-64 and ARM-64 to UACES atomic instructions are given. The instruction sequences are classified and statistically analyzed using the UACES layer as a unified intermediary, so as to realize the quantitative comparison of the execution behavior of the same application on different ISAs in a unified semantic space.

[0084] 4. By constructing a unified atomic computing semantic layer (UACES) and providing corresponding bit-width normalization measurement rules and cross-ISA semantic mapping methods, this invention can map the arithmetic, logic, memory access, and control flow behaviors of the same application on different ISAs to a unified and measurable semantic space without relying on specific ISA syntax details and microarchitecture implementations. This significantly improves the accuracy of semantic alignment and the interpretability of indicator statistics in engineering scenarios such as cross-ISA performance evaluation, instruction-level simulation analysis, and compiler backend optimization, and reduces the structural bias caused by traditional statistics based on instruction entries or addressing methods. Attached Figure Description

[0085] Figure 1This is a schematic diagram illustrating the bit width scaling calculation rules for the weights relative to 64 bits in this embodiment.

[0086] Figure 2 This is a schematic diagram illustrating the mapping relationship between UACES atomic instructions and x86-64 and ARM-64 (AArch64) instructions in this embodiment.

[0087] Figure 3 This is a schematic diagram of procedure 1 in this embodiment.

[0088] Figure 4 This is a schematic diagram of the X86 assembly code corresponding to Program 1 in this embodiment.

[0089] Figure 5 This is a schematic diagram of the UACES atomic instruction conversion result corresponding to the X86 assembly code of Program 1 in this embodiment.

[0090] Figure 6 This is a schematic diagram of the ARM assembly code corresponding to program 1 in this embodiment.

[0091] Figure 7 This is a schematic diagram of the UACES atomic instruction conversion result corresponding to the ARM assembly of Program 1 in this embodiment.

[0092] Figure 8 This is a schematic diagram of a cross-ISA mapping method for a unified atomic computing semantic layer in this embodiment. Detailed Implementation

[0093] The technical solution of the present invention will be explained in detail below with reference to the accompanying drawings and specific embodiments.

[0094] Because the same application exhibits drastically different instruction counts, instruction structures, and bit width distributions on different ISAs, existing cross-ISA performance evaluation and modeling methods based on instruction entries or simple memory access counts are insufficient to eliminate the differences in instruction complexity, addressing modes, and conditional execution mechanisms between RISC and CISC, and cannot accurately reflect the true strength and semantic correspondence of arithmetic, logic, memory, and control flow. This embodiment constructs a unified atomic computation-electrical semantic layer (UACES), proposing a cross-ISA semantic alignment and measurement method that unifies the abstraction of instruction semantics across different ISAs "below the assembly layer" and normalizes the measurement of different bit widths and addressing modes. This provides a measurement basis for cross-ISA performance evaluation and benchmarking.

[0095] In this context, "computer semantics" refers to abstracting the underlying operations actually performed by instructions, focusing on arithmetic / logic operations and their bit widths, without relying on specific encoding forms. "Semantics" in this context refers to the essential meaning of what an instruction truly does, rather than its syntax or encoding within a particular instruction set.

[0096] For example, a prefixed addition instruction in x86, a conditionally executable addition instruction in ARM, and a regular addition instruction in RISC V have different "syntaxes," but their essential "semantics" are all addition. We extract these essential actions into a unified "atomic instruction semantics" and ignore the superficial differences in encoding length, addressing form, condition codes, etc., among different ISAs, making it easier to compare them under the same conditions.

[0097] Specifically, such as Figure 8 As shown, this embodiment discloses a cross-ISA mapping method for a unified atomic computing semantic layer, including the following steps:

[0098] 1. Obtain the instruction sequence to be evaluated or analyzed on the target ISA.

[0099] 2. Based on the predefined UACES abstract instruction set, translate each instruction of the target ISA into one or more UACES atomic instructions according to the instruction set conversion translation rules.

[0100] 3. The obtained UACES atomic instructions are normalized according to the bit width scaling rules to obtain arithmetic, logic, memory access and control flow indicators based on 64 bits.

[0101] 4. Aggregate and analyze the normalized UACES instruction statistics for engineering scenarios such as performance evaluation, cost modeling, or instruction-level simulation between different ISAs.

[0102] The instruction set definition rules are as follows:

[0103] 1) General bit width and ring semantics: The default bit width is 64 bits; the arithmetic result adopts the ring semantics of "mod 2^64", that is, the calculation result is uniformly processed in the range of [0,2^64) modulo 2^64, so as to align the overflow / carry processing of different ISAs in this field.

[0104] 2) Bit width normalization measurement: Using 64 bits as the default benchmark, different bit widths are equivalently converted to this benchmark. For example, two 32-bit instructions are equivalent to one 64-bit instruction; the weight of one 32-bit instruction is counted as 0.5 64-bit instructions.

[0105] 3) Operand and register conventions: rd is the result register, rs1 / rs2 are the source operands, and ra is the address / destination register; register namespaces are R0 to R63.

[0106] 4) Immediate values ​​and register operands: The operands of atomic instructions can be registers or immediate values.

[0107] 5) Addressing and memory access constraints: Memory access is only performed through a unified LOAD / STORE; complex addressing (such as base + index × scale + disp or base address + offset) must first be combined by atomic instructions to form the address register ra, and then used by LOAD / STORE.

[0108] 6) Control flow semantics: Conditions and branches are uniformly abstracted into control flow atomic instructions (such as BRZ / BRNZ / JMP / CALL), which do not depend on ISA-specific condition codes / predicate syntax.

[0109] 7) Combinatorial constructs and single function: Each atomic instruction has a single semantic meaning and can be combined to form more complex operations.

[0110] like Figure 1 As shown, the bit width scaling calculation rule has the following weights relative to 64 bits:

[0111] Weights are calculated linearly with bit width: weight(w bits) = w / 64.

[0112] Example: If a program contains 3 32-bit ADDs and 1 128-bit LOAD, then its 64-bit normalized count is 1.5 ADDs and 2 LOADs.

[0113] The atomic combination specification for address synthesis is:

[0114] Objective: To unify complex addressing into a single register ra, which can then be accessed via LOAD rd, [ra] or STORE rs, [ra], where base represents the base address register, disp represents the offset, index represents the index register, and scale represents the scaling factor.

[0115] 1) Base address + offset (base + disp) ra ← base + disp:

[0116] ADD ra, base, disp;

[0117] 2) Index × Scale (index × scale, scale∈{1,2,4,8,…}) ra ← index ×scale:

[0118] MUL ra, index, scale;

[0119] 3) Base address + index × scaling factor (base + index × scale) ra ← base + index × scale:

[0120] MUL ra, index, scale;

[0121] ADD ra, ra, base;

[0122] 4) Base address + index × scale factor + displacement (base + index × scale + disp) ra ← base + index × scale + disp (two additions are sufficient to preserve order):

[0123] MUL ra, index, scale;

[0124] ADD ra, ra, base;

[0125] ADD ra, ra, disp

[0126] The specific contents of the instruction set are as follows:

[0127] (1) Arithmetic and logical atomic instructions

[0128] ADD rd, rs1, rs2: Calculates rd ← (rs1 + rs2) mod 2^64, a 64-bit atomic addition instruction. Overflow is wrapped in two's complement. No condition code or flags are set.

[0129] SUB rd, rs1, rs2: rd ← (rs1 − rs2)mod 2^64, a 64-bit subtraction atomic instruction with the same semantics as above.

[0130] MUL rd, rs1, rs2: rd ← (rs1 × rs2) mod 2^64, a 64-bit multiplication atomic instruction that returns the lower 64 bits.

[0131] DIV rd, rs1, rs2: rd ← (rs1 / rs2) mod 2^64, a 64-bit division atom instruction.

[0132] AND rd, rs1, rs2: rd ← (rs1 & rs2) mod 2^64, a 64-bit bitwise AND atomic instruction.

[0133] OR rd, rs1, rs2: rd ← (rs1 | rs2) mod 2^64, a 64-bit bitwise OR atomic instruction.

[0134] XOR rd, rs1, rs2: rd ← (rs1 ^ rs2) mod 2^64, a 64-bit XOR atomic instruction.

[0135] NOT rd, rs1: rd ← (~ rs1) mod 2^64, a 64-bit NOT atomic instruction (inverts each bit of rs1).

[0136] (2) Memory access atomic instructions

[0137] LOAD rd, [ra]: Takes 64 bits from the absolute memory address specified by ra and puts them into rd. Only naive addressing with "address given by register" is supported; more complex addressing is achieved by combining atomic instructions to synthesize the address first.

[0138] STORE rs, [ra]: Writes the 64-bit data from register rs to the absolute address given by register ra.

[0139] (3) Control flow atomic instructions

[0140] JMP ra: Jump unconditionally to the absolute address given by register ra;

[0141] BRZ ra, rs: If register rs is zero (all bits are zero), then jump to the absolute address given by ra;

[0142] BRNZ ra, rs: If register rs is not zero, jump to the absolute address given by ra;

[0143] CALL ra: Procedure call and return, with ra as the return address.

[0144] (4) Other atomic instructions

[0145] MOV rd, rs: Copies the value of register rs to rd.

[0146] The instruction set conversion translation rules include:

[0147] (1) Arithmetic and logical operation instruction translation rules:

[0148] For the x86-64 architecture: Because x86-64 uses a two-address format, the destination operand is also the first source operand. Therefore, a MOV instruction is needed to copy the first source operand to the destination register before performing the operation. For example, the x86-64 addition instruction `add rD, rS2` is translated into the UACES atomic instruction sequence: `MOV rD, rD; ADD rD, rD, rS2`. The multiplication instruction `imul rD, rS2` is translated into: `MOV rD, rD; MUL rD, rD, rS2`. The division instruction `div rS2` uses a fixed combination of the rdx and rax registers and is translated into: `MOV rax, rS1; XOR rdx, rdx; DIV rD, rax, rS2; MOV rD, rax`. Logical operation instructions (such as `and rD, rS2`) also follow this rule and are translated into: `MOV rD, rD; AND rD, rD, rS2`.

[0149] For the ARM64 architecture: Because ARM64 uses a three-address format, the destination register and source register are specified independently. Therefore, arithmetic and logical instructions can be directly mapped one-to-one to UACES atomic instructions. For example, add xD, xN, xM is translated as ADD rD, rN, rM; sub xD, xN, xM is translated as SUB rD, rN, rM; mul xD, xN, xM is translated as MUL rD, rN, rM; and udiv xD, xN, xM is translated as DIV rD, rN, rM. Logical operation instructions (such as and xD, xN, xM) are translated as ANDrD, rN, rM.

[0150] (2) Memory access instruction translation rules:

[0151] For the x86-64 architecture: the load instruction `mov rD, [rA]` is translated as `LOAD rD, [rA]`, and the store instruction `mov[rA], rS` is translated as `STORE rS, [rA]`. When x86-64 uses complex addressing mode, the address register must first be synthesized through atomic instruction combination before a unified memory access is performed. For example, base-address-offset addressing `mov rD, [rBX+disp]` is translated as: `ADDrA, rBX, disp; LOAD rD, [rA]`.

[0152] For the ARM64 architecture: the load instruction `ldr xD, [xA]` is translated as `LOAD rD, [rA]`, and the store instruction `strxS, [xA]` is translated as `STORE rS, [rA]`. Similarly, the ARM64 base-address offset addressing instruction `ldr xD, [xN, #disp]` is translated as: `ADD rA, rN, disp`; `LOAD rD, [rA]`.

[0153] (3) Control flow instruction translation rules:

[0154] For the x86-64 architecture: the unconditional jump instruction `jmp rA` is translated as `JMP rA`. Conditional jumps are implemented using the `TEST` instruction, for example, `test rS, rS`; `jz label` is translated as `SUB rT, rS, rS`; `BRZ label, rT`. The `TEST` instruction uses subtraction to detect zero values. Similarly, `jnz label` is translated as `BRNZlabel, rS`. The function call instruction `call rA` is translated as `CALL rA`.

[0155] For the ARM64 architecture: Unconditional jump `br xA` is translated as `JMP rA`. Conditional jump instructions `cbz xS, label` (jump to zero on comparison) are directly translated as `BRZ label, rS`, and `cbnz xS, label` (jump to non-zero on comparison) are translated as `BRNZlabel, rS`. Function calls `blr xA` are translated as `CALL rA`.

[0156] (4) Register mapping convention:

[0157] To maintain semantic consistency, a unified register mapping relationship is established during the translation process. For x86-64, general-purpose registers rAX, rBX, rCX, rDX, rSI, rDI, rBP, and rSP are mapped to UACES registers R0 through R7, and the remaining registers are mapped sequentially. For ARM64, general-purpose registers x0 through x30 are mapped to UACES registers R0 through R30. Zero register mapping is achieved through XOR operations; that is, XOR Rd, Rd, Rd sets the target register to zero.

[0158] (5) Bit width normalization processing:

[0159] When the operand width of the target ISA instruction is not 64 bits, normalization is performed according to the bit width scaling rules. For example, when the 32-bit addition instruction `add eax, ebx` is translated into a UACES atomic instruction, it is weighted at 0.5 based on a 64-bit baseline, which is equivalent to half a 64-bit ADD instruction. 128-bit SIMD instructions are weighted at 2.0.

[0160] (6) Rules for decomposing complex instructions:

[0161] For compound instructions containing multiple atomic operations, they are semantically decomposed into multiple UACES atomic instruction sequences. For example, the x86-64 instruction lea rD, [rS1+rS2*4] (effective address calculation) is decomposed into: MUL rT, rS2, 4; ADD rD, rS1, rT. The ARM64 instruction mul xD, xN, xM; add xD, xD, xA (multiply-accumulate instruction) is decomposed into: MUL rT, rN, rM; ADD rD, rT, rA.

[0162] Figure 2 This is an example of the mapping relationship between UACES atomic instructions and x86-64 and ARM-64 (AArch64) instructions. To maintain semantic consistency, 64-bit general-purpose registers are used uniformly (x86-64 uses rAX / rBX / rCX / rDX / ..., ARM-64 uses x0..x30).

[0163] Figure 2 In the table, rD / rS / rA are placeholders corresponding to specific registers. In x86-64, lea rD, [rS1+rS2] can also perform addition, but here the add form is used uniformly to align semantics.

[0164] Example 1:

[0165] like Figures 3-7 As shown, this embodiment selects a simple loop program containing integer addition operations for testing (hereinafter referred to as Program 1). The main function of Program 1 is to execute 10 billion loop iterations, and in each loop, add two preset 64-bit integer constants and save the result. Figure 3 The C source code for Program 1 is given, which defines two 64-bit unsigned integer constants a and b, and a loop counter N, and repeatedly performs addition operations through a for loop structure.

[0166] Compile Program 1 into x86-64 and ARM64 assembly code respectively, and obtain Figure 4 and Figure 6The assembly instruction sequence is shown. Comparing the assembly code of the two ISAs reveals significant differences: In terms of instruction count, the x86-64 version contains approximately 28 assembly instructions, while the ARM64 version contains approximately 25; in terms of addressing modes, x86-64 uses a base pointer plus offset addressing mode (e.g., [rbp-16]), while ARM64 uses a stack pointer plus offset addressing mode (e.g., [sp,32]); in terms of constant loading, x86-64 uses the movabs instruction to directly load 64-bit immediate values, while ARM64 loads constants in segments using a combination of mov and movk instructions; in terms of conditional jumps, x86-64 uses a combination of cmp and jb, while ARM64 uses the cmp plus bhi unsigned greater than jump instruction.

[0167] According to the instruction set conversion translation rules described in this invention, x86-64 assembly code is translated into UACES atomic instruction sequences, resulting in... Figure 5 The results are shown. The translation process mainly includes: First, translating the function prologue part of x86-64 (push rbp; mov rbp, rsp) into UACES stack frame saving operations; Second, translating the constant loading instruction movabs into an ADD instruction combined with immediate operands; Third, decomposing the memory access instruction mov QWORD PTR [rbp-8], rax into a combination of address calculation (SUB instruction synthesizes offset address) and STORE instruction; Fourth, translating the addition instruction add rax, rdx in the loop body into UACES ADD instruction; Fifth, translating the loop control instruction cmp rax, [rbp-8]; jb .L3 into a subtraction-based zero-value detection and BRNZ conditional jump instruction.

[0168] Similarly, translating the ARM64 assembly code into a UACES atomic instruction sequence yields... Figure 7 The results are shown. The translation process includes: translating the ARM64 stack allocation instructions sub sp, sp, #48 into UACES SUB instructions; translating the constant loading instructions combined with mov and movk into ADD instructions; translating the memory access instructions str and ldr into STORE and LOAD instructions; directly mapping the add instruction to the UACES ADD instruction; and translating the combination of cmp and bhi into SUB subtraction instructions in conjunction with BRNZ conditional jumps.

[0169] contrast Figure 5 and Figure 7The UACES conversion results show that, despite significant differences in instruction format, addressing mode, and instruction count between the original x86-64 and ARM64 assembly codes, the atomic instruction sequences obtained by the two ISAs after the UACES mapping of this invention are highly consistent in structure and semantics. Both conversion results contain the same core operations: ADD instructions for constant initialization, STORE instructions for variable storage, ADD addition operations within loop bodies, LOAD / STORE memory access operations, and BRNZ-based loop control. Statistical results show that the x86-64 version converts to approximately 45 UACES atomic instructions, while the ARM64 version converts to approximately 43 UACES atomic instructions, a difference of only about 4.4%, far less than the difference in the number of instructions in the original assembly code.

[0170] The above UACES conversion results were aggregated and analyzed as follows: First, the atomic instructions were classified and statistically analyzed according to their functional types. For the 45 atomic instructions of the x86-64 version, 12 arithmetic operation instructions were identified (10 ADD instructions and 2 SUB instructions), 0 logical operation instructions, 28 memory access operation instructions (14 LOAD instructions and 14 STORE instructions), and 5 control flow instructions (1 JMP instruction and 4 BRNZ instructions). For the 43 atomic instructions of the ARM64 version, 12 arithmetic operation instructions were identified (10 ADD instructions and 2 SUB instructions), 0 logical operation instructions, 26 memory access operation instructions (13 LOAD instructions and 13 STORE instructions), and 5 control flow instructions (1 JMP instruction and 4 BRNZ instructions).

[0171] Next, calculate the strength metrics. For the x86-64 version, the arithmetic strength AI = 12 / 45 ≈ 0.267, the logic strength LI = 0 / 45 = 0, the memory access strength MI = 28 / 45 ≈ 0.622, and the control flow strength CI = 5 / 45 ≈ 0.111. For the ARM64 version, the arithmetic strength AI = 12 / 43 ≈ 0.279, the logic strength LI = 0 / 43 = 0, the memory access strength MI = 26 / 43 ≈ 0.605, and the control flow strength CI = 5 / 43 ≈ 0.116.

[0172] Third, a cross-ISA comparative analysis was performed. The similarity between the two ISAs was calculated: Sim(x86-64,ARM64) = (0.267×0.279 + 0×0 + 0.622×0.605 + 0.111×0.116) / √(0.267²+0²+0.622²+0.111²)× √(0.279²+0²+0.605²+0.116²) ≈ 0.999. The similarity value is very close to 1, indicating that the two ISAs have highly consistent execution behavior in procedure 1, thus verifying the effectiveness of the method of this invention.

[0173] Finally, a performance efficiency evaluation is performed. Assuming the power consumption of executing Program 1 on the x86-64 platform is 2.8 Joules, and the power consumption of the ARM64 platform is 2.5 Joules, then the power efficiency index (CEI) for the x86-64 version is 45 / 2.8 ≈ 16.07, and the CEI for the ARM64 version is 43 / 2.5 ≈ 17.20. The comparison shows that in the Program 1 scenario, the ARM64 platform outperforms the x86-64 platform in terms of energy efficiency. This result provides a quantitative basis for hardware selection.

[0174] It should be understood that although this specification describes the system according to embodiments, not every embodiment contains only one independent technical solution. This narrative style is only for clarity, and those skilled in the art should consider this specification as a whole. The technical features in each embodiment can also be reasonably combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A cross-ISA mapping method for unified atomic computing semantic layer, characterized by: Includes the following steps: Step 1: Obtain the instruction sequence to be evaluated or analyzed on the target ISA; Step 2: Based on the predefined UACES abstract instruction set, translate each instruction of the target ISA into one or more UACES atomic instructions according to the instruction set conversion and translation rules; Step 3: Perform bit-width normalization measurement on the obtained UACES atomic instructions according to the bit-width scaling rules to obtain arithmetic, logic, memory access and control flow indicators based on 64 bits; Step 4: Aggregate and analyze the normalized UACES instruction statistics for use in scenarios involving different ISAs.

2. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 1, characterized in that, In step two, the definition rules for the abstract instruction set include: General bit width and ring semantics: The default bit width is 64 bits; the arithmetic results adopt the ring semantics of "mod 2^64", that is, the calculation results are uniformly processed modulo 2^64 within the range of (0, 2^64); Bit width normalization measurement: using 64 bits as the default base, converting different bit widths to this base equivalently; Operand and register conventions: rd is the result register, rs1 / rs2 are the source operands, and ra is the address / destination register; register namespaces are R0 to R63; Immediate values ​​and register operands: The operands of atomic instructions are either registers or immediate values; Addressing and memory access constraints: Memory access is only performed through a unified LOAD / STORE; complex addressing is first synthesized into an address register ra by atomic instructions, and then used by LOAD / STORE; Control flow semantics: Conditions and branches are uniformly abstracted into control flow atomic instructions, which do not depend on ISA-specific condition codes / predicate syntax; Combinatorial constructivism and functional singularity: Each atomic instruction has a single semantic meaning and can be combined to form complex operations.

3. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 1, characterized in that, In step two, the specific content of the abstract instruction set includes: Arithmetic and logical atomic instructions: ADD rd, rs1, rs2: Calculates rd ← (rs1 + rs2) mod 2^64, a 64-bit atomic addition instruction. Overflow is wrapped in two's complement. No condition code or flags are set. SUB rd, rs1, rs2: rd ← (rs1 − rs2)mod 2^64, a 64-bit atomic subtraction instruction. Overflow is wrapped in two's complement. No condition code or flags are set. MUL rd, rs1, rs2: rd ← (rs1 × rs2) mod 2^64, a 64-bit multiplication atomic instruction that returns the lower 64 bits; DIV rd, rs1, rs2: rd ← (rs1 / rs2) mod 2^64, a 64-bit division atomic instruction; AND rd, rs1, rs2: rd ← (rs1 & rs2) mod 2^64, a 64-bit bitwise AND atomic instruction; OR rd, rs1, rs2: rd ← (rs1 | rs2) mod 2^64, a 64-bit bitwise OR atomic instruction; XOR rd, rs1, rs2: rd ← (rs1 ^ rs2) mod 2^64, a 64-bit XOR atomic instruction; NOT rd, rs1: rd ← (~ rs1) mod 2^64, a 64-bit non-atomic instruction that inverts each bit of rs1; Memory access atomic instructions: LOAD rd, [ra]: Loads 64 bits from the absolute memory address specified by ra into rd. Only supports addressing where the address is given by a register. Complex addressing is achieved by combining atomic instructions to synthesize the address first. STORE rs, [ra]: Writes the 64-bit data in register rs to the absolute address given in register ra; Control flow atomic instructions: JMP ra: Jump unconditionally to the absolute address given by register ra; BRZ ra, rs: If register rs is zero, i.e. all bits are zero, then jump to the absolute address given by ra; BRNZ ra, rs: If register rs is not zero, jump to the absolute address given by ra; CALL ra: Procedure call and return, with ra as the return address; Other atomic instructions: MOV rd, rs: Copies the value of register rs to rd.

4. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 1, characterized in that, In step two, the instruction set conversion translation rules include: (1) Arithmetic and logical operation instruction translation rules: For the x86-64 architecture: the first source operand is copied to the destination register using a single MOV instruction before the operation is performed; For the ARM64 architecture: arithmetic logic instructions are directly mapped one-to-one to UACES atomic instructions; (2) Memory access instruction translation rules: For the x86-64 architecture: the load instruction mov rD, [rA] is translated as LOAD rD, [rA], and the store instruction mov [rA], rS is translated as STORE rS, [rA]. When x86-64 uses complex addressing mode, the address register must first be synthesized by combining atomic instructions before performing a unified memory access. For the ARM64 architecture: the load instruction ldr xD, [xA] is translated as LOAD rD, [rA], and the store instruction str xS, [xA] is translated as STORE rS, [rA]; the ARM64 base address plus offset addressing ldr xD, [xN, #disp] is translated as: ADDrA, rN, disp; LOAD rD, [rA]; (3) Control flow instruction translation rules: For the x86-64 architecture: the unconditional jump instruction jmp rA is translated to JMP rA; conditional jumps are implemented using the TEST instruction in conjunction with conditional jumps. For the ARM64 architecture: the unconditional jump instruction br xA is translated as JMP rA; the conditional jump instruction cbz xS, label is translated as BRZ label, rS, cbnz xS, label is translated as BRNZ label, rS, and the function call blr xA is translated as CALLrA; (4) Register mapping convention: The x86-64 general-purpose registers rAX, rBX, rCX, rDX, rSI, rDI, rBP, and rSP are mapped to UACES registers R0 to R7, respectively. The ARM64 general-purpose registers x0 to x30 are mapped to UACES registers R0 to R30, respectively. Zero register mapping is achieved through the XOR operation, that is, XOR Rd, Rd, Rd sets the target register to zero. (5) Bit width normalization processing: When the operand width of the target ISA instruction is not 64 bits, normalization is performed according to the bit width scaling rules. (6) Rules for decomposing complex instructions: For compound instructions containing multiple atomic operations, they are semantically decomposed into multiple UACES atomic instruction sequences.

5. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 1, characterized in that, In step three, the weight is calculated linearly by bit width as follows: weight(w bits) = w / 64, where w represents the bit width of the instruction operand, in bits.

6. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 2, characterized in that, In the addressing and memory access constraints, the atomic combination specification for address synthesis is as follows: Objective: To unify complex addressing into a single register ra, followed by memory access via LOAD rd, [ra] or STORE rs, [ra], including: Case 1: Base address + offset (base + disp) ra ← base + disp: ADD ra, base, disp; Case 2: Index × Scale (index × scale, scale∈{1,2,4,8,…}) ra ← index × scale: MUL ra, index, scale; Case 3: Base address + index × scale factor (base + index × scale) ra ← base + index × scale: MUL ra, index, scale; ADD ra, ra, base; Case 4: Base address + Index × Scale factor + Shift (base + index × scale + disp)ra ← base + index × scale + disp, two additions are sufficient to preserve order: MUL ra, index, scale; ADD ra, ra, base; ADD ra, ra, disp; Where base represents the base address register, disp represents the offset, index represents the index register, and scale represents the scaling factor.

7. The cross-ISA mapping method for the unified atomic computing semantic layer according to claim 1, characterized in that, In step four, the aggregation and analysis specifically include: S41: Instruction Classification Statistics: Based on the functional types of UACES atomic instructions, the translated instruction sequences are divided into four categories for statistical analysis: arithmetic operations, logical operations, memory access operations, and control flow operations. For each category of instructions, the number of times they are executed is counted, and the equivalent number of 64-bit instructions is calculated according to the bit width normalization rule. The specific statistical formula is: Ni' = Σ(wj / 64) × nij, where Ni' represents the normalized statistical result of the i-th type of instruction, wj represents the bit width of the j-th instruction, and nij represents the number of times the j-th instruction is executed. S42: Strength Index Calculation: Based on the classification statistics, four strength indicators are calculated: Arithmetic Strength AI, Logical Strength LI, Memory Access Strength MI, and Control Flow Strength CI. Arithmetic Strength AI is defined as the ratio of the normalized total number of arithmetic operation instructions to the total number of instructions, i.e., AI = NA / Ntotal, where NA is the normalized count of arithmetic operation instructions and Ntotal is the sum of the normalized counts of all instructions; Logical Strength LI = NL / Ntotal, Memory Access Strength MI = NM / Ntotal, and Control Flow Strength CI = NC / Ntotal. S43: Cross-ISA Comparison Analysis: For the execution of the same application on different ISAs, the instruction sequences of each ISA are translated into UACES atomic instructions and statistically analyzed to compare the differences in their strength indicators. By calculating similarity, the similarity of execution behavior between different ISAs is quantified. Specifically, the similarity between ISA1 and ISA2 is defined as Sim(ISA1,ISA2) = (AI1×AI2 + LI1×LI2 +MI1×MI2 + CI1×CI2) / √(AI1²+LI1²+MI1²+CI1²) × √(AI2²+LI2²+MI2²+CI2²). The closer the similarity value is to 1, the more similar the execution behavior of the two ISAs is. S44: Performance Efficiency Assessment: Combining the normalized index based on 64-bit obtained in step three, the computing power output efficiency per unit power consumption is calculated; the computing power efficiency index CEI is defined as Ntotal / P, where Ntotal is the total number of normalized UACES instructions and P is the power consumption during execution; by comparing the CEI values ​​of different ISAs, their energy efficiency performance in the same application scenario is evaluated, providing a basis for decision-making on hardware selection, compilation optimization and system scheduling.

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