Circuits, chips, and electronic devices that control the direction of data read and write in an I2C hub chip.

Abstract

The application discloses a circuit for controlling data read-write direction in an I2C HUB chip, a chip and electronic equipment, and belongs to the technical field of integrated circuit communication. In view of the problems of level lock and communication interruption caused by bidirectional transmission in the multi-slave I2C bus expansion, the application integrates a voltage detection circuit at each slave side port, monitors the SDA line level state of each SSP in real time, and uses a centralized control N-input NAND gate to uniformly generate the control signal of the pull-down driving tube of the host side port, so as to realize automatic and reliable switching of the data transmission path. The application is suitable for the multi-slave I2C bus expansion system, such as the fields of intelligent devices, industrial control, sensor networks and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit communication technology, and more specifically to a circuit, chip, and electronic device for controlling the direction of data read and write in an I2C HUB chip. Background Technology

[0002] The I2C bus, as a simple and efficient serial communication protocol, is widely used for short-distance communication between various integrated circuits such as microcontrollers, sensors, and memory. This bus employs an open-drain output structure, requiring pull-up resistors to maintain a default high level. It uses wired-AND logic to achieve multi-master, multi-slave communication. When multiple masters initiate communication simultaneously, the wired-AND logic can perform preliminary bus arbitration through level contention. When multiple slaves respond to communication, level superposition ensures the consistency of the bus signals. However, this bus structure has inherent limitations: if any device on the bus outputs a low level, a clamping effect will keep the entire bus at a low level. During bus expansion, a single device malfunction can easily cause communication interruptions, threatening system stability.

[0003] In practical electronic systems, a master device typically needs to communicate with multiple slave devices to achieve collaborative operation, such as data exchange between a microcontroller and multiple sensors. However, due to the limited load capacity of the I2C bus, exceeding the limit can lead to signal attenuation, increased bit error rate, or even communication interruption. Therefore, I2C hubs are widely used for bus expansion. As a repeater, it connects to the master device through a master-side port (MSP) and to different slave devices through multiple slave-side ports (SSPs), enabling bidirectional transmission and distribution of clock (SCL) and data (SDA) signals. Simultaneously, the I2C hub provides port isolation, blocking signal crosstalk between SSPs and ensuring data consistency across the entire network, thereby effectively expanding bus load capacity and improving communication stability.

[0004] Because the I2C bus is bidirectional, the hub must precisely control the data direction when transmitting signals; otherwise, level lock-up can easily occur. Specifically, when the host sends a low-level signal to a slave device on an SSP via the MSP, if the hub does not block the reverse path, this low-level signal may be fed back to the MSP through other SSPs, forming a positive feedback loop with the low-level signal output by the host. This causes the MSP to be continuously clamped to a low level. Even if the host subsequently releases the bus, the feedback low level will remain in a locked state, ultimately causing the entire I2C system to malfunction.

[0005] Currently, mature solutions for point-to-point I2C bus expansion include I2C buffers and repeaters. These devices detect port levels using analog comparators and automatically control the on / off state of unidirectional transmission paths: when a low level is detected from the master output, the master-to-slave path is enabled while the reverse path is disabled to prevent low-level feedback; after the master releases the bus, the path is switched to ensure slave signal transmission. This solution effectively solves the lock-up problem in point-to-point scenarios. However, this type of solution is only suitable for single master-to-slave connections and cannot meet the practical needs of multi-slave interconnection.

[0006] For I2C hubs with multiple SSP ports, existing technologies have significant shortcomings. Traditional point-to-point buffers cannot be directly adapted because their path control logic can only handle unidirectional transmission between two ports. However, multi-SSP hubs need to coordinate complex bidirectional data interactions between the master and multiple slaves. This requires not only directional data transmission from the master to the target slave but also accurate data distribution to non-target slaves, while ensuring the unidirectional nature of data feedback from slaves to the master. Simply adopting a "multi-buffer stacking" structure with independent control circuitry for each SSP leads to two problems: firstly, it significantly increases the complexity, area, and power consumption of the internal chip circuitry, driving up design costs; secondly, the response speeds of the control circuits at each SSP differ, easily causing timing conflicts when switching directions, leading to multi-path contention, bus level fluctuations, and reduced communication stability.

[0007] Therefore, there is an urgent need in this field for a communication control scheme suitable for multi-port I2C HUB chips. This scheme should have the ability to automatically and reliably determine the direction of read and write operations, completely avoid level lock-up through an intelligent internal data transmission path switching mechanism, and efficiently complete data exchange between the host and the target slave and data distribution to non-target slaves, so as to meet the high stability and high reliability requirements of multi-slave I2C bus expansion. Summary of the Invention

[0008] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows:

[0009] On one hand, this invention discloses a circuit for controlling the data read / write direction in an I2C HUB chip, comprising the following steps:

[0010] Each SSP of the I2C HUB chip is equipped with a voltage detection circuit and an output driver stage circuit.

[0011] The voltage detection circuit is used to monitor the SDA line level status of the SSP in real time.

[0012] Connect the output signal of the voltage detection circuit of each SSP to the enable terminal of the output driver stage circuit of the SSP respectively.

[0013] The output signals of the voltage detection circuits of all SSPs are connected to the input of an N-input NAND gate, where N is the number of SSPs;

[0014] The output signal of the N-input NAND gate is used to control the on / off state of the pull-down drive transistor of the MSP;

[0015] When any SSP's output driver circuit is enabled, it transmits the MSP's SDA signal to the SDA line of the SSP; when any SSP's output driver circuit is disabled, it disconnects from the SDA line of the SSP.

[0016] In one embodiment, the voltage detection circuit is implemented using a comparator.

[0017] In one embodiment, the comparator includes a first input terminal and a second input terminal, the first input terminal of the comparator being connected to the SSP SDA line, and the second input terminal of the comparator being connected to the reference voltage VREF.

[0018] In one embodiment, the comparator outputs a logic low level when the voltage of the SSP SDA line is lower than the reference voltage VREF; and outputs a logic high level when the voltage of the SSP SDA line is higher than the reference voltage VREF.

[0019] In one embodiment, when the output signal of the N-input NAND gate is at a logic high level, the pull-down driver of the MSP is turned on; when the output signal of the N-input NAND gate is at a logic low level, the pull-down driver of the MSP is turned off.

[0020] In one embodiment, during a host write operation, the comparators of all SSPs output a high level, enabling the output driver stages of all SSPs and disabling the pull-down driver transistors of the MSPs, thereby distributing data from the MSPs to all SSPs.

[0021] In one embodiment, when the host performs a read operation and the target slave sends a low-level signal, the comparator of the SSP where the target slave is located outputs a low-level signal, disables the output driver stage of the SSP where the target slave is located, and enables the pull-down driver transistor of the MSP, thereby enabling the transmission of the low-level signal from the SSP where the target slave is located to the host and the SSPs where the non-target slave is located via the MSP.

[0022] On the other hand, this invention discloses an I2C HUB chip, comprising:

[0023] One MSP, the MSP SDA line is connected to the pull-down drive transistor;

[0024] Multiple SSPs, each SSP including a voltage detection circuit and an output driver stage circuit;

[0025] An N-input NAND gate is used. The input of the N-input NAND gate is connected to the output of the voltage detection circuit of each SSP, and the output of the N-input NAND gate is connected to the control terminal of the pull-down driver transistor of the MSP, where N is the number of SSPs.

[0026] And, as described in the previous item, a circuit in the I2C HUB chip that controls the direction of data read / write.

[0027] In one embodiment, the pull-down driving transistor of the MSP is an NMOS transistor, the source of the pull-down driving transistor of the MSP is grounded, the drain of the pull-down driving transistor of the MSP is connected to the SDA line of the MSP, and the control terminal of the pull-down driving transistor of the MSP receives the output signal of the N-input NAND gate.

[0028] On the other hand, the present invention discloses an electronic device comprising an I2CHUB chip as described in any of the preceding claims.

[0029] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0030] (1) It effectively avoids the problem of level lock-up and has high reliability and high timeliness;

[0031] (2) Automatic and intelligent switching of transmission direction without external intervention, resulting in a simpler circuit structure;

[0032] (3) It also has data distribution function, is compatible with standard I2C protocol, and is easy to expand system.

[0033] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0034] Figure 1 This is a typical I2C HUB structure diagram;

[0035] Figure 2 This is a circuit diagram illustrating the automatic control of the read / write operation direction of this invention.

[0036] Figure 3 This is a flowchart illustrating the automatic control method for read / write operations of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0038] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.

[0039] The term "target slave" refers to a slave device that is exchanging data with the master in a specific I2C communication transaction. The master addresses and selects the target slave by sending a data frame containing the slave's address. In a multi-slave system, only one slave is the target slave at any given time, while the others are non-target slaves.

[0040] This invention is applied in I2C networks and involves the following core components:

[0041] Master Side Port IO (MSP): This is a bidirectional IO port that connects the I2C HUB to the upstream host (such as a CPU, MCU, or other control device) to enable data interaction between the I2C HUB and the host.

[0042] Slave Side Port IO (SSP): This is a bidirectional IO port for connecting an I2C hub to downstream slave devices (such as sensors, memory, and other controlled devices). An I2C hub typically contains multiple SSPs to enable data interaction between the I2C hub and different slave devices.

[0043] I2C Hub: As a repeater between a master and multiple slave devices, its core functions include: enabling bidirectional data transmission between the master and slave devices; distributing data to non-target slave devices; ensuring data consistency throughout the I2C network; and achieving reliable data relay between the master and multiple slave devices.

[0044] Pull-down driver transistor: The pull-down driver transistor is a transistor located inside the MSP, typically an NMOS transistor. Its source is grounded, its drain is connected to the MSP's SDA line, and its gate is controlled by a control logic signal (in this invention, the output of an N-input NAND gate). When this transistor is turned on (enabled), it pulls the MSP's SDA line low.

[0045] Figure 1 This is a typical I2C hub diagram. The structure includes one MSP (Master Service Provider) and multiple SSPs (Slave Service Providers). The MSP connects to the upstream host, and the SSPs connect to the downstream slaves. Because the I2C bus uses a bidirectional open-drain architecture, the data line (SDA) exhibits bidirectional transmission characteristics. Therefore, directly connecting the MSP and SSP inside the hub can lead to a low-level lockout. For example, if the SDA on the MSP is pulled low at a certain moment, this low-level signal is transmitted to the SSP via the hub; if the SSP also shows a low level at this time, the signal may be fed back to the MSP, forming a closed-loop lockout. In this situation, even if the host attempts to release the bus to output a high level, the signal remains low due to the closed-loop structure, resulting in communication abnormalities.

[0046] In one specific embodiment of the present invention, the I2C HUB chip employs an automatic data read / write direction control method. This method ensures that when the host initiates a read / write operation, it correctly forwards control commands and data signals, and guarantees that the data state presented on the slave bus connected to each SSP remains consistent with the data received or sent by the MSP. Specifically, when the host sends data to a slave, only the forward path from MSP to SSP is opened; when the slave replies to the host, the reverse path from SSP to MSP is switched, thereby physically blocking feedback loops that could cause level lock-up and ensuring that the bus can return to a high-level state normally. Furthermore, this I2C HUB also has a data distribution function. When the host communicates with a slave, the HUB can simultaneously distribute the transmitted data to all other slaves, ensuring data consistency throughout the I2C network. Devices throughout the I2C network can monitor the communication content on the current bus, which is beneficial for applications such as multi-device synchronization or status monitoring.

[0047] Figure 2 This is a circuit diagram illustrating the automatic control of read / write operation direction according to the present invention. As shown in the figure, the I2C HUB chip system includes one master-side port (MSP) and multiple slave-side ports (N, where N is a positive integer). Figure 2The structure is illustrated using SSP0 and SSPN as examples; the structures of the remaining SSPs are the same. The MSP is used to connect to the upstream host (such as a CPU or MCU), and internally contains a controllable pull-down driver transistor directly controlled by control logic signals. The source of this pull-down driver transistor is grounded, its drain is directly connected to the SDA line of the MSP, and its gate is controlled by the logic signal output of an N-input NAND gate. When the gate is turned on, it pulls the SDA line of the MSP low. The slave-side ports (SSP0 to SSPN) are used to connect to downstream slave devices (such as sensors or EEPROMs). Each SSP port integrates two key circuits: a voltage detection circuit (preferably implemented using a comparator, referred to as a voltage detection comparator below) and an output driver stage circuit. The output signals of the voltage detection comparators on all SSP ports are uniformly connected to the inputs of an N-input NAND gate, whose output signal directly controls the gate of the pull-down driver transistor of the MSP port. This centralized control architecture ensures the simplicity of the control logic and high-speed response.

[0048] Furthermore, one input of each voltage sense comparator is connected to the SDA line of its corresponding SSP port, and the other input is connected to the reference voltage VREF (Voltage Reference Element). The value of VREF is typically set near the low-level threshold specified by the I2C protocol. When the voltage on the SSP SDA line is lower than VREF, the voltage sense comparator outputs a low level (logic low "0"); otherwise, it outputs a high level (logic high "1"). The output signal of the voltage sense comparator is used to determine whether the corresponding slave device is actively pulling the bus low.

[0049] Furthermore, the output driver stage circuit is a buffer (or driver) controlled by an enable signal. Its input is connected to the MSP SDA line, and its output is connected to the corresponding SSP SDA line. The enable terminal is only controlled by the output signal of the voltage detection comparator on this port. When enabled, it can transmit the signal on the MSP SDA line to the SSP SDA line; when disabled, its output is in a high-impedance state and disconnected from the SSP SDA line, thereby avoiding interference with the signal on that cable.

[0050] Figure 3 This is a flowchart illustrating the automatic control method for read / write operations of the present invention. As shown in the figure, the present invention automatically identifies whether the current communication is a host write operation or a host read operation by detecting the status of each SSP port, and controls the connection or disconnection of the data transmission path accordingly.

[0051] During a master write operation, the master sends data (address, command, or write data) to the target slave. All slaves are in receive mode and do not actively pull down the SSP SDA line. Since none of the slaves are driving the bus, the SDA line of all SSPs (SSP0 to SSPN) is pulled high by their pull-up resistors. Therefore, the voltage sense comparator inside each SSP detects a high level (the voltage sense comparator voltage is greater than the reference voltage VREF), meaning its output is always a logic high level "1". Because the voltage sense comparator outputs of all SSPs are high, the output driver stage of all SSPs is enabled. At this time, the master controls the high and low levels of the MSP SDA line. These changes are transmitted simultaneously to all SSP ports (SSP0 to SSPN) through all enabled driver stages, realizing the function of distributing data to all slaves. Simultaneously, since all signals input to the N-input NAND gate are logic high "1", its output signal is logic low "0". This signal disables the pull-down driver transistor of the MSP port, thereby cutting off all feedback paths from SSP to MSP. In this case, the data flow direction is MSP→SSP0 to SSPN (the symbol "→" indicates that the data flow direction is from the former to the latter, and the same applies below). Because the path from MSP to SSP is unidirectional, and the path from SSP to MSP is physically disconnected, the possibility of forming a low-level latch-up loop is completely eliminated, while ensuring the correct distribution of data.

[0052] When a master read operation is in progress and the target slave needs to send a low-level signal to the master, the master requests to read data from the target slave (taking SSP0 as an example). The target slave (connected to SSP0) sends a low-level signal by pulling the SDA line low. The voltage detection comparator inside SSP0 detects the low level (the voltage detection comparator voltage is less than the reference voltage VREF), and its output signal becomes a logic low level "0". The SDA line from SSP1 to SSPN, which is connected to a non-target slave, remains high, meaning that the voltage detection comparator inside SSP1 to SSPN detects a high level (the voltage detection comparator voltage is greater than the reference voltage VREF), and the output signal of the voltage detection comparator corresponding to the non-target slave remains a logic high level "1". Since the voltage detection comparator output signal of SSP0 is a logic low level "0", this signal disables the output driver stage circuit of SSP0. Therefore, the bidirectional loop between MSP and SSP0 is broken, preventing the low level of MSP from feeding back to the slave that is sending data. The voltage detection comparators from SSP1 to SSPN still output a logic high level "1", therefore, the corresponding output driver stages from SSP1 to SSPN remain enabled. Simultaneously, since one of the input signals of the N-input NAND gate is a logic low level "0" (SSP0), and the rest are logic high level "1", according to the NAND gate logic, the output signal of the N-input NAND gate becomes a logic high level "1". This signal enables the pull-down driver transistor of the MSP port, thereby pulling the MSP SDA line low. Thus, the low level generated by the target slave on SSP0 is successfully transmitted to the MSP through the enabled pull-down driver transistor, and the master receives this logic low level "0" signal, realizing the function of transmitting the low-level signal generated by the target slave to the master. Meanwhile, the voltage detection comparator outputs of the remaining non-target slave devices (SSP1 to SSPN) remain high, and their output drivers remain enabled. Therefore, the low-level signal on the MSP SDA line (i.e., the signal received by the master) is also distributed to all non-target slave devices, ensuring the synchronization and consistency of the entire network data. In this case, for the transmission of low-level signals, the data flow direction is SSP0 → MSP → SSP1 to SSPN. Similarly, the system always maintains unidirectional transmission, effectively avoiding level lock-up and perfectly realizing the distribution of read data. When the target slave device needs to send a logic high level "1", the target slave device only needs to release the bus, and the bus is automatically pulled high by the pull-up resistor. The system state automatically returns to the initial state where all voltage detection comparators output high, all SSP driver stages are enabled, and the MSP pull-down transistors are disabled.

[0053] The above-described implementation achieves real-time, automatic, and reliable control of data transmission direction through the collaboration of analog detection circuits and digital logic circuits. Particularly noteworthy is the innovative use of a centralized control architecture, employing a simple N-input NAND gate to uniformly manage all SSP-to-MSP transmissions. Compared to the complex structure of traditional solutions where each port requires independent control logic, this invention significantly simplifies circuit design and improves system reliability. The entire control process is completed automatically by hardware, requiring no host intervention and not relying on clock signals, thus ensuring the real-time performance and stability of the system response.

[0054] This invention is not limited to the specific circuit implementation described above. For example, the voltage detection function can also be implemented by a Schmitt trigger combined with logic circuits. The core control logic can also be implemented by using other gate circuits such as NOR gates and adjusting the control polarity accordingly. All technical solutions formed by equivalent substitution or equivalent transformation fall within the protection scope of this invention.

[0055] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.

[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit for controlling the data read / write direction in an I2C HUB chip, characterized in that: Each slave-side port (SSP) of the I2C HUB chip is equipped with a voltage detection circuit and an output driver stage circuit; the voltage detection circuit is used to monitor the SDA line level status of the SSP in real time. The output signal of the voltage detection circuit of each SSP is connected to the enable terminal of the output driver stage circuit of its respective SSP; the output signals of the voltage detection circuits of all SSPs are connected to the input terminal of an N-input NAND gate, where N is the number of SSPs. The output signal of the N-input NAND gate is used to control the on / off state of the pull-down drive transistor of the host-side port MSP; wherein, when the output drive stage circuit of any SSP is in the enabled state, the SDA signal of the MSP is transmitted to the SDA line of the SSP. When any output driver stage circuit of an SSP is disabled, the output driver stage circuit is disconnected from the SDA line of the SSP. Specifically, when the voltage detection circuits of all SSPs output a high level, the output driver stage circuits of all SSPs are enabled, and the N-input NAND gate outputs a low level to turn off the pull-down driver transistor of the MSP; when the voltage detection circuit of any SSP outputs a low level, the output driver stage circuit of that SSP is disabled, and the N-input NAND gate outputs a high level to turn on the pull-down driver transistor of the MSP.

2. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 1, characterized in that: The voltage detection circuit is implemented using a comparator.

3. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 2, characterized in that: The comparator includes a first input terminal and a second input terminal. The first input terminal of the comparator is connected to the SSP and SDA lines, and the second input terminal of the comparator is connected to the reference voltage VREF.

4. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 3, characterized in that: When the voltage of the SSP SDA line is lower than the reference voltage VREF, the comparator outputs a logic low level; When the voltage on the SSP SDA line is higher than the reference voltage VREF, the comparator outputs a logic high level.

5. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 1, characterized in that: When the output signal of the N-input NAND gate is at a logic high level, the pull-down driver of the MSP is enabled; When the output signal of the N-input NAND gate is at a logic low level, the pull-down driver transistor of the MSP is turned off.

6. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 1, characterized in that: During a host write operation, the comparators of all SSPs output a high level, enabling the output driver stage of all SSPs and disabling the pull-down driver transistor of the MSP, so as to achieve the purpose of distributing data from the MSP to all SSPs.

7. The circuit for controlling the data read / write direction in an I2C HUB chip according to claim 1, characterized in that: When the host performs a read operation and the target slave sends a low-level signal, the comparator of the SSP where the target slave is located outputs a low-level signal, disabling the output driver stage of the SSP where the target slave is located and enabling the pull-down driver transistor of the MSP, thus enabling the transmission of the low-level signal from the SSP where the target slave is located to the host and the SSPs where the non-target slave is located via the MSP.

8. An I2C HUB chip, characterized in that, include: One host-side port MSP, the MSP SDA line is connected to a pull-down drive transistor; Multiple slave-side port SSPs, each SSP including a voltage detection circuit and an output drive stage circuit; An N-input NAND gate is used. The input of the N-input NAND gate is connected to the output of the voltage detection circuit of each SSP, and the output of the N-input NAND gate is connected to the control terminal of the pull-down driver transistor of the MSP, where N is the number of SSPs. And, the circuit for controlling the data read / write direction in the I2C HUB chip as described in any one of claims 1-7.

9. The I2C HUB chip according to claim 8, characterized in that: The pull-down drive transistor of the MSP is an NMOS transistor. The source of the pull-down drive transistor of the MSP is grounded, and the drain of the pull-down drive transistor of the MSP is connected to the SDA line of the MSP. The control terminal of the pull-down drive transistor of the MSP receives the output signal of the N-input NAND gate.

10. An electronic device, characterized in that: The electronic device includes an I2C HUB chip as described in any one of claims 8-9.

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