A network packet parsing device and chip

By leveraging the state control unit-driven cyclic parsing mechanism and template flexibility, the problems of high hardware resource overhead and fixed parsing levels are solved, enabling flexible network packet parsing, reducing hardware costs and latency, and improving processing efficiency.

CN121728177BActive Publication Date: 2026-05-26SHENZHEN JAGUAR MICROSYSTEMS CO LTD
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Patent Information

Application Number
CN202610215815.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-02-14
Publication Date
2026-05-26
Estimated Expiration
2046-02-14

AI Technical Summary

Technical Problem

In existing technologies, network packet parsing devices have high hardware resource overhead, cannot flexibly adapt to different protocols and parsing depths, and the traditional pipelined parsing chain has a fixed number of parsing levels, which cannot parse packets exceeding the preset number of levels.

Method used

A network packet parsing device is adopted, including a packet receiving module, a scheduling output module, and multiple network packet parsing engines. It performs cyclic parsing through a state control unit, dynamically selects the target logical unit, and realizes the reuse of L2, L3, L4 and L5 packet parsing logical units. Combined with fixed and custom parsing templates, it supports flexible parsing of different protocols and depths.

Benefits of technology

It reduces hardware resource requirements, chip area and power consumption, improves flexibility and scalability, can adapt to complex protocol combinations and extremely deep encapsulation layers, and ensures message processing efficiency and throughput.

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Abstract

This application relates to a network packet parsing device and chip, comprising: a packet receiving module that, upon receiving a packet to be parsed, selects an idle network packet parsing engine and sends the packet to the selected engine; the selected engine performs cyclic parsing of the packet and outputs the parsing result to a scheduling output module; in each round of cyclic parsing, a state control unit obtains the parsing status and header position of the current round, and selects a target parsing logic unit from multiple parsing logic units based on the parsing status; the selected target parsing logic unit parses the packet based on the parsing status and header position, and outputs the parsing result to the state control unit; the state control unit also determines whether to end the cyclic parsing based on the parsing status; finally, the scheduling output module outputs the received parsing result to a subsequent module.
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Citation Information

Patent Citations

  • Message header analysis device and method, equipment, storage medium and program product

    CN119316496A