Running ahead branch target buffer

Abstract

A branch target buffer structure is provided. A device may include a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers having gradually slowed access times. The apparatus may include a first program counter configured to generate a first program counter value associated with executing a next instruction of the application. The apparatus may include a second program counter configured to predict a second program counter value associated with executing a subsequent instruction of the application following the next instruction. The apparatus may include a first branch prediction circuit configured to populate a branch target buffer of the branch target buffers based on a second program counter value.

Description

BACKGROUND

[0001] In computing, processor pipeline design benefits from attempting to predict which next instruction might be executed after execution of a current instruction. Execution of a current instruction can result in a branch to one of two or more next instructions. Instruction branch speculation is used to determine the most likely next instruction, called the target instruction.

[0002] Pipeline design splits a computing operation into multiple stages. Each stage is typically performed by dedicated hardware. An example computing pipeline includes the following stages: (i) fetch an instruction, (ii) read the instruction, (iii) decode the instruction, (iv) execute the decoded instruction, (v) access memory to read an operand from memory, and (vi) write a result to memory. Each stage relies on the output of the previous stage to perform its operation. The next instruction begins passing through the pipeline before the first instruction passes through the pipeline, rather than waiting for the first instruction to pass through the entire pipeline.

[0003] Traditionally, branch speculation is achieved by predicting the target of a branch. When the instruction set architecture supports, these targets can be fixed (unconditional direct branch), variable (indirect branch), two (taken, not taken) (conditional branch), or a combination of fixed, two, or variable.

[0004] To perform such prediction, different algorithms exist that use specialized storage (often called a branch target buffer (BTB)) to remember key details about branch location, type, and potential targets. Traditionally, performance is achieved by improving the accuracy of such prediction. However, in certain workloads, capacity is also important, i.e., the ability to track and anticipate large sets of working branches, without necessarily being difficult to predict accurately. The storage used to track branches is traditionally composed of several levels, each level including several entries, the number of which exceeds the previous level, but also slower than the previous level. Increasing the storage capacity of the branch prediction structure typically impacts the latency required to resolve such branches, impacting performance. SUMMARY

[0005] Circuits, devices, and methods for branch target buffer (BTB) entry anticipation and management are provided. BTB entries are anticipated by a prediction circuit that includes a special program counter that runs ahead of the normal program counter. Entries that are predicted to be used can be moved to the BTB with faster access time relative to the prediction circuit.

[0006] An apparatus can include a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers having progressively slower access times. The apparatus can include a first program counter and a second program counter. The first program counter can be configured to generate a first program counter value associated with a next instruction of an application for execution. The second program counter can be configured to predict a second program counter value associated with a subsequent instruction of the application for execution after the next instruction. A first branch prediction circuit of the apparatus can be configured to populate a branch target buffer of the branch target buffers based on the second program counter value. The first branch prediction circuit can be configured to populate a branch target buffer of the respective branch target buffers having a faster access time with an entry corresponding to the second program counter value from a branch target buffer of the branch target buffers having a slower access time.

[0007] The apparatus can further include a first branch history register and a second branch history register. The first branch history register can store branch data associated with a most recent branch instruction of the application for execution in accordance with the first program counter. The second branch history register can store branch data associated with the most recent branch instruction of the application for execution in accordance with the second program counter.

[0008] The apparatus can further include a first return stack buffer and a second return stack buffer. The first return stack buffer can be populated in accordance with the first program counter value. The second return stack buffer can be populated in accordance with the second program counter value. The second return stack buffer can store less data than the first return stack buffer.

[0009] The first branch prediction circuit can operate based on the second program counter value when a compute pipeline operating based on the first program counter value stalls. The apparatus can further include a second branch prediction circuit operating based on the second program counter value. The second branch prediction circuit can only predict a specified number of instructions beyond the next instruction. The first branch prediction circuit can be configured to set the second program counter to the first program counter value when the compute pipeline operating based on the first program counter value stalls.

[0010] The device may also include a victim cache configured to receive entries that have been evicted from branch target buffers in the branch target buffer. A first branch prediction circuit may be configured to access the victim cache based on a second program counter value in response to receiving a corresponding missing indication from each branch target buffer in the branch target buffer. The first branch prediction circuit may be configured to populate the branch target buffers in the branch target buffer with entries from the victim cache associated with the second program counter value. Attached Figure Description

[0011] Figure 1 An illustration of an embodiment of a system for predicting branch objectives is shown by way of example.

[0012] Figure 2 An illustration of an embodiment of a BTB system including run-ahead BTB is shown by way of example.

[0013] Figure 3 An illustration of an embodiment of a BTB system including redundant prediction circuitry is shown by way of example.

[0014] Figure 4 A flowchart illustrating an embodiment of an evicted entry in a system including a BTB victim cache is shown by way of example.

[0015] Figure 5 An illustration of an embodiment of a BTB system including a victim cache is shown by way of example.

[0016] Figure 6 An illustration of an embodiment of a method for running a branch target buffer ahead of time is shown by way of example.

[0017] Figure 7 This is a schematic block diagram of a computer system that may include a BTB victim cache, a pre-run BTB, a combination thereof, and is used to perform methods and algorithms according to an example embodiment. Detailed Implementation

[0018] In the following description, reference is made to the accompanying drawings, which form a part of this document, illustrating specific embodiments that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it should be understood that other embodiments can be utilized and structural, logical, and electrical changes can be made without departing from the scope of the invention. Therefore, the following description of exemplary embodiments should not be considered limiting, and the scope of the invention is defined by the appended claims.

[0019] Improved branch target buffer (BTB) operation achieves both low latency and high capacity by anticipating branch prediction entries used in future predictions made by the branch prediction circuitry. Where possible, anticipated branch predictions are moved from larger and slower BTB levels to smaller and faster BTB levels. Studies have shown that reducing latency by several cycles can significantly improve performance. Advancing the branch prediction circuitry can help identify future branch predictions that can be made at smaller and faster BTB levels, thus reducing latency.

[0020] For the following description, we can assume a design where the branch prediction circuitry runs before and separates from the computation pipeline. The branch prediction circuitry and the computation pipeline are separated by a queue, referred to herein as the Branch Prediction Queue (BPQ). In the presence of branch instructions, the branch prediction pipeline iterates and follows a series of program counter (PC) values. Typical architectures and algorithms are used to find and predict the target bytes of branches in the instruction stream before decoding them; this occurs downstream of the BPQ in the computation pipeline.

[0021] Improved branch buffering operations can include a second branch prediction pipeline that runs ahead of the existing pipeline ("ahead" indicates an anticipated subsequent instruction to be executed). The second branch prediction pipeline anticipates missing entries in the predictor architecture. This pipeline can provide the predictor architecture with anticipated branch targets not present in the predictor architecture, propagate entries to a faster BTB than the current BTB access, prefetch entries from the BTB victim cache, or combinations thereof. This advance execution generates additional energy, which can be compensated for by reducing branch misprediction due to better quality predictions in the pipeline. A net benefit of advance prediction is the additional performance achieved by hitting faster BTB entries and optionally prefetching them from the BTB victim cache.

[0022] The following is a high-level description of the branch target buffer operation. Following this, the description includes an improved branch buffer operation that runs the predictor ahead of time.

[0023] Figure 1 An illustration of an embodiment of a system 100 for branch target prediction is shown by way of example. As shown, system 100 includes the following components: program counter 102, branch history register 104, branch prediction structure 106, branch prediction circuit 110, branch prediction queue 112, computation pipeline 114, data memory 116, program memory 118, processor 120, and branch parsing circuit 122.

[0024] Program counter 102 identifies the instruction to be executed in program memory 118, such as by address. Program counter 102 typically increments after the instruction counter value is provided to the prediction structure 106 and branch prediction circuit 110. Therefore, program counter 102 typically defaults to a linearly incrementing program counter. Branch instructions are instructions that can provide a non-linear sequence of instructions for execution. Therefore, the default operation of program counter 102 needs to be overridden depending on the branch instruction whose branch is taken.

[0025] The Branch History Register (BHR) 104 contains data for a specified number of recently executed conditional branches. The data for a given conditional branch can be a single bit. This bit can be set to "0" if the branch was not taken, and to "1" if the branch was taken. For each new conditional branch encountered during application execution, the entry in BHR 104 is shifted left, and the result of the new branch predicted by the branch prediction circuit 110 is written to the rightmost position of BHR 104. During the shift, the leftmost bit of BHR 104 is lost. For example, for a 5-bit BHR, after 5 conditional branches since the start of processor execution, BHR 104 might contain the example sequence "10101," indicating that the last conditional branch seen in the program sequence was taken, while the previous branch was not, and so on. If a new conditional branch is seen and determined to be taken, the new content of BHR 104 will be 01011, due to the left shift of the previous value, the loss of the leftmost bit, and the addition of a new bit on the right. The size of BHR 104 depends on the implementation.

[0026] Branch prediction structure 106 includes branch destination buffers (BTBs) 124, 126, and 128, which are typically indexed by a subset of program counter values. For example, multiple least significant bits (LSBs) can be used to index into BTBs 124, 126, and 128. In another example, the same number of consecutive bits (not LSBs) can be used to index into BTBs 124, 126, and 128. BTBs 124, 126, and 128 include entries that contain the branch destinations of branches historically corresponding to the branch. Therefore, each BTB 124, 126, and 128 includes a program counter value that was historically executed immediately after the branch instruction indexed into that entry.

[0027] Figure 1The diagram illustrates multiple BTBs 124, 126, and 128; however, a system may include only a single BTB 124, 126, or 128. In a system comprising multiple BTBs 124, 126, and 128, one BTB is typically physically stored in a relatively small memory location close to the prediction circuitry 110. Another BTB is stored slightly further away or in a slower-access, larger-capacity memory location. Yet another BTB is stored even further away or in an even slower-access, larger-capacity memory location. The BTB closest to the prediction circuitry 110 is analogous to the processor's L1 cache because it provides the fastest access time and has the smallest capacity among the BTBs. Other BTBs may be stored in different locations within the same package.

[0028] Other prediction structures 130 may include a direction buffer. The direction buffer may indicate whether a branch jumps to a program counter value less than or greater than the current program counter value. Prediction structure 130 may include data indicating the history of one or more program counter values ​​that led to the branch or were implemented after the branch. Other prediction structures 130 may include an array of arrays accessed using different subsets of the PC index and BHR 104. Entries in other prediction structures 130 may be tagged and provide dynamic taken / not taken predictions for dynamically changing conditional branches (conditional branch predictors, such as the Tagged Geometric Length Predictor (TAGE)). Other prediction structures 130 may include specialized structures, loop predictors, return predictors, etc., specifically designed to help determine which of the different targets of the indirect predictor will be followed by the current PC and BHR 104 (indirect predictors, such as the Indirect Target Tagged Geometric Length Predictor (ITTAGE)).

[0029] Prediction structure 106 and branch prediction circuit 110 can predict nonlinearities in program counter 102 in advance, instead of waiting for computation pipeline 114 to indicate nonlinearities to program counter 102. Branch prediction circuit 110 can identify branches that may be taken and the program counter value associated with those branches. Branch prediction circuit 110 can provide program counter values ​​to program counter 102. Branch prediction circuit 110 receives program counter values, entries in BTBs 124, 126, and 128, the contents of prediction structure 130 and branch history register 104, and indicator data from branch prediction queue 112 indicating whether branch prediction queue 112 is full. Branch prediction circuit 110 determines the possible next program counter value based on the received data. Branch prediction circuit 110 can receive all of BHR 104, such as information to help determine the final result of the branch. Branch prediction circuit 110 can use information from BTBs 124, 126, and 128, BHR 104, and all other prediction structures 130 to predict the final result of the branch.

[0030] Branch prediction circuit 110 can implement many types of branch prediction. Example types of branch prediction include static techniques, dynamic techniques, history-based prediction, or combinations thereof. Example static techniques include using heuristics such as "assuming the branch will never be taken" or "assuming the branch will always be taken," and providing a program counter value accordingly.

[0031] In the case of dynamic branch prediction, the prediction circuit 110 monitors the actual branch behavior by recording the most recent history of each branch. Dynamic branch prediction assumes that future behavior will continue in the same manner and makes predictions accordingly. Examples of dynamic branch prediction techniques include using a 1-bit branch prediction buffer, a 2-bit branch prediction buffer, a correlated branch prediction buffer, a tournament branch predictor, using the output from the BTB without further processing, a return address predictor, or a combination thereof. These predictors are known, but a brief summary of each predictor is provided, excluding the BTB, as it has already been explained.

[0032] The 1-bit branch predictor stores a 1-bit value to indicate whether a branch was predicted to be taken or not. This table can be indexed in the same way as BTB 124, 126, and 128.

[0033] A 2-bit predictor changes its prediction only after two consecutive incorrect predictions. It holds two bits in the prediction buffer and has four distinct states: two states corresponding to the taken state and two corresponding to the untaken state. The 2-bit predictor scheme uses only the most recent behavior of a single branch to predict the future behavior of that branch.

[0034] In a correlated branch predictor, the behavior of one branch depends on the behavior of other branches. Correlation exists between different branches. A branch predictor that uses the behavior of other branches for prediction is called a correlated or two-level predictor. These predictors typically use global information rather than local behavioral information. Information about any number of earlier branches can be maintained in BHR 104. For example, prediction circuit 110 can maintain information about three earlier branches such that the behavior of the current branch now depends on the behavior of these three earlier branches.

[0035] The tournament predictor predicts other predictors and attempts to select the correct predictor for the correct branch. Two or more different predictors are maintained, typically one based on global information and one based on local information, and the selection of predictors is based on a selection strategy. For example, a local predictor can be used, and then the prediction can be changed to the global predictor each time an error occurs. Alternatively, switching between predictors is only possible when there are two or more consecutive incorrect predictions.

[0036] Note that in some BTB schemes, there is no one-cycle penalty for the fastest BTB124 when calculating the program counter value of the branch being taken. BTB schemes using program counter values ​​from BTB124 do not incur this penalty. BTB126 and 128 may take longer to provide results and therefore may still incur one or more cycles of penalty.

[0037] The return address predictor predicts indirect returns, i.e., jumps whose target address changes at runtime. Indirect branches are branches whose target may change when the same branch instruction is seen. Indirect branches can be divided into two categories: returns and remainders. Both returns and remainders can have cases where the target never changes; in these cases, both are easily predicted and can be predicted by BTB 124, 126, 128 without the intervention of additional prediction architectures. Indirect branches are difficult to predict when the target of the indirect branch changes. Returns are predicted by the return stack buffer 334, and remainder hard indirect branches are predicted by the indirect predictor of other prediction structures 130. While process returns can be predicted using BTB, the accuracy of this prediction technique can be low if the process is called from multiple sites and calls from one site are not clustered in time. To overcome this problem, the return address predictor uses a small buffer that operates on the return address as a stack in the return stack buffer 334. Return stack buffer 334 (see...) Figure 3 The latest return address is cached: a return address is pushed onto the stack during a call and popped from the stack upon return. If the cache is as large as the maximum call depth, it will perfectly predict the return.

[0038] When branch prediction queue 112 has sufficient space, the program counter value from branch prediction circuit 110 is input into the branch prediction queue. Branch prediction queue 112 stores branches predicted by branch prediction circuit 110 in a first-in-first-out (FIFO) manner. Branch prediction queue 112 provides its oldest stored program counter value to computation pipeline 114.

[0039] The computation pipeline 114 is a series of stages that provide processor 120 with instructions to be executed and store the execution results in data memory 116. The computation pipeline 114 determines which instruction to fetch from program memory 118 and provides that instruction and corresponding data to processor 120. Processor 120 executes the instruction and stores the result in data memory 116.

[0040] Branch parsing circuit 122 determines whether branch prediction circuit 110 generates a program counter value that is the same as the program counter value associated with the instruction executed by processor 120 during branch execution. If a mismatch exists between program counter values, branch parsing circuit 122 updates branch history register 104 and associated prediction structure 106. Furthermore, if the prediction from branch prediction circuit 110 is incorrect, pipeline 114 may pause upon re-fetching. A processor 120 intelligently prevents pauses upon re-fetching by allowing the execution of known correct instructions (as they are in program order) to be older than the incorrectly predicted branch, while aborting the execution of instructions incorrectly fetched after the branch.

[0041] Each component of System 100 is implemented using electrical or electronic circuitry. Electrical or electronic circuitry may include resistors, transistors, capacitors, inductors, diodes, amplifiers, logic gates (AND, OR, XOR, negation, buffers, etc.), multiplexers, switches, memory devices (e.g., random access memory (RAM) or read-only memory (ROM)), processing units (e.g., central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.), power supplies, etc.

[0042] In order for branch prediction to be correct, System 100 needs to correctly guess: whether the program counter value corresponds to a branch, whether to take the branch, and if so, what the target program counter is.

[0043] Figure 2An illustration of an embodiment of a BTB system 200 including early-run BTB is shown by way of example. System 200, as shown, is similar to system 100, wherein system 200 includes a second program counter (early-run program counter 220), a second branch history register (early-run branch history register 222), and two return stack buffers 224, 226. Return stack buffers 224, 226 are examples of prediction structure 130. The early-run program counter 220, the early-run branch history register 222, and the early-run return stack buffer 226 provide a second branch prediction pipeline. The second branch prediction pipeline operates independently of... Figure 1 The BTB pipeline shown operates as follows. The first branch predictive pipeline is sometimes called the demand pipeline. The second branch predictive pipeline is sometimes called the advance run pipeline.

[0044] Run-ahead program counter 220 operates in the same manner as program counter 102. However, run-ahead program counter 220 may operate when program counter 102 is paused or otherwise inactive. Run-ahead program counter 102 generates the next program counter value based on the previous program counter value (typically an integer increment).

[0045] The advance branch history register 222 is similar to the branch history register 104. The advance branch history register 222 has at least the same entries as the branch history register 104, but may contain data not present in the branch history register 104. This is because data generated when predicting the destination of a future branch may be found to be the instruction of that branch. If the prediction of the future branch is accurate, the advance branch history register 222 thus maintains the future state of the branch history register 104.

[0046] The operation of return stack buffer 224 and early execution return stack buffer 226 is similar. Each of the return stack buffers 224 and 226 provides a prediction for return instructions. Note that a return instruction is a branch instruction that jumps to the top entry of the return stack buffer.

[0047] At any given time, two independent branch prediction sequences can occur in the branch prediction pipeline, mostly in parallel. Mostly in parallel means that fully parallel branch prediction sequences can exist, or that branch prediction sequences with mostly independent resources can exist but still share one or more resources. One of these branch prediction sequences (called the demand sequence) runs normally and writes entries in BPQ 112, which will be consumed by the computation pipeline 114. The other branch prediction sequence (called the early run sequence) runs ahead of the demand sequence in terms of program counter values. The early run sequence anticipates that lower-level BTBs (BTBs with relatively low access times within BTBs) will be missing and potentially from the BTB victim cache 420 (see...). Figure 4 ) prefetch entries in ). However, running the predictive pipeline ahead of time will not write any entries to BPQ 112.

[0048] Both sequences detect instruction branches and their targets, and follow the branch target before providing the instruction. However, these sequences operate on different program counter values. The demand sequence works in conjunction with computation pipeline 114 to provide the program counter value corresponding to the next instruction. The advance run sequence operations predict the program counter value via program counter 220, and the branch target that may be seen after the next instruction.

[0049] After system 200 is reset, and after each "synchronization event", the two program counters 102 and 220 can be set to the same state and thus provide the same program counter value. The reset can be caused by a device power cycle, a pause in the computational pipeline 114 due to branch error prediction, a software reset, etc.

[0050] Then, when execution resumes after a reset or synchronization event, program counter 102, branch history register 104, and other components dedicated to the demand sequence can operate while the advance run sequence remains idle. Running both sequences simultaneously in this scenario would be a waste of energy and resources. In some cases, as the demand sequence operates, the advance run program counter 220 and the advance run branch history register 222 are updated to reflect the states of program counter 102 and branch history register 104.

[0051] Whenever the demand sequence pauses, for example because BPQ 112 is full, the early run sequence will automatically begin running. In some cases, one of the demand sequence and the early run sequence operates only if the other does not operate. This is called "opportunism" because the early run sequence only operates when the demand sequence pauses, otherwise it does not operate. When another pause event occurs, the early run program counter 220 is loaded with the program counter value from program counter 102, and operation continues from there. In some cases, the demand sequence and the early run sequence operate in complete parallel, and the pause event is the trigger for the early run sequence to start operating. The early run sequence then operates until a synchronization event occurs, the confidence level predicted in the early run sequence falls below a threshold, etc.

[0052] Synchronization events depend on the implementation, but they are essentially events for any sequence of redirection requirements, typically branch error prediction or pipeline refresh, but many other cases are possible.

[0053] When demand sequences and advance run sequences run in parallel, they may share some resources or include some dedicated resources. Dedicated resources can be replicated, but operated on based on different entries or program counter values. For example, the "read ports" of BTB124, 126, 128 or tables in prediction support structure 130 can be replicated, stored, or shared. If they are replicated, demand and advance run sequences can run completely independently, while if one or more structure ports in the structure ports are shared, strategies can favor the allocation of resources between demand sequences and advance run sequences.

[0054] For example, a strategy can be set so that the demand sequence always has priority, and the early-run sequence only proceeds if the demand sequence has no pending access requests. If there are no conflicts in accessing the shared resource, both can proceed simultaneously, but if there are any conflicts, the demand sequence will proceed, while the early-run sequence will pause until the conflict is resolved, either because the two sequences are now accessing different libraries and can proceed together, or because the demand sequence has stalled.

[0055] Shared infrastructure can be divided into banks. When the entries required by the demand pipeline and the advance run pipeline are in different banks, they can run in parallel without any conflict. However, when the two entries happen to be in the same bank, only one can proceed, usually the demand pipeline, while the advance run pipeline waits for another opportunity. Banking provides most of the benefits of replicating ports at a lower implementation cost. Furthermore, infrastructure is often banked for other implementation reasons, so banks can be used in this way at the lowest cost, typically just wiring.

[0056] The structure used to track the state of the branch prediction circuit 110 can be replicated. An example of such a structure is the return stack buffer (RSB) 224 and the branch history register (BHR) 104. In some cases, components or structures that change their output based on state can be replicated, such that there is a separate instance of each of these components or structures in both the demand sequence and the advance run sequence. This state is updated with each step of each sequence in the sequence; therefore, if the two sequences operate based on different program counter values, each sequence must track this state separately to avoid destructive interference. Another approach is to convert the structure (such as RSB 224) into a doubly linked list. Using a doubly linked list eliminates the need for a separate instance in each sequence of the demand sequence and the advance run sequence.

[0057] RSB 226 can be implemented as a lightweight version of RSB 224 to help minimize the cost of copying RSB 224 to RSB 226. Compared to RSB 224, the lightweight version can store less information, instead of storing the full PC address when a call instruction is observed (and restoring such a PC when a return instruction is observed). RSB 226 can store the current BTB entry index and offset, which typically requires less storage. This reduced RSB 226 can also have fewer entries than the required RSB 224. When the maximum capacity of the reduced RSB 226 is reached, the early-run sequence can pause.

[0058] To prevent the early-run sequence from running too far ahead, using additional energy, and potentially exceeding branch error predictions and potentially filling a small BTB level with useless entries, a "confidence" value can be maintained. The confidence value indicates the probability that the predicted branch is correct. For each branch prediction that exceeds the most immediate next branch prediction, the confidence can be maintained or decreased (e.g., but not increased). The amount of change in confidence can be based on the individual confidence of each branch prediction. When the confidence value falls below a threshold (e.g., dynamically configurable), the early-run sequence can pause and wait for the demand sequence to approach. This can be calculated using a prediction counter for each sequence, with the difference between the two counters indicating how many branches the early-run sequence is ahead of. When this distance reaches the dynamically configurable threshold, the early-run sequence resumes, resetting the confidence value, which is also reset upon a resynchronization event. The reset value of the confidence is dynamically configurable via control register 228. Note that one speculation is positive, as this will prefetch entries for code paths that may be followed in the near future.

[0059] Figure 3A schematic illustration of an embodiment of a BTB system 300 including redundant prediction circuitry 330 is shown by way of example. System 300 is similar to system 200, wherein system 300 includes branch prediction circuitry 110 dedicated to predicting branches of the demand sequence and branch prediction circuitry 330 dedicated to predicting branches of the advance run sequence. Branch prediction circuitry 330 may be a physical copy of branch prediction circuitry 110. However, branch prediction circuitry 330 operates based on a program counter value (from program counter 220) that is different from the program counter value (from program counter 102) of branch prediction circuitry 110, and is therefore in a different state. Furthermore, branch prediction circuitry 330 is not coupled to branch prediction queue 112, branch parsing circuitry 122, or a combination thereof.

[0060] The demand sequence operates using program counter 102, BHR 104, BTB 124, 126, 128, RSB 224, branch prediction circuit 110, branch prediction queue 112, and their downstream coupled components. The early run sequence operates using early run program counter 220, early run BHR 222, BTB 124, 126, 128, early run RSB 226, and branch prediction circuit 330. Branch prediction circuit 330 is communicatively decoupled from computation pipeline 114 and can only affect computation pipeline 114 by changing BTB 124, 126, and 128.

[0061] Figure 4 A flowchart illustrating an embodiment of an evicted entry in a system including a BTB victim cache 420 is shown by way of example. Figure 4 A specific allocation / eviction strategy for sets of BTBs 124, 126, and 128 is described, but many other strategies exist. For example, processor 120 may always allocate a new entry only in the last level BTB 128. Then, when the entry is used, it is promoted to one or more earlier levels. Furthermore, eviction entries from different BTB levels 124, 126, and 128 can be directly evicted without attempting allocation at other levels, thus the eviction entry does not need to be sent to the next level, depending on the implementation.

[0062] Figure 4Examples include a hierarchy of three BTBs 124, 126, and 128, and more or fewer BTBs can be used. A new entry 428 is written to the nearest BTB 124. The new entry 428 can be prompted by the branch parsing circuit 122. The branch parsing circuit 122 can detect when an instruction corresponds to a branch and the counter value of the next point to be executed after the branch. The branch parsing circuit 122 can update BTB 124 to change entries or provide entirely new entries. Because BTB 124 has fewer entries than the applications (multiple) executed using program memory 118, BTB 124 may not have enough space to accommodate additional entries. Therefore, a new entry 428 may cause an instruction to be evicted from BTB 124. Evicted entry 422 is an example of such an entry.

[0063] The evicted entry 422 can be stored in the next BTB, in Figure 2 In the example, BTB 126 is used. BTB 126 is typically larger than BTB 124 and accesses slower. In most cases, N > M. BTB 126 can also be full, and the arrival of evicted entry 422 may result in the evicting of another entry. Evicted entry 424 is an example of such an entry.

[0064] Evicted entry 424 can be stored in the next BTB, in Figure 4 In the example, BTB 128 is used. BTB 128 is typically larger than BTB 126 and accesses slower. In most cases, P>N. BTB 128 can also be full, and the arrival of evicted entry 424 may result in the evicting of another entry. Evicted entry 426 is an example of such an entry.

[0065] exist Figure 4 In the example, entries evicted from the last BTB 128 in the hierarchy can be stored in the BTB victim cache 420. In other examples, BTB entries evicted from any of BTBs 124, 126, or 128 can be assigned to the victim cache 420. BTB 128 is the slowest BTB in the hierarchy. The victim cache 420 is typically larger than BTB 128 and is accessed more slowly. In most cases, Q > P.

[0066] System 100 can determine whether to check entries in victim cache 420 based on indicator data 430, 432, and 434. Indicator data 430, 432, and 434 can be associated with each entry in BTB caches 124, 126, and 128. Indicator data 430, 432, and 434 details whether the entry has been previously evicted. If branch lookups in BTBs 124, 126, and 128 are unsuccessful, and indicator data 430, 432, and 434 details that the entry has been previously evicted, a lookup operation can be performed on BTB victim cache 420. Note that lookups on BTBs 124, 126, and 128 typically occur in parallel, so the latency is only as long as the slowest BTB lookup, which typically corresponds to BTB 128.

[0067] The indicator data 430 for an entry does not refer to the entry itself, but rather to the entry that follows it. For example, if a BTB entry identifies branch X and specifies that the branch's target is Y, then indicator data 430 refers to the entries for address Y in BTBs 124, 126, and 128. When Y is not found, but previous predictions of X indicate that an entry for it exists, it is known that a BTB entry for Y exists. In this case, the victim cache 420 can be accessed to find the entry corresponding to Y.

[0068] Note that the victim cache 420 includes indicator data 436 to maintain the structural consistency of the data in the victim cache 420, such as for decoding and reallocation purposes. If an entry in the victim cache 420 is later rewritten to one of BTBs 124, 126, or 128, indicator data 436 indicating whether the continuation of the BTB entry is expected will also be entered. Thus, the indicator data 430 linking to another existing BTB entry will only be explicitly lost when an entry in the victim cache 420 is evicted.

[0069] Figure 5 A schematic diagram of an embodiment of a BTB system 500 including a victim cache 420 is shown by way of example. System 500 is similar to system 100, and includes a victim cache 420, a miss queue circuit 530, an eviction queue circuit 532, and a return stack buffer 534. The miss queue circuit 530 and the eviction queue circuit 532 manage the contents of the victim cache 420.

[0070] The entries in prediction structure 106 are typically a small subset of information associated with memory blocks in a given address space (whether virtual or not). BTB entries store information about instruction branches present in these blocks, such as the branch's location, branch type, branch address target (e.g., virtual address target), and combinations thereof. A BTB entry may be considered nonexistent when no branch exists in the corresponding virtual address block, or when conditional branches exist but are never followed. The same applies to code regions with branches that have not yet been discovered. BTB entries are created upon the first discovery of a branch, the entry's content is filled with details from those branches, and the entry is written to one or more BTBs. When one entry in BTBs 124, 126, or 128 is evicted, the evicted entry is assigned to the evict queue of evict queue circuit 532, which can hold several entries.

[0071] A finite state machine (FSM) or other logic-based structure (as part of the eviction queue circuit 532) can opportunistically pick up entries from the eviction queue circuit 532. An FSM comprises circuitry that can be in one of a finite number of states at any given time. An FSM can change from one state to another in response to changes in its input. The output of an FSM can change based on the state. The logic-based structure initiates the process of writing the evictioned entry into the victim cache 420.

[0072] The evicted entry may already exist in the victim cache 420. The eviction queue circuit 532 can perform a lookup operation before allocation. If the evicted entry already exists in the index, it can be replaced with the contents of the BTB, which may include the latest information about the branch. Otherwise, a new entry will be allocated, and another entry may be erased and discarded. No control flow is required for the eviction queue because writes to the victim cache 420 can be discarded without affecting functionality.

[0073] When a lookup is missing in all BTBs 124, 126, and 128, a load operation is initiated for the victim cache 420. Since some BTB entries are not present for certain addresses, a method exists to distinguish between missing and non-existent BTB entries. This is achieved by commenting out direct links between BTB entries. Indicator data 430, 432, and 434 can provide links indicating the presence of a BTB entry. If a previously existing indication has been seen in a previous BTB entry redirected to that entry, a fetch from the victim cache 420 can be issued. If no presence has been seen previously, the lookup can be saved to BTBs 124, 126, and 128.

[0074] When an existing BTB entry is followed by another existing BTB entry, whether the branch is taken or not, the first entry can be annotated using indicator data 430, 432, 434 to indicate the presence of the next BTB entry. Since an existing BTB entry can be followed by several valid existing BTB entries, depending on the path indicated by branch prediction circuit 110, several annotations regarding the presence of these BTB entries can be used in indicator data 430, 432, 434. Each annotation can be implemented using a single bit (present / absent). For conditional branches that can follow taken and untaken paths, one bit for each of the two paths is feasible. Prediction circuit 110 can then indicate whether the branch is predicted to be taken or untaken, and the corresponding bit can be used for the next BTB 124, 126, 128 access. For "simple" indirect branches that always follow the same path, a single bit is sufficient, and this covers a large portion of such branches. However, the objective of some indirect branches changes each time they are accessed, and this objective is typically determined by the value at BHR at each access. This multi-target case is resolved by an indirect predictor that is part of another prediction structure 130. For this case, it is straightforward to include indicator bits in the indirect predictor along with the targets. Thus, different targets will have their own bits to indicate whether a continuation has been observed previously, and the continuation bits from the indirect predictor will override the bits in the BTB entry. Note that these “difficult” indirect branches are marked, as this is typically commented in BTBs 124, 126, and 128, indicating that the final resolution of this branch must come from the indirect predictor. This can also be done for returns, which are sub-cases of indirect branches but are handled by the return stack buffer 534, and the indicator data 430 can be stored in the return stack buffer 534 along with the targets.

[0075] The return stack buffer 534 provides prediction of return instructions. Note that a return instruction is a branch instruction that jumps to the top entry of the return stack buffer 534.

[0076] When there is no other existing BTB entry following an existing BTB entry in one of BTBs 124, 126, and 128, it can be assumed that the continuation of the code has not been observed, or that the entry indicating its existence has been discarded, and no attempt to find such an entry will be performed, thus saving energy and latency for known fruitless operations.

[0077] When a previously existing BTB entry is missing in all BTBs 124, 126, and 128, a load operation can be requested from the missing queue circuit 530 by the branch prediction circuit 110. The load operation can cause the missing queue circuit 530 to return an entry from the victim cache 420 (if any). The missing queue of the missing queue circuit 530 can hold several entries waiting to be served, even though there is only one missing entry at a given time.

[0078] The branch prediction circuit 110 can be paused after a request is made to the missing queue circuit 530, because it cannot continue operating without the information contained in the missing BTB entry. This saves energy from following paths that were previously found to be incorrect, since the presence of the BTB entry indicates the existence of a branch.

[0079] Optionally, the BTB missing indication can be sent to pipeline 114 to the instruction fetch engine. This optimization of the algorithm attempts to minimize the performance impact of waiting for the BTB victim cache 420 by starting to decode the instruction and finding the branch again. The following steps describe this optimization.

[0080] At this point, competition begins between the two operation sequences: (i) the first operation sequence is a lookup in the BTB victim cache 420, which is an opportunistic pick-up from the missing queue circuit 530. Since earlier missing entries can be marked as discarded due to redirection, the first operation does not need to maintain the first position in the queue. This address (e.g., a virtual address) can be used to look up the missing entry in the BTB victim cache 420.

[0081] If an entry corresponding to the address is found in the BTB victim cache 420, the contents of that entry can be sent back to the branch prediction circuit 110. Refilling of one or more BTBs 124, 126, 128 can be performed, such as via the branch prediction circuit 110 or the missing queue circuit 530. The operation of the branch prediction circuit 110 can be recovered.

[0082] The BTB (Blind Branch Tolerance) missing indication can arrive at the decoding stage of the computation pipeline 114 before the victim cache 420 responds to a request from the missing branch queue circuitry 530. This can occur if the branch prediction queue 112 is present, which separates the prediction and fetch pipelines to allow execution before branch prediction instructions are fetched. When this occurs, the prediction circuitry 110 can modify the BTB missing indication when the victim cache 420 is refilled with missing branch information that was missing at the initial prediction time, and normal operation can resume without affecting the performance of the instruction flow. This is the best case for which the present invention addresses.

[0083] If no entry corresponding to the address is found in the victim cache 420, a "missing" response is provided by the missing queue circuit 530. The branch prediction circuit 110 can remain suspended until the decoding engine of the computation pipeline 114 determines the next branch to take. In this case, the victim cache 420 will not benefit the system 500.

[0084] (ii) The second sequence of operations in the contention occurs in the fetch and execution section of pipeline 114. During the decoding phase of pipeline 114, the type of branch that the branch prediction circuit 110 cannot find is determined. Several outcomes are possible, and they may or may not win the contention with the BTB victim cache 420: (i) The decoder of pipeline 114 can resolve direct unconditional branches by resolving the target address of the branch and redirecting processor 120. This includes direct calls. (ii) A static prediction method or a different method can be followed, and the branch prediction circuit 110 can be redirected or unsuspended to resolve direct conditional branches as taken or not taken. (iii) Indirect branches do not know which path to follow, so processor 120 can be suspended on the indirect branch itself to conserve energy and wait for the victim cache 420 to resolve the target, or for it to be missing, and then continue with or without the target, respectively. This includes indirect calls and return instructions. The response from the victim cache 420 can then be used to resume the pipeline. Optimizations could include sending indirect branches through pipeline 114 for execution and resolution without waiting for a response from victim cache 420. After the target of the branch is resolved by the instruction that caused the missing branch, processor 120 can be redirected and restarted (if it was paused). Another possible optimization is to avoid computation of some operations in pipeline 114 when a response from victim cache 420 arrives before branch resolution and matches its result. In this case, processor 120 can resume the response and then verify it by resolving the indirect branch.

[0085] Before parsing in computation pipeline 114, the target of a branch is resolved using the response from victim cache 420. This reduces latency and energy consumption, providing the energy savings gained by not fully executing code responding to indirect branches with unknown targets. When a response from victim cache 420 is later than the resolution in computation pipeline 114, the corresponding request in missing queue 530 can be annotated, either by discarding the request or because decoding was resolved first, so that the response is discarded upon receipt. A bit can indicate whether an entry is still relevant.

[0086] The improved branch buffer operation is applicable to various BTB hierarchy levels and allocation and eviction policies. The improved branch buffer operation is not limited to a set of allocation and eviction policies or a subset thereof.

[0087] The improved branch buffering operation could include a simple method that suspends the indirect branch itself and the instructions following it, and then resumes processing the indirect branch when the victim cache 420 is resolved. The victim cache 420 may have a target or report a missing target if it does not exist. In either case, processing of the indirect branch can proceed, and the computation pipeline 114 can resolve the actual target of the indirect branch.

[0088] The improved branch buffer operation could alternatively include a more complex approach that pauses instructions after an indirect branch but does not pause further processing of the indirect branch itself. The indirect branch can be sent to computation pipeline 114 to begin resolving the target, while victim cache 420 is accessed to potentially provide the predicted target. The advantage of this approach is that resolution from computation pipeline 114 is parallel to the operation of victim cache 420. These more complex improved branch buffer operations can save time and may resolve earlier than simpler improved branch buffer operations. The difficulty with the more complex approach is that the indirect branch needs to be "intercepted" and stopped after a hit in victim cache 420. The indirect branch is located somewhere in computation pipeline 114 to provide the target obtained from victim cache 420, making it available for comparison with the branch target determined by computation pipeline 114.

[0089] Figure 6 A diagram illustrating an embodiment of a method 600 for early branch target prediction is shown by way of example. The method 600, as shown, includes: in operation 660, storing entries corresponding to branch instructions by a hierarchy of branch target buffers, the hierarchy including corresponding branch target buffers with progressively slower access times; in operation 662, generating a first program counter value associated with the next instruction of the executing application by a first program counter; in operation 664, generating a second program counter value associated with a subsequent instruction of the executing application after the next instruction by a second program counter; and in operation 666, moving entries from one branch target buffer in the branch target buffer to another branch target buffer in the branch target buffer based on the second program counter value.

[0090] Method 600 may further include having a branch prediction circuit fill the corresponding branch target buffer with a faster access time from the branch target buffer with an entry corresponding to the second program counter value. Method 600 may further include having a first branch history register store branch target data associated with the latest branch instruction of the executed application according to a first program counter. Method 600 may further include having a second branch history register store branch target data associated with the latest branch instruction of the executed application according to a second program counter.

[0091] Method 600 may further include filling a first return stack buffer based on the first program counter value. Method 600 may further include filling a second return stack buffer based on the second program counter value. The second return stack buffer may store less data than the first return stack buffer.

[0092] Figure 7 This is a schematic block diagram of a computer system 700, which may include a BTB victim cache, a pre-run BTB, combinations thereof, and is used to perform methods and algorithms according to example embodiments. Any component of systems 100, 200, 300, 500, victim cache 420, method 600, or other components or operations may be implemented using system 700 or its components. Not all components of system 700 are required in various embodiments.

[0093] An example computing device in the form of computer 700 may include a processing unit 702, a memory 703, a removable storage device 710, and a non-removable storage device 712. While the example computing device is shown and described as computer 700, the computing device may take different forms in different embodiments. For example, the computing device may be replaced by a smartphone, tablet, smartwatch, smart storage device (SSD), or include... Figure 7 Other computing devices with the same or similar elements as those shown and described. Devices such as smartphones, tablets, and smartwatches are generally referred to as mobile devices or user devices.

[0094] While various data storage elements are shown as part of computer 700, the memory may additionally or alternatively include cloud-based storage accessible via a network, such as internet-based storage, or server-based storage. It should also be noted that the SSD may include a processor on which a parser can run to allow parsed, filtered data to be transferred via the I / O channels between the SSD and main memory.

[0095] Memory 703 may include volatile memory 714 and non-volatile memory 708. Computer 700 may include or have access to a computing environment that includes various computer-readable media, such as volatile memory 714 and non-volatile memory 708, removable storage device 710, and non-removable storage device 712. Computer storage devices include random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies, optical disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic tape cassette, magnetic tape, disk storage or other magnetic storage devices, or any other medium capable of storing computer-readable instructions.

[0096] Computer 700 may include or have access to a computing environment including an input interface 706, an output interface 704, and a communication interface 716. Output interface 704 may include a display device, such as a touchscreen, which can also be used as an input device. Input interface 706 may include one or more of the following: a touchscreen, a touchpad, a mouse, a keyboard, a camera, one or more device-specific buttons, one or more sensors integrated into computer 700 or coupled to computer 700 via a wired or wireless data connection, and other input devices. The computer may operate in a networked environment using a communication connection for connecting to one or more remote computers, such as a database server. Remote computers may include personal computers (PCs), servers, routers, network PCs, peer-to-peer devices, or other common data stream network switches. Communication connections may include local area networks (LANs), wide area networks (WANs), cellular networks, Wi-Fi, Bluetooth, or other networks. According to one embodiment, various components of computer 700 are connected to system bus 720.

[0097] Computer-readable instructions stored on a computer-readable medium can be executed by a processing unit 702 of computer 700, such as program 718. In some embodiments, program 718 includes software for implementing one or more methods described herein. Hard disk drives, CD-ROMs, and RAM are some examples of articles that include non-transitory computer-readable media, such as storage devices. The terms computer-readable medium, machine-readable medium, and storage device do not include carrier waves or signals because carrier waves and signals are considered too transient. Storage may also include network storage, such as storage area networks (SANs). Computer program 718, together with workspace manager 722, can be used to cause processing unit 702 to execute one or more methods or algorithms described herein.

[0098] Additional notes and examples

[0099] Example 1 includes an apparatus comprising: a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy including corresponding branch target buffers having progressively slower access times; a first program counter configured to generate a first program counter value associated with a next instruction of an executing application; a second program counter configured to predict a second program counter value associated with a subsequent instruction of the executing application after the next instruction; and a first branch prediction circuit configured to populate the branch target buffers in the branch target buffers based on the second program counter value.

[0100] In Example 2, Example 1 further includes: wherein the first branch prediction circuit is configured to fill the corresponding branch target buffer with a faster access time with an entry from the branch target buffer that corresponds to the second program counter value and is from the branch target buffer with a slower access time.

[0101] In Example 3, at least one of Examples 1 to 2 further includes: a first branch history register storing branch data associated with the latest branch instruction of the application being executed, based on a first program counter; and a second branch history register storing branch data associated with the latest branch instruction of the application being executed, based on a second program counter.

[0102] In Example 4, at least one of Examples 1 to 3 further includes: a first return stack buffer filled according to a first program counter value; and a second return stack buffer filled according to a second program counter value.

[0103] In Example 5, Example 4 also includes: wherein the second return stack buffer stores less data than the first return stack buffer.

[0104] In Example 6, at least one of Examples 1 to 5 further includes: wherein when the computational pipeline operating based on the first program counter value pauses, the first branch prediction circuit operates based on the second program counter value.

[0105] In Example 7, at least one of Examples 1 to 6 further includes: a second branch prediction circuit that operates based on a second program counter value.

[0106] In Example 8, Example 7 also includes: wherein the second branch prediction circuit predicts only a specified number of instructions beyond the next instruction.

[0107] In Example 9, at least one of Examples 7 to 8 further includes: wherein the first branch prediction circuit and the second branch prediction circuit are configured to operate concurrently, and the second branch prediction circuit promotes an entry from a branch target buffer with a slower access time to a branch target buffer with a faster access time and no such entry.

[0108] In Example 10, at least one of Examples 1 to 9 further includes: wherein the first branch prediction circuit is configured to set the second program counter to the first program counter value when the computation pipeline operating based on the first program counter value is paused.

[0109] In Example 11, at least one of Examples 1 to 10 further includes: a victim cache configured to receive entries that have been evicted from branch target buffers in the branch target buffer; and wherein the first branch prediction circuit is configured to access the victim cache based on a second program counter value in response to receiving a corresponding missing indication from each branch target buffer in the branch target buffer.

[0110] In Example 12, Example 11 further includes: wherein the first branch prediction circuit is configured to fill the branch target buffer in the branch target buffer with an entry from the victim cache associated with the second program counter value.

[0111] Example 13 includes a method comprising: storing entries corresponding to branch instructions in a hierarchy of branch target buffers, the hierarchy including corresponding branch target buffers having progressively slower access times; generating a first program counter value associated with the next instruction of the executing application by a first program counter; generating a second program counter value associated with a subsequent instruction of the executing application after the next instruction by a second program counter; and moving entries of the branch target buffers in the branch target buffers to another branch target buffer in the branch target buffers based on the second program counter value.

[0112] In Example 14, Example 13 further includes: the branch prediction circuit filling the corresponding branch target buffer with a faster access time with an entry from the branch target buffer that corresponds to the second program counter value and comes from the branch target buffer with a slower access time.

[0113] In Example 15, at least one of Examples 13 to 14 further includes: storing branch target data associated with the latest branch instruction of the application being executed by a first branch history register according to a first program counter; and storing branch target data associated with the latest branch instruction of the application being executed by a second branch history register according to a second program counter.

[0114] In Example 16, at least one of Examples 13 to 15 further includes: filling a first return stack buffer according to a first program counter value; and filling a second return stack buffer according to a second program counter value.

[0115] In Example 17, Example 16 also includes: wherein the second return stack buffer stores less data than the first return stack buffer.

[0116] Example 18 includes an apparatus comprising: a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy including respective branch target buffers having progressively slower access times; a first program counter configured to generate a first program counter value associated with a next instruction of an executing application; a second program counter configured to predict a second program counter value associated with a subsequent instruction of the executing application following the next instruction; and a first branch prediction circuit configured to populate the respective branch target buffers having faster access times with entries from the branch target buffers having slower access times, corresponding to the second program counter value.

[0117] In Example 19, Example 18 further includes: a first branch history register storing branch data associated with the latest branch instruction of the application being executed, based on a first program counter; and a second branch history register storing branch data associated with the latest branch instruction of the application being executed, based on a second program counter.

[0118] In Example 20, at least one of Examples 18 to 19 further includes: wherein when the computational pipeline operating based on the first program counter value pauses, the branch prediction circuit operates based on the second program counter value.

[0119] In Example 21, at least one of Examples 18 to 20 further includes: a second branch prediction circuit that operates based on a second program counter value.

[0120] In one embodiment, the functions or algorithms described herein may be implemented in software. The software may consist of computer-executable instructions stored on a computer-readable medium or computer-readable storage device, such as one or more non-transitory memories or other types of hardware-based local or network storage devices. Furthermore, these functions correspond to modules, which may be software, hardware, firmware, or any combination thereof. Multiple functions may be executed in one or more modules as needed, and the described embodiments are merely examples. The software may execute on a digital signal processor, ASIC, microprocessor, or other type of processor running on a computer system, such as a personal computer, server, or other computer system, to turn such a computer system into a specially programmed machine.

[0121] This function can be configured to perform operations using, for example, software, hardware, firmware, etc. For example, the phrase "configured to" can refer to the logic circuit structure of a hardware element used to implement the relevant function. The phrase "configured to" can also refer to the logic circuit structure of a hardware element used in a coded design to implement the relevant function of the firmware or software. The term "module" refers to a structural element that can be implemented using any suitable hardware (e.g., a processor), software (e.g., an application), firmware, or any combination of hardware, software, and firmware. The term "logic" includes any function that performs a task. For example, each operation shown in the flowchart corresponds to the logic used to perform that operation. Operations can be performed using software, hardware, firmware, etc. The terms "component," "system," etc., can refer to computer-related entities, hardware, and executing software, firmware, or combinations thereof. A component can be a process, object, executable file, program, function, subroutine, computer, or a combination of software and hardware running on a processor. The term "processor" can refer to a hardware component, such as the processing unit of a computer system.

[0122] Furthermore, the claimed subject matter can be implemented as a method, apparatus, or article of manufacture for controlling a computing device to implement the disclosed subject matter using standard programming and engineering techniques. The term "article of manufacture" as used herein is intended to cover a computer program accessible from any computer-readable storage device or medium. Computer-readable storage media may include, but is not limited to, magnetic storage devices such as hard disks, floppy disks, magnetic stripes, optical disks, optical discs (CDs), digital versatile discs (DVDs), smart cards, flash memory devices, etc. In contrast, computer-readable media may additionally include communication media, such as transmission media for wireless signals (i.e., non-storage media).

[0123] While some embodiments have been described in detail above, other modifications are possible. For example, the logical flow depicted in the figures does not require the specific order shown or the sequence in which the desired result is achieved. Other steps may be provided, or these steps may be removed from the described flow, and other components may be added to or removed from the described system. Other embodiments are within the scope of the following claims.

Claims

1. An apparatus (200), comprising: A hierarchy of multiple branch target buffers (124, 126, 128) storing entries corresponding to branch instructions, the hierarchy of multiple branch target buffers (124, 126, 128) including corresponding multiple branch target buffers (124, 126, 128) with progressively slower access times. A first program counter (102) is configured to generate a first program counter value associated with the next instruction of the application. A second program counter (220) is configured to predict a second program counter value associated with a subsequent instruction of the executing application after the next instruction; as well as The first branch prediction circuit (110) is configured to fill the branch target buffers (124, 126, 128) among the plurality of branch target buffers (124, 126, 128) based on the second program counter value.

2. The apparatus of claim 1, wherein the first branch prediction circuit is configured to: fill the corresponding branch target buffer with a faster access time among the plurality of branch target buffers with entries corresponding to the second program counter value and from the branch target buffer with a slower access time among the plurality of branch target buffers.

3. The device according to claim 1, further comprising: A first branch history register stores branch data associated with the latest branch instruction of the executing application based on the first program counter; as well as The second branch history register stores branch data associated with the latest branch instruction of the executing application according to the second program counter.

4. The device according to claim 1, further comprising: The first return stack buffer is filled according to the first program counter value; as well as The second return stack buffer is filled according to the second program counter value.

5. The device of claim 4, wherein the second return stack buffer stores less data than the first return stack buffer.

6. The apparatus of claim 1, wherein when the computational pipeline operating based on the first program counter value pauses, the first branch prediction circuit operates based on the second program counter value.

7. The device according to claim 1, further comprising: The second branch prediction circuit operates based on the second program counter value.

8. The apparatus of claim 7, wherein the second branch prediction circuit predicts only a specified number of instructions beyond the next instruction.

9. The apparatus of claim 7, wherein the first branch prediction circuit and the second branch prediction circuit are configured to operate concurrently, and the second branch prediction circuit promotes an entry from a branch target buffer with a slower access time to a branch target buffer with a faster access time and no such entry in the plurality of branch target buffers.

10. The apparatus of claim 1, wherein the first branch prediction circuit is configured to set the second program counter to the first program counter value when the computation pipeline operating based on the first program counter value is paused.

11. The device according to claim 1, further comprising: The victim cache is configured to receive entries that have been evicted from the branch target buffers of the plurality of branch target buffers; and The first branch prediction circuit is configured to access the victim cache based on the second program counter value in response to receiving a corresponding missing indication from each of the plurality of branch target buffers.

12. The apparatus of claim 11, wherein the first branch prediction circuit is configured to fill one of the plurality of branch target buffers with an entry from the victim cache associated with the second program counter value.

13. A method (600) comprising: The hierarchical structure of multiple branch target buffers stores entries corresponding to branch instructions, the hierarchy of multiple branch target buffers including corresponding multiple branch target buffers (660) with progressively slower access times. A first program counter value is generated from the first program counter, and the first program counter value is associated with the next instruction of the application being executed (662). A second program counter value is generated from the second program counter, and the second program counter value is associated with a subsequent instruction of the executing application after the next instruction (664). as well as The branch prediction circuit moves an entry of one of the plurality of branch target buffers to another branch target buffer (666) based on the second program counter value.

14. The method of claim 13, further comprising filling the respective branch target buffers with faster access times by the branch prediction circuit with entries corresponding to the second program counter value and from the branch target buffers with slower access times.

15. The method of claim 13, further comprising: The first branch history register stores branch target data associated with the latest branch instruction of the executing application based on the first program counter; as well as The second branch history register stores the branch target data associated with the latest branch instruction of the executing application based on the second program counter.

16. The method of claim 13, further comprising: The first return stack buffer is filled according to the first program counter value; as well as The second return stack buffer is filled according to the second program counter value.

17. The method of claim 16, wherein the second return stack buffer stores less data than the first return stack buffer.

18. An apparatus (200) comprising: A hierarchy of multiple branch target buffers (124, 126, 128) storing entries corresponding to branch instructions, the hierarchy of multiple branch target buffers (124, 126, 128) including corresponding multiple branch target buffers (124, 126, 128) with progressively slower access times. A first program counter (102) is configured to generate a first program counter value associated with the next instruction of the application. A second program counter (220) is configured to predict a second program counter value, which is associated with a subsequent instruction of the executing application following the next instruction. as well as The first branch prediction circuit (110) is configured to fill the branch target buffer (124, 126, 128) with a faster access time among the plurality of branch target buffers (124, 126, 128) with entries corresponding to the second program counter value and from the slower access time branch target buffer (124, 126, 128).

19. The apparatus of claim 18, further comprising: A first branch history register stores branch data associated with the latest branch instruction of the executing application based on the first program counter; as well as The second branch history register stores branch data associated with the latest branch instruction of the executing application according to the second program counter.

20. The apparatus of claim 18, wherein the branch prediction circuit operates based on the second program counter value when the computation pipeline operating based on the first program counter value pauses.

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