Display device, controller, and electronic device including the same

Abstract

The invention discloses a display device, a controller and an electronic device including the display device. The display device includes: a display panel including a pixel including a light emitting element and a first transistor configured to generate a driving current based on a first power supply voltage and a second power supply voltage and supply the driving current to the light emitting element; a gate driver configured to supply a gate signal to the pixels; a data driver configured to supply a data voltage to the pixels; and a driving controller configured to control the gate driver and the data driver. The first transistor includes a back gate electrode receiving a bias voltage. The bias voltage is a fixed bias voltage during an address scan period and a variable bias voltage during at least one self-scan period after the address scan period.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, a controller, and an electronic device including the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, transmitter lines, and pixels. The display panel driver includes a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, a transmitter driver for providing transmitter signals to the transmitter lines, and a drive controller for controlling the gate driver, data driver, and transmitter driver.

[0003] The driving frequency of a display device refers to the frequency at which signals are applied to drive the pixels of the display panel. Display devices can support variable driving frequencies. As the driving frequency of the display panel increases, the driving time of the driving transistors in each pixel can also increase, potentially leading to changes in the threshold voltage or hysteresis characteristics of the driving transistors. In this case, the display quality of the display device may be degraded. Summary of the Invention

[0004] Embodiments of the present invention provide a display device, a controller, and an electronic device including the display device for applying a bias voltage to a driving transistor to improve display quality.

[0005] In an embodiment of a display device according to the present invention, the display device includes: a display panel including pixels, each pixel including a light-emitting element and a first transistor configured to generate a drive current based on a first power supply voltage and a second power supply voltage and to provide the drive current to the light-emitting element; a gate driver configured to provide a gate signal to the pixel; a data driver configured to provide a data voltage to the pixel; and a drive controller configured to control the gate driver and the data driver. The first transistor includes a back gate electrode that receives a bias voltage. The bias voltage is a fixed bias voltage during an address scan period and a variable bias voltage during at least one self-scan period after the address scan period.

[0006] In this embodiment, the first transistor may be a PMOS transistor.

[0007] In this embodiment, the fixed bias voltage may be a first power supply voltage.

[0008] In an embodiment, the variable bias voltage may have a value between a voltage that decreases the set voltage from the fixed bias voltage and a voltage that increases the set voltage from the fixed bias voltage. For example, the variable bias voltage may be within a range defined by adding or subtracting a set voltage from the fixed bias voltage.

[0009] In an embodiment, the variable bias voltage may vary based on the threshold voltage or hysteresis characteristics of the first transistor.

[0010] In an embodiment, data voltage may be provided to the pixel during the address scan period and the first self-scan period after the address scan period, and data voltage may not be provided to the pixel during the second self-scan period after the first self-scan period.

[0011] In an embodiment, when the bias voltage is a fixed bias voltage during the address scan period and the first self-scan period and the bias voltage is a variable bias voltage during the second self-scan period, the variable bias voltage can be a global signal simultaneously provided to the pixel rows of the display panel.

[0012] In an embodiment, when the bias voltage is a fixed bias voltage during the address scan period and a variable bias voltage during the first self-scan period and the second self-scan period, the variable bias voltage can be a sequential signal provided sequentially to the pixel rows.

[0013] In an embodiment, when the variable bias voltage is a sequential signal, the display device may further include a signal generator comprising multiple stages. Each of these stages may include: a first switching element including a gate electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a first control node; a second switching element including a gate electrode receiving a low gate voltage, a first electrode connected to a second control node, and a second electrode connected to a third control node; a third switching element including a gate electrode connected to a third control node, a first electrode receiving a low gate voltage, and a second electrode connected to an inverting control node; a fourth switching element including a gate electrode connected to the second control node, a first electrode receiving a high gate voltage, and a second electrode connected to an inverting control node; and a fifth switching element including a gate electrode connected to the third control node, receiving a high gate voltage, a first electrode receiving a high gate voltage, and a second electrode connected to an inverting control node; and a fifth switching element including a gate electrode connected to the third control node, receiving a high gate voltage, a first electrode receiving a high gate voltage, and a second electrode connected to an inverting control node. A first electrode with a variable bias voltage and a second electrode connected to a bias output node from which the bias voltage is output; a sixth switching element including a gate electrode connected to an inverting control node, a first electrode receiving a fixed bias voltage, and a second electrode connected to a bias output node; a seventh switching element including a gate electrode connected to a third control node, a first electrode receiving a low gate voltage, and a second electrode connected to a carry output node from which a carry signal is output; an eighth switching element including a gate electrode connected to an inverting control node, a first electrode receiving a high gate voltage, and a second electrode connected to a carry output node; and a first capacitor including a first electrode connected to a third control node and a second electrode connected to a bias output node.

[0014] In an embodiment, each of these stages may further include a ninth switching element, which includes a gate electrode receiving a high gate voltage, a first electrode connected to a first control node, and a second electrode connected to a second control node.

[0015] In the embodiments, the first switching element, the second switching element, the fourth switching element, the fifth switching element, the sixth switching element, the seventh switching element, and the eighth switching element can be PMOS transistors, and the third switching element and the ninth switching element can be NMOS transistors.

[0016] In an embodiment, each of these stages may further include a second capacitor, the second capacitor including a first electrode receiving a high gate voltage and a second electrode connected to an inverting control node.

[0017] In an embodiment, the first transistor may include a gate electrode connected to a first node, a first electrode connected to a second node, a second electrode connected to a third node, and a back gate electrode for receiving a bias voltage. The light-emitting element may include an anode connected to a fourth node and a cathode for receiving a second power supply voltage. The pixel may further include: a second transistor including a gate electrode for receiving a data write gate signal, a first electrode connected to a data line for transmitting data voltage, and a second electrode connected to the second node; a third transistor including a gate electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; and a fourth transistor including a gate electrode for receiving an initialization gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the first node.

[0018] In an embodiment, the pixel may further include: a fifth transistor, including a gate electrode for receiving a transmitted signal, a first electrode for receiving a first power supply voltage, and a second electrode connected to a second node; and a sixth transistor, including a gate electrode for receiving a transmitted signal, a first electrode connected to a third node, and a second electrode connected to a fourth node.

[0019] In an embodiment, the pixel may further include a seventh transistor, which includes a gate electrode for receiving an anode initialization gate signal, a first electrode for receiving an anode initialization voltage, and a second electrode connected to a fourth node.

[0020] In an embodiment, the first transistor may include a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, a second electrode connected to a second node, and a back gate electrode receiving a bias voltage, and the light-emitting element may include an anode connected to a fourth node and a cathode receiving a second power supply voltage. The pixel may further include: a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; and a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the third node.

[0021] In an embodiment, the pixel may further include: a fifth transistor, including a gate electrode for receiving a compensation gate signal, a first electrode for receiving a first power supply voltage, and a second electrode connected to a third node; and a sixth transistor, including a gate electrode for receiving a transmission signal, a first electrode connected to a second node, and a second electrode connected to a fourth node.

[0022] In an embodiment, the pixel may further include a seventh transistor, which includes a gate electrode for receiving an anode initialization gate signal, a first electrode for receiving an anode initialization voltage, and a second electrode connected to a fourth node.

[0023] In an embodiment of an electronic device according to the present invention, the electronic device includes: a display panel including pixels, each pixel including a light-emitting element and a first transistor configured to generate a drive current based on a first power supply voltage and a second power supply voltage and to provide the drive current to the light-emitting element; a gate driver configured to provide a gate signal to the pixel; a data driver configured to provide a data voltage to the pixel; a drive controller configured to control the gate driver and the data driver; and a processor configured to control the drive controller. The first transistor includes a back gate electrode that receives a bias voltage. The bias voltage is a fixed bias voltage during an address scan period and a variable bias voltage during at least one self-scan period after the address scan period.

[0024] In an embodiment of the present invention, a controller is provided, comprising a gate driver, a drive controller, and a signal generator. The drive controller is configured to determine a fixed bias voltage, determine a variable bias voltage, and control the gate driver to provide gate signals to the gate lines of the display panel and to provide scan drive signals. The signal generator is configured to apply the fixed bias voltage to the back gate electrode during an address scan period in synchronization with the scan drive signals, and to apply the variable bias voltage to the back gate electrode during at least one self-scan period after the address scan period.

[0025] Depending on the pixel, display device, and electronic device, a bias voltage can be applied to the back gate electrode of the driving transistor. The bias voltage can be constant during the address scan period and variable during at least one self-scan period after the address scan period. Accordingly, the threshold voltage or hysteresis characteristics of the driving transistor can be improved. Attached Figure Description

[0026] The above and other features of the embodiments of the present invention will become more apparent from the detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0028] Figure 2 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel;

[0029] Figure 3 It is shown Figure 1 A circuit diagram of an example pixel;

[0030] Figure 4 This shows when the transmission frequency is 480Hz. Figure 3 Timing diagram of the driving signals for the pixels;

[0031] Figure 5 This shows when the transmission frequency is 240Hz. Figure 3 Timing diagram of the driving signals for the pixels;

[0032] Figure 6 It is shown Figure 3 Timing diagram of an example of the transmitted signal and bias voltage;

[0033] Figure 7 It is shown Figure 3 Timing diagram of an example of the transmitted signal and bias voltage;

[0034] Figure 8 This is a circuit diagram showing a signal generator that generates a bias voltage;

[0035] Figure 9 It is shown Figure 1 A circuit diagram of an example pixel;

[0036] Figure 10 It is shown Figure 1 A circuit diagram of an example pixel;

[0037] Figure 11 This is a block diagram showing an electronic device;

[0038] Figure 12 It is shown that Figure 11 The diagram shows an embodiment of an electronic device implemented as a smartphone; and

[0039] Figure 13 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0040] The inventive concept will be described in more detail below with reference to the accompanying drawings.

[0041] This invention relates to a display device, a controller, and an electronic device including the display device that improves display quality by dynamically adjusting the bias voltage applied to the back gate electrode of the driving transistor in each pixel. The display panel of the display device operates at a variable refresh rate and includes a period for writing data (e.g., an address scan period) and a period for emitting light when no new data is input (e.g., a self-scan period). During the address scan period, a fixed bias voltage is applied to the back gate electrode of the driving transistor. However, during the self-scan period, a variable bias voltage is applied, which can be adjusted based on characteristics such as the threshold voltage or hysteresis performance of the driving transistor. This dynamic biasing method helps stabilize the performance of the driving transistor over time, compensates for changes due to long-term operation, and maintains consistent image quality even when the driving frequency is changed.

[0042] Figure 1 This is a block diagram illustrating a display device 10 according to an embodiment of the concept of the present invention.

[0043] refer to Figure 1 The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200 (e.g., a controller circuit), a gate driver 300 (e.g., a first driver circuit), a gamma reference voltage generator 400, a data driver 500 (e.g., a second driver circuit), and a transmit driver 600 (e.g., a third driver circuit).

[0044] The display panel 100 may include a display area for displaying images and a peripheral area adjacent to the display area.

[0045] The display panel 100 may include a gate line GL, a data line DL, an emission line EML, and pixels PX electrically connected to the gate line GL, the data line DL, and the emission line EML, respectively. The gate line GL may extend in a first direction D1, the data line DL may extend in a second direction D2 intersecting the first direction D1, and the emission line EML may extend in the first direction D1.

[0046] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0047] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0048] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0049] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and can output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0050] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0051] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0052] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and can output the fourth control signal CONT4 to the transmitter driver 600.

[0053] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0054] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0055] For example, the gamma reference voltage generator 400 can be located within the drive controller 200, or it can be located within the data driver 500.

[0056] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and can receive a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 can output the data voltage to the data line DL.

[0057] The transmit driver 600 can generate a transmit signal for driving the transmit line EML in response to a fourth control signal CONT4 received from the drive controller 200. The transmit driver 600 can output the transmit signal to the transmit line EML.

[0058] exist Figure 1 For ease of explanation, the gate driver 300 may be disposed on the first side of the display panel 100, and the transmitter driver 600 may be disposed on the second side of the display panel 100; however, the inventive concept is not limited thereto. For example, both the gate driver 300 and the transmitter driver 600 may be disposed on the first side of the display panel 100. For example, both the gate driver 300 and the transmitter driver 600 may be disposed on both sides of the display panel 100. For example, the gate driver 300 and the transmitter driver 600 may be formed as a single unit.

[0059] Figure 2 It is shown Figure 1 A conceptual diagram of the driving frequency of the display panel 100.

[0060] refer to Figure 1 and Figure 2 The display panel 100 can be driven at a variable frequency. A first frame period FR1 having a first frequency may include a first active period AC1 and a first blank period BL1. A second frame period FR2 having a second frequency different from the first frequency may include a second active period AC2 and a second blank period BL2. A third frame period FR3 having a third frequency different from the first and second frequencies may include a third active period AC3 and a third blank period BL3.

[0061] The first valid time period AC1 can have the same length as the second valid time period AC2, and the first blank time period BL1 can have a different length than the second blank time period BL2.

[0062] The second valid time period AC2 can have the same length as the third valid time period AC3, and the second blank time period BL2 can have a different length than the third blank time period BL3.

[0063] The display device 10 supporting variable driving frequency may include an address scan period in which data voltage is applied to the pixel PX and a self-scan period in which no data voltage is written to the pixel PX (e.g., only light emission is performed). The address scan period may be arranged within active periods AC1, AC2, and AC3. The self-scan period may be arranged within blank periods BL1, BL2, and BL3.

[0064] Figure 3 It is shown Figure 1 A circuit diagram of an example of a display panel 100 with pixels PX.

[0065] refer to Figure 3 Pixel PX may include first transistors T1 to seventh transistors T7, storage capacitor CST, and light-emitting element EL. In an embodiment, first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, and seventh transistor T7 may be P-type metal-oxide-semiconductor (PMOS) transistors, and third transistor T3 and fourth transistor T4 may be N-type metal-oxide-semiconductor (NMOS) transistors.

[0066] The first transistor T1 may include a gate electrode (e.g., a front gate electrode) connected to a first node N1, a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a back gate electrode receiving a bias voltage VOBS. The first transistor T1 can generate a drive current based on its gate-source voltage. Therefore, the first transistor T1 can be referred to as a drive transistor. As the drive time of the first transistor T1 increases, its threshold voltage or hysteresis characteristics may change. When the bias voltage VOBS is applied to the back gate electrode of the first transistor T1, its threshold voltage or hysteresis characteristics can be improved. In an embodiment, the bias voltage VOBS is constant during the address scan period and variable during the self-scan period after the address scan period. The constant bias voltage VOBS can be referred to as a fixed bias voltage, and the variable bias voltage VOBS can be referred to as a variable bias voltage.

[0067] For example, the bias voltage VOBS required to improve the threshold voltage or hysteresis characteristics of the first transistor T1 can be pre-designed and stored in the memory of the display device 10 or in the electronic device including the display device 10.

[0068] The second transistor T2 may include a gate electrode for receiving a data write gate signal GW, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to the second node N2. The second transistor T2 may provide the data voltage VDATA to the second node N2 in response to the data write gate signal GW.

[0069] The third transistor T3 may include a gate electrode for receiving the compensation gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may connect the first transistor T1 diode in response to the compensation gate signal GC.

[0070] The fourth transistor T4 may include a gate electrode for receiving an initialization gate signal GI, a first electrode for receiving an initialization voltage VINT, and a second electrode connected to the first node N1. The fourth transistor T4 may provide the initialization voltage VINT to the first node N1 in response to the initialization gate signal GI.

[0071] The fifth transistor T5 may include a gate electrode for receiving the transmitted signal EM, a first electrode for receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 can determine whether the light-emitting element EL emits light in response to the transmitted signal EM.

[0072] The sixth transistor T6 may include a gate electrode for receiving the transmitted signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 can determine whether the light-emitting element EL emits light in response to the transmitted signal EM.

[0073] The seventh transistor T7 may include a gate electrode for receiving an anode initialization gate signal GB, a first electrode for receiving an anode initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may provide the anode initialization voltage VAINT to the fourth node N4 in response to the anode initialization gate signal GB. The storage capacitor CST may include a first electrode for receiving a first power supply voltage ELVDD and a second electrode connected to the first node N1.

[0074] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode receiving a second power supply voltage ELVSS. The light-emitting element EL may emit light based on a drive current.

[0075] Figure 4 This shows when the transmission frequency is 480Hz. Figure 3 Timing diagram of the driving signals EM, GB, GI, GC, and GW for pixel PX. Figure 5 This shows when the transmission frequency is 240Hz. Figure 3 The timing diagram shows the driving signals EM, GB, GI, GC, and GW for pixel PX. The emission frequency is the frequency at which the light-emitting element EL performs its light-emitting operation.

[0076] refer to Figures 1 to 5 The display panel 100 can be driven at a variable frequency.

[0077] For example, refer to Figure 4 The display panel 100 can be driven at a maximum frequency of 240Hz. When the display panel 100 is driven at 240Hz, the data write gate signal GW has valid pulses in the first time period DU1, the third time period DU3, the fifth time period DU5, and the seventh time period DU7, and a data write operation can be performed. For ease of illustration, the data write gate signal GW is shown as having valid pulses in the first time period DU1, the third time period DU3, the fifth time period DU5, and the seventh time period DU7; however, the data write operation can continue. Figure 4 The data write operation occurs in two time periods. Specifically, when the display panel 100 is driven at 240Hz, a first data write operation can be performed in the first time period DU1 and the second time period DU2; a second data write operation can be performed in the third time period DU3 and the fourth time period DU4; a third data write operation can be performed in the fifth time period DU5 and the sixth time period DU6; and a fourth data write operation can be performed in the seventh time period DU7 and the eighth time period DU8. When the display panel 100 is driven at 120Hz, the data write gate signal GW has valid pulses in the first time period DU1 and the fifth time period DU5, and the data write operation can be performed. The data write operation can be continuous. Figure 4 The two time periods. That is, when the display panel 100 is driven at 120Hz, the first data write operation can be performed in the first time period DU1 and the second time period DU2, and the second data write operation can be performed in the fifth time period DU5 and the sixth time period DU6.

[0078] When the display panel 100 is driven at 240Hz, the light emission operation of the light-emitting element EL can be performed at 480Hz, the initialization operation of the light-emitting element EL can also be performed at 480Hz, and the initialization operation / threshold voltage compensation operation of the first transistor T1 can also be performed at 480Hz.

[0079] Therefore, when the display panel 100 is driven at 240Hz and the light-emitting operation is performed at 480Hz, it can be said that the display panel 100 operates in 2 cycles.

[0080] When the display panel 100 is driven at 120Hz, the light emission operation of the light-emitting element EL can be performed at 480Hz, the initialization operation of the light-emitting element EL can also be performed at 480Hz, and the initialization operation / threshold voltage compensation operation of the first transistor T1 can also be performed at 480Hz.

[0081] Therefore, when the display panel 100 is driven at 120Hz and the light-emitting operation is performed at 480Hz, it can be said that the display panel 100 operates in 4 cycles.

[0082] In the display device 10 that supports variable drive frequency, the drive sequence of the display panel 100 may include an address scan period and a self-scan period following the address scan period.

[0083] In an embodiment, the address scan period can be the period in which data write operations are performed, and the self-scan period can be the period in which only light emission operations are performed without data write operations. For example, refer to Figure 4 When the display panel 100 is driven at 160Hz, data writing operations can be performed in the first time period DU1, the fourth time period DU4, and the seventh time period DU7. Therefore, the first time period DU1, the fourth time period DU4, and the seventh time period DU7 can be address scan periods. On the other hand, in the second time period DU2, the third time period DU3, the fifth time period DU5, the sixth time period DU6, and the eighth time period DU8, no data writing operations are performed, and only light emission operations can be performed. Therefore, the second time period DU2, the third time period DU3, the fifth time period DU5, the sixth time period DU6, and the eighth time period DU8 can be self-scanning periods.

[0084] In another embodiment, the address scan period and the first self-scan period following the address scan period can be periods in which data write operations are performed, and the self-scan period following the first self-scan period can be periods in which only light emission operations are performed without data write operations. For ease of illustration, the data write gate signal GW is shown as having valid pulses in the first period DU1, the fourth period DU4, and the seventh period DU7; however, the data write operation can be performed at other times. Figure 4 The two time periods in the text last for a duration. For example, refer to... Figure 4When the display panel 100 is driven at 160Hz, data writing operations can be performed in the first time period DU1, the second time period DU2, the fourth time period DU4, the fifth time period DU5, and the seventh time period DU7 and the eighth time period DU8. Therefore, the first time period DU1, the fourth time period DU4, and the seventh time period DU7 can be address scan periods, and the second time period DU2, the fifth time period DU5, and the eighth time period DU8 can be the first self-scan period after the address scan period. On the other hand, in the third time period DU3 and the sixth time period DU6, data writing operations may not be performed, and only light emission operations may be performed. Therefore, the third time period DU3 and the sixth time period DU6 can be the self-scan period after the first self-scan period.

[0085] refer to Figure 5 The display panel 100 can be driven at a variable frequency, for example, up to 120Hz. When the display panel 100 is driven at 120Hz, the data write gate signal GW has valid pulses in the first time period DU1 and the third time period DU3, and a data write operation can be performed. When the display panel 100 is driven at 80Hz, the data write gate signal GW has valid pulses in the first time period DU1 and the fourth time period DU4, and a data write operation can be performed.

[0086] Figure 6 It is shown Figure 3 The timing diagram shows an example of the transmit signal EM and the bias voltage VOBS.

[0087] refer to Figures 1 to 6 In the display device 10 that supports variable frequency, the driving sequence of the display panel 100 may include an address scan period and at least one self-scan period following the address scan period. For example, refer to Figure 6 The driving sequence of the display panel 100 may include an address scan period, a first self-scan period, a second self-scan period, and a third self-scan period.

[0088] In this embodiment, the data write operation can be performed at any time. Figure 6 The two time periods in the process last continuously. That is, data write operations can be performed during the address scan period and the first self-scan period. In the embodiment, no data write operations are performed during the second and third self-scan periods, and only light emission operations are performed during the second and third self-scan periods.

[0089] The variable frequency-supporting display device 10 may include a display panel 100 comprising pixels PX, and perform a bias operation in which a bias voltage VOBS is applied to the back gate electrode of a first transistor T1 of the pixels PX. When the bias operation is performed, the threshold voltage or hysteresis characteristics of the first transistor T1 may be improved.

[0090] In this embodiment, the bias voltage VOBS has a fixed bias voltage VOBS_CON during the address scan period and the first self-scan period. For example, the fixed bias voltage VOBS_CON can be a constant voltage or a direct current (DC) voltage. For example, the fixed bias voltage VOBS_CON can be a first power supply voltage ELVDD.

[0091] In an embodiment, during the self-scan period following the address scan period, the bias voltage VOBS has a variable bias voltage VOBS_VAR. For example, the bias voltage VOBS may have a variable bias voltage VOBS_VAR during the second and third self-scan periods. The variable bias voltage VOBS_VAR may have a value between a voltage that decreases the set voltage from the fixed bias voltage VOBS_CON and a voltage that increases the set voltage from the fixed bias voltage VOBS_CON. For example, the range of the variable bias voltage VOBS_VAR may be a value lower than the set voltage of the fixed bias voltage VOBS_CON to a value higher than the fixed bias voltage VOBS_CON by the same set voltage. For example, the fixed bias voltage VOBS_CON may be a first power supply voltage ELVDD and the set voltage may be 4V. When the bias voltage VOBS has a fixed bias voltage VOBS_CON during the address scan period and the first self-scan period, the variable bias voltage VOBS_VAR may be a global signal simultaneously provided to several pixel rows.

[0092] In this embodiment, the variable bias voltage VOBS_VAR varies based on the threshold voltage or hysteresis characteristics of the first transistor T1. The variable bias voltage VOBS_VAR, or the value representing the variable bias voltage VOBS_VAR, can be stored in memory in the form of a lookup table through multiple programming operations, and the display device 10 may further include this memory.

[0093] Assuming the fixed bias voltage VOBS_CON is 12V and the set voltage is 4V, the variable bias voltage VOBS_VAR can vary between 8V and 16V. Figure 6 In this configuration, the display panel 100 operates in four time periods: an address scan period, a first self-scan period, and two additional self-scan periods (e.g., a second self-scan period and a third self-scan period). During the address scan period and the first self-scan period, the bias voltage VOBS applied to the back gate electrode of the first transistor T1 remains constant at 12V to ensure stable data writing and initial light emission. Starting in the second self-scan period, the bias voltage VOBS begins to change; for example, it decreases to 11V during the second self-scan period and remains at that level during the third self-scan period. This controlled change in the bias voltage VOBS during the self-scan period helps compensate for threshold voltage offset and hysteresis of the first transistor T1.

[0094] Figure 7 It is shown Figure 3 The timing diagram shows an example of the transmit signal EM and the bias voltage VOBS. Figure 8 This is a circuit diagram showing the signal generator that generates the bias voltage VOBS.

[0095] refer to Figures 1 to 5 as well as Figure 7 The driving sequence of the display panel 100 in the display device 10 that supports variable driving frequency may include an address scan period and a self-scan period following the address scan period. For example, refer to Figure 7 The driving sequence of the display panel 100 may include an address scan period, a first self-scan period, a second self-scan period, and a third self-scan period.

[0096] In this embodiment, the data write operation is performed in... Figure 7 The two time periods in the process last continuously. That is, data writing operations can be performed during the address scan period and the first self-scan period. In this embodiment, no data writing operations are performed during the second and third self-scan periods, and only light emission operations are performed during the second and third self-scan periods.

[0097] The display device 10 supporting variable drive frequency may include a display panel 100 containing pixels PX, and performs a bias operation in which a bias voltage VOBS is applied to the back gate electrode of a first transistor T1 of the pixel PX. When the bias operation is performed, the threshold voltage or hysteresis characteristics of the first transistor T1 may be improved.

[0098] In this embodiment, the bias voltage VOBS has a fixed bias voltage VOBS_CON during the address scan period. The fixed bias voltage VOBS_CON can be a constant voltage. For example, the fixed bias voltage VOBS_CON can be a first power supply voltage ELVDD.

[0099] In an embodiment, the bias voltage VOBS has a variable bias voltage VOBS_VAR during the self-scan period following the address scan period. For example, the bias voltage VOBS may have a variable bias voltage VOBS_VAR during a first self-scan period, a second self-scan period, and a third self-scan period. The variable bias voltage VOBS_VAR may have a value between a voltage that decreases the set voltage from the fixed bias voltage VOBS_CON and a voltage that increases the set voltage from the fixed bias voltage VOBS_CON. For example, the fixed bias voltage VOBS_CON may be a first power supply voltage ELVDD, and the set voltage may be 4V. When the bias voltage VOBS has a fixed bias voltage VOBS_CON only during the address scan period, the variable bias voltage VOBS_VAR may be a sequential signal that is sequentially applied to several pixel rows. When the variable bias voltage VOBS_VAR is a sequential signal, the variable bias voltage VOBS_VAR may be generated by a signal generator, and the display device 10 may further include the signal generator. For example, the variable bias voltage VOBS_VAR may be sequentially applied to multiple pixel rows.

[0100] The variable bias voltage VOBS_VAR can vary based on the threshold voltage or hysteresis characteristics of the first transistor T1. The variable bias voltage VOBS_VAR, or the value representing the variable bias voltage VOBS_VAR, can be stored in memory in the form of a lookup table through multiple programming operations, and the display device 10 may further include this memory.

[0101] Assuming the fixed bias voltage VOBS_CON is 12V and the set voltage is 4V, the variable bias voltage VOBS_VAR can vary between 8V and 16V. Figure 7 In this process, the display panel 100 operates in four time periods: an address scan period, a first self-scan period, and additional self-scan periods (e.g., a second self-scan period and a third self-scan period). During the address scan period, the bias voltage VOBS applied to the back gate electrode of the first transistor T1 remains constant at 12V to support accurate data writing. At the beginning of the first self-scan period, the bias voltage VOBS begins to change; for example, it may decrease to 11V during the first self-scan period and remain at that level during the second and third self-scan periods.

[0102] The bias voltage VOBS can be sequentially applied to pixels in rows by a signal generator. For example, the signal generator can sequentially generate the bias voltage VOBS in synchronization with a scan drive signal (e.g., a control signal) output from the gate driver 300. The signal generator can apply a fixed bias voltage VOBS_CON to the back gate electrode during the address scan period and a variable bias voltage VOBS_VAR to the back gate electrode during the self-scan period after the address scan period, in synchronization with the scan drive signal. The drive controller 200 can determine the fixed bias voltage VOBS_CON, determine the variable bias voltage VOBS_VAR, and control the gate driver 300 to provide gate signals to the gate lines GL of the display panel 100 and provide scan drive signals.

[0103] refer to Figures 1 to 5 , Figure 7 and Figure 8 A signal generator can include multiple stages.

[0104] Each of the stages may include a first switching element S1 through a ninth switching element S9, a first capacitor C1, and a second capacitor C2. The first switching element S1, the second switching element S2, the fourth switching element S4, the fifth switching element S5, the sixth switching element S6, the seventh switching element S7, and the eighth switching element S8 may be PMOS transistors, and the third switching element S3 and the ninth switching element S9 may be NMOS transistors.

[0105] The first switching element S1 may include a gate electrode that receives a first clock signal CLK1, a first electrode that receives an input signal IN, and a second electrode that is connected to a first control node NQ1.

[0106] The second switching element S2 may include a gate electrode that receives a low gate voltage VGL, a first electrode connected to a second control node NQ2, and a second electrode connected to a third control node NQ3.

[0107] The third switching element S3 may include a gate electrode connected to the third control node NQ3, a first electrode receiving a low gate voltage VGL, and a second electrode connected to the inverting control node NQB.

[0108] The fourth switching element S4 may include a gate electrode connected to the second control node NQ2, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the inverting control node NQB.

[0109] The fifth switching element S5 may include a gate electrode connected to the third control node NQ3, a first electrode receiving a variable bias voltage VOBS_VAR, and a second electrode connected to a bias output node NOBS from which it outputs a bias voltage VOBS.

[0110] The sixth switching element S6 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a fixed bias voltage VOBS_CON, and a second electrode connected to the bias output node NOBS.

[0111] The seventh switching element S7 may include a gate electrode connected to the third control node NQ3, a first electrode receiving a low gate voltage VGL, and a second electrode connected to a carry output node NCR from which it outputs a carry signal CR.

[0112] The eighth switching element S8 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a high gate voltage VGH, and a second electrode connected to the carry output node NCR.

[0113] The ninth switching element S9 may include a gate electrode that receives a high gate voltage VGH, a first electrode connected to a first control node NQ1, and a second electrode connected to a second control node NQ2.

[0114] The first capacitor C1 may include a first electrode connected to the third control node NQ3 and a second electrode connected to the bias output node NOBS.

[0115] The second capacitor C2 may include a first electrode that receives a high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0116] For example, the input signal IN, the first clock signal CLK1, and the carry signal CR can be generated by the drive controller 200.

[0117] Figure 9 It is shown Figure 1 The circuit diagram of an example pixel PX' for pixel PX.

[0118] refer to Figures 1 to 9 When the bias voltage VOBS is applied to Figure 3 When the back gate electrode of the first transistor T1 of pixel PX is used, the threshold voltage or hysteresis characteristics of the first transistor T1 can be improved. This is not limited to... Figure 3 The pixel PX. Figure 9 The pixel PX' is an example.

[0119] Pixel PX' may include first transistors T1 to seventh transistors T7, storage capacitor CST, boost capacitor CBST, and light-emitting element EL. In an embodiment, first transistors T1 to third transistors T3 and fifth transistors T5 to seventh transistors T7 may be PMOS transistors, and fourth transistor T4 may be an NMOS transistor.

[0120] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2', and a back gate electrode receiving a bias voltage VOBS. The first transistor T1 can generate a drive current based on its gate-source voltage. Therefore, the first transistor T1 can be referred to as a drive transistor. As the drive time of the first transistor T1 increases, its threshold voltage or hysteresis characteristics may change. When the bias voltage VOBS is applied to the back gate electrode of the first transistor T1, its threshold voltage or hysteresis characteristics can be improved. In an embodiment, the bias voltage VOBS is constant during the address scan period and variable during the self-scan period after the address scan period. The constant bias voltage VOBS can be referred to as a fixed bias voltage, and the variable bias voltage VOBS can be referred to as a variable bias voltage.

[0121] The second transistor T2 may include a gate electrode for receiving a data write gate signal GW, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to a third node N3'. The second transistor T2 may provide the data voltage VDATA to the third node N3' in response to the data write gate signal GW.

[0122] The third transistor T3 may include a gate electrode for receiving the compensation gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the second node N2'. The third transistor T3 may connect the first transistor T1 diode in response to the compensation gate signal GC.

[0123] The fourth transistor T4 may include a gate electrode for receiving the initialization gate signal GI, a first electrode for receiving the initialization voltage VINT, and a second electrode connected to the third node N3'. The fourth transistor T4 may provide the initialization voltage VINT to the third node N3' in response to the initialization gate signal GI.

[0124] The fifth transistor T5 may include a gate electrode for receiving a compensation gate signal GC, a first electrode for receiving a first power supply voltage ELVDD, and a second electrode connected to the third node N3'. The fifth transistor T5 may supply the first power supply voltage ELVDD to the third node N3' in response to the compensation gate signal GC.

[0125] The sixth transistor T6 may include a gate electrode for receiving the transmitted signal EM, a first electrode connected to the second node N2', and a second electrode connected to the fourth node N4. The sixth transistor T6 can determine whether the light-emitting element EL emits light in response to the transmitted signal EM.

[0126] The seventh transistor T7 may include a gate electrode for receiving the anode initialization gate signal GB, a first electrode for receiving the anode initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may provide the anode initialization voltage VAINT to the fourth node N4 in response to the anode initialization gate signal GB.

[0127] The storage capacitor CST may include a first electrode that receives a first power supply voltage ELVDD and a second electrode connected to a third node N3'.

[0128] The boost capacitor CBST may include a first electrode connected to the first node N1 and a second electrode connected to the third node N3'.

[0129] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode receiving a second power supply voltage ELVSS.

[0130] Figure 9 The pixel PX' and Figure 3 The difference between pixel PX' and pixel PX' is that pixel PX' additionally includes a boost capacitor CBST connected between the first node N1 and the third node N3'. This boost capacitor CBST in pixel PX' can help improve the gate voltage swing of the first transistor T1 during the compensation and emission phases, potentially improving current drive performance, reducing programming errors, and improving brightness consistency.

[0131] Figure 10 It is shown Figure 1 The circuit diagram of the example pixel PX.

[0132] refer to Figures 1 to 8 as well as Figure 10 When the bias voltage VOBS is applied to Figure 3 When the back gate electrode of the first transistor T1 of pixel PX is used, the threshold voltage or hysteresis characteristics of the first transistor T1 can be improved. This is not limited to... Figure 3 The pixel PX. Figure 10 "Pixel PX" is an example.

[0133] A pixel PX may include a first transistor T1 to a seventh transistor T7, a storage capacitor CST, and a light-emitting element EL. In an embodiment, the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7 may be PMOS transistors, and the third transistor T3 may be an NMOS transistor.

[0134] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a back gate electrode receiving a bias voltage VOBS. The first transistor T1 can generate a drive current based on its gate-source voltage. Therefore, the first transistor T1 can be referred to as a drive transistor. As the drive time of the first transistor T1 increases, its threshold voltage or hysteresis characteristics may change. When the bias voltage VOBS is applied to the back gate electrode of the first transistor T1, its threshold voltage or hysteresis characteristics can be improved. The bias voltage VOBS can be constant during the address scan period and variable during the self-scan period after the address scan period. A constant bias voltage VOBS can be referred to as a fixed bias voltage, and a variable bias voltage VOBS can be referred to as a variable bias voltage.

[0135] The second transistor T2 may include a gate electrode for receiving a data write gate signal GW, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to the second node N2. The second transistor T2 may provide the data voltage VDATA to the second node N2 in response to the data write gate signal GW.

[0136] The third transistor T3 may include a gate electrode for receiving the compensation gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may connect the first transistor T1 diode in response to the compensation gate signal GC.

[0137] The fourth transistor T4 may include a gate electrode for receiving the initialization gate signal GI, a first electrode for receiving the initialization voltage VINT, and a second electrode connected to the third node N3. The fourth transistor T4 may provide the initialization voltage VINT to the third node N3 in response to the initialization gate signal GI.

[0138] The fifth transistor T5 may include a gate electrode for receiving the transmitted signal EM, a first electrode for receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 can determine whether the light-emitting element EL emits light in response to the transmitted signal EM.

[0139] The sixth transistor T6 may include a gate electrode for receiving the transmitted signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 can determine whether the light-emitting element EL emits light in response to the transmitted signal EM.

[0140] The seventh transistor T7 may include a gate electrode for receiving the initial gate signal GI, a first electrode for receiving the anode initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may provide the anode initialization voltage VAINT to the fourth node N4 in response to the initial gate signal GI.

[0141] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode receiving a second power supply voltage ELVSS.

[0142] The difference between "Pixel PX" and "Pixel PX" lies in the fact that "Pixel PX" further modifies the transistor terminal connections and control signal distribution to potentially simplify the driving scheme and improve layout flexibility. In "Pixel PX", the first electrode of the first transistor T1 is connected to the second node N2 instead of to the power line, potentially affecting how the drive current flows through the circuit. Furthermore, the seventh transistor T7 in "Pixel PX" receives the initialization gate signal GI instead of the separate anode initialization gate signal GB as in "Pixel PX". This change reduces the number of unique control signals required, thus streamlining the pixel control scheme.

[0143] Figure 11 This is a block diagram showing the electronic device 1000. Figure 12 It is shown that Figure 11 The diagram shows an embodiment of the electronic device 1000 implemented as a smartphone.

[0144] refer to Figure 11 and Figure 12 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 10. In this case, the processor 1010 can be configured to control Figure 1 The drive controller 200 is included. Furthermore, the electronic device 1000 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0145] In an embodiment, such as Figure 12 As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, and head-mounted display (HMD) device, etc.

[0146] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be coupled to other components via address bus, control bus, and data bus, etc. In addition, processor 1010 can be coupled to an expansion bus such as the peripheral component interconnect (PCI) bus.

[0147] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile (DRAM) device.

[0148] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and CD-ROM devices, etc.

[0149] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, and touchscreen, or output devices such as a printer and speaker. In some embodiments, I / O device 1040 may include display device 1060.

[0150] Power supply 1050 can provide power for the operation of electronic device 1000.

[0151] The display device 1060 can be connected to other components via a bus or other communication link.

[0152] Figure 13 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. (See reference) Figure 13 An electronic device 1000 according to an embodiment of the present invention can, for example, correspond to Figure 1 The display module 1140 of the display device 10 shown outputs various information (e.g., images, text, music, etc.). When the processor 1110 (e.g., Figure 11 The processor 1010 shown in the figure executes the functions stored in the memory 1120 (e.g., Figure 11 When used in the memory device 1020 shown, the display module 1140 (e.g., Figure 11 The display device 1060 shown can provide application information to the user through the display panel 1141.

[0153] In some embodiments, the electronic device 1000 may be configured as a smartphone, camera, smart TV, monitor, smartwatch, tablet computer, automotive display, or AR / VR head-mounted display. For example, the electronic device 1000 may be a smartphone including a touch-sensitive display area for interaction and a non-display area including sensors and circuitry for enhanced functionality. For example, the electronic device 1000 may be a television or monitor including a large display area for high-resolution video playback and a non-display area containing driving circuitry or a connection module for external input. For example, the electronic device 1000 may be a smartwatch including a display area optimized for compact and high-definition visual effects and a non-display area integrating biometric sensors for health monitoring. In some cases, the electronic device 1000 may be an AR / VR head-mounted display.

[0154] In some embodiments, memory 1120 may store information such as software code for operating application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may operate under the control of processor 1110 and utilize data stored in memory 1120 to deliver a wide range of features such as productivity tools, multimedia streaming and playback, file or email delivery, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touchscreen 1142, allowing a user to launch, navigate, and utilize the program via user input such as touch, tap, gesture, or voice interaction.

[0155] When a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123, retrieved from memory 1120, corresponding to the selected application, to perform the application's functions. For example, when a user selects a camera application by tapping an icon (or camera application icon) displayed on display panel 1141, processor 1110 activates the camera module. Processor 1110 can then transfer image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can then display the image corresponding to the captured image via display panel 1141.

[0156] As another example, when a user wishes to make a phone call, the user taps a phone icon displayed on display module 1140, and processor 1110 can execute a phone application stored in memory 1120. A phone keypad can be displayed on display panel 1141 for the user to enter the phone number to call.

[0157] As another example, the display module 1140 can be integrated into an electronic device 1000, such as a laptop computer, smart TV, or tablet computer. Users wishing to access multimedia streaming applications (e.g., watching music videos or movies) can do so by tapping the corresponding icon. This action activates the application, allowing the user to watch the streaming content.

[0158] Processor 1110 may include a main processor 1111 and an auxiliary or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU). The main processor 1111 may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0159] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. The controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specifications of the display module 1140, and output image data. The controller 1112-1 can output various control signals for driving the display module 1140. For example, the controller 1112-1 can drive the display module 1140 to display icons suitable for user selection on the display screen (or display panel 1141) to trigger the execution of the application program 1123.

[0160] The memory 1120 may store one or more applications 1123 used by at least one component of the electronic device 1000 (e.g., processor 1110 or user interface 1161) and various data, as well as input or output data of commands associated therewith. For example, camera applications, GPS applications, augmented reality and virtual reality applications, and other applications may be executed by the processor 1110 when the user selects a corresponding icon presented on the display screen (or display panel 1141) via the touchscreen 1142 or user interface 1161. Additionally, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0161] Display module 1140 can output visual information (images) to a user. Display module 1140 may include a display panel 1141, a gate driver, a source driver, a voltage generation circuit, and a touchscreen 1142. Display module 1140 may further include a window, housing, and bracket for protecting the display panel 1141. Display module 1140 may include... Figure 1 At least a portion of the structure of the display device 10 shown in the figure.

[0162] User interface 1161 acts as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input from a part of the user's body (e.g., a finger) or from a pen or mouse, and generate electrical signals or data values ​​corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0163] The fingerprint sensor 1162 can sense fingerprints used for biometric identification of a user, and can also measure one or more biosignals related to biometric information such as blood pressure, water content, or weight.

[0164] Input sensor 1163 can sense user interactions including touch, taps, gestures, motion, verbal commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared or semiconductor photodetectors. Input sensor 1163 includes audio and acoustic sensors, which can be MEMS microphones for voice recognition or voice-based interaction. The audio and acoustic sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0165] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of pen or mouse input to control the movement of the cursor on the screen. The digitizer 1164 can generate the amount of electromagnetic change caused by the input as this data value. The digitizer 1164 can detect input using a passive pen, or send and receive data using an active pen or remote control.

[0166] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 by a process that is continuous with the process of forming elements (e.g., light-emitting elements and transistors) included in the display panel 1141.

[0167] Additionally, the user interface 1161 may further include, for example, a gesture sensor, a gyroscope sensor for sensing rotational motion, an accelerometer sensor for tracking translational motion, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer sensor, and infrared emitter and camera may be particularly suitable for AR / VR head-mounted display functions.

[0168] Touchscreen 1142 includes a touch sensor embedded in display panel 1141 to sense pressure applied to the top layer (screen) of display panel 1141. The touch sensor can be capacitive or resistive. Touchscreen 1142 can serve as a main interface for users to select and navigate applications, control electronics 1000, and interact with electronics 1000.

[0169] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 1141 is not particularly limited. The display panel 1141 may be of a rigid type or a flexible type that can be rolled or folded. The display module 1140 may further include supports, brackets, and heat dissipation components for supporting the display panel 1141. The display module 1140 can be used to implement... Figure 11 The display device 1060 shown in the figure. The display panel 1141 may include Figure 1 The display panel 100 shown in the figure.

[0170] Power module 1150 (e.g., Figure 11 The power supply 1050 shown can supply power to components of the electronic device 1000. A power module 1150 can be used to implement the power supply 1050. The power module 1150 can include a battery charged with a power supply voltage. The battery can include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module 1150 can include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the aforementioned components, including the display module 1140.

[0171] This invention can be applied to any display device and any electronic device, including touchpads. For example, it can be applied to mobile phones, smartphones, tablet computers, digital televisions (TVs), 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0172] The foregoing is illustrative of the inventive concept and is not intended to limit the inventive concept. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without departing from the teachings of the inventive concept. Thus, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the term "means plus function clause" is intended to cover structures described herein as performing the described functions, covering not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the claims.

Claims

1. A display device, comprising: A display panel includes pixels, each pixel including a light-emitting element and a first transistor configured to generate a drive current based on a first power supply voltage and a second power supply voltage and to provide the drive current to the light-emitting element; A gate driver is configured to provide a gate signal to the pixel; A data driver is configured to provide a data voltage to the pixel; as well as The drive controller is configured to control the gate driver and the data driver. The first transistor includes a back gate electrode that receives a bias voltage, and The bias voltage is a fixed bias voltage during the address scan period and a variable bias voltage during at least one self-scan period after the address scan period.

2. The display device according to claim 1, wherein, The first transistor is a P-type metal-oxide-semiconductor transistor.

3. The display device according to claim 1, wherein, The fixed bias voltage is the first power supply voltage.

4. The display device according to claim 1, wherein, The variable bias voltage is within a range defined by adding or subtracting a set voltage from the fixed bias voltage.

5. The display device according to claim 1, wherein, The variable bias voltage varies based on the threshold voltage or hysteresis characteristics of the first transistor.

6. The display device according to claim 1, wherein, During the address scan period and the first self-scan period following the address scan period, the data voltage is provided to the pixel, and during the second self-scan period following the first self-scan period, the data voltage is not provided to the pixel.

7. The display device according to claim 6, wherein, When the bias voltage is the fixed bias voltage during the address scan period and the first self-scan period, and the bias voltage is the variable bias voltage during the second self-scan period, the variable bias voltage is a global signal simultaneously provided to the pixel rows of the display panel.

8. The display device according to claim 6, wherein, When the bias voltage is the fixed bias voltage during the address scan period and the bias voltage is the variable bias voltage during the first self-scan period and the second self-scan period, the variable bias voltage is a sequential signal provided to the pixel rows of the display panel.

9. The display device according to claim 8, wherein, When the variable bias voltage is the sequence signal, the display device further includes a signal generator, the signal generator comprising multiple stages, and Each of the levels includes: The first switching element includes a gate electrode that receives a first clock signal, a first electrode that receives an input signal, and a second electrode that is connected to a first control node. The second switching element includes a gate electrode that receives a low gate voltage, a first electrode connected to a second control node, and a second electrode connected to a third control node. The third switching element includes a gate electrode connected to the third control node, a first electrode receiving the low gate voltage, and a second electrode connected to the inverting control node; The fourth switching element includes a gate electrode connected to the second control node, a first electrode receiving a high gate voltage, and a second electrode connected to the inverting control node; The fifth switching element includes a gate electrode connected to the third control node, a first electrode receiving the variable bias voltage, and a second electrode connected to a bias output node from which the bias voltage is output; The sixth switching element includes a gate electrode connected to the inverting control node, a first electrode receiving the fixed bias voltage, and a second electrode connected to the bias output node; The seventh switching element includes a gate electrode connected to the third control node, a first electrode receiving the low gate voltage, and a second electrode connected to a carry output node from which a carry signal is output; The eighth switching element includes a gate electrode connected to the inverting control node, a first electrode receiving the high gate voltage, and a second electrode connected to the carry output node; and The first capacitor includes a first electrode connected to the third control node and a second electrode connected to the bias output node.

10. The display device according to claim 9, wherein, Each of the stages further includes a ninth switching element, the ninth switching element comprising a gate electrode receiving the high gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

11. The display device according to claim 10, wherein, The first switching element, the second switching element, the fourth switching element, the fifth switching element, the sixth switching element, the seventh switching element, and the eighth switching element are P-type metal-oxide-semiconductor transistors, and the third switching element and the ninth switching element are N-type metal-oxide-semiconductor transistors.

12. The display device according to claim 9, wherein, Each stage in the stage further includes a second capacitor, the second capacitor including a first electrode receiving the high gate voltage and a second electrode connected to the inverting control node.

13. The display device according to claim 1, wherein, The first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, a second electrode connected to a third node, and a back gate electrode that receives the bias voltage. The light-emitting element includes an anode connected to the fourth node and a cathode that receives the second power supply voltage. The pixel further includes: The second transistor includes a gate electrode for receiving a data write gate signal, a first electrode connected to a data line that transmits the data voltage, and a second electrode connected to the second node. The third transistor includes a gate electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the third node; and The fourth transistor includes a gate electrode for receiving an initial gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the first node.

14. The display device according to claim 13, wherein, The pixel further includes: The fifth transistor includes a gate electrode for receiving a transmitted signal, a first electrode for receiving the first power supply voltage, and a second electrode connected to the second node; and The sixth transistor includes a gate electrode for receiving the transmitted signal, a first electrode connected to the third node, and a second electrode connected to the fourth node.

15. The display device according to claim 14, wherein, The pixel further includes: The seventh transistor includes a gate electrode for receiving an anode initialization gate signal, a first electrode for receiving an anode initialization voltage, and a second electrode connected to the fourth node.

16. The display device according to claim 1, wherein, The first transistor includes a gate electrode connected to a first node, a first electrode receiving the first power supply voltage, a second electrode connected to a second node, and a back gate electrode receiving the bias voltage. The light-emitting element includes an anode connected to the fourth node and a cathode that receives the second power supply voltage. The pixel further includes: The second transistor includes a gate electrode for receiving a data write gate signal, a first electrode connected to a data line that transmits the data voltage, and a second electrode connected to a third node. The third transistor includes a gate electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; and The fourth transistor includes a gate electrode for receiving an initialization gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the third node.

17. The display device according to claim 16, wherein, The pixel further includes: The fifth transistor includes a gate electrode for receiving the compensation gate signal, a first electrode for receiving the first power supply voltage, and a second electrode connected to the third node; and The sixth transistor includes a gate electrode for receiving a transmitted signal, a first electrode connected to the second node, and a second electrode connected to the fourth node.

18. The display device according to claim 17, wherein, The pixel further includes: The seventh transistor includes a gate electrode for receiving an anode initialization gate signal, a first electrode for receiving an anode initialization voltage, and a second electrode connected to the fourth node.

19. An electronic device comprising: The display device according to any one of claims 1 to 18; as well as The processor is configured to control the drive controller.

20. A controller for a display device, the display device comprising a display panel including pixels, each pixel including a driving transistor having a back gate electrode, the controller comprising: Gate driver; The drive controller is configured to determine a fixed bias voltage, determine a variable bias voltage, and control the gate driver to provide gate signals to the gate lines of the display panel and provide scan drive signals. as well as A signal generator is configured to apply the fixed bias voltage to the back gate electrode during an address scan period in synchronization with the scan drive signal, and to apply the variable bias voltage to the back gate electrode during at least one self-scan period after the address scan period.

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