A multi-chip parallel orthogonal current sharing module and its fabrication method

Abstract

This invention discloses a multi-chip parallel orthogonal current sharing module and its fabrication method. The module provides a first chip layer where the lower power semiconductor devices are arranged in a planar symmetrical layout, and the vertical positions of each lower power semiconductor device correspond to the corresponding upper power semiconductor device. Due to the vertical position correspondence combined with the planar symmetrical layout, the inductance of each path within the first and second chip layers is consistent, thus easily achieving a better current sharing effect. Furthermore, the metal pads connected to the lower part of the decoupling capacitor, which are set in the copper plate holes at the AC end, are arranged parallel to each lower metal pad. This allows the decoupling capacitor to have reverse mutual inductance with each lower power semiconductor device. The upper metal pads of the capacitor are also arranged parallel to the upper metal pads of the capacitor, thereby achieving reverse mutual inductance between the decoupling capacitor and each upper power semiconductor device. This, in turn, cancels out the vertical path mutual inductance, achieving the goal of reducing parasitic inductance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device packaging, specifically relating to a multi-chip parallel orthogonal current sharing module and its preparation method. Background Technology

[0002] Power electronic modules are mainly used in power electronic systems, including DC-DC converters, inverters, and rectifiers, for the conversion and regulation of electrical energy. The closest existing technology to this invention is the traditional double-sided multi-chip stacked power module, which is mainly used in high-power-density, high-frequency switching power electronic systems, such as automobiles and radar.

[0003] like Figure 1 The diagram shows a typical conventional structure of a power electronic module. A conventional double-sided cooling module, from top to bottom, includes upper copper-clad ceramic substrates (copper-ceramic-copper) 21, 22, and 23; metal pads 24 for chip interconnection; power semiconductor devices 25; and lower copper-clad ceramic substrates (copper-ceramic-copper) 26, 27, and 28, as shown. Figure 2 As shown, another typical traditional structure of power electronic modules, namely a common parallel quadrature power module, includes, from top to bottom, a decoupling capacitor 31, an upper copper-clad ceramic substrate (copper-ceramic-copper) 32, 33 and 34, a metal via (copper) 35, a power semiconductor device (MOSFET or IGBT) 36, a junction block (copper / molybdenum copper) 37, a metal pad (copper / molybdenum copper alloy) 38, and an upper copper-clad ceramic substrate (copper-ceramic-copper) 39, 310 and 311. However, the typical traditional double-sided packaging structure has the following problems:

[0004] (1) The circuit path is relatively long and the parasitic inductance is large, which can easily lead to device switching overshoot and electromagnetic interference problems.

[0005] (2) For multi-chip parallel modules, single-sided packaging has a good current sharing effect but generally has a large parasitic inductance, while double-sided packaging has a small parasitic inductance but it is difficult to achieve current sharing balance.

[0006] (3) Existing packages have limited heat dissipation paths, high thermal resistance, uneven chip temperature, which can easily cause thermal mismatch and performance degradation, and large package thermal capacity.

[0007] Patent application CN120727696A discloses an orthogonally stacked, double-sided cooled power module and its fabrication method, comprising decoupling capacitors, a copper-clad ceramic substrate, power chips, and metal pads. The metal pads and power chips are stacked layer by layer in a metal pad-power chip-metal pad configuration to form a series chip group. The copper-clad ceramic substrate is connected to both sides of the metal pads in the series chip group and is perpendicular to the power chips. This invention achieves synergistic optimization of the electrical and thermal performance of the cooled power module through the synergistic effect of orthogonal stacking packaging and double copper pad double-sided cooling, resulting in a significant reduction in parasitic inductance and a significant improvement in transient overcurrent support capability. This packaging technology offers good flexibility and is applicable to power modules with different packaging types.

[0008] Patent application CN120568828A discloses a 3D-packaged low parasitic inductance SiC power module, comprising a substrate layer, a chip layer, a connection layer, an intermediate layer, and decoupling capacitors. The chip layer is electrically connected to the substrate layer. The intermediate layer is located between the upper and lower chip layers. The upper and lower connection layers are windowed copper blocks with external DC terminals for connecting the upper substrate layer and the decoupling capacitors. The decoupling capacitors are two sets of capacitors located beside the intermediate layer and electrically connected to the upper and lower connection layers. By using high-conductivity copper material and connecting it to the stacked layers and the copper layers within the substrate to form the intermediate layer, the inductance of the module is significantly reduced, and the heat dissipation effect is improved. This provides significant advantages in high-frequency, high-voltage, and high-power applications, effectively improving the overall performance and reliability of power electronic systems.

[0009] However, the balance of parasitic inductance and current sharing in the modules disclosed in the two patent applications above still needs further improvement. Summary of the Invention

[0010] This invention provides a multi-chip parallel orthogonal current sharing module, which can achieve a smaller parasitic inductance and a better current sharing effect.

[0011] This invention provides a multi-chip parallel orthogonal current sharing module, comprising, from bottom to top:

[0012] DC negative copper plate, used to connect to the external bus negative terminal;

[0013] The first chip layer is located on the DC negative electrode copper plate. The first chip layer includes each lower power semiconductor device arranged in a planar symmetrical layout and a lower metal pad located on each lower power semiconductor device.

[0014] The AC end metal copper plate and terminals are located on each lower metal pad. A decoupling capacitor is set inside the AC end metal pad. A capacitor upper connection metal pad and a capacitor lower connection metal pad are set on the upper and lower surfaces of the decoupling capacitor. The capacitor lower connection metal pad and each lower metal pad are arranged parallel to each other, thereby realizing reverse mutual inductance between the decoupling capacitor and each lower power semiconductor device.

[0015] The second chip layer is located on the AC terminal copper plate and terminal. The second chip layer includes upper power semiconductor devices corresponding to the upper and lower positions of each lower power semiconductor device. Each upper power semiconductor device is provided with an upper metal pad. The upper metal pad and the metal pad connected to the capacitor are arranged parallel to each other, thereby realizing the reverse mutual inductance between the decoupling capacitor and each upper power semiconductor device.

[0016] The DC positive copper plate is located on each upper metal pad and is used to connect to the external bus positive terminal.

[0017] Preferably, the first chip layer further includes each lower flexible printed circuit board, wherein each lower flexible printed circuit board is symmetrically arranged in a plane with each lower power semiconductor device, and each lower flexible printed circuit board is used to connect to the gate of the corresponding lower power semiconductor device and lead it to the outside.

[0018] Preferably, the second chip layer further includes upper flexible printed circuit boards, which are symmetrically arranged in planar layout with each upper power semiconductor device. Each upper flexible printed circuit board is connected to the gate and terminal of the corresponding upper power semiconductor device, so that the gate is led out to the outside through the terminal.

[0019] Preferably, each of the lower power semiconductor devices and each of the upper power semiconductor devices are arranged symmetrically with respect to the terminals.

[0020] Preferably, the decoupling capacitor is located at the center of the AC terminal metal pad, and each lower power semiconductor device is equally spaced around the decoupling capacitor.

[0021] Preferably, the materials of the AC terminal copper plate, the lower metal pad, the lower metal pad of the capacitor, the upper metal pad of the capacitor, and the upper metal pad are all copper or copper-molybdenum.

[0022] Preferably, each of the lower power semiconductor devices and the upper power semiconductor devices is a MOSFET or an IGBT.

[0023] The materials of each lower power semiconductor device and the upper power semiconductor device are silicon carbide.

[0024] Preferably, the lower power semiconductor devices are connected in parallel to form the lower bridge arm;

[0025] The upper power semiconductor devices are connected in parallel to form the upper bridge arm.

[0026] On the other hand, the present invention also provides a method for fabricating the multi-chip parallel orthogonal current sharing module, comprising:

[0027] (1) Form each lower power semiconductor device and each lower flexible printed circuit board in a planar symmetrical layout on the DC negative copper plate. Connect the gate and Kelvin source of each lower power semiconductor device to the corresponding lower flexible printed circuit board. Transfer the silver film of the lower metal pad to the corresponding lower power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the lower power semiconductor device and thus obtaining the lower bridge arm.

[0028] Each upper power semiconductor device and each upper flexible printed circuit board are formed in a planar symmetrical layout on the AC terminal copper plate. The gate and Kelvin source of each upper power semiconductor device are wired to the corresponding upper flexible printed circuit board. The silver film of the upper metal pad is transferred to the corresponding upper power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the upper power semiconductor device, and thus obtaining the upper bridge arm.

[0029] (2) Connect the AC terminal copper plate to the terminal, place the decoupling capacitor in the internal hole of the AC terminal copper plate, and use reflow soldering to connect the upper metal pad and the lower metal pad to the upper and lower surfaces of the decoupling capacitor respectively.

[0030] (3) The lower bridge arm and the upper bridge arm are attached to the copper plate and the terminal of the AC end in corresponding positions, so that the lower connecting metal pad of the capacitor and each lower metal pad are arranged parallel to each other, and the upper metal pad and the upper connecting metal pad of the capacitor are arranged parallel to each other. The upper and lower flexible printed circuit boards are connected to the terminals so as to bring out the gate and Kelvin source of the upper and lower power semiconductor devices.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] The lower power semiconductor devices in the first chip layer provided by the present invention are arranged in a planar symmetrical layout, and the first chip layer and the second chip layer are stacked. This makes it relatively easy to achieve the vertical correspondence between the lower power semiconductor devices and the corresponding upper power semiconductor devices. Due to the vertical correspondence and the planar symmetrical layout, the inductance of each path in the first and second chip layers is consistent, thus making it relatively easy to achieve a good current sharing effect.

[0033] This invention utilizes a decoupling capacitor with a metal pad below the capacitor and other lower metal pads arranged parallel to each other. This allows the decoupling capacitor to have reverse mutual inductance with each lower power semiconductor device. The upper metal pad of the capacitor is also arranged parallel to the upper metal pad of the capacitor. This achieves reverse mutual inductance between the decoupling capacitor and the upper power semiconductor devices, thereby canceling the mutual inductance along the vertical path and reducing parasitic inductance. Attached Figure Description

[0034] Figure 1 This is a diagram of the packaging structure of a double-sided cooling module in the background technology;

[0035] Figure 2 This is a diagram of the packaging structure of a typical parallel orthogonal power module in the background technology.

[0036] Figure 3 A structural diagram of a multi-chip parallel orthogonal current sharing module provided in a specific embodiment of the present invention;

[0037] Figure 4 A comparison chart of parasitic parameter performance of a double-sided cooling module, a conventional parallel orthogonal power module, and a multi-chip parallel orthogonal current sharing module;

[0038] Figure 5 The current sharing performance diagram of the four chips in the lower arm of the multi-chip parallel orthogonal current sharing module provided in a specific embodiment of the present invention. Detailed Implementation

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0040] This invention provides a multi-chip parallel orthogonal current sharing module that combines the low parasitic inductance of traditional double-sided packaging with the dynamic current sharing advantages of single-sided packaging. In this structure, the upper and lower arms of the half-bridge are each composed of multiple chips connected in parallel, and a high-frequency decoupling capacitor is placed between the DC positive and negative copper plates. Dynamic current balancing is achieved through the reverse mutual inductance between the capacitor and the parallel chips. This module significantly reduces parasitic inductance in the power circuit, achieving excellent dynamic current sharing performance. The module employs a multi-layer copper block stacked heat conduction path to improve overall heat dissipation and overcurrent capacity. Inside the chip layers, each chip and terminal maintain a highly symmetrical layout, thereby balancing the magnetic field distribution, further reducing the current imbalance coefficient, and improving the overall electro-thermal performance of the package.

[0041] A specific embodiment of the present invention provides a multi-chip parallel orthogonal current sharing module, such as... Figure 3As shown, from bottom to top, it includes: DC negative copper plate 6, first chip layer, AC terminal copper plate and terminal 3, second chip layer and DC positive copper plate 5.

[0042] The DC negative copper plate 6 provided in the specific embodiment of the present invention is used to connect to the negative terminal of the external bus.

[0043] In a specific embodiment of the present invention, the first chip layer is located on the DC negative copper plate 6. The first chip layer includes a planar symmetrical arrangement of each lower power semiconductor device 10 and a lower metal pad 9 located on each lower power semiconductor device 10. The lower power semiconductor devices 10 are connected in parallel through the lower metal pads 9. The gate of each lower power semiconductor device 10 is led out through a set circuit, the source of the lower power semiconductor device is led out to the outside through the lower metal pad 9, and the drain of the corresponding lower power semiconductor device is led out to the outside through the AC terminal copper plate and terminal 3. Since each lower power semiconductor device 10 and the circuit are arranged in a highly symmetrical manner, the inductance of each path is consistent, so the current sharing effect is good.

[0044] In one specific embodiment, the circuit for leading out the gate of the lower power semiconductor device 10 provided in this embodiment is each lower flexible printed circuit board (FPC) 4. Each lower flexible printed circuit board 4 and each lower power semiconductor device 10 are arranged in a planar symmetrical layout. In the prior art, the source, drain and gate of the semiconductor device are generally led out through a ceramic substrate. However, the thermal conductivity of the ceramic substrate is poor. In this specific embodiment of the invention, the source and drain electrodes of the semiconductor device are led out through metal pads, which improves the heat transfer efficiency. Since the heat of the gate is less, this specific embodiment of the invention uses FPC to lead out the gate, which reduces the difficulty of the process.

[0045] In a specific embodiment of the present invention, the AC terminal copper plate and terminal 3 are located on each lower metal pad 9. The terminal 3 provided in this specific embodiment of the present invention can lead the source of the upper power semiconductor device and the drain of the lower power semiconductor device to the outside, while the drain of the upper power semiconductor device and the source of the lower power semiconductor device are led to the outside through the corresponding metal pads. The terminal and each lower power semiconductor device also maintain a highly symmetrical layout, thereby balancing the magnetic field distribution, further reducing the current imbalance coefficient, and improving the overall electro-thermal performance of the package. A decoupling capacitor 8 is provided inside the AC terminal copper plate. On the upper and lower surfaces of the decoupling capacitor 8, there are metal pads connecting the capacitor and metal pads connecting the capacitor below. The metal pads connecting the capacitor below are arranged parallel to each other with each lower metal pad, thereby realizing reverse mutual inductance between the decoupling capacitor and each lower power semiconductor device.

[0046] In one specific embodiment, the decoupling capacitor 8 is located at the center of the AC terminal metal pad, and each lower power semiconductor device 10 and each lower flexible printed circuit board 4 are equally spaced around the decoupling capacitor. This layout can further improve the current sharing effect by averaging the mutual inductance between the parallel path of each chip and the capacitor current path.

[0047] The second chip layer provided in this specific embodiment of the invention is located on the AC copper plate and terminal 3. The second chip layer includes upper power semiconductor devices 2 corresponding to the upper and lower positions of each lower power semiconductor device 10, such as... Figure 3 As shown, the lower power semiconductor device 10 and the corresponding upper power semiconductor device 2 are substantially overlapped in the horizontal direction and stacked in the vertical direction. Each upper power semiconductor device 2 is provided with an upper metal pad 7. The upper metal pad 7 and the metal pad connected to the capacitor are arranged parallel to each other, thereby realizing the reverse mutual inductance between the decoupling capacitor 8 and each upper power semiconductor device 2.

[0048] Since the current paths formed by the stacked upper power semiconductor devices 2 and the lower power semiconductor devices 10 are mutually inducted in the opposite direction with the decoupling capacitor 8, the mutual inductance of the vertical path is canceled, which significantly reduces the parasitic inductance of the power circuit.

[0049] In one specific embodiment, the materials of the AC terminal copper plate, the lower metal pad, the lower metal pad of the capacitor, the upper metal pad of the capacitor, and the upper metal pad provided in this embodiment are copper or copper-molybdenum, respectively.

[0050] In one specific embodiment, each of the lower power semiconductor devices and the upper power semiconductor devices provided in this embodiment is a MOSFET or an IGBT; and each of the lower power semiconductor devices and the upper power semiconductor devices is made of silicon carbide.

[0051] In one specific embodiment, this embodiment provides that each lower power semiconductor device is connected in parallel to form the lower arm of the half-bridge; and each upper power semiconductor device is connected in parallel to form the upper arm of the half-bridge.

[0052] On the other hand, the present invention provides a method for fabricating a multi-chip parallel orthogonal current sharing module, comprising:

[0053] (1) Form each lower power semiconductor device and each lower flexible printed circuit board in a planar symmetrical layout on the DC negative copper plate. Connect the gate and Kelvin source of each lower power semiconductor device to the corresponding lower flexible printed circuit board. Transfer the silver film of the lower metal pad to the corresponding lower power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the lower power semiconductor device and thus obtaining the lower bridge arm.

[0054] Each upper power semiconductor device and each upper flexible printed circuit board are formed in a planar symmetrical layout on the AC terminal copper plate. The gate and Kelvin source of each upper power semiconductor device are wired to the corresponding upper flexible printed circuit board. The silver film of the upper metal pad is transferred to the corresponding upper power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the upper power semiconductor device, and thus obtaining the upper bridge arm.

[0055] (2) Connect the AC terminal copper plate to the terminal, place the decoupling capacitor in the internal hole of the AC terminal copper plate, and use reflow soldering to connect the upper and lower metal pads of the capacitor to the upper and lower surfaces of the decoupling capacitor respectively.

[0056] (3) The lower bridge arm and the upper bridge arm are attached to the copper plate and the terminal of the AC terminal respectively, so that the lower connecting metal pad of the capacitor and each lower metal pad are arranged parallel to each other, and the upper metal pad and the upper connecting metal pad of the capacitor are arranged parallel to each other. The upper and lower flexible printed circuit boards are connected to the terminals to facilitate the gate of the upper and lower power semiconductor devices. The drain of the upper power semiconductor device of the upper bridge arm and the source of the lower power semiconductor device of the lower bridge arm are led out through the protruding terminals on the upper and lower copper plates respectively. The source of the upper power semiconductor device of the upper bridge arm and the drain of the lower power semiconductor device of the lower bridge arm are led out through the AC terminal. The last step of connecting the flexible printed circuit board to the terminal is by reflow soldering.

[0057] In specific embodiments of the present invention, matching metal pads and connectors are processed according to the size and layout of the capacitor and silicon carbide chip. The size of the capacitor connection pad is matched according to the size of the capacitor, and a 2mm high source pad is selected to alleviate stress problems in subsequent sintering.

[0058] In a specific embodiment of the present invention, the upper and lower surfaces of the metal pad are polished to improve the smoothness. Then, the surface impurities and oxide layer are thoroughly removed by a composite cleaning process of acid pickling and plasma water ultrasonic cleaning, so that the surface of the metal frame can meet the high flatness requirements and the levelness deviation does not exceed 20 μm.

[0059] In a specific embodiment of the present invention, a silver sintering process is used for the interconnection between the chip and the upper and lower metal blocks. Silver film is transferred onto the bottom surface of the chip and the metal blocks respectively, and then sintered sequentially in a vertical direction. At the same time, the capacitor is interconnected with the upper and lower metal substrates by reflow soldering.

[0060] In a specific embodiment of the present invention, the chip gate and Kelvin source are wired to multiple FPC flexible boards using flexible printed circuit board technology, and reflow soldering terminals are brought out on the upper layer of each FPC.

[0061] Specifically, the flexible printed circuit board (FPC) process is used to wire bond the chip gate and Kelvin source to multiple FPC boards. This includes first connecting the adhesive-free high-temperature resistant FPC board and the copper plate through a silver sintering process, and then performing a wire bonding process on the FPC.

[0062] In a specific embodiment of the present invention, the module is encapsulated to form a reliable insulation and protective layer, thereby protecting the power chip and internal interconnect structure and preventing external environmental factors from affecting the device performance and reliability.

[0063] like Figure 4 As shown, compared with the two traditional double-sided cooling modules and ordinary parallel orthogonal power modules, the parasitic inductance of the multi-chip parallel orthogonal current sharing module provided in the specific embodiment of the present invention is reduced by 97.14% compared with the traditional double-sided cooling module, and reduced by 85.71% compared with the latest orthogonal stacking module.

[0064] like Figure 5 As shown in the specific embodiment of the present invention, the current sharing performance of the four parallel lower bridge arms of the multi-chip parallel orthogonal current sharing module, namely the current curves of M5, M6, M7 and M8, are basically completely overlapping, and the dynamic current non-uniformity of the parallel multi-chip is 0.

Claims

1. A multi-chip parallel orthogonal current sharing module, characterized in that, From bottom to top, they include: DC negative copper plate, used to connect to the external bus negative terminal; The first chip layer is located on the DC negative electrode copper plate. The first chip layer includes each lower power semiconductor device arranged in a planar symmetrical layout and a lower metal pad located on each lower power semiconductor device. The AC end metal copper plate and terminals are located on each lower metal pad. A decoupling capacitor is set inside the AC end metal pad. A capacitor upper connection metal pad and a capacitor lower connection metal pad are set on the upper and lower surfaces of the decoupling capacitor. The capacitor lower connection metal pad and each lower metal pad are arranged parallel to each other, thereby realizing reverse mutual inductance between the decoupling capacitor and each lower power semiconductor device. The second chip layer is located on the AC terminal copper plate and terminal. The second chip layer includes upper power semiconductor devices corresponding to the upper and lower positions of each lower power semiconductor device. Each upper power semiconductor device is provided with an upper metal pad. The upper metal pad and the metal pad connected to the capacitor are arranged parallel to each other, thereby realizing the reverse mutual inductance between the decoupling capacitor and each upper power semiconductor device. The DC positive copper plate is located on each upper metal pad and is used to connect to the external bus positive terminal.

2. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The first chip layer also includes each lower flexible printed circuit board, which is symmetrically arranged in planar with each lower power semiconductor device. Each lower flexible printed circuit board is used to connect to the gate of the corresponding lower power semiconductor device and lead it to the outside.

3. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The second chip layer also includes upper flexible printed circuit boards, which are symmetrically arranged in planar with the upper power semiconductor devices. Each upper flexible printed circuit board is connected to the gate and the terminal of the corresponding upper power semiconductor device, so that the gate is led out to the outside through the terminal.

4. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The lower and upper power semiconductor devices are arranged symmetrically with respect to the terminals.

5. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The decoupling capacitor is located at the center of the metal pad at the AC end, and the lower power semiconductor devices are evenly spaced around the decoupling capacitor.

6. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The materials of the AC terminal copper plate, the lower metal pad, the lower metal pad of the capacitor, the upper metal pad of the capacitor, and the upper metal pad are copper or copper-molybdenum.

7. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The lower and upper power semiconductor devices are MOSFETs or IGBTs; The materials of the lower and upper power semiconductor devices are silicon carbide.

8. The multi-chip parallel orthogonal current sharing module according to claim 1, characterized in that, The lower power semiconductor devices are connected in parallel to form the lower bridge arm; The upper power semiconductor devices are connected in parallel to form the upper bridge arm.

9. A method for fabricating a multi-chip parallel orthogonal current sharing module according to any one of claims 1-8, characterized in that, include: (1) Form each lower power semiconductor device and each lower flexible printed circuit board in a planar symmetrical layout on the DC negative copper plate. Connect the gate and Kelvin source of each lower power semiconductor device to the corresponding lower flexible printed circuit board. Transfer the silver film of the lower metal pad to the corresponding lower power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the lower power semiconductor device and thus obtaining the lower bridge arm. Each upper power semiconductor device and each upper flexible printed circuit board are formed in a planar symmetrical layout on the AC terminal copper plate. The gate and Kelvin source of each upper power semiconductor device are wired to the corresponding upper flexible printed circuit board. The silver film of the upper metal pad is transferred to the corresponding upper power semiconductor device through the silver sintering process, thereby leading out the source and drain electrodes of the upper power semiconductor device, and thus obtaining the upper bridge arm. (2) Connect the AC terminal copper plate to the terminal, place the decoupling capacitor in the internal hole of the AC terminal copper plate, and use reflow soldering to connect the upper metal pad and the lower metal pad to the upper and lower surfaces of the decoupling capacitor respectively. (3) The lower bridge arm and the upper bridge arm are attached to the copper plate and the terminal of the AC end in corresponding positions, so that the lower connecting metal pad of the capacitor and each lower metal pad are arranged parallel to each other, and the upper metal pad and the upper connecting metal pad of the capacitor are arranged parallel to each other. The upper and lower flexible printed circuit boards are connected to the terminals so as to bring out the gate and Kelvin source of the upper and lower power semiconductor devices.

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