Clock synchronization system and method

Abstract

The invention provides a clock synchronization system and method, and the system comprises at least one clock source which is used for generating clock synchronization signals at intervals of a first preset time period, and the at least one clock source at least comprises a real-time clock source; the first processing module is used for determining a target clock source from the at least one clock source and adjusting the clock time of the first clock source configured by the first processing module based on a target clock synchronization signal generated by the target clock source; the second processing module is used for receiving a target clock synchronization signal generated by the target clock source and adjusting the clock time of the second clock source configured by the second processing module based on the target clock synchronization signal; wherein the adjusted clock time of the first clock source is synchronous with the adjusted clock time of the second clock source.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to a clock synchronization system and method. Background Technology

[0002] In the field of autonomous driving technology, autonomous driving systems include multiple sensors, such as cameras, radar, lidar, and ultrasonic sensors. High-precision time synchronization is crucial for multi-sensor data fusion. However, existing technologies mainly rely on a single clock source, such as a Global Positioning System (GPS) clock source or a Generalized Precision Time Protocol (GPTP) clock source. However, GPS clock sources are prone to loss and cannot guarantee clock synchronization; GPTP clock sources may also experience unstable clock signals due to hardware failures, resulting in low clock synchronization accuracy. Summary of the Invention

[0003] This disclosure provides a clock synchronization system and method to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this disclosure, a clock synchronization system is provided, wherein the system comprises: At least one clock source is used to generate a clock synchronization signal at each first preset time interval, wherein the at least one clock source includes at least a real-time clock source; The first processing module is configured to determine a target clock source from the at least one clock source, and adjust the clock time of the first clock source configured by the first processing module itself based on the target clock synchronization signal generated by the target clock source. The second processing module is used to receive the target clock synchronization signal generated by the target clock source, and adjust the clock time of the second clock source configured by the second processing module itself based on the target clock synchronization signal; wherein the clock time of the first clock source after adjustment is synchronized with the clock time of the second clock source after adjustment.

[0005] In one possible implementation, the first processing module is configured to detect whether the clock synchronization signal of the system default clock source among at least one clock source is read; if the clock synchronization signal of the system default clock source is read, the system default clock source is determined as the target clock source; if the clock synchronization signal of the system default clock source is not read, the clock synchronization signal of other clock sources among at least one clock source is read, and the other clock sources are determined as the target clock source.

[0006] In one possible implementation, the system further includes: An external selection device is used to generate a clock source selection signal and transmit it to the first processing module; The first processing module is used to acquire the clock source selection signal and determine the clock source corresponding to the clock source selection signal as the target clock source.

[0007] In one possible implementation, the system further includes: A signal switching switch is connected to each of the clock sources, as well as the first processing module and the second processing module, respectively. The at least one clock source is also used to send the clock synchronization signal to the signal switching switch; The signal switching switch is used to send the target clock synchronization signal generated by the target clock source to the first processing module and the second processing module.

[0008] In one possible implementation, the system further includes: The temperature compensation unit is used to monitor the system ambient temperature information and compare the system ambient temperature information with the preset ambient temperature information to determine the offset frequency; The real-time clock source is used to correct its own clock source frequency based on the offset frequency, so as to improve the timing accuracy of the real-time clock source.

[0009] In one possible implementation, the first processing module is configured to clear the non-integer seconds in the clock time of the first clock source when adjusting the clock time of the first clock source configured by itself. The second processing module is used to clear the non-integer seconds in the clock time of the second clock source to zero when adjusting the clock time of the second clock source configured by itself, so as to synchronize the clock time of the first clock source with the clock time of the second clock source.

[0010] In one possible implementation, the system further includes: At least one camera is connected to the first processing module; The first processing module is further configured to trigger the at least one camera to perform an exposure based on the target clock synchronization signal, so that the exposure time of the at least one camera is synchronized with the clock time of the first clock source and the clock time of the second clock source.

[0011] In one possible implementation, the second processing module is further configured to acquire device attribute information of the at least one camera and transmit the device attribute information to the first processing module; The first processing module is configured to determine the rising edge of the target clock synchronization signal as a trigger signal, and send the trigger signal and the device attribute information to the at least one camera; The at least one camera is used to take the time indicated by the trigger signal as the exposure time and perform exposure based on its corresponding device attribute information.

[0012] In one possible implementation, the first processing module is configured to determine the rising edge time of the target clock synchronization signal as the clock time of a first clock source configured by itself. The second processing module is used to determine the rising edge time of the target clock synchronization signal as the clock time of its own configured second clock source.

[0013] According to a second aspect of this disclosure, a clock synchronization method is provided, wherein the method includes: At least one clock source is determined, and each clock source generates a clock synchronization signal every first preset time interval; The first processing module determines the target clock source from the at least one clock source and adjusts the clock time of the first clock source configured by the first processing module itself based on the target clock synchronization signal generated by the target clock source. Based on the target clock synchronization signal generated by the target clock source, the clock time of the second clock source configured by the second processing module is adjusted; wherein, the adjusted clock time of the first clock source is synchronized with the adjusted clock time of the second clock source.

[0014] The clock synchronization system and method disclosed herein provide at least one clock source, and each clock source generates a clock synchronization signal at regular intervals. A first processing module can determine a suitable clock source as a target clock source from the at least one clock source. The first and second processing modules can adjust their times based on the target clock synchronization signal of the target clock source to synchronize the time of the first clock source of the first processing module and the second clock source of the second processing module. In this disclosure, the clock source includes at least a real-time clock source. The time provided by the real-time clock source is not synchronized with UTC (Universal Time Coordinated), avoiding time jumps when restoring the use of external GPS and GPTP clock sources. It also addresses scenarios where GPS is lost or there is no GPS algorithm. The target clock source generates a clock synchronization signal at regular intervals, thus enabling the first clock source of the first processing module and the second clock source of the second processing module to synchronize their times at regular intervals, ensuring the accuracy of time synchronization and the consistency of data acquisition. Furthermore, when multiple clock sources exist, if one clock source malfunctions, other clock sources can be used for time synchronization to ensure overall time synchronization.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0016] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0017] Figure 1 This is a schematic diagram of the structure of a clock synchronization system provided in an embodiment of the present disclosure; Figure 2 Circuit diagram for the RTC clock source; Figure 3 A circuit diagram of a signal switching switch provided in an embodiment of this disclosure; Figure 4 This is a timing diagram of camera exposure; Figure 5 A flowchart of a clock synchronization method provided in an embodiment of this disclosure. Detailed Implementation

[0018] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0019] This disclosure provides a clock synchronization system. Figure 1 This is a schematic diagram of the structure of a clock synchronization system provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the system includes: At least one clock source 10 is used to generate a clock synchronization signal at each first preset time interval, and the at least one clock source 10 includes at least a real-time clock source. The first processing module 20 is configured to determine a target clock source from at least one clock source 10, and adjust the clock time of the first clock source configured by the first processing module 20 itself based on the target clock synchronization signal generated by the target clock source. The second processing module 30 is used to receive the target clock synchronization signal generated by the target clock source, and adjust the clock time of the second clock source configured by the second processing module 30 itself based on the target clock synchronization signal; wherein the clock time adjusted by the first clock source is synchronized with the clock time adjusted by the second clock source.

[0020] In this embodiment of the disclosure, the system includes three clock sources as an example for illustration.

[0021] In one embodiment, at least one clock source includes: a real-time clock source, a global positioning system clock source, and an Ethernet clock source.

[0022] like Figure 1 As shown, the real-time clock source is the RTC (Real-Time Clock) clock source, the global positioning system clock source is the GPS clock source, and the Ethernet clock source is the GPTP clock source.

[0023] RTC, GPS, and GPTP clock sources can all generate clock synchronization signals (1PPS). However, GPTP clock sources require an Ethernet switch to generate the clock synchronization signal. The Ethernet switch can use the SJA1105 chip, and the signal generated by the GPTP clock source is used by the TSC (Time Switch Controller) module of the Ethernet switch to generate the clock synchronization signal.

[0024] In this embodiment, the GPS clock source and GPTP clock source are the original clock sources in the electronic device. However, because the error of the GPTP clock source is in the sub-millisecond or even millisecond range, it will increase the error and reduce the accuracy in actual testing. The GPS clock source is easily lost in actual use. After the GPS is lost as a clock source, the electronic device will suddenly receive satellite signals and synchronize with GNSS (Global Navigation Satellite System) time, causing the time sent by GPS to the electronic device to jump, making it impossible to ensure clock consistency. Therefore, this disclosure also adds an RTC clock source. The time provided by the RTC clock source is not synchronized with UTC (Universal Time Coordinated) time, avoiding time jumps when restoring the use of external GPS clock sources and GPTP clock sources. It can also cope with application scenarios where GPS is lost or there is no GPS algorithm.

[0025] In one embodiment, the system further includes: a temperature compensation unit (not shown in the figure), used to monitor the system ambient temperature information and compare the system ambient temperature information with preset ambient temperature information to determine the offset frequency; A real-time clock source is used to correct its own clock source frequency based on the offset frequency in order to improve the timing accuracy of the real-time clock source.

[0026] The RTC clock source in this embodiment is a clock source that integrates a TCXO (Temperature Compensated Crystal Oscillator). By dynamically adjusting the crystal oscillation frequency, it can offset the frequency drift caused by temperature changes, making the RTC clock source more accurate when performing clock synchronization.

[0027] The RTC clock source uses a button battery as a backup power source to ensure continuous operation.

[0028] Figure 2 The circuit diagram is for the RTC clock source.

[0029] like Figure 2 As shown, the RTC clock source uses a PCF2129AT chip with an integrated 32.768KHz crystal oscillator (circle 1 in the figure). After the RTC clock source internal register is configured to divide the frequency through the I2C channel, a 1Hz pulse signal (1PPS pulse signal) can be output through the CLK_OUT pin (circle 2 in the figure). This signal can be used as the basis for the time stream.

[0030] The real-time time information from the RTC clock source is transmitted to the first and second processing modules via the SCL (Serial Clock Line) pin (circle 3 in the diagram) using the I2C protocol. Simultaneously, both the first and second processing modules receive a 1PPS pulse signal (clock synchronization signal) and synchronize the real-time time transmitted via the I2C protocol upon receiving it.

[0031] In this embodiment of the disclosure, the first processing module 20 can be an MCU (Microcontroller Unit), and the second processing module 30 can be a SOC (System on Chip).

[0032] See also Figure 1 At least one clock source 10 generates a clock synchronization signal of 1PPS (PPS: pulses per second), which means that the time is updated once per second.

[0033] The clock synchronization signal generated by each clock source 10 is first transmitted to its respective buffer, and then to the signal switching switch 40. The buffer has a level shifter and unidirectional conductivity, allowing the signal to conduct in one direction. The signal switching switch 40 ensures the correct access of clock synchronization signals from different clock sources, achieving nanosecond-level accuracy.

[0034] The signal switching switch 40 can be a high-side switch.

[0035] In one embodiment, the signal switching switch 40 is connected to each clock source 10, the first processing module 20, and the second processing module 30, respectively. At least one clock source 10 is also used to send a clock synchronization signal to a signal switching switch 40; The signal switching switch 40 is used to send the target clock synchronization signal generated by the target clock source to the first processing module 20 and the second processing module 30.

[0036] Figure 3 A circuit diagram of a signal switching switch provided in an embodiment of this disclosure.

[0037] like Figure 1 and Figure 3 As shown, the clock synchronization signals generated by the RTC clock source, GPS clock source, and GPTP clock source are transmitted to the signal switching switch 40. Specifically, the clock synchronization signal generated by the GPS clock source is transmitted to the IA0 pin of the signal switching switch 40, the clock synchronization signal generated by the GPTP clock source is transmitted to the IA1 pin of the signal switching switch 40, and the clock synchronization signal generated by the RTC clock source is transmitted to the IA2 pin of the signal switching switch 40.

[0038] Then, the first processing module 20 determines the target clock source from the signal switching switch 40, and the signal switching switch 40 transmits the target clock synchronization signal of the target clock source to the first processing module 20 and the second processing module 30 through the Y pin.

[0039] In one embodiment, the signal switching switch 40 also transmits the target clock synchronization signal to the Ethernet switch, which is connected to multiple sensors, thus enabling clock synchronization of multiple sensors via the Ethernet switch.

[0040] In this disclosure, when multiple clock sources 10 exist, a circuit employing a signal switching switch and a buffer functions as a level converter and also has unidirectional conductivity. This can compensate for the signal crosstalk problem during the transmission of clock synchronization signals on PCB traces, improve the load capacity of clock synchronization signals, and meet the requirements of different users and different solutions for different clock sources. It can automatically switch clock sources and also avoid the problem that electronic devices cannot guarantee time synchronization accuracy after a single clock source is lost.

[0041] In one embodiment, the first processing module 20 is configured to clear the non-integer seconds in the clock time of the first clock source when adjusting the clock time of the first clock source configured by itself. The second processing module 30 is used to clear the non-integer seconds in the clock time of the second clock source when adjusting the clock time of the second clock source configured by itself, so as to synchronize the clock time of the first clock source with the clock time of the second clock source.

[0042] After receiving the target clock synchronization signal, the first processing module 20 and the second processing module 30 adjust the clock time of their respective internal clock sources. During the adjustment process, non-integer second time data is cleared. For example, the first processing module 20 may read a time of 8931.567S, while the second processing module 30 may read a time of 8931.876S. After reading the target clock synchronization signal once, the first processing module 20 and the second processing module 30 clear the non-integer second time data and change it to 8931.000S to achieve high-precision synchronization at the nanosecond level.

[0043] In one embodiment, the first processing module 20 is used to determine the time corresponding to the rising edge of the target clock synchronization signal as the clock time of the first clock source configured by itself. The second processing module 30 is used to determine the rising edge time of the target clock synchronization signal as the clock time of the second clock source configured by itself.

[0044] The clock synchronization signal is a series of pulses alternating between high and low levels. When the clock synchronization signal is a 1PPS pulse signal, the difference between the rising edges of two high levels is 1 second. In this disclosure, when the target clock synchronization signal is on a rising edge, the first processing module 20 and the second processing module 30 determine the time corresponding to that rising edge as the clock time of their configured clock source.

[0045] In one embodiment, the first processing module 20 is specifically used to detect whether the clock synchronization signal of the system default clock source among at least one clock source 10 is read; if the clock synchronization signal of the system default clock source is read, the system default clock source is determined as the target clock source; if the clock synchronization signal of the system default clock source is not read, the clock synchronization signal of other clock sources among at least one clock source is read, and the other clock source is determined as the target clock source.

[0046] Specifically, among at least one clock source 10, there will be a system default clock source. For example, in this embodiment, the RTC clock source can be set as the system default clock source. Therefore, the first processing module 20 will first detect whether the clock synchronization signal of the RTC clock source is read. If the clock synchronization signal of the RTC clock source is read, the RTC clock source is determined as the target clock source, and the clock synchronization signal generated by the RTC clock source is transmitted to the first processing module 20 and the second processing module 30 as the target clock synchronization signal. If the clock synchronization signal of the RTC clock source is not read, the clock synchronization signal of other clock sources (e.g., GPS clock source) is read. If the clock synchronization signal of other clock sources is read, the other clock source is used as the target clock source; if the clock synchronization signal of other clock sources is not read, the clock synchronization signal of the RTC clock source is read again until the clock synchronization signal of one of the clock sources is read.

[0047] Specifically, the first processing module 20 is connected to the S0, S1 and EN pins of the signal switching switch 40. By switching the signals on these three pins, the clock synchronization signals from different clock sources can be read.

[0048] Table 1 shows the switching logic for the S0, S1, and EN pins.

[0049] As shown in Table 1 above, when the first processing module 20 outputs S0, S1 and EN pins as 010, the RTC clock source is determined as the target clock source; when the first processing module 20 outputs S0, S1 and EN pins as 000, the GPS clock source is determined as the target clock source; and when the first processing module 20 outputs S0, S1 and EN pins as 001, the GPTP clock source is determined as the target clock source.

[0050] In one embodiment, an external selection device (not shown) is used to generate a clock source selection signal and transmit it to the first processing module 20; The first processing module 20 is used to acquire the clock source selection signal and determine the clock source corresponding to the clock source selection signal as the target clock source.

[0051] Specifically, when determining the target clock source, the user can also select it through an external selection device (APP). The user provides the first processing module 20 with a clock source selection signal, which includes which clock source the user wants to select. After receiving the clock source selection signal, the first processing module 20 determines the target clock source based on the clock source in the clock source selection signal, thereby ensuring compatibility with different users' usage of the electronic device.

[0052] In one embodiment, the system further includes at least one camera 50 connected to the first processing module 20; The first processing module 20 is also used to trigger at least one camera 50 to perform exposure based on the target clock synchronization signal, so that the exposure time of at least one camera is synchronized with the clock time of the first clock source and the clock time of the second clock source.

[0053] In one embodiment, the second processing module 30 is further configured to acquire device attribute information of at least one camera 50 and transmit the device attribute information to the first processing module 20; The first processing module 20 is used to determine the rising edge of the target clock synchronization signal as a trigger signal, and send the trigger signal and device attribute information to at least one camera 50; At least one camera 50 is used to take the time of trigger signal identification as the exposure time and perform exposure based on its respective corresponding device attribute information.

[0054] Specifically, such as Figure 1 As shown, the second processing module 30 transmits the device attribute information corresponding to each camera to the first processing module 20 via UART (Universal Asynchronous Receiver and Transmitter). The device attribute information includes the camera number, the camera's frame rate, and the delayed exposure time. After reading the target clock synchronization signal, the first processing module 20 determines the rising edge of the target clock synchronization signal as the trigger signal and sets the frame rate and exposure time of each camera through its timer function module. Then, the first processing module 20 sends the trigger signal to the camera deserializer, which then sends it to each camera 50. Each camera 50 then uses the time indicated by the trigger signal as the exposure time and performs exposure based on its corresponding device attribute information. In this disclosure, using the time corresponding to the rising edge of the target clock synchronization signal as the camera exposure time ensures that the camera exposure time is synchronized with the time of the first clock source of the first processing module and the second clock source of the second processing module, thereby guaranteeing data time consistency.

[0055] Figure 4 This is a timing diagram of camera exposure. For example... Figure 4As shown, taking three cameras as an example, the cameras begin exposure when the target clock synchronization signal is at its rising edge. However, each camera has different device attribute information. For example, camera 1 delays exposure by 10ms, with a frame rate of 30 frames per second (PPS pulse), so each frame lasts 33.3ms. Camera 2 delays exposure by 20.5ms, with a frame rate of 20 frames per second, so each frame lasts 50ms. Camera 3 does not delay exposure, with a frame rate of 25 frames per second, so each frame lasts 40ms. Each camera uses the rising edge of the target clock synchronization signal as the trigger signal for exposure, ensuring the consistency and timeliness of the exposure times of multiple cameras and reducing exposure time errors.

[0056] In this disclosure, the aforementioned clock synchronization system can be applied to an advanced driving assistance system (ADAS).

[0057] This disclosure also provides a clock synchronization method. Figure 5 A flowchart of the clock synchronization method provided in the embodiments of this disclosure is shown below. Figure 5 As shown, the method includes: Step 501: Determine at least one clock source, each clock source generates a clock synchronization signal at a first preset time interval, and at least one clock source includes at least a real-time clock source. Step 502: The first processing module determines the target clock source from at least one clock source and adjusts the clock time of the first clock source configured by the first processing module itself based on the target clock synchronization signal generated by the target clock source. Step 503: Based on the target clock synchronization signal generated by the target clock source, adjust the clock time of the second clock source configured by the second processing module itself; wherein the adjusted clock time of the first clock source is synchronized with the adjusted clock time of the second clock source.

[0058] The specific details of each part of the above method have been described in detail in the device implementation section. For any undisclosed details, please refer to the device implementation section, and therefore will not be repeated here.

[0059] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0061] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A clock synchronization system, characterized in that, The system includes: At least one clock source is used to generate a clock synchronization signal at each first preset time interval, wherein the at least one clock source includes at least a real-time clock source; The first processing module is configured to determine a target clock source from the at least one clock source, and adjust the clock time of the first clock source configured by the first processing module itself based on the target clock synchronization signal generated by the target clock source. The second processing module is used to receive the target clock synchronization signal generated by the target clock source, and adjust the clock time of the second clock source configured by the second processing module itself based on the target clock synchronization signal; wherein the clock time of the first clock source after adjustment is synchronized with the clock time of the second clock source after adjustment.

2. The clock synchronization system according to claim 1, characterized in that, The first processing module is used to detect whether the clock synchronization signal of the system default clock source in at least one clock source is read; If the clock synchronization signal of the system default clock source is read, then the system default clock source is determined as the target clock source; If the clock synchronization signal of the system's default clock source is not read, then the clock synchronization signal of at least one other clock source is read, and the other clock source is determined as the target clock source.

3. The clock synchronization system according to claim 1, characterized in that, The system also includes: An external selection device is used to generate a clock source selection signal and transmit it to the first processing module; The first processing module is used to acquire the clock source selection signal and determine the clock source corresponding to the clock source selection signal as the target clock source.

4. The clock synchronization system according to claim 1, characterized in that, The system also includes: A signal switching switch is connected to each of the clock sources, as well as the first processing module and the second processing module, respectively. The at least one clock source is also used to send the clock synchronization signal to the signal switching switch; The signal switching switch is used to send the target clock synchronization signal generated by the target clock source to the first processing module and the second processing module.

5. The clock synchronization system according to claim 1, characterized in that, The system also includes: The temperature compensation unit is used to monitor the system ambient temperature information and compare the system ambient temperature information with the preset ambient temperature information to determine the offset frequency; The real-time clock source is used to correct its own clock source frequency based on the offset frequency, so as to improve the timing accuracy of the real-time clock source.

6. The clock synchronization system according to claim 1, characterized in that, The first processing module is used to clear the non-integer seconds in the clock time of the first clock source when adjusting the clock time of the first clock source configured by itself. The second processing module is used to clear the non-integer seconds in the clock time of the second clock source to zero when adjusting the clock time of the second clock source configured by itself, so as to synchronize the clock time of the first clock source with the clock time of the second clock source.

7. The clock synchronization system according to claim 1, characterized in that, The system also includes: At least one camera is connected to the first processing module; The first processing module is further configured to trigger the at least one camera to perform an exposure based on the target clock synchronization signal, so that the exposure time of the at least one camera is synchronized with the clock time of the first clock source and the clock time of the second clock source.

8. The clock synchronization system according to claim 7, characterized in that, The second processing module is further configured to acquire device attribute information of the at least one camera and transmit the device attribute information to the first processing module; The first processing module is configured to determine the rising edge of the target clock synchronization signal as a trigger signal, and send the trigger signal and the device attribute information to the at least one camera; The at least one camera is used to take the time indicated by the trigger signal as the exposure time and perform exposure based on its corresponding device attribute information.

9. The clock synchronization system according to claim 1, characterized in that, The first processing module is used to determine the rising edge time of the target clock synchronization signal as the clock time of the first clock source configured by itself; The second processing module is used to determine the rising edge time of the target clock synchronization signal as the clock time of its own configured second clock source.

10. A clock synchronization method, characterized in that, The method includes: At least one clock source is determined, and each clock source generates a clock synchronization signal at a first preset time interval. The at least one clock source includes at least a real-time clock source. The first processing module determines the target clock source from the at least one clock source and adjusts the clock time of the first clock source configured by the first processing module itself based on the target clock synchronization signal generated by the target clock source. Based on the target clock synchronization signal generated by the target clock source, the clock time of the second clock source configured by the second processing module is adjusted; wherein, the adjusted clock time of the first clock source is synchronized with the adjusted clock time of the second clock source.

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