FPGA-based electric piano teaching management system and communication method

Abstract

The invention relates to an FPGA-based electric piano teaching management system and a communication method. The FPGA-based electric piano teaching management system comprises a mainboard, an upper computer, a plurality of daughter boards and a communication unit, the mainboard comprises a first FPGA module, the daughter board comprises a second FPGA module, and both the first FPGA module and the second FPGA module are provided with crystal oscillator modules; the second FPGA module is also connected with an audio encoding and decoding device, and the second FPGA module is connected with an electric piano through the audio encoding and decoding device; the communication unit comprises an RJ45 module, an RS422 transceiver chip and a USB module. The first FPGA module, the second FPGA module and the upper computer communicate with each other through a communication method. The intelligent networking architecture of the main board and the sub-boards is adopted, the FPGA module is adopted as a processing chip, full-duplex real-time communication between the main board and the sub-boards is ensured through a communication method, and the system can be used for transmitting audio data and also can be used for transmitting control information, so that teaching and management of the whole team and group are realized.

Description

Technical Field

[0001] This invention relates to the field of electric piano teaching management technology, specifically to an FPGA-based electric piano teaching management system and communication method. Background Technology

[0002] In recent years, with the development of electronic technology, the trend of intelligent teaching management equipment has become increasingly apparent, and multimedia teaching technology has been widely used. However, compared with the teaching of conventional subjects, the significant characteristics of electric piano teaching are the large number of devices, complex management, and diverse modes. Depending on the size of the classroom, each classroom can generally accommodate 30 to 70 students and an electric piano. The larger the classroom capacity, the greater the difficulty of teaching and management. Group practice and teacher feedback, which are common in music teaching, are also very easy to interfere with each other.

[0003] Currently, some intelligent digital piano teaching management systems have emerged on the market, but most of them use MCU microcontrollers as the main control unit, such as CN203026112U, which uses a single-chip microcomputer as the controller. Due to the limitations of the serial architecture and processing capabilities of the MCU, the performance is acceptable when the data volume is small, but as the number of students increases, the pressure of data sampling and processing rises sharply, inevitably causing problems such as packet loss, distortion, and large delays. It is difficult to guarantee the distortion-free sampling and transmission of digital audio, and there will be a significant signal-to-noise ratio loss when multi-channel synthesis. In practical applications, the performance is not outstanding, hindering the further improvement of music teaching methods and means. Summary of the Invention

[0004] To address the problem that existing electric piano teaching management systems cannot be applied to large-group teaching scenarios, this invention provides an FPGA-based electric piano teaching management system and communication method. It adopts an intelligent networking architecture of a motherboard and multiple daughterboards, uses an FPGA module as the processing chip, and ensures full-duplex real-time communication between the motherboard and multiple daughterboards through a communication method. It can be used not only to transmit audio data but also to transmit control information, enabling teaching and management of the entire class.

[0005] To achieve the above objectives, the first aspect of the present invention proposes an FPGA-based electric piano teaching management system, including a motherboard, a host computer, multiple daughterboards, and a communication unit; The motherboard includes a first FPGA module, and the daughterboard includes a second FPGA module. Both the first FPGA module and the second FPGA module are equipped with a crystal oscillator module. The first FPGA module is also connected to a power supply module. The second FPGA module is also connected to an audio encoder / decoder, and the second FPGA module is connected to an electric piano through the audio encoder / decoder. The communication unit includes an RJ45 module, an RS422 transceiver chip, and a USB module. The first FPGA module communicates with the second FPGA module through the RS422 transceiver chip and the RJ45 interface. The first FPGA module communicates with the host computer through the USB module.

[0006] Based on the actual classroom capacity, each digital piano is equipped with a daughterboard and a headset, and a host computer is equipped with a motherboard. The motherboard connects to all daughterboards via an RJ45 module and to the host computer via a USB module. The overall hardware structure is simple and easy to set up.

[0007] Furthermore, the daughterboard is provided with an RJ45 interface, which is connected to the second FPGA module. Two of the RJ45 interfaces are used for RS422 data transmission, two for RS422 data reception, two for daughterboard power supply, and two for daughterboard grounding. The subboard is also equipped with an audio input interface, which is connected to an audio codec and also to an electric piano; The subboard is also equipped with an audio output interface, which is connected to an audio codec and a headset. The subboard is also equipped with a microphone input interface, which is connected to an audio codec and a headset.

[0008] The connection between the motherboard and the daughterboard uses an RJ45 interface, which is connected via an RJ45 module (Category 5 network cable) to enable communication between the motherboard and the daughterboard. The daughterboard does not require an additional dedicated power supply, as it meets the power supply needs of the daughterboard.

[0009] Furthermore, the second FPGA module is connected to the audio encoder / decoder via an I2S interface; The second FPGA module is connected to multiple buttons, and the second FPGA module is electrically connected to each of the multiple buttons. Multiple indicator lights are set for each of the multiple buttons, and the multiple indicator lights are electrically connected to the FPGA module. The buttons include a volume up button, a volume down button, a microphone on button, a microphone mute button, a hand raise button, and a hand cancel button.

[0010] The buttons facilitate human-computer interaction, and the audio encoder / decoder converts digital audio signals into analog signals or analog input audio / microphone signals into digital signals.

[0011] Furthermore, the first FPGA module includes a PLL module and a global reset module. The PLL module is connected to the crystal oscillator module, multiplies the clock signal output by the crystal oscillator module, and outputs the working clock. The global reset module receives asynchronous reset signals from external inputs to achieve synchronous reset and synchronous release. The USB module contains a transmit FIFO and a receive FIFO. The first FPGA module is connected to the RS422 transceiver chip via a UART serial port.

[0012] A second aspect of the present invention provides a communication method for an FPGA-based electric piano teaching management system, comprising: Step 1: On the host computer, set one sub-board as the teacher sub-board and the other multiple sub-boards as student sub-boards. The host computer sends the setting parameters of the teacher sub-board to the main board. Step 2: The teacher sub-board or one student sub-board transmits the audio output from the electric piano to the main board, and the main board sends the real-time audio data to other sub-boards; Step 3: The motherboard monitors the connection status of the teacher sub-board and multiple student sub-boards. The motherboard receives the hand-raise button and the cancel hand-raise button from the sub-boards and sends them to the host computer one by one.

[0013] Furthermore, the host computer sends downlink frames to the motherboard, and the motherboard sends uplink frames to the host computer. If the data to be transmitted needs to be divided into multiple bytes, the little-endian mode is used by default, that is, the low-order data is sent first, and then the high-order data is sent. After receiving the downlink frame, the motherboard sends a return frame to the host computer. The downlink frame includes: a reset frame, used to complete a device reset; Device firmware readback frames are used to confirm whether the firmware information is correct; Broadcast control frames are used to enable or disable the broadcast function of any daughterboard; The monitoring control frame is used for real-time uploading and monitoring of audio from any one or more daughterboards. Subboard grouping control frame, used to group multiple student subboards; The daughterboard operating mode setting frame is used to reset the daughterboard, enable / mute the microphone, control the volume, and detect whether the daughterboard is receiving data from the motherboard. The teacher subboard designated frame is used to transmit the teacher subboard's setting parameters to the mainboard.

[0014] Furthermore, the uplink frame includes: The "Raise Hand" indicator frame on the sub-board indicates that after the raise hand button or cancel raise hand button on any sub-board is pressed, the main board records the corresponding "raise hand status" and sends it to the host computer one by one. The motherboard monitors the connection status of each daughterboard in real time. When the connection status of any daughterboard changes (connecting or unplugging the network cable), the motherboard uploads the connection status of the daughterboard to the host computer. Furthermore, the motherboard sends a lower communication frame to the daughterboard, and the daughterboard sends an upper communication frame to the motherboard. The lower communication frame includes: The daughterboard audio pass-through frame is used by the motherboard to send real-time audio data to the daughterboard. The daughterboard MIDI configuration frame is used to configure the MIDI interface of the electric piano. The daughterboard status control frame is used to control the call cancellation, volume, and MIC gain functions of a single daughterboard. The upper communication frame includes: Subboard MIDI upload frame, used to upload the MIDI information of the current electric piano in real time; After each daughterboard is powered on and configured, it automatically uploads its MIC and audio input combined data at a 43.945K sampling rate, 16-bit dual-channel mode, and hand-raising information to the motherboard periodically. The motherboard then receives and processes the data.

[0015] The beneficial effects of the present invention through the above technical solution are as follows: 1. This invention can be used for multi-person teaching of electric pianos, achieving lossless digital audio sampling and transmission. Based on the actual classroom capacity, each electric piano is equipped with a daughterboard and headset, and a host computer is equipped with a motherboard. The motherboard connects to all daughterboards via an RJ45 module and a USB module, and the motherboard connects to the host computer via a USB module. A first FPGA module is used as the control unit of the motherboard, and a second FPGA module is used as the control unit of the daughterboards. Compared with MCU chips, FPGA modules have better hardware parallelism and higher clock frequency, enabling higher baud rates without changing the UART timing, meeting the 1406.25Kbps digital signal rate received by the audio encoder / decoder. Full-duplex real-time communication between the motherboard and daughterboards allows for the transmission of not only audio data but also control information.

[0016] 2. In this invention, the motherboard and multiple daughterboards are connected via an RJ45 module. The daughterboards are used to complete the data processing of the audio codec and to interact with the motherboard. The RJ45 module meets the communication and power supply needs between the motherboard and the daughterboards, and the hardware circuit structure is simple.

[0017] 3. This invention utilizes communication methods to meet the needs of electric piano classrooms of different sizes. It employs hardware-level sampling and processing, ensuring no additional data latency even with multi-channel mixing and synthesis. This further guarantees distortion-free digital audio sampling and transmission, and provides support for comprehensive and flexible teaching management. It features connectivity status monitoring, broadcasting, electronic calling, group practice, recording, and monitoring functions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an FPGA-based electric piano teaching management system according to the present invention; Figure 2 This is a schematic diagram of the sub-board structure of an FPGA-based electric piano teaching management system according to the present invention. Figure 3 This is a schematic diagram of the motherboard structure of an FPGA-based electric piano teaching management system according to the present invention. Figure 4 This is a schematic diagram of the first FPGA module structure of an FPGA-based electric piano teaching management system according to the present invention. Figure 5 This is a flowchart illustrating the steps of a communication method for an FPGA-based electric piano teaching management system according to the present invention.

[0019] The diagram numbers are as follows: 1 is the motherboard, 2 is the host computer, 3 is the daughter board, 4 is the first FPGA module, 5 is the second FPGA module, 7 is the crystal oscillator module, 8 is the power supply module, 9 is the audio encoder / decoder, 10 is the electric piano, 11 is the RJ45 module, 12 is the RS422 transceiver chip, 13 is the USB module, 14 is the headset, 15 is the button, and 16 is the indicator light. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figures 1-5 As shown, an FPGA-based electric piano teaching management system includes a motherboard 1, a host computer 2, multiple daughter boards 3, and a communication unit. The motherboard 1 includes a first FPGA module 4, and the daughterboard 3 includes a second FPGA module 5. Both the first FPGA module 4 and the second FPGA module 5 are equipped with a crystal oscillator module 7. The first FPGA module 4 is also connected to a power supply module 8. The second FPGA module 5 is also connected to an audio encoder / decoder 9, and the second FPGA module 5 is connected to an electric piano 10 through the audio encoder / decoder 9. The communication unit includes an RJ45 module 11, an RS422 transceiver chip 12, and a USB module 13. The first FPGA module 4 is connected to the second FPGA module 5 through the RS422 transceiver chip 12 and the RJ45 interface. The first FPGA module 4 is connected to the host computer 2 through the USB module 13.

[0021] In this invention, the first FPGA module 4 is equipped with 80 high-speed UART serial full dual-port interfaces. Each serial interface is then converted to RS422 differential level via an RS422 transceiver chip. The first FPGA module 4 is connected to the RS422 transceiver chip on one side of the second FPGA module 5 via an RJ45 module 11 to convert the signals into UART signals for communication with the second FPGA module 5. The first FPGA module 4 and the second FPGA module 5 are connected via a Category 5 network cable.

[0022] FPGA: It is short for Field Programmable Gate Array. It contains a large number of programmable resources, mainly including lookup tables (LUTs), registers, memory, hardware multipliers, PLLs, etc.

[0023] The corresponding number of electric pianos 10 is 80.

[0024] Preferably, the daughterboard 3 is provided with an RJ45 interface, which is connected to the second FPGA module 5. Two of the RJ45 interfaces are used for RS422 data transmission, two for RS422 data reception, two for the power supply of the daughterboard 3, and two for the grounding of the daughterboard 3. The subboard 3 is also provided with a 3.5mm audio input interface, which is connected to the audio codec 9 and also to the electric piano 10; The sub-board 3 is also provided with a 3.5mm audio output interface, which is connected to the audio codec 9 and is also connected to a headset 14. The sub-board 3 is also equipped with a 3.5mm microphone input interface, which is connected to the audio codec 9 and is also connected to a headset 14.

[0025] Preferably, the second FPGA module 5 is connected to the audio encoder / decoder 9 via an I2S interface, the crystal oscillator module 7 provides the operating clock for the second FPGA module 5, and the RS422 transceiver chip 12 converts the TTL level generated by the second FPGA module 5 into an RS422 level and sends it to the motherboard 1.

[0026] To ensure distortion-free transmission of the playing sound from the electric piano 10, the sampling rate of the audio encoder / decoder 9 is set to 43.945kHz, exceeding the Nyquist sampling theorem requirement of 20kHz, which is the limit of human hearing.

[0027] The digital output of audio codec 9 is 16-bit sampled quantized data in stereo, with a net bit rate of 43.945 * 16 * 2 = 1406.25 Kbps. Similarly, the digital signal rate received by audio codec 9 is also 1406.25 Kbps. This high transmission rate significantly exceeds the standard baud rate of conventional UART serial ports (typically 115.2 Kbps), making it difficult for ordinary MCUs, microcontrollers, and other microcontrollers to handle. However, FPGAs, with their excellent hardware parallelism and higher clock speeds, can achieve higher baud rates without altering the UART timing. Generally, an FPGA's clock speed only needs to be at least eight times the UART baud rate to successfully complete full-duplex UART transmission and reception. To allow for sufficient margin, the main frequency of the second FPGA module 5 is set to 45MHz, and all other frequencies are integer multiples of this frequency. The UART's division ratio is set to 9, which means the baud rate is as high as 5Mbps. This ensures full-duplex real-time communication between the motherboard 1 and the daughterboard 3, which can be used not only to transmit audio data, but also to transmit control information and status flags.

[0028] The second FPGA module 5 is connected to multiple buttons 15, and the second FPGA module 5 is electrically connected to the multiple buttons 15 respectively. Multiple indicator lights 16 are provided corresponding to the multiple buttons 15, and the multiple indicator lights 16 are electrically connected to the FPGA module respectively. The button 15 includes a volume + button, a volume - button, a microphone on button, a microphone mute button, a hand raise button, and a hand cancel button.

[0029] Preferably, the first FPGA module 4 includes a PLL module 401 and a global reset module 402. The PLL module 401 is connected to the crystal oscillator module 7, multiplies the clock signal output by the crystal oscillator module 7, and outputs the working clock. The global reset module 402 receives an externally input asynchronous reset signal to achieve synchronous reset and synchronous release. The USB module 13 contains a transmit FIFO and a receive FIFO; The first FPGA module 4 is connected to the RS422 transceiver chip 12 via a UART serial port.

[0030] When host computer 2 sends a command to motherboard 1, the command is cached in the receive FIFO and an indication signal and command identification code are given to motherboard 1 to facilitate timely processing. When motherboard 1 sends data to host computer 2, the data is first written to the transmit FIFO and then uploaded to host computer 2 by USB module 13. Since the operating frequency of USB module 13 is different from that of motherboard 1, data reading and writing here need to be synchronized across clock domains. This design adopts a 3-level register synchronization strategy to effectively avoid metastability and timing constraint tension caused by cross-clock domains.

[0031] The power module 8 includes a rectifier unit and a DC-DC unit. The power module 8 is connected to AC220V mains power. After rectification, it outputs DC current. The DC-DC unit adjusts the voltage to power the main board 1. The daughter board 3 is connected to the main board 1 through the RJ45 module 11 to be powered on.

[0032] Example 2 like Figure 5 As shown, the communication method of an FPGA-based electric piano teaching management system based on the hardware part of Embodiment 1 includes: Step 1: On the host computer 2, set one sub-board 3 as the teacher sub-board and the other multiple sub-boards 3 as student sub-boards. The host computer 2 sends the setting parameters of the teacher sub-board to the main board 1. Step 2: The teacher sub-board or a student sub-board transmits the audio output of the electric piano 10 to the main board 1, and the main board 1 sends the real-time audio data to other sub-boards 3; Step 3: The main board 1 monitors the connection status of the teacher sub-board and multiple student sub-boards. The main board 1 receives the hand-raise button and the cancel hand-raise button from the sub-board 3 and sends them to the host computer 2 one by one.

[0033] Preferably, the host computer 2 sends downlink frames to the motherboard 1, and the motherboard 1 sends uplink frames to the host computer 2. If the data to be transmitted needs to be divided into multiple bytes, the little-endian mode is used by default, that is, the low-order data is sent first, and then the high-order data is sent. After receiving the downlink frame, the motherboard 1 sends a return frame to the host computer 2. The downlink frame includes: a reset frame, used to complete a device reset; Device firmware readback frames are used to confirm whether the firmware information is correct; Broadcast control frames are used to enable or disable the broadcast function of any daughterboard 3; The monitoring control frame is used for real-time uploading and monitoring of any one or more daughterboard audio channels. Sub-board 3 grouping control frame, used to group multiple student sub-boards; In this embodiment, up to 40 groups can be supported, and the number of sub-boards 3 contained in each group is unlimited. The working mode setting frame for subboard 3 is used to reset subboard 3, enable / mute the microphone, control the volume, and detect whether subboard 3 receives data from motherboard 1. The teacher subboard designated frame is used to transmit the setting parameters of the teacher subboard to the mainboard 1.

[0034] Preferably, the uplink frame includes: When the hand-raising button 15 or the cancel hand-raising button 15 of any sub-board 3 is pressed, the main board 1 records the corresponding "hand-raising state" and sends it to the host computer 2 one by one. The motherboard 1 monitors the connection status of each sub-board 3 in real time. When the connection status of any sub-board 3 changes (connecting or unplugging the network cable), the motherboard 1 uploads the connection status of the sub-board 3 to the host computer 2. The host computer 2 can grasp the connection information of 80 sub-boards 3 through the sub-board 3 connection status indication frame.

[0035] In this embodiment, the mainboard 1 and each daughterboard 3 communicate bidirectionally via an RS422 transceiver chip 12 (full-duplex 422 differential bus), using the UART protocol with 1 start bit, 8 data bits, no parity bit, and 1 stop bit, at a baud rate of 5 Mbps. Both ends utilize 9-bit oversampling for UART data reception, corresponding to a working frequency of 45 MHz. When the receiving end detects a certain number of consecutive high levels, it considers itself to be in a frame idle state, automatically resetting the on-chip receive buffer address to avoid subsequent frame processing anomalies caused by reception misalignment.

[0036] Preferably, the motherboard 1 sends a lower communication frame to the daughterboard 3, and the daughterboard 3 sends an upper communication frame to the motherboard 1. The lower communication frame includes: The audio pass-through frame on the daughterboard 3 is used by the motherboard 1 to send real-time audio data to the daughterboard 3. Subboard 3 MIDI configuration frame, used to configure the MIDI interface of electric piano 10; The sub-board 3 status control frame is used to control the call cancellation, volume, and MIC gain functions of a single sub-board 3. The upper communication frame includes: Subboard 3 MIDI upload frame, used to upload the MIDI information of the current electric piano 10 in real time; After each sub-board 3 is powered on and configured, it automatically uploads its MIC and audio input combined data at a sampling rate of 43.945K, 16-bit dual-channel mode, and hand-raising information to the main board 1 periodically. The main board 1 then receives and processes the data.

[0037] Based on the communication method, the host computer 2 is equipped with control software in actual use. It can perform device reset, detect the online status of student subboards, and configure and manage data for any subboard 3, such as microphone on / off, volume control. It can also support teachers to broadcast to student subboards, monitor audio, and record audio, enabling teachers to accurately manage the teaching of any student.

[0038] In addition, the software supports flexible student grouping, meaning that any N students can form a group. The group supports audio synthesis, and teachers can join the discussion at any time. The same student can even join multiple groups, which greatly facilitates various group teaching and exercises.

[0039] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, all equivalent changes or modifications made to the structure, features and principles described in the claims of the present invention should be included within the scope of the present invention.

Claims

1. An FPGA-based electric piano teaching management system, characterized in that, It includes a motherboard (1), a host computer (2), multiple daughter boards (3), and a communication unit; The motherboard (1) includes a first FPGA module (4), and the daughterboard (3) includes a second FPGA module (5). Both the first FPGA module (4) and the second FPGA module (5) are equipped with crystal oscillator modules (7). The first FPGA module (4) is also connected to a power supply module (8). The second FPGA module (5) is also connected to an audio encoder / decoder (9), and the second FPGA module (5) is connected to an electric piano (10) through the audio encoder / decoder (9). The communication unit includes an RJ45 module (11), an RS422 transceiver chip (12), and a USB module (13). The first FPGA module (4) communicates with the second FPGA module (5) through the RS422 transceiver chip (12) and the RJ45 interface. The first FPGA module (4) communicates with the host computer (2) through the USB module (13).

2. The FPGA-based electric piano teaching management system according to claim 1, characterized in that, The sub-board (3) is provided with an RJ45 interface, which is connected to the second FPGA module (5). Two of the RJ45 interfaces are used for RS422 data transmission, two for RS422 data reception, two for the sub-board (3) power supply line, and two for the sub-board (3) grounding line. The subboard (3) is also provided with an audio input interface, which is connected to an audio encoder / decoder (9) and also connected to an electric piano (10); The sub-board (3) is also provided with an audio output interface, which is connected to an audio codec (9) and is also connected to a headset (14). The sub-board (3) is also provided with a microphone input interface, which is connected to the audio codec (9) and is also connected to a headset (14).

3. The FPGA-based electric piano teaching management system according to claim 1, characterized in that, The second FPGA module (5) is connected to the audio encoder / decoder (9) via an I2S interface; The second FPGA module (5) is connected to multiple buttons (15). The second FPGA module (5) is electrically connected to the multiple buttons (15) respectively. Multiple indicator lights (16) are provided for the multiple buttons (15). The multiple indicator lights (16) are electrically connected to the FPGA module respectively. The button (15) includes a volume + button, a volume - button, a microphone on button, a microphone mute button, a hand raise button, and a hand cancel button.

4. The FPGA-based electric piano teaching management system according to claim 1, characterized in that, The first FPGA module (4) includes a PLL module (401) and a global reset module (402). The PLL module (401) is connected to the crystal oscillator module (7), multiplies the clock signal output by the crystal oscillator module (7), and outputs the working clock. The global reset module (402) receives an externally input asynchronous reset signal to achieve synchronous reset and synchronous release. The USB module (13) contains a transmit FIFO and a receive FIFO; The first FPGA module (4) is connected to the RS422 transceiver chip (12) via a UART serial port.

5. A communication method for an FPGA-based electric piano teaching management system according to any one of claims 1 to 4 includes: Step 1: On the host computer (2), set one sub-board (3) as the teacher sub-board and the other multiple sub-boards (3) as student sub-boards. The host computer (2) sends the setting parameters of the teacher sub-board to the main board (1). Step 2: The teacher subboard or a student subboard transmits the audio output of the electric piano (10) to the mainboard (1), and the mainboard (1) sends the real-time audio data to other subboards (3). Step 3: The main board (1) monitors the connection status of the teacher sub-board and multiple student sub-boards. The main board (1) receives the hand-raising button and the cancel hand-raising button from the sub-board (3) and sends them to the host computer (2) one by one.

6. The communication method of the FPGA-based electric piano teaching management system according to claim 5, characterized in that, The host computer (2) sends downlink frames to the motherboard (1), and the motherboard (1) sends uplink frames to the host computer (2). If the data to be transmitted needs to be divided into multiple bytes, the little-endian mode is used by default, that is, the low-order data is sent first, and then the high-order data is sent. After receiving the downlink frame, the motherboard (1) sends a return frame to the host computer (2). The downlink frame includes: a reset frame, used to complete a device reset; Device firmware readback frames are used to confirm whether the firmware information is correct; Broadcast control frames are used to turn the broadcast function of any subboard (3) on or off; The monitoring control frame is used for real-time audio upload monitoring of any one or more sub-boards (3); Sub-board (3) grouping control frame, used to group multiple student sub-boards; The working mode setting frame of the sub-board (3) is used to reset the sub-board (3), turn on / mute the microphone, control the volume, and detect whether the sub-board (3) receives data from the motherboard (1); The teacher subboard designated frame is used to transmit the setting parameters of the teacher subboard to the mainboard (1).

7. The communication method of an FPGA-based electric piano teaching management system according to claim 6, characterized in that, The uplink frame includes: When the hand-raising button (15) or the cancel hand-raising button (15) of any sub-board (3) is pressed, the main board (1) records the corresponding "hand-raising state" and sends it to the host computer (2) one by one. The motherboard (1) monitors the connection status of each sub-board (3) in real time. When the connection status of any sub-board (3) changes, the motherboard (1) uploads the connection status of the sub-board (3) to the host computer (2).

8. The communication method of an FPGA-based electric piano teaching management system according to claim 5, characterized in that, The motherboard (1) sends a lower communication frame to the daughterboard (3), and the daughterboard (3) sends an upper communication frame to the motherboard (1). The lower communication frame includes: The sub-board (3) audio pass-through frame is used by the motherboard (1) to send real-time audio data to the sub-board (3). Subboard (3) MIDI configuration frame, used to configure the MIDI interface of the electric piano (10); The sub-board (3) status control frame is used to control the call cancellation, volume, and MIC gain functions of a single sub-board (3); The upper communication frame includes: Subboard (3) MIDI upload frame, used to upload the MIDI information of the current electric piano (10) in real time; After each sub-board (3) is powered on and configured, it automatically uploads its MIC and audio input combined data at a sampling rate of 43.945K, 16-bit dual-channel mode, and hand-raising information to the main board (1) periodically. The main board (1) then receives and processes the data.

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