Semiconductor element

Abstract

A semiconductor device includes a substrate structure, a source structure, a drain structure and a gate structure. The source structure, the drain structure and the gate structure are located above the substrate structure and are arranged along a first direction. The drain electrode structure comprises a plurality of first electrode units and a plurality of second electrode units which are alternately arranged in the second direction. The second direction is substantially perpendicular to the first direction. Each first electrode unit comprises a p-type semiconductor layer and a first metal electrode. The p-type semiconductor layer has a first base area. Each second electrode unit comprises a second metal electrode. The second metal electrode has a second base area. The second base area is larger than the first base area. Energy consumption can be reduced, and damage caused by voltage overshoot can be suppressed.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] III-V semiconductor compounds are widely used in integrated circuit devices due to their semiconductor properties, such as high power field effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). In high electron mobility transistors, gallium nitride-based materials have received particular attention in recent years due to their wide bandgap, high saturation velocity, and suitability for high frequency and high power density operation. However, in order to cope with the increasing integration density, it is necessary to further reduce the energy consumption and on-state resistance of high electron mobility transistors. SUMMARY

[0003] Therefore, an object of the present application is to provide a semiconductor device that can solve the above problems.

[0004] One aspect of the present application relates to a semiconductor device including a substrate structure, a source structure, a gate structure, and a drain structure. The substrate structure includes a semiconductor layer. The source structure is located above the semiconductor layer of the substrate structure. The gate structure is located above the semiconductor layer. The drain structure is located above the semiconductor layer and arranged along a first direction with the source structure and the gate structure. The drain structure includes a plurality of first electrode units and a plurality of second electrode units. Each first electrode unit includes a p-type semiconductor layer and a first metal electrode located above the p-type semiconductor layer. The p-type semiconductor layer has a first bottom area. Each second electrode unit includes a second metal electrode. The second metal electrode has a second bottom area. The second bottom area is greater than the first bottom area. The first electrode units and the second electrode units are alternately arranged along a second direction. The second direction is substantially perpendicular to the first direction.

[0005] In summary, in the semiconductor device of some embodiments of the present application, first electrode units and second electrode units are arranged alternately and separated from each other, wherein the first electrode units include metal electrodes and p-type semiconductor layers forming Schottky barrier diodes, and the second electrode units include metal electrodes forming ohmic contacts with underlying semiconductor layers. At the same time, the bottom area of the metal electrode of each second electrode unit is greater than the bottom area of the p-type semiconductor layer of each first electrode unit. In this way, in the on-state, the metal electrodes of the first electrode units and the metal electrodes of the second electrode units have different potentials, which can further reduce energy consumption through the contact area relationship between the first electrode units, the second electrode units, and the semiconductor layer, and inhibit damage caused by voltage overshoot. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings illustrate one or more embodiments of the application and together with the written description, serve to explain the principles of the application. In all the drawings, similar reference characters signify similar or identical elements throughout the several views, in which:

[0007] Figure 1 is a top view of a semiconductor element according to some embodiments of the application.

[0008] Figure 2 , Figure 3 and Figure 4 are partial cross-sectional views of the semiconductor element 10 taken along line segments A-A', B-B' and C-C' respectively.

[0009] Figure 5 is an equivalent circuit schematic of the semiconductor element 10.

[0010] Figure 6 is a top view of a semiconductor element according to some other embodiments of the application.

[0011] Figure 7 is a top view of a semiconductor element according to yet other embodiments of the application. DETAILED DESCRIPTION

[0012] Reference will now be made to Figures 1 to 5 . Figure 1 is a top view of a semiconductor element 10 according to some embodiments of the application. Figure 2 , Figure 3 and Figure 4 are partial cross-sectional views of the semiconductor element 10 taken along line segments A-A', B-B' and C-C' respectively. Figure 1 Figure 5 is an equivalent circuit schematic of the semiconductor element 10.

[0013] As shown in Figure 1 , the semiconductor element 10 includes a substrate structure 100, a source structure 110, a drain structure 120 and a gate structure 130. The source structure 110, the drain structure 120 and the gate structure 130 are located above the semiconductor layer 108 of the substrate structure 100 and are arranged along a first direction D1. The gate structure 130 is located between the source structure 110 and the drain structure 120. The source structure 110 and the gate structure 130 extend along a second direction D2 respectively. As shown in Figure 1 , the first direction D1 is substantially perpendicular to the gate width direction, and the second direction D2 is substantially parallel to the gate width direction.

[0014] In some embodiments, the substrate structure 100 includes a semiconductor stack. For example, as shown in Figure 2 , the semiconductor stack includes a first semiconductor layer 102, a second semiconductor layer 104 and a third semiconductor layer 106. The first semiconductor layer 102 is located between the second semiconductor layer 104 and the third semiconductor layer 106. The first semiconductor layer 102 is a semiconductor layer of a first conductivity type. The second semiconductor layer 104 is a semiconductor layer of a second conductivity type. The third semiconductor layer 106 is a semiconductor layer of the first conductivity type. The first semiconductor layer 102 is located between the second semiconductor layer 104 and the third semiconductor layer 106.​Figure 3 as well as Figure 4 As shown, the substrate structure 100 includes a substrate 102, a buffer layer 104, a semiconductor layer 106, and a semiconductor layer 108. The buffer layer 104 is located above the substrate 102. The semiconductor layer 106 is located above the buffer layer 104. The semiconductor layer 108 is located above the semiconductor layer 106. In some embodiments, semiconductor layers 106 and 108 comprise group III-V semiconductor compounds. For example, semiconductor layer 106 may comprise gallium nitride (GaN), and semiconductor layer 108 may comprise aluminum gallium nitride (AlGaN). In this way, semiconductor layers 106 and 108 form a heterostructure with a high two-dimensional electron gas (2DEG) channel at their interface, resulting in semiconductor device 10 having lower energy consumption and higher power density compared to silicon-based semiconductor devices.

[0015] In some embodiments, the source structure 110 includes a source electrode 111, a source via 112, and a source metal interconnect 113. For example... Figure 1 As shown, the source electrode 111 is an elongated strip of material extending along the second direction D2. The source structure 110 may include a plurality of source vias 112 arranged along the second direction D2. Figure 2 and Figure 3 As shown, the source metal interconnect 113 is located above the source electrode 111 and is electrically connected to the source electrode 111 through the source via 112. In some embodiments, the materials of the source electrode 111 and the source metal interconnect 113 may include, but are not limited to, titanium, titanium nitride, aluminum, copper, or combinations thereof.

[0016] In some embodiments, the drain structure 120 includes a first electrode unit 121, a second electrode unit 122, and a drain metal interconnect 123. For example... Figure 1 and Figure 4 As shown, the first electrode unit 121 and the second electrode unit 122 are arranged alternately and at intervals along the second direction D2. When there is a gap G between adjacent first electrode units 121 and second electrode units 122, adjacent first electrode units 121 are separated from each other, and adjacent second electrode units 122 are separated from each other, forming an island-like structure. The central axis of each first electrode unit 121 coincides with the central axis of each second electrode unit 122 (e.g., coincides with line segment C-C') and is parallel to the second direction D2. Detailed features of the first electrode units 121 and second electrode units 122 will be described in subsequent paragraphs.

[0017] In some embodiments, the gate structure 130 includes a gate semiconductor 131 and a gate metal electrode 132. As shown in FIG. 1B, the gate semiconductor 131 and the gate metal electrode 132 are long strip-shaped materials extending along the second direction D2. As shown in FIG. 1B, the gate semiconductor 131 is located above the semiconductor layer 108. In some embodiments, the gate semiconductor 131 includes, but is not limited to, gallium nitride or p-type doped gallium nitride. As shown in FIG. 1B, the gate metal electrode 132 is located above the gate semiconductor 131. In some embodiments, the gate metal electrode 132 includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. Figure 1 Figure 2 As shown in FIG. 1B, the gate metal electrode 132 is located above the gate semiconductor 131. In some embodiments, the gate semiconductor 131 includes, but is not limited to, gallium nitride or p-type doped gallium nitride, while the gate metal electrode 132 includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. Figure 3 As shown in FIG. 1B, the first electrode unit 121 includes a p-type semiconductor layer 121a, a metal electrode 121b located above the p-type semiconductor layer 121a, and a first drain via 121c located above the metal electrode 121b. In some embodiments, the p-type semiconductor layer 121a is made of gallium nitride with p-type dopants. In some embodiments, the metal electrode 121b includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 121b contacts a top surface of the p-type semiconductor layer 121a, forming a Schottky barrier diode (SBD). A bottom surface of the p-type semiconductor layer 121a contacts the semiconductor layer 108. The metal electrode 121b and the p-type semiconductor layer 121a are electrically connected to the drain metal line 123 through the first drain via 121c.

[0018] Figure 2 As shown in FIG. 1B, the second electrode unit 122 includes a metal electrode 122a and a second drain via 122b located above the metal electrode 122a. The metal electrode 122a contacts the semiconductor layer 108, forming an ohmic contact. In some embodiments, the metal electrode 122a includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 122a is electrically connected to the drain metal line 123 through the second drain via 122b. Figure 4 As shown in FIG. 1B, the second electrode unit 122 includes a metal electrode 122a and a second drain via 122b located above the metal electrode 122a. The metal electrode 122a contacts the semiconductor layer 108, forming an ohmic contact. In some embodiments, the metal electrode 122a includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 122a is electrically connected to the drain metal line 123 through the second drain via 122b.

[0019] Figure 3 As shown in FIG. 1B, the second electrode unit 122 includes a metal electrode 122a and a second drain via 122b located above the metal electrode 122a. The metal electrode 122a contacts the semiconductor layer 108, forming an ohmic contact. In some embodiments, the metal electrode 122a includes, but is not limited to, titanium, titanium nitride, aluminum, copper, or a combination thereof. The metal electrode 122a is electrically connected to the drain metal line 123 through the second drain via 122b. Figure 4 Figure 4 ​​​​As shown in FIG. 1C, in a cross-section along line segment C-C', the metal electrode 122a of the second electrode unit 122 has a lower portion directly contacting the semiconductor layer 108 and an upper portion above the lower portion and contacting the second drain via 122b. There is a gap G between the edge of the upper portion of the metal electrode 122a and the edge of the p-type semiconductor layer 121a. In other words, the orthographic projection area of the metal electrode 122a of the second electrode unit 122 on the substrate structure 100 is separate from and does not overlap with the orthographic projection area of the p-type semiconductor layer 121a of the first electrode unit 121 on the substrate structure 100.

[0020] As shown in FIG. 1C, in a cross-section along line segment C-C', the metal electrode 122a of the second electrode unit 122 has a lower portion directly contacting the semiconductor layer 108 and an upper portion above the lower portion and contacting the second drain via 122b. There is a gap G between the edge of the upper portion of the metal electrode 122a and the edge of the p-type semiconductor layer 121a. In other words, the orthographic projection area of the metal electrode 122a of the second electrode unit 122 on the substrate structure 100 is separate from and does not overlap with the orthographic projection area of the p-type semiconductor layer 121a of the first electrode unit 121 on the substrate structure 100. Figure 4 As shown in FIG. 1C, in a cross-section along line segment C-C', the metal electrode 122a of the second electrode unit 122 has a lower portion directly contacting the semiconductor layer 108 and an upper portion above the lower portion and contacting the second drain via 122b. There is a gap G between the edge of the upper portion of the metal electrode 122a and the edge of the p-type semiconductor layer 121a. In other words, the orthographic projection area of the metal electrode 122a of the second electrode unit 122 on the substrate structure 100 is separate from and does not overlap with the orthographic projection area of the p-type semiconductor layer 121a of the first electrode unit 121 on the substrate structure 100.

[0021] Figure 1 As shown in FIG. 1C, in a cross-section along line segment C-C', the metal electrode 122a of the second electrode unit 122 has a lower portion directly contacting the semiconductor layer 108 and an upper portion above the lower portion and contacting the second drain via 122b. There is a gap G between the edge of the upper portion of the metal electrode 122a and the edge of the p-type semiconductor layer 121a. In other words, the orthographic projection area of the metal electrode 122a of the second electrode unit 122 on the substrate structure 100 is separate from and does not overlap with the orthographic projection area of the p-type semiconductor layer 121a of the first electrode unit 121 on the substrate structure 100.

[0022] As shown in FIG. 1C, in a cross-section along line segment C-C', the metal electrode 122a of the second electrode unit 122 has a lower portion directly contacting the semiconductor layer 108 and an upper portion above the lower portion and contacting the second drain via 122b. There is a gap G between the edge of the upper portion of the metal electrode 122a and the edge of the p-type semiconductor layer 121a. In other words, the orthographic projection area of the metal electrode 122a of the second electrode unit 122 on the substrate structure 100 is separate from and does not overlap with the orthographic projection area of the p-type semiconductor layer 121a of the first electrode unit 121 on the substrate structure 100. Figure 1 ​As shown, the first drain via 121c and the second drain via 122b are arranged at intervals along the second direction D2. In some embodiments, the sum of the bottom areas of the second drain vias 122b of each second electrode unit 122 (or the sum of the contact areas between the second drain vias 122b of each second electrode unit 122 and the metal electrode 122a) is greater than the sum of the bottom areas of the first drain vias 121c of each first electrode unit 121 (or the sum of the contact areas between the first drain vias 121c of each first electrode unit 121 and the metal electrode 121b). Therefore, the total resistance of the second drain vias 122b of each second electrode unit 122 is less than the total resistance of the first drain vias 121c of each first electrode unit 121.

[0023] In this configuration, since the first electrode unit 121 and the second electrode unit 122 are separated from each other and electrically connected to the drain metal connection 123 via the first drain via 121c and the second drain via 122b respectively, the metal electrode 121b of the first electrode unit 121 and the metal electrode 122a of the second electrode unit 122 can have different potentials in the on-state. Specifically, please refer to... Figure 5 Current can flow through two paths from the drain metal connection 123 (which has a potential value V). 123 ) flows into the two-dimensional electron gas channel (with a potential value V) 2DEG The path on the left passes through the first drain via 121c and the Schottky barrier diode SD formed by the metal electrode 121b and the p-type semiconductor layer 121a. The path on the right passes through the second drain via 122b and the metal electrode 122a. Therefore, the potential value V of the metal electrode 121b is... 121b Potential value V with metal electrode 122a 122a They can be different.

[0024] As mentioned above, the sum of the bottom areas of the second drain vias 122b in each second electrode unit 122 is greater than the sum of the bottom areas of the first drain vias 121c in each first electrode unit 121, such that the second drain via 122b has a resistance value R. 122b The resistance value R is smaller than that of the first drain via 121c. 121c In this way, the current value I1 flowing through the left path is less than the current value I2 flowing through the right path, thus reducing the energy consumption of the first electrode unit 121. In addition, setting the first drain via 121c as a protective resistor can suppress voltage overshoot caused by abnormal disturbances in the drain metal connection 123, and prevent damage to the Schottky barrier diode SD.

[0025] Similarly, such as Figure 4As shown, in some embodiments, the cross-sectional area of ​​the first drain via 121c is smaller than the cross-sectional area of ​​the second drain via 122b. In some embodiments, the bottom end of the first drain via 121c is lower than the bottom end of the second drain via 122b, and the top surface of the metal electrode 121b is lower than the top surface of the metal electrode 122a. In other words, the height of the first drain via 121c can be greater than the height of the second drain via 122b, further increasing the resistance value R. 122b Less than the resistance value R 121c Furthermore, the thickness of the p-type semiconductor layer 121a is less than the thickness of the second metal electrode 122a.

[0026] In addition, such as Figure 1 As shown, in some embodiments, the edge of the p-type semiconductor layer 121a of the first electrode unit 121 is aligned with the edge of the second metal electrode 122a of the second electrode unit 122. This maximizes the gate-drain length (L). gd , equivalent to Figure 1 The spacing X1 and X2 in the first electrode unit 121 is used to reduce electric field spikes, provide a larger breakdown voltage, and improve the reliability of the device. In this case, the spacing X1 between the p-type semiconductor layer 121a of the first electrode unit 121 and the gate semiconductor 131 of the gate structure 130 along the first direction D1 is substantially equal to the spacing X2 between the second metal electrode 122a of the second electrode unit 122 and the gate semiconductor 131 along the first direction D1. It is worth noting that the spacings X1 and X2 are greater than the spacing X3 between the source structure 110 and the gate structure 130.

[0027] Next, we will match... Figure 1 and Figure 4A method for manufacturing a semiconductor element 10 according to some embodiments of the present invention will be described. First, a substrate structure 100 is provided. For example, a buffer layer 104, a semiconductor layer 106, and a semiconductor layer 108 are sequentially formed on a substrate 102. Next, a plurality of p-type semiconductor layers 121a, which are separated from each other and arranged along a second direction D2, are formed. In some embodiments, the gate semiconductor 131 of the gate structure 130 may be formed simultaneously at this stage. Next, a first metal electrode 121b is formed above each p-type semiconductor layer 121a. In some embodiments, the gate metal electrode 132 of the gate structure 130 may be formed simultaneously at this stage. Next, a second metal electrode 122a is formed between the p-type semiconductor layers 121a, such that the p-type semiconductor layers 121a and the second metal electrode 122a are arranged alternately and at intervals along the second direction D2. In some embodiments, the source electrode 111 of the source structure 110 may be formed simultaneously at this stage. Next, a first drain via 121c and a second drain via 122b are formed above the first metal electrode 121b and the second metal electrode 122a, respectively, such that the sum of the bottom areas of the second drain vias 122b in each second electrode unit 122 is greater than the sum of the bottom areas of the first drain vias 121c in each first electrode unit 121. In some embodiments, a source via 112 can be formed simultaneously above the source electrode 111 at this stage. Next, a drain metal interconnect 123 is formed above the first drain via 121c and the second drain via 122b. In some embodiments, a source metal interconnect 113 can be formed simultaneously above the source via 112 at this stage.

[0028] Please refer to Figure 6 This is a top view of a semiconductor element 10' according to other embodiments of the present invention. One difference between semiconductor element 10' and semiconductor element 10 is that the width W1 of the p-type semiconductor layer 121a of each first electrode unit 121 along the first direction D1 is different from the width W2 of the metal electrode 122a of each second electrode unit 122 along the first direction D1. For example, the width W1 is greater than the width W2. In some embodiments, the length L1 of the p-type semiconductor layer 121a of each first electrode unit 121 along the second direction D2 is less than the length L2 of the metal electrode 122a of each second electrode unit 122 along the second direction D2, such that the top view area of ​​each first electrode unit 121 is smaller than the top view area of ​​each second electrode unit 122, thereby increasing the area ratio occupied by the second electrode unit 122 and relatively reducing the on-resistance.

[0029] Furthermore, another difference between semiconductor element 10' and semiconductor element 10 is that each second electrode unit 122 of semiconductor element 10' may have three separate second drain vias 122b arranged along the second direction D2 above the second metal electrode 122a. The size of each second drain via 122b is approximately the same as that of the first drain via 121c. In these embodiments, the sum of the bottom areas of all the second drain vias 122b above each second electrode unit 122 is still greater than the sum of the bottom areas of all the first drain vias 121c above each first electrode unit 121, so that the total resistance of the second drain vias 122b of each second electrode unit 122 is less than the total resistance of the first drain vias 121c of each first electrode unit 121. In other embodiments, more than one first drain via 121c may also be present above the first metal electrode 121b.

[0030] In some embodiments, the first drain via 121c and the second drain via 122b can have arbitrary shapes. For example, please refer to... Figure 7 This is a top view of a semiconductor element 10” according to some other embodiments of the present invention. The difference between semiconductor element 10” and semiconductor element 10 is that the first drain via 121c and the second drain via 122b of semiconductor element 10” have circular top view profiles. At the same time, in these embodiments, four second drain vias 122b are distributed above the second metal electrode 122a of each second electrode unit 122. Similarly, the sum of the bottom areas of all the second drain vias 122b above each second electrode unit 122 is greater than the sum of the bottom areas of all the first drain vias 121c above each first electrode unit 121, so that the total resistance value of the second drain vias 122b of each second electrode unit 122 is less than the total resistance value of the first drain vias 121c of each first electrode unit 121.

[0031] In summary, in some embodiments of the semiconductor device of the present invention, a first electrode unit and a second electrode unit are provided that are separated from each other and arranged alternately. The first electrode unit includes a metal electrode forming a Schottky barrier diode and a p-type semiconductor layer, and the second electrode unit includes a metal electrode forming an ohmic contact with the underlying semiconductor layer. Simultaneously, the bottom area of ​​the metal electrode of each second electrode unit is larger than the bottom area of ​​the p-type semiconductor layer of each first electrode unit. In this way, in the on-state, the metal electrodes of the first electrode unit and the second electrode unit have different potentials, which can further reduce energy consumption and suppress damage caused by voltage overshoot through the contact area relationship between the first electrode unit, the second electrode unit, and the semiconductor layer.

[0032] [Symbol Explanation]

[0033] 10,10',10”: Semiconductor element

[0034] 100: Substrate Structure

[0035] 102: Substrate

[0036] 104: Buffer layer

[0037] 106, 108: Semiconductor layer

[0038] 110: Source structure

[0039] 111: Source electrode

[0040] 112: Source perforation

[0041] 113: Source Metal Connection

[0042] 120: Drain structure

[0043] 121: First electrode unit

[0044] 121a: p-type semiconductor layer

[0045] 121b, 122a: Metal electrodes

[0046] 121c: First drain via

[0047] 122: Second electrode unit

[0048] 122b: Second drain via

[0049] 123: Drain metal connection

[0050] 130: Gate structure

[0051] 131: Gate Semiconductor

[0052] 132: Gate metal electrode

[0053] A-A', B-B', C-C': line segments

[0054] D1: First Direction

[0055] D2: Second Direction

[0056] G: Interval

[0057] I1, I2: Current values

[0058] L1, L2: Length

[0059] R 121c ,R 122b Resistance value

[0060] SD: Schottky barrier diode

[0061] V 121b V 122a V 123 V 2DEG Potential value

[0062] W1, W2: Width

[0063] X1, X2, X3: Spacing.

Claims

1. A semiconductor element, characterized in that, Include: Substrate structure, including a semiconductor layer; A source structure is located above the semiconductor layer of the substrate structure; A gate structure is located above the semiconductor layer; as well as A drain structure, located above the semiconductor layer and arranged along a first direction with the source structure and the gate structure, the drain structure comprising: Multiple first electrode units, each comprising a p-type semiconductor layer and a first metal electrode located above the p-type semiconductor layer, wherein the p-type semiconductor layer has a first bottom area; and Multiple second electrode units, each comprising a second metal electrode, wherein the second metal electrode has a second bottom area, and the second bottom area is larger than the first bottom area. The plurality of first electrode units and the plurality of second electrode units are arranged alternately along a second direction, which is substantially perpendicular to the first direction.

2. The semiconductor device according to claim 1, characterized in that, The p-type semiconductor layer of each of the plurality of first electrode units is separated from the second metal electrode of each of the plurality of second electrode units.

3. The semiconductor device according to claim 1, characterized in that, Viewed from above, the area of ​​each of the plurality of first electrode units is smaller than the area of ​​each of the plurality of second electrode units.

4. The semiconductor device according to claim 1, characterized in that, The width of the p-type semiconductor layer along the first direction is substantially equal to the width of the second metal electrode along the first direction.

5. The semiconductor device according to claim 1, characterized in that, The width of the p-type semiconductor layer along the first direction is different from the width of the second metal electrode along the first direction.

6. The semiconductor element according to claim 1, characterized in that, The length of the p-type semiconductor layer along the second direction is less than the length of the second metal electrode along the second direction.

7. The semiconductor element according to claim 1, characterized in that, The thickness of the p-type semiconductor layer is less than the thickness of the second metal electrode.

8. The semiconductor element according to claim 1, characterized in that, The drain structure further includes a drain metal interconnect, and the plurality of first electrode units further include at least one first drain via located above the first metal electrode and electrically connected to the drain metal interconnect, and the plurality of second electrode units further include at least one second drain via located above the second metal electrode and electrically connected to the drain metal interconnect.

9. The semiconductor element according to claim 8, characterized in that, The bottom end of the at least one first drain via is lower than the bottom end of the at least one second drain via.

10. The semiconductor element according to claim 8, characterized in that, The at least one first drain via and the at least one second drain via are arranged at intervals along the second direction.

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