Semiconductor device, power module, and electronic device

Abstract

This invention discloses a semiconductor device, a power module, and an electronic device, relating to the field of semiconductor technology. The semiconductor device includes a first gate material, a gate, and a dummy gate. The first gate material is connected to a first contact hole. A gate portion is formed on the first gate material and electrically connected to a metal electrode through the first contact hole. A dummy gate is formed between the first gate material and the gate and connected to a second contact hole, electrically connected to a metal electrode through the second contact hole. The dummy gate is disposed at a distance from the first gate material and the gate. The semiconductor device provided by this invention has a second contact hole directly etched on the dummy gate, eliminating the connection method through the gate material and the second contact hole. This avoids the size of the semiconductor device being affected by the minimum dimension between the gate material of the dummy gate and the first gate material, thus facilitating miniaturization design.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, power module, and electronic device. Background Technology

[0002] In the design of high-power-density semiconductor devices, it is usually necessary to set up a normal gate and a dummy gate. The traditional dummy gate connection method is to make a cover contact between the dummy gate and the polysilicon, and the polysilicon is connected to the metal electrode through a contact hole, thereby realizing the electrical connection of the dummy gate.

[0003] However, since the normal gate also needs to be in contact with the polysilicon, there is a minimum design size between the polysilicon in contact with the virtual gate and the normal gate. This means that the normal gate and the virtual gate cannot be too close together. Therefore, the above-mentioned virtual gate connection method increases the size of the semiconductor device and is not conducive to the miniaturization design of the semiconductor device. Summary of the Invention

[0004] The main objective of this invention is to provide a semiconductor device, power module, and electronic device that aims to achieve miniaturized design of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device, the semiconductor device comprising: A first gate material, wherein the first gate material is connected to a first contact hole; A gate, wherein the gate portion is formed in the first gate material, and the gate is electrically connected to a metal electrode through the first contact hole; A virtual gate is formed between the first gate material and the gate, and the virtual gate is connected to a second contact hole. The virtual gate is electrically connected to a metal electrode through the second contact hole. The virtual gate is spaced between the first gate material and the gate arrangement.

[0006] In one embodiment, the first gate material has a first portion and a second portion, the first portion and the second portion of the first gate material are spaced apart along a first direction, the first portion and the second portion are spaced apart to form a gate forming region, the gate and the dummy gate are disposed in the gate forming region along the first direction, and the gate and the dummy gate are spaced apart and staggered along a second direction.

[0007] In one embodiment, the number of gates is multiple, and among the multiple gates, adjacent gates form a group of gate components; At least one virtual gate is provided between every two groups of the gate components.

[0008] In one embodiment, the number of virtual gates is multiple, and the adjacent virtual gates form a group of virtual gate components; Each of the virtual gate components is connected to at least one of the second contact holes.

[0009] In one embodiment, the two ends of the virtual gate assembly are respectively connected to the two second contact holes.

[0010] In one embodiment, the virtual gate is connected to at least one second contact hole, and the second contact hole is disposed along the length direction of the virtual gate.

[0011] In one embodiment, the shape of the second contact hole is adapted to the shape of the virtual gate; And / or, the size of the second contact hole is adapted to the size of the virtual gate.

[0012] In one embodiment, at least two second contact holes are connected to the virtual gate, and the two ends of the virtual gate are respectively connected to the two second contact holes.

[0013] In one embodiment, the number of virtual gates is multiple, and the number of second contact holes corresponds to the number of virtual gates.

[0014] In one embodiment, the first portion and the second portion of the first gate material are both square, the gate forming region is square, and the gate and the dummy gate are arranged in parallel.

[0015] In one embodiment, the first gate material is polycrystalline silicon.

[0016] The present invention also provides a power module comprising at least one semiconductor device as described in any of the preceding claims.

[0017] The present invention also provides an electronic device, the electronic device comprising: Semiconductor devices as described in any of the above; and / or, The power module as described above.

[0018] In summary, the semiconductor device proposed in this invention enables miniaturized design of semiconductor devices. The semiconductor device includes a first gate material and a gate electrode. The first gate material is connected to a first contact hole, and the gate electrode, after being connected to the first gate material, is connected to a metal electrode through the first contact hole. The dummy gate is directly connected to a second contact hole. Compared to the prior art, which connects a gate material to the dummy gate and then achieves electrical connection to the metal electrode through a second contact hole connected to the gate material, this invention directly etches the second contact hole on the corresponding insulating material of the dummy gate. This allows the semiconductor device to be free from the influence of the shortest distance between the two first gate materials, thus reducing the distance between the dummy gate and the gate electrode, which helps to achieve miniaturized design of the semiconductor device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the structure of the first embodiment of the semiconductor device provided by the present invention; Figure 2 A schematic diagram of the structure of a second embodiment of the semiconductor device provided by the present invention; Figure 3 A schematic diagram of the structure of the third embodiment of the semiconductor device provided by the present invention; Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device provided by the present invention.

[0021] Explanation of icon numbers: First gate material 100, first portion 110, second portion 120, gate forming region 130, gate 200, gate assembly 210, dummy gate 300, dummy gate assembly 310, first contact hole 400, second contact hole 500.

[0022] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0025] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0026] In existing semiconductor devices, it is usually necessary to set a normal gate and a virtual gate. Traditional semiconductor devices face challenges such as short-channel effect and increased leakage current. The virtual gate enhances the gate's control over the channel region by introducing additional control mechanisms, such as sidewall gate or back gate, thereby improving switching characteristics and reducing power consumption.

[0027] The traditional virtual gate connection method involves covering the virtual gate with the gate material, and then connecting the gate material to the metal electrode through a contact hole to achieve the electrical connection of the virtual gate.

[0028] However, since the normal gate also needs to be in contact with the polysilicon cover, and the normal gate and the dummy gate need to be connected to different potentials through two independent polysilicon layers, these two polysilicon layers must maintain sufficient spacing to prevent them from short-circuiting during manufacturing. This means that the normal gate and the dummy gate cannot be too close together, increasing the size of the semiconductor device and hindering its miniaturization design.

[0029] Therefore, in order to solve the above problems, such as Figure 1As shown, this invention proposes a semiconductor device including a first gate material 100, a gate 200, and a dummy gate 300. The first gate material 100 has a first contact hole 400 etched on it. The gate 200 is partially formed on the first gate material 100 and electrically connected to a metal electrode through the first contact hole 400. The dummy gate 300 is connected to a second contact hole 500 and is formed between the first gate material 100 and the gate 200, and is electrically connected to a metal electrode through the second contact hole 500. The dummy gate 300 is positioned spaced apart from the first gate material 100 and the gate 200. It is understood that, unlike the prior art, the dummy gate 300 in this semiconductor device may not have a gate material, thus avoiding the negative impact caused by the size requirements between the gate materials of the dummy gate 300 and the gate material of the gate 200 in the prior art, thereby achieving miniaturization.

[0030] In this embodiment, the first gate material 100 can be one of silicon, silicide, nitride, polycrystalline silicon, etc. The first gate material 100, gate 200, and dummy gate 300 are all formed on a substrate, which can be a commonly used substrate such as a silicon substrate, silicon carbide substrate, silicon-germanium substrate, gallium arsenide, etc. The first gate material 100 can be formed by commonly used deposition methods such as chemical vapor deposition and atomic layer deposition, and the corresponding shape is etched by etching after deposition.

[0031] In this embodiment, the first gate material 100 is polycrystalline silicon. Polycrystalline silicon has good conductivity and stability, which can ensure good contact between the gate 200 and the first gate material 100. A first contact hole 400 is etched into the insulating material at a corresponding position on the first gate material 100. Thus, after the gate 200 makes contact with the first gate material 100, it can be electrically connected to the metal electrode through the first contact hole 400.

[0032] In this embodiment, firstly, the gate 200 can be formed directly by etching the first gate material 100, meaning the gate 200 and the first gate material 100 are integrally formed without the need for additional materials or steps, thus simplifying the manufacturing process. Secondly, the gate 200 and the first gate material 100 can also be in a cover contact, meaning that first, another gate material (which can be the same material as the first gate material 100) is etched to form the gate 200, and then the first gate material 100 is re-etched on this gate 200 to form the first gate material 100 of the corresponding shape. Regardless of whether it is the first or the second, the connection between the gate 200 and the first gate material 100 will be used to describe this in the preceding and subsequent descriptions.

[0033] It is understood that the first gate material 100 is connected to a first contact hole 400. Since an insulating material, such as silicon dioxide, needs to be deposited between the first gate material 100 and the metal electrode to isolate the gate 200 and the subsequent metal electrode, contact holes are required in the insulating material to achieve electrical connection between the gate oxide layer and the metal electrode. These include the first contact hole 400 and the second contact hole 500. After the first gate material 100 contacts the first contact hole 400, the gate 200 connects to the first gate material 100, thus achieving electrical connection with the metal electrode through the first contact hole 400. Optionally, a contact hole (not shown in the figure) is also provided at the interval between each corresponding gate 200 and dummy gate 300.

[0034] In this embodiment, the virtual gate 300 can be etched by another gate material (or the same as the first gate material 100). It should be noted that the virtual gate 300 needs to be spaced apart from the gate 200 and from the first gate material 100. The distance between the virtual gate 300, the gate 200, and the gate material should not be too close, because the virtual gate 300 and the gate 200 need to be connected to different potentials and cannot be in direct contact. Therefore, these two parts must be spaced sufficiently, otherwise failure may occur. If the two parts are connected together, it will cause the semiconductor device to fail.

[0035] In this embodiment, the virtual gate 300 is not connected to a gate material. In the prior art, the virtual gate 300 is also connected to a gate material (polysilicon), which is not conducive to the miniaturization design of the device. However, in this embodiment, the virtual gate 300 is not connected to a gate material. Instead, the second contact hole 500 is deposited directly in the insulating material at the location corresponding to the virtual gate 300. In this way, the electrical connection between the virtual gate 300 and the metal electrode can be directly achieved. In addition, in some examples, the second contact hole 500 may be etched only on the insulating material, or it may be etched through the insulating material into the virtual gate 300. However, the contact method and contact area between the second contact hole 500 and the virtual gate 300 are not limited here.

[0036] It should be noted that the effective cells and virtual gate cells in the semiconductor device provided by this invention can be set according to application requirements, and miniaturization can be achieved for different settings. Specifically, the effective cell contains the actual working circuit part, which is responsible for performing the main functions, such as signal amplification and logic operations; while the virtual gate cell contains a virtual gate 300, which is used to help control the electric field distribution in the channel region and improve the short-channel effect and leakage current problem.

[0037] It is understandable that semiconductor devices can refer to MOSFETs or IGBTs. They can be N-type or P-type.

[0038] In summary, the semiconductor device proposed in this invention enables miniaturized design of semiconductor devices. The semiconductor device includes a first gate material 100, a gate 200, and a dummy gate 300. The first gate material 100 is connected to a first contact hole 400. After the gate 200 is connected to the first gate material 100, it is connected to a metal electrode through the first contact hole 400. The dummy gate 300 is directly connected to a second contact hole 500. Compared to the prior art, where a gate material is also connected to the dummy gate 300, and then the electrical connection to the metal electrode is achieved through the second contact hole 500 connected to the gate material, this invention directly etches the second contact hole 500 on the corresponding insulating material of the dummy gate 300. This allows the semiconductor device to be free from the influence of the shortest distance between the two first gate materials 100, thus reducing the distance between the dummy gate 300 and the gate 200, which helps to achieve miniaturized design of the semiconductor device.

[0039] In one implementation, such as Figure 1 As shown, the first gate material 100 has a first portion 110 and a second portion 120, which are spaced apart along a first direction, and form a gate forming region 130. It should be noted that... Figure 1 The diagram shows a partial cross-sectional view of a semiconductor device. The first gate material 100 is shown in the diagram with a first portion 110 and a second portion 120. While the first portion 110 and the second portion 120 are clearly marked, they can be integrally formed or independently formed. Regardless of whether they are integrally formed or independently formed, the key point is that a certain spacing is formed between the first portion 110 and the second portion 120. This spacing constitutes the gate formation region 130.

[0040] In this embodiment, a gate forming region 130 is formed between the first portion 110 and the second portion 120. This region is provided with a gate 200 and a dummy gate 300. One end of the gate 200 is disposed in the first portion 110 of the first gate material 100, and the other end of the gate 200 is disposed in the second portion 120 of the first gate material 100. The dummy gate 300 is disposed between the first portion 110 and the second portion 120 of the first gate material 100, that is, the dummy gate 300 is disposed between the first portion 110 and the second portion 120 of the first gate material 100, but does not directly contact the first portion 110 or the second portion 120. In this way, sufficient spacing can be ensured between the dummy gate 300 and the normal gate 200 to avoid short circuits.

[0041] Understandably, in existing technologies, the contact holes of the virtual gate 300 are often located on one side of the virtual gate 300, i.e., the outward-facing side. However, due to the need to maintain the spacing between polysilicon wafers, the contact holes of the normal gate 200 can only be located on the side further away from the gate material than the contact holes of the virtual gate 300, i.e., in a more outward-facing position, which leads to an increase in the overall chip area. Therefore, in this invention, the virtual gate 300 is directly located between the first portion 110 and the second portion 120. Simultaneously, the second contact hole 500 is directly etched onto the insulating material on the virtual gate 300, because the second contact hole 500 does not need to be located further away from the gate material to maintain the polysilicon spacing. Instead, it can be located directly above or near the virtual gate 300, thereby making the layout of the entire semiconductor device more compact, saving space, and facilitating miniaturization design.

[0042] Optionally, the gate 200 and the dummy gate 300 are disposed in the gate forming region 130 along the first direction, and the gate 200 and the dummy gate 300 are alternately disposed along the second direction, wherein the first direction and the second direction intersect. In this way, a relatively well-defined gate oxide layer can be formed.

[0043] In this embodiment, the first portion 110 and the second portion 120 of the first gate material 100 are both connected to the first contact hole 400. Through these contact holes, the polysilicon layer is electrically connected to the metal electrode to ensure the normal operation of the gate 200.

[0044] In one embodiment, there are multiple gates 200, and adjacent gates 200 form a group of gate components 210; at least one dummy gate 300 is provided between every two groups of gate components 210. It is understood that the semiconductor device also includes at least one gate component 210, which may include multiple parallel gates 200. Optionally, each gate component 210 includes two gates 200, thus forming a gate-virtual gate-gate-gate-virtual gate-gate… structure. Each gate-virtual gate-gate can be considered a gate unit, and each device may have one or more gate units, depending on actual needs. It should be explained that the gate 200, as a core control component, is responsible for controlling the opening and closing of the channel. However, at the nanoscale, short-channel effects and leakage current problems become particularly severe, and relying solely on the main gate 200 is insufficient to completely solve these problems. The introduction of the dummy gate 300, by providing an additional control point in the channel region, allows for more precise adjustment of the electric field distribution in the channel region. Specifically, multiple virtual gates 300 can form a denser electric field control network, ensuring more uniform conduction in the channel region during the on-state and less leakage current during the off-state, thereby improving the switching characteristics and overall performance of the device.

[0045] In this embodiment, each gate assembly 210 includes multiple gates 200 arranged in parallel with each other, and the gate assembly 210 and the dummy gate 300 are arranged in parallel. This ensures the reliability and uniformity of the electrical connection, while also reducing interference between the gates 200 and the dummy gate 300, thus improving device performance. Furthermore, more gates 200 and dummy gates 300 can be integrated within a limited chip area, significantly improving the device's integration density.

[0046] In one embodiment, one end of the gate assembly 210 is disposed on the first portion 110 of the first gate material 100, and the other end of the gate assembly 210 is disposed on the second portion 120 of the first gate material 100. It is understood that if both ends of each gate 200 in the gate assembly 210 are respectively connected to the first portion 110 and the second portion 120, it is equivalent to both ends of the gate assembly 210 being respectively connected to the first portion 110 and the second portion 120. It is understood that in this embodiment, the length of each gate 200 is greater than that of each virtual gate 300. Thus, it is possible to achieve the following: when both ends of the gate assembly 210 are respectively in contact with the first portion 110 and the second portion 120 of the first gate assembly 210, the two ends of the virtual gate 300 are spaced apart from the first portion 110 and the second portion 120 of the first gate assembly 210.

[0047] In this embodiment, the first direction and the second direction intersect and are perpendicular to each other, thus making full use of the limited chip area and achieving higher integration and a more compact layout. Specifically, the first direction can be understood as the length direction of the gate component 210 and the virtual gate 300, while the second direction is the arrangement direction of the multiple gate components 210 and the virtual gate 300. Thus, by setting multiple gate components 210 and virtual gates 300 in the first direction and arranging them alternately in the second direction, more gates 200 and virtual gates 300 can be integrated in the same plane.

[0048] In one embodiment, such as Figure 3 and 4 As shown, there are multiple virtual gates 300, and adjacent virtual gates 300 form a group of virtual gate components 310; each virtual gate component 310 is connected to at least one second contact hole 500. It is understood that each virtual gate component 310 may include multiple virtual gates 300. When multiple virtual gates 300 are included, in order to cover the entire width direction of the virtual gate component 310, the area of ​​the two second contact holes 500 needs to be increased to cover the entire width direction of the virtual gate component 310. It is understood that in this embodiment, the area of ​​the second contact hole 500 can be relatively large, that is, the area of ​​the second contact hole 500 can be designed according to the width of the virtual gate 300. In this case, the width design of the virtual gate 300 is no longer limited, and the virtual gate 300 can be designed arbitrarily to enhance the function of the virtual gate 300. However, it should be noted that when the area of ​​the second contact hole 500 is too large, it may have a different etching rate than other contact holes in the process (such as the contact hole between the virtual gate 300 and the gate 200), which may affect the performance of the semiconductor device.

[0049] In one embodiment, such as Figure 4 As shown, the two ends of the virtual gate assembly 310 are respectively connected to the two second contact holes 500. The two second contact holes 500 need to be set at a certain distance to avoid electrical interference.

[0050] In one embodiment, such as Figure 3As shown, each of the virtual gate components 310 is connected to a second contact hole 500, which covers at least a portion of each virtual gate 300 in the virtual gate component 310. It is understood that the second contact hole 500 can be relatively large in order to connect to each virtual gate 300 of the virtual gate component 310. Optionally, the second contact hole 500 can be etched extending from one end of the virtual gate component 310 to the other, i.e., it can cover the entire virtual gate component 310, thus providing better contact and a more stable connection. However, it should be noted that due to the minimum size limitations between contact holes, if the second contact hole 500 covers the entire virtual gate component 310, it may negatively impact the contact hole between the virtual gate 300 and the gate 200, affecting the performance of the semiconductor device.

[0051] In one embodiment, such as Figure 1 and Figure 2 As shown, the virtual gate 300 is connected to at least one second contact hole 500, and the second contact hole 500 is disposed along the length direction of the virtual gate 300. It should be explained that, unlike the previous embodiment, in this embodiment each virtual gate 200 is connected to at least one second contact hole 500, while in the previous embodiment, one virtual gate assembly 310 was connected to at least one second contact hole 500.

[0052] In one embodiment, such as Figure 1 As shown, each virtual gate 300 is connected to at least two second contact holes 500, and both ends of the virtual gate 300 are respectively connected to the two second contact holes 500. It is understood that in this embodiment, each virtual gate 300 is connected to two second contact holes 500. Even in a virtual gate assembly 310 composed of multiple virtual gates 300, each virtual gate 300 in the virtual gate assembly 310 is also connected to two second contact holes. This ensures the electrical connection between each virtual gate 300 and the metal electrode without polysilicon. The spacing between the two second contact holes 500 needs to meet the minimum size requirements of the manufacturing process to prevent short circuits and increased parasitic effects. By reasonably setting the distance between the contact holes, the electrical connection of each contact hole can be ensured to be independent and reliable, reducing contact resistance and improving signal transmission efficiency.

[0053] In one embodiment, such as Figure 2As shown, the shape of the second contact hole 500 is adapted to the shape of the virtual gate 300; and / or, the size of the second contact hole 500 is adapted to the size of the virtual gate 300. It is understood that in some examples, the shape of the second contact hole 500 may be the same as the shape of the virtual gate 300, and the size of the second contact hole 500 may be the same as the size of the virtual gate 300. In other examples, the shape of the second contact hole 500 may be the same as the shape of the virtual gate 300, but the size of the second contact hole 500 is slightly smaller than, equal to, or smaller than the virtual gate 300. In this embodiment, the second contact hole 500 extends from one end of the virtual gate 300 to the other end, that is, the size of the second contact hole 500 is slightly smaller than the virtual gate 300, and the shape of the second contact hole 500 is the same as the virtual gate 300. This ensures that the potential is uniformly distributed across the entire virtual gate 300, avoiding performance fluctuations caused by localized potential unevenness. Furthermore, the uniform potential distribution reduces the impact of external noise on the virtual gate 300, improves the device's anti-interference capability, and ensures its stable operation in complex environments. However, it should be noted that since there are also minimum size limitations between contact holes, if the second contact hole 500 covers the entire virtual gate 300, it may have a negative impact on the contact hole between the virtual gate 300 and the gate 200, affecting the performance of the semiconductor device.

[0054] In one embodiment, there are multiple virtual gates 300, and the number of second contact holes 500 corresponds to the number of virtual gates 300. In this way, it can be ensured that when the semiconductor device includes multiple virtual gates 300, each virtual gate 300 can be connected to a second contact hole 500 to achieve electrical connection with the metal electrode.

[0055] It is understood that in all the above embodiments, the key point is to remove the gate material corresponding to the virtual gate 300 and directly etch the second contact hole 500 at the position corresponding to the virtual gate 300. This allows connection to the metal electrode without gate material, avoiding the negative impact of the size requirements between the gate material to be connected to the virtual gate 300 and the first gate material 100 mentioned above. This also reduces the distance between the virtual gate 300 and the gate 200, achieving miniaturization. It should be noted that the position design of the second contact hole 500 on the virtual gate 300 can be as described in the above embodiments or other designs; the key is that contact with the metal electrode can be achieved through this second contact hole 500.

[0056] Additionally, it should be noted that the first portion 110 and the second portion 120 of the first gate material 100 are both square, and the gate 200 and the dummy gate 300 are arranged in parallel. Since the first gate material 100 can be divided into the first portion 110 and the second portion 120, and are arranged horizontally along the first direction, and the gate forming region 130 is square, all the gates 200 and dummy gates 300 arranged in the gate forming region 130 can be arranged in parallel and spaced apart along the second direction. It should be explained that under these conditions, the lengths of the gate 200 and the dummy gate 300 need to be different. Because the gate 200 needs to be connected to the first portion 110 and the second portion 120, while the dummy gate 300 cannot be connected to the first portion 110 and the second portion 120, the length of the gate 200 needs to be greater than the length of the dummy gate 300.

[0057] In one embodiment, the first gate material 100 is polycrystalline silicon, a commonly used semiconductor material with good conductivity and stability. Furthermore, not only is the first gate material 100 made of polycrystalline silicon, but optionally, all other gate materials mentioned above, excluding the first gate material 100, can also be made of polycrystalline silicon.

[0058] In the above embodiments, the gate assembly 210 includes two parallel gates 200, and the virtual gate assembly 310 includes three parallel virtual gates 300. It is understood that the virtual gate assembly 310 is provided at adjacent positions of each gate 200, and a gate 200-virtual gate 300-virtual gate 300-virtual gate 300-gate 200 is defined as a gate unit.

[0059] The present invention also provides a power module, which includes at least one semiconductor device. The specific structure of the semiconductor device is as described in the above embodiments. Since the present electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0060] In this embodiment, the number of semiconductor devices in the power module can be one, four, six, or more; the specific number is not limited. It is understood that when there is one semiconductor device, it can be used as a switching transistor; when there are four, the four semiconductor devices can be used as an H-bridge and a unidirectional inverter, for bidirectional driving of DC motors, stepper motor control, etc.; when there are six, the six semiconductor devices can be used as a three-phase rectifier circuit or a three-phase inverter. Of course, the application and function of the semiconductor device in the power module are not limited. Importantly, after applying the semiconductor device proposed in this invention, the power module can also achieve a miniaturized design because the semiconductor device facilitates miniaturization. Moreover, because the semiconductor device allows for miniaturization, more semiconductor devices can be integrated without changing the size of the power module.

[0061] The present invention also proposes an electronic device, which includes a semiconductor device or a power module. The specific structure of the semiconductor device and the power module is as described in the above embodiments. Since the electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0062] Optionally, the electronic device includes a circuit board on which the semiconductor device is integrated. Integrating the semiconductor device onto the circuit board enables high integration and miniaturization, improving the overall performance and reliability of the electronic device. This allows the electronic device to process signals more efficiently, reduce power consumption, and improve response speed, making it suitable for high-performance computing, communications, and consumer electronics. Alternatively, the circuit board may integrate a power module on which the semiconductor device is integrated. Integrating the semiconductor device into the power module allows for a higher level of integration and optimization. This allows the power module to provide higher performance and lower power consumption in a smaller size, suitable for applications such as motor drives, power management, and industrial automation.

[0063] Optionally, the electronic device may include household appliances, such as water heaters, air conditioners, washing machines, refrigerators, and cleaning machines; the electronic device may also be a smartphone, laptop, or smart wearable device. Specific application scenarios are not limited; the focus is on this semiconductor device, which facilitates miniaturization design.

[0064] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first gate material, wherein the first gate material is connected to a first contact hole; A gate, wherein the gate portion is formed in the first gate material, and the gate is electrically connected to a metal electrode through the first contact hole; A virtual gate is formed between the first gate material and the gate, and the virtual gate is connected to a second contact hole. The virtual gate is electrically connected to a metal electrode through the second contact hole. The virtual gate is spaced between the first gate material and the gate arrangement.

2. The semiconductor device as claimed in claim 1, characterized in that, The first gate material has a first portion and a second portion, the first portion and the second portion of the first gate material are spaced apart along a first direction, the first portion and the second portion are spaced apart to form a gate forming region, the gate and the dummy gate are disposed in the gate forming region along the first direction, the gate and the dummy gate are spaced apart and staggered along a second direction, and the first direction and the second direction intersect.

3. The semiconductor device as described in claim 1, characterized in that, The number of gates is multiple, and among the multiple gates, adjacent gates form a group of gate components; At least one virtual gate is provided between every two groups of the gate components.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The number of virtual gates is multiple, and adjacent virtual gates form a group of virtual gate components; Each of the virtual gate components is connected to at least one of the second contact holes.

5. The semiconductor device as claimed in claim 4, characterized in that, The two ends of the virtual gate assembly are respectively connected to the two second contact holes.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The virtual gate is connected to at least one second contact hole, and the second contact hole is disposed along the length direction of the virtual gate.

7. The semiconductor device as claimed in claim 6, characterized in that, The shape of the second contact hole is adapted to the shape of the virtual gate; And / or, the size of the second contact hole is adapted to the size of the virtual gate.

8. The semiconductor device as claimed in claim 6, characterized in that, The virtual gate is connected to at least two second contact holes, and the two ends of the virtual gate are respectively connected to the two second contact holes.

9. The semiconductor device as claimed in claim 6, characterized in that, The number of virtual gates is multiple, and the number of second contact holes corresponds to the number of virtual gates.

10. The semiconductor device as claimed in claim 2, characterized in that, The first and second portions of the first gate material are both square, the gate forming region is square, and the gate and the virtual gate are arranged in parallel.

11. The semiconductor device as claimed in claim 1, characterized in that, The first gate material is polycrystalline silicon.

12. A power module, characterized in that, The power module integrates at least one semiconductor device as described in any one of claims 1 to 11.

13. An electronic device, characterized in that, The electronic device includes: The semiconductor device as described in any one of claims 1 to 11; and / or, The power module as described in claim 12.

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