A high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack and a preparation method thereof
By synergistically designing the hafnium aluminum oxy ferroelectric layer and the aluminum oxide intermediate layer, the durability problem of hafnium oxide-based FeFETs was solved, resulting in a smaller coercive electric field and polarization intensity, a lower operating voltage, improved FeFET durability, and compatibility with CMOS processes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2023-02-23
- Publication Date
- 2026-05-22
AI Technical Summary
Existing hafnium oxide-based FeFETs have poor durability, mainly due to the interface trapping between the ferroelectric layer and the intermediate layer and the large electric field strength, which leads to charge trapping and dielectric layer breakdown problems. There is a lack of overall optimization research.
By employing a synergistic design of a hafnium aluminum oxy ferroelectric layer and an alumina intermediate layer, and controlling the atomic ratio of the hafnium aluminum oxy ferroelectric layer to 24:1 through atomic layer deposition, combined with the high dielectric constant and thermal stability of the alumina intermediate layer, a highly durable FeFET structure is formed.
It lowers the operating voltage of FeFETs, reduces interface trapping and dielectric layer breakdown, improves device durability, and is compatible with CMOS processes, making it suitable for hybrid integration.
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Figure CN116072733B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a novel high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate dielectrics and its fabrication method. Background Technology
[0002] With the advent of the big data era and the rapid development of fields such as artificial intelligence, the Internet of Things, and wearable devices, the storage and real-time processing of massive amounts of data has become an urgent need. The integrated circuit industry faces severe bottlenecks in computing power and power consumption, making high-speed, low-power, and high-density memory device technologies crucial. The rapidly developing novel non-volatile memory holds promise for providing new solutions to overcome these bottlenecks, partially replacing or supplementing existing memory hierarchies, and this field has become a research hotspot in academia. Following the discovery of hafnium oxide-doped ferroelectric materials, research on hafnium oxide-doped ferroelectric materials and their applications in memory has progressed rapidly.
[0003] Among them, hafnium oxide ferroelectric field-effect transistors (FeFETs) are likely to become one of the most promising new embedded non-volatile memories due to their advantages such as ultra-low write power consumption, high read and write speed, high integration density, better miniaturization, and compatibility with advanced integrated circuit node processes. The basic working principle of FeFET is to use the polarization states of the ferroelectric layer in the gate in two different directions (up and down) to modulate the threshold voltage of the device, thereby distinguishing between the different storage states of '0' and '1'.
[0004] Significant progress has been made in the research of hafnium oxide-based FeFETs, but they still face the critical issue of poor durability. This is mainly due to interface trapping and new trap formation between the ferroelectric layer and the intermediate layer during electrical cycling. Interface trapping is closely related to both the ferroelectric layer and the intermediate layer. For the ferroelectric layer, the large coercive electric field and polarization intensity of hafnium oxide-based ferroelectric materials result in a large electric field intensity in the intermediate layer, making it easier for charges to be injected from the substrate into the gate stack and trapped. For the intermediate layer, the relatively low permittivity of the conventional SiO2 dielectric layer leads to a large electric field intensity. At the same time, the poor thermal stability of the dielectric layer leads to the formation of more interface traps in subsequent ferroelectric activation processes, exacerbating charge trapping and durability degradation. In addition, there are requirements for process compatibility and low interface trap density between the ferroelectric layer and the intermediate dielectric layer. Although many research groups have proposed methods to suppress interface trap charge trapping from the perspective of optimizing the ferroelectric layer and the intermediate layer respectively, there is still a lack of research on the overall optimization of the ferroelectric layer and the intermediate layer to further improve the durability of FeFETs. Summary of the Invention
[0005] The purpose of this invention is to propose a high-durability FeFET and its fabrication method by utilizing the synergistic design of the ferroelectric layer and intermediate layer in the gate stack.
[0006] Specifically, the technical solution of the present invention is as follows:
[0007] A high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack includes a silicon substrate. A patterned aluminum oxide intermediate layer, a hafnium aluminum oxide ferroelectric layer, a gate metal electrode, and a contact metal are sequentially disposed on the surface of the silicon substrate. Source and drain regions are formed on the surface of the silicon substrate by self-aligned ion doping. The source and drain metal contact electrodes are located above the source and drain regions. The hafnium aluminum oxide ferroelectric layer is grown by atomic layer deposition. During the atomic layer deposition cycle, the number of cycles of hafnium oxide and aluminum oxide is controlled to control the ratio of doped atoms. The final hafnium aluminum oxide ferroelectric layer has a hafnium atom to aluminum atom ratio of 24:1. Different polarization states of the hafnium aluminum oxide ferroelectric layer store two storage states.
[0008] The aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack uses a p-type silicon substrate for n-type FeFETs and an n-type silicon substrate for p-type FeFETs. The p-type substrate can be a silicon substrate with a low concentration of boron doping, and the n-type substrate can be a silicon substrate with a low concentration of arsenic or phosphorus doping.
[0009] The aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack has an aluminum oxide intermediate layer grown by atomic layer deposition, which can ensure its high quality and control its thickness. The thickness of the aluminum oxide intermediate layer is about 1 to 3 nm.
[0010] The aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stacks has its hafnium aluminum oxide ferroelectric layer grown by atomic layer deposition. The growth method involves controlling the number of cycles of hafnium oxide and aluminum oxide during the atomic layer deposition cycle to control the ratio of doped atoms. The final hafnium aluminum oxide ferroelectric layer has a hafnium to aluminum atom ratio of 24:1, thereby ensuring a small coercive electric field and polarization intensity. The thickness of the hafnium aluminum oxide ferroelectric layer on the aluminum oxide intermediate layer is 10-15 nm.
[0011] The aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack requires its gate metal electrode to have a suitable work function, certain heat resistance and mechanical strength, and also to form a certain stress on the ferroelectric layer. Common metallic materials such as TiN, TaN, Pt, and Wu can be selected.
[0012] The aforementioned high-drain FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack has its source and drain regions formed by self-aligned ion implantation after patterning the gate region, with the channel region located between the source and drain regions. For n-type FeFETs, high-concentration doping such as arsenic or phosphorus can be used, while for p-type FeFETs, high-concentration doping such as boron can be used, and the source and drain structures are formed through high-temperature annealing.
[0013] The aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack should have its source and drain contact metals forming good ohmic contacts with the source and drain regions to reduce contact resistance. Selectable metals include, but are not limited to, Al, Sc, Pt, Cr, Pd, Au, Ti, and other materials.
[0014] In the aforementioned high-durability FeFET based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack, the silicon substrate thickness must be greater than 100 nm, the gate metal electrode thickness on the hafnium aluminum oxide ferroelectric layer is about 30-50 nm, and the metal contact electrode thickness above the source / drain region is about 50 nm.
[0015] This invention also provides a method for fabricating the above-mentioned high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack, comprising the following steps:
[0016] (1) Perform routine cleaning on the silicon substrate;
[0017] (2) A thick silicon dioxide layer is grown on the whole wafer by oxidation or chemical vapor deposition (CVD). Then, the active region is defined by photolithography, and the silicon dioxide layer of the active region is removed by dry etching and wet etching to expose the underlying silicon substrate.
[0018] (3) Use diluted hydrofluoric acid solution to remove the natural oxide layer on the surface of the active silicon substrate;
[0019] (4) An aluminum oxide intermediate layer and a hafnium aluminum oxy ferroelectric layer are deposited on the whole wafer using atomic layer deposition (ALD). During the atomic layer deposition cycle, the number of cycles of hafnium oxide and aluminum oxide are controlled to control the ratio of doped atoms. Finally, the ratio of hafnium atoms to aluminum atoms in the hafnium aluminum oxy ferroelectric layer is 24:1.
[0020] (5) Deposit gate metal electrode material on the whole wafer by sputtering or physical vapor deposition (PVD);
[0021] (6) Define the gate region by photolithography, and then remove the gate metal electrode material of the non-gate region by dry etching;
[0022] (7) Perform self-aligned ion implantation on the entire sheet;
[0023] (8) Perform rapid thermal annealing on the entire sheet to activate the ferroelectricity of the ferroelectric layer and activate the ions injected into the source and drain regions.
[0024] (9) A silicon dioxide passivation layer is grown on the whole wafer by chemical vapor deposition (CVD). Then, the contact hole area of the gate metal and source drain area is defined by photolithography. The silicon dioxide of the contact hole area is removed by dry etching and wet etching. Then, the contact metal pattern above the gate metal and source drain area is defined by photolithography. The contact metal is grown by physical vapor deposition (PVD), sputtering, evaporation and other methods and then stripped. Finally, alloy annealing is performed to form ohmic contacts.
[0025] In the above preparation method, the atomic layer deposition of the aluminum oxide intermediate layer and the hafnium aluminum oxide ferroelectric layer with an atomic ratio of 24:1 in step (3) can be completed in the same ALD step; in step (7) self-aligned ion implantation, due to the obstruction of the photoresist in the gate region, the ions will not be implanted into the gate below, but will be implanted into the substrate regions on the left and right sides of the gate to form the source and drain regions, and the middle of the source and drain regions is the channel region; the temperature and time of the rapid thermal annealing process in step (8) need to meet the appropriate conditions for the activation of the hafnium aluminum oxide ferroelectric layer and the activation of the source and drain at the same time. The temperature and time are flexibly adjusted according to the different ferroelectric layer materials, gate metal electrode materials, implanted ion types and doses. The approximate range is: annealing temperature of 700~900℃ and annealing time of 10~60s.
[0026] As can be seen, the fabrication method of the high-durability FeFET based on the ferroelectric hafnium aluminum oxide and aluminum oxide gate stack is fully compatible with mature CMOS front-end processes. The only difference from the main structure of conventional MOSFETs is the addition of a ferroelectric layer. Therefore, the high-durability FeFET memory based on the ferroelectric hafnium aluminum oxide and aluminum oxide gate stack can be integrated with CMOS logic circuits.
[0027] The technical effects of this invention are as follows:
[0028] 1. Replacing the commonly used hafnium zirconium ferroelectric layer in FeFET with a hafnium atom to aluminum atom ratio of 24:1 results in a smaller coercive electric field and polarization intensity, which can reduce the operating voltage of FeFET and improve durability.
[0029] Compared to the hafnium-zirconium oxide (hafnium to zirconium atom ratio of 1:1) commonly used in FeFETs, the hafnium-aluminum oxide ferroelectric layer with an atomic ratio of 24:1 used in this invention reduces both the coercive electric field and polarization intensity by more than half. On one hand, the reduced coercive electric field of the hafnium-aluminum oxide ferroelectric layer means that a lower voltage is required to achieve polarization switching, thus helping to reduce the operating voltage of the FeFET. This effectively suppresses gate dielectric layer breakdown, reduces memory write power consumption, and facilitates compatibility with the operating voltage of logic circuits. On the other hand, the durability degradation of FeFETs is mainly caused by interface trap charge capture. The reduced coercive electric field and polarization intensity of the hafnium-aluminum oxide ferroelectric layer both help to reduce the electric field intensity of the intermediate layer, thereby effectively suppressing charge tunneling injection from the substrate into the gate stack, reducing the charge density trapped by interface traps, and thus improving the durability of the FeFET.
[0030] Second, using alumina grown by atomic layer deposition as an intermediate layer, alumina has a relatively high permittivity and better thermal stability, which is beneficial to improving the durability of FeFET.
[0031] Compared to silicon dioxide, which has a relative permittivity of 3.9 and is commonly used as an interlayer in FeFETs, alumina has a relative permittivity of approximately 9, which is higher. In the FeFET gate stack, the ferroelectric layer and the interlayer form a series capacitor structure. The higher relative permittivity of the interlayer means that, at the same thickness, the voltage drop across the interlayer is smaller, and most of the operating voltage drops across the ferroelectric layer. Therefore, the electric field strength of the interlayer is reduced, effectively suppressing charge injection, interface trapping, and interlayer breakdown, thus improving durability. Furthermore, alumina has good thermal stability. During the high-temperature annealing process for activating ferroelectricity and source / drain properties in FeFETs, oxygen in alumina is difficult to diffuse to the silicon substrate surface and react with silicon to form a silicon oxide interface layer. Typically, this thin silicon oxide interface layer contains a large number of interface traps, leading to the trapping of a large amount of charge and degrading durability. Therefore, introducing an alumina interlayer can improve durability by avoiding the formation of this silicon oxide interface layer.
[0032] Third, the combination of hafnium aluminum oxy ferroelectric layer and alumina intermediate layer has a synergistic optimization effect, which can effectively reduce the interface trap density between the two, thereby improving the durability of FeFET and simplifying the process complexity.
[0033] In addition to the advantages of the HAO ferroelectric layer and the alumina interlayer mentioned above, the most important advantage lies in the synergistic optimization effect of the combination of the HAO ferroelectric layer and the alumina interlayer in this invention. Since both the HAO ferroelectric layer and the alumina interlayer are mature materials in atomic layer deposition (ALD) processes, and their lattice matching is high, there are fewer defects at their interface, resulting in a lower interface trap density. This better suppresses interface trap trapping and improves the durability of the FeFET. By extracting the interface trap density, we found that the interface trap density between the HAO ferroelectric layer and the Al2O3 interlayer is approximately 8.3 × 10⁻⁶. 13 cm -2 The density of the ferroelectric hafnium aluminum oxide and aluminum oxide gate stack of this invention is lower than that of FeFETs with only HZO or HAO ferroelectric layers and the interface trap density between HAO and SiO2. Therefore, the FeFET of this invention can achieve high durability. At the same time, the HAO ferroelectric layer and the Al2O3 intermediate layer can be grown in the same atomic layer deposition step, ensuring compatibility between the two and simplifying the process steps.
[0034] Fourth, the fabrication process is mature and compatible with advanced node CMOS technology, and can be hybrid integrated with CMOS logic circuits.
[0035] Most of the materials, equipment, and technologies used in this fabrication process are widely used in CMOS manufacturing and are fully compatible with advanced node CMOS processes. This high-durability FeFET memory based on ferroelectric hafnium aluminum oxide and aluminum oxide gate stack is expected to achieve hybrid integration with CMOS logic circuits, which is beneficial for realizing tasks such as in-memory computing. Attached Figure Description
[0036] Figure 1 This is a schematic cross-sectional view of a high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack prepared according to an embodiment of the present invention.
[0037] In the picture:
[0038] 1—Silicon substrate; 2—Silicon dioxide in non-active regions
[0039] 3 – Alumina intermediate layer; 4 – Hafnium aluminum oxy ferroelectric layer
[0040] 5—Gate metal electrode; 6—Source
[0041] 7 - Leakage; 8 - Silicon dioxide passivation layer
[0042] 9—Source, Drain, and Gate Contact Metals
[0043] Figure 2 This is a schematic diagram illustrating the steps involved in preparing a high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack according to an embodiment of the present invention, wherein:
[0044] (a) is a cross-sectional view of non-active region silicon dioxide grown on a silicon substrate by oxidation or chemical vapor deposition (CVD) for isolation;
[0045] (b) is a cross-sectional view of the alumina intermediate layer and hafnium aluminum oxy ferroelectric layer grown by atomic layer deposition (ALD) based on (a);
[0046] (c) is a cross-sectional view of the gate metal electrode grown by sputtering or physical vapor deposition (PVD) and patterned by photolithography and dry etching, based on (b).
[0047] (d) is a cross-sectional view of the source and drain structures formed by self-aligned ion implantation based on (c);
[0048] (e) is a cross-sectional view of the silicon dioxide passivation layer grown by chemical vapor deposition (CVD) based on (d);
[0049] (f) is a cross-sectional view of the contact metal grown and stripped using methods such as physical vapor deposition (PVD), sputtering, and evaporation, based on (e).
[0050] In the picture:
[0051] 1—Silicon substrate; 2—Silicon dioxide in non-active regions
[0052] 3 – Alumina intermediate layer; 4 – Hafnium aluminum oxy ferroelectric layer
[0053] 5—Gate metal electrode; 6—Source
[0054] 7 - Leakage; 8 - Silicon dioxide passivation layer
[0055] 9—Source, Drain, and Gate Contact Metals
[0056] Figure 3 This involves a comparison of the interface trap densities extracted using the quasi-static CV (QSCV) method with those of the ferroelectric hafnium aluminum oxide and aluminum oxide gate stacked FeFETs prepared in the embodiments of the present invention, as well as other conventional gate stacked FeFETs.
[0057] (a) shows the extracted hafnium zirconium oxide as the ferroelectric layer, with silicon oxide (SiO) as the intermediate layer. x The interface trap density of the FeFET quasi-static CV layer is 2.5 × 10⁻⁶. 14 cm -2 ;
[0058] (b) is an extracted hafnium aluminum oxide layer as the ferroelectric layer, with silicon oxide (SiO) as the intermediate layer. xThe interface trap density of the FeFET layer is 1.6 × 10⁻⁶. 14 cm -2 ;
[0059] (c) shows the interface trap density of a FeFET with extracted hafnium aluminum oxide as the ferroelectric layer and a silicon dioxide (SiO2) layer as the intermediate layer, which is 1.5 × 10⁻⁶. 14 cm -2 ;
[0060] (d) is the interface trap density of the FeFET in this embodiment of the invention, where hafnium aluminum oxide is used as the ferroelectric layer and the intermediate layer is aluminum oxide (Al2O3), which is 8.3 × 10⁻⁶. 13 cm -2 . Detailed Implementation
[0061] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0062] like Figure 1 As shown, the fabricated high-durability FeFET based on a ferroelectric hafnium aluminum oxide and aluminum oxide gate stack includes a silicon substrate 1, a non-active region silicon dioxide 2 for isolation, an aluminum oxide intermediate layer 3, a hafnium aluminum oxide ferroelectric layer 4, a gate metal electrode 5, a source 6, a drain 7, a silicon dioxide passivation layer 8, and gate, source, and drain contact metals 9. The aluminum oxide intermediate layer 3 is located above the silicon substrate 1, the hafnium aluminum oxide ferroelectric layer 4 is located above the aluminum oxide intermediate layer 3, the gate metal electrode 5 is located above the hafnium aluminum oxide ferroelectric layer 4, the source 6 and drain 7 are located on either side below the gate structure in the silicon substrate 1, and the gate, source, and drain contact metals 9 are located above the gate metal electrode 5, the source 6, and the drain 7, respectively.
[0063] The preparation method includes the following steps: Figure 2 As shown, it specifically includes:
[0064] 1) A relatively thick silicon dioxide layer (approximately 500 nm) is grown on the entire silicon substrate 1 using oxidation or chemical vapor deposition (CVD). The active region is defined by photolithography, and the silicon dioxide in the active region is removed by dry etching. After removing the photoresist, a diluted hydrofluoric acid solution is used for etching for a certain period to ensure complete removal of the silicon dioxide in the active region, exposing the underlying silicon substrate. The remaining non-active silicon dioxide 2 is used for isolation between devices, such as... Figure 2 As shown in (a);
[0065] 2) After rinsing off the native oxide layer on the surface of silicon substrate 1 with diluted hydrofluoric acid solution, a 3 nm thick aluminum oxide intermediate layer 3 and a 12 nm thick hafnium aluminum oxy ferroelectric layer 4 are deposited on the entire wafer using atomic layer deposition (ALD). During the ALD cycle, the number of cycles for hafnium oxide and aluminum oxide is controlled to adjust the doping atomic ratio. The final hafnium aluminum oxy ferroelectric layer has a hafnium to aluminum atom ratio of 24:1. Figure 2 As shown in (b);
[0066] 3) A 50 nm thick gate metal electrode 5 is grown over the entire wafer using sputtering or physical vapor deposition (PVD). The gate region is then defined by photolithography, and the gate metal electrode 5, hafnium aluminum oxy ferroelectric layer 4, and aluminum oxide intermediate layer 3 in the non-gate region are removed using dry etching. Figure 2 As shown in (c);
[0067] 4) Depending on whether it's an n-type or p-type FeFET, phosphorus, arsenic, or boron is selected for ion implantation across the entire wafer. Due to the photoresist blocking the gate region, ions will not implant into the gate structure. Ions implanted into the silicon substrate 1 form the source 6 and drain 7 regions. Subsequently, the entire wafer undergoes rapid thermal annealing at 700–900℃ for 10–60 seconds. Annealing conditions need to be flexibly adjusted based on the ferroelectric layer doping ratio, gate electrode type, and the type, concentration, and dosage of implanted ions. It is essential to ensure simultaneous activation of the ferroelectric layer's ferroelectricity and complete activation of the source and drain regions. Figure 2 As shown in (d);
[0068] 5) A relatively thick silicon dioxide passivation layer 8 (approximately 500 nm) is grown over the entire wafer using chemical vapor deposition (CVD), such as... Figure 2 As shown in (e);
[0069] 6) Vias in the gate metal electrode 5, source 6, and drain 7 regions are defined by photolithography. These vias are formed in the silicon dioxide passivation layer 8 using a combination of dry etching and wet etching. Then, contact metal electrode patterns are defined by photolithography. Contact metal 9 is grown using methods such as physical vapor deposition (PVD), sputtering, and evaporation. Acetone is used for stripping, and finally, alloying annealing is performed. Figure 2 As shown in (f);
[0070] At this point, the high-durability FeFET based on the ferroelectric hafnium aluminum oxide and aluminum oxide gate stack can be obtained.
[0071] This invention utilizes aluminum-doped hafnium oxide (HAO, with a hafnium to aluminum atomic ratio of 24:1) as the ferroelectric material and aluminum oxide (Al₂O₃) as the interlayer of the FeFET. Compared to conventional zirconium-doped hafnium oxide (HZO, with a hafnium to zirconium atomic ratio of 1:1), HAO ferroelectric material exhibits a lower coercive electric field and ferroelectric polarization. Therefore, when a voltage is applied, the electric field strength on the interlayer is lower, which suppresses charge injection from the substrate through the interlayer into the gate stack and its trapping by interface traps, thus improving durability. Simultaneously, the lower electric field strength in the interlayer effectively prevents performance failure due to breakdown of the interlayer dielectric. Furthermore, the lower coercive electric field of HAO also means a reduced voltage required for ferroelectric polarization reversal, thereby effectively reducing the operating voltage of the FeFET. For the Al2O3 interlayer, firstly, its relative permittivity is relatively high (approximately 9), which is higher than that of the conventional silicon oxide interlayer (relative permittivity 3.9). Therefore, it can further reduce the voltage division of the interlayer, thereby reducing the electric field strength of the interlayer and suppressing interface trapping. Secondly, Al2O3 has good thermal stability, which can effectively prevent oxygen atoms from diffusing to the silicon substrate surface and reacting with silicon to form a layer of silicon oxide (SiO2) during the high-temperature annealing process of FeFET. x ) layer. This SiO layer x Containing numerous defects, these defects act as interface traps, trapping charges and leading to durability degradation. Besides the advantages mentioned above for HAO and Al2O3 as the ferroelectric layer and intermediate layer respectively, the combination of HAO and Al2O3 has a synergistic optimization effect, allowing for optimization of the coupling effect between the ferroelectric layer and the intermediate layer. Because aluminum doping is used in the ferroelectric layer, the lattice of the HAO ferroelectric layer and the Al2O3 intermediate layer are more matched, resulting in a lower interface trap density and better suppression of interface trap charge trapping. Figure 3 As shown. Furthermore, both HAO and Al2O3 are mature materials in atomic layer deposition (ALD) processes, and can be grown in a single ALD step, ensuring process compatibility and simplifying the process steps. Therefore, using HAO and Al2O3 as gate layers can comprehensively optimize the storage performance of FeFETs, especially effectively improving their durability and helping to solve this key problem faced by FeFETs. Moreover, this structure has a simple fabrication process, is compatible with advanced CMOS front-end processes, and has the capability for large-scale integration.
[0072] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.
Claims
1. A FeFET device, characterized in that, The device includes a silicon substrate, on which a patterned aluminum oxide intermediate layer, a hafnium aluminum oxy ferroelectric layer, a gate metal electrode, and a contact metal are sequentially disposed. Source and drain regions are formed on the surface of the silicon substrate by self-aligned ion doping. Above the source and drain regions are source and drain metal contact electrodes. The hafnium aluminum oxy ferroelectric layer is grown by atomic layer deposition. During the atomic layer deposition cycle, the number of cycles of hafnium oxide and aluminum oxide is controlled to control the ratio of doped atoms. The final hafnium aluminum oxy ferroelectric layer has a hafnium atom to aluminum atom ratio of 24:
1. Different polarization states of the hafnium aluminum oxy ferroelectric layer store two storage states.
2. The FeFET device as described in claim 1, characterized in that, For n-type FeFETs, a p-type silicon substrate with low boron doping is selected, and for p-type FeFETs, an n-type silicon substrate with low arsenic or phosphorus doping is selected.
3. The FeFET device as described in claim 1, characterized in that, The alumina intermediate layer is grown by atomic layer deposition and has a thickness ranging from 1 to 3 nm.
4. The FeFET device as described in claim 1, characterized in that, The thickness of the hafnium aluminum oxy ferroelectric layer ranges from 10 to 15 nm.
5. The FeFET device as claimed in claim 1, characterized in that, The gate metal electrode is made of TiN, TaN, Pt or Wu, with a thickness ranging from 30 to 50 nm.
6. The FeFET device as claimed in claim 1, characterized in that, The source / drain metal contact electrodes are selected from Al, Sc, Pt, Cr, Pd, Au, or Ti.
7. A method for fabricating a FeFET device, characterized in that, Includes the following steps: 1) Perform routine cleaning on the silicon substrate; 2) A thick silicon dioxide layer is grown by oxidation or chemical vapor deposition (CVD), and then the active region is defined by photolithography. The silicon dioxide layer of the active region is removed by dry etching and wet etching to expose the underlying silicon substrate. 3) Rinse off the native oxide layer on the surface of the active silicon substrate with a diluted hydrofluoric acid solution; 4) An alumina intermediate layer and a hafnium aluminum oxy ferroelectric layer are deposited using atomic layer deposition (ALD). During the ALD cycle, the number of cycles of hafnium oxide and alumina oxide is controlled to control the ratio of doped atoms. The final hafnium aluminum oxy ferroelectric layer has a hafnium atom to aluminum atom ratio of 24:
1. 5) Deposit gate metal electrode materials by sputtering or physical vapor deposition (PVD); 6) Define the gate region by photolithography, and then remove the gate metal electrode material of the non-gate region by dry etching; 7) Perform self-aligned ion implantation. Due to the obstruction of photoresist in the gate region, ions will not be implanted into the gate below. Ions are implanted into the substrate regions on the left and right sides of the gate, forming the source and drain regions. The middle of the source and drain regions is the channel region. 8) Perform rapid thermal annealing to simultaneously activate the ferroelectricity of the ferroelectric layer and the ions implanted into the source and drain regions; 9) A silicon dioxide passivation layer is grown by chemical vapor deposition (CVD). Then, the contact hole regions of the gate metal and source / drain regions are defined by photolithography. The silicon dioxide in the contact hole regions is removed by dry etching and wet etching. Subsequently, the contact metal pattern above the gate metal and source / drain regions is defined by photolithography. The contact metal is grown by physical vapor deposition (PVD), sputtering, and evaporation and then stripped. Finally, alloy annealing is performed to form ohmic contacts.
8. The method for fabricating the FeFET device as described in claim 7, characterized in that, In step 8), the rapid thermal annealing process is carried out at a temperature of 700–900°C and an annealing time of 10–60 seconds.