Display panel and display device

Abstract

The invention provides a display panel and a display device. A gate drive circuit in the display panel comprises a plurality of cascaded shift registers, and an ith-level first-class register in a first gate drive circuit is a first register; i > = 1 and i is an integer. In the first register, the control end of the first input transistor is electrically connected with a first clock signal line, part of transistors in the second control unit are electrically connected with a second clock signal line, and the first end of the first adjusting transistor is electrically connected with a first voltage adjusting signal line. Enabling switching moments of signals transmitted by the first clock signal line, the second clock signal line and the first voltage regulating signal line are a first moment, a second moment and a third moment; the enabling switching time is the time when the electric signal starts to be switched from the non-enabling signal to the enabling signal. Wherein in the first stage, the first moment is earlier than the second moment and the third moment, and the time interval between the first moment and the third moment is smaller than the time interval between the first moment and the second moment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Under the existing design, the gate potential of the plurality of transistors in the pixel circuit is usually controlled by the gate control signal output by the gate drive circuit, and the output of the gate control signal of the gate drive circuit is often realized with the participation of a plurality of clock signals. It needs to be clear that there is a timing difference between the plurality of clock signals (which can refer to the time interval between the adjacent rising edges corresponding to the two clock signals respectively), which causes the abnormality of the timing corresponding to the gate control signal output by the gate drive circuit, and further causes the delay of the opening and closing time of part of the transistors in the pixel circuit, thereby reducing the display effect. SUMMARY

[0003] The present application provides a display panel and a display device to facilitate solving the problem of reducing the display effect caused by the abnormality of the timing of the gate control signal.

[0004] Therefore, the present application provides a display panel, which comprises a plurality of gate drive circuits; the gate drive circuit comprises a plurality of cascaded shift registers, and the output end of the shift register is electrically connected with a scan signal line.

[0005] The shift register comprises a first output unit and a second output unit; the first end of the first output unit is electrically connected with a first signal line, the first end of the second output unit is electrically connected with a second signal line, and the second end of the first output unit and the second end of the second output unit are both electrically connected with the scan signal line; the level of the signal transmitted by the first signal line is lower than the level of the signal transmitted by the second signal line.

[0006] The shift register further comprises a first control unit and a second control unit.

[0007] The first control unit comprises an adjusting capacitor, a first adjusting transistor, a first transmission transistor and a first input transistor; the first end of the first input transistor is electrically connected with an input signal line, and the second end of the first input transistor is electrically connected with the first end of the first transmission transistor; the second end of the first transmission transistor is electrically connected with the first plate of the adjusting capacitor, the control end of the first adjusting transistor and the control end of the first output unit, and the control end of the first transmission transistor is electrically connected with the first signal line; the second end of the first adjusting transistor is electrically connected with the second plate of the adjusting capacitor.

[0008] The output end of the second control unit is electrically connected with the control end of the second output unit. The plurality of gate drive circuits comprises a first gate drive circuit, the shift register in the first gate drive circuit is a first type register, and the i-th first type register is a first register; i≥1 and i is an integer.

[0009] In the first register, the control end of the first input transistor is electrically connected with the first clock signal line, part of the transistors in the second control unit are electrically connected with the second clock signal line, and the first end of the first adjusting transistor is electrically connected with the first voltage regulating signal line.

[0010] The enabling switching time of the signal transmitted by the first clock signal line is the first time, the enabling switching time of the signal transmitted by the second clock signal line is the second time, and the enabling switching time of the signal transmitted by the first voltage regulating signal line is the third time; the enabling switching time is the time when the electrical signal starts to switch from the non-enabling signal to the enabling signal.

[0011] In the first stage, the first time is earlier than the second time and the third time, and the time interval between the first time and the third time is less than the time interval between the first time and the second time.

[0012] Based on the same inventive concept, the application also provides a display device comprising the display panel.

[0013] Compared with the prior art, the display panel and the display device provided by the application at least achieve the following beneficial effects: By introducing the first voltage regulating signal line, the voltage regulating signal transmitted thereby can be used in cooperation with the input signal transmitted by the input signal line, and the self-discharging effect of the adjusting capacitor is combined to further lower the potential of the control end of the first output unit, so that the target low level can be reached after the high-low level switching of the gate control signal. In addition, the timing design of Δta less than Δtb is realized in the application, which means that, compared with the way of using the clock signals transmitted by two clock signal lines for self-discharging adjustment in the prior design, the design advantage of the application of using the voltage regulating signal in cooperation with the input signal lies in that the time interval between the falling edges of the two cooperating signals (the signals written to the two polar plates of the adjusting capacitor) can be reduced or even eliminated, thereby helping to reduce the jump time of the gate control signal, so that the potential of the gate control signal can be switched in time, further improving the working state of the pixel circuit and maintaining good display effect. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 The equivalent circuit diagram of part of the structure of the gate drive circuit in the related art; Figure 2 isFigure 1 A timing diagram of the partial position potentials and the signals transmitted by the partial signal lines in the shift register of the display panel shown in FIG. 6; Figure 3 A schematic diagram of a partial structure of a display panel provided in the present application; Figure 4 A schematic diagram of a partial structure of a display panel provided in the present application; Figure 3 An equivalent circuit diagram of the shift register in the display panel shown in FIG. 6; Figure 5 A schematic diagram of a partial structure of a display panel provided in the present application; Figure 3 An equivalent circuit diagram of the pixel circuit in the display panel shown in FIG. 6; Figure 6 A timing diagram of the partial position potentials and the signals transmitted by the partial signal lines in the shift register of the display panel shown in FIG. 6; Figure 7 Another timing diagram of the partial position potentials and the signals transmitted by the partial signal lines in the shift register of the display panel shown in FIG. 6; Figure 8 A schematic diagram of a partial structure of a display panel provided in the present application; Figure 9 Equivalent circuit diagrams corresponding to different shift registers; Figure 10 A timing diagram of the signals transmitted by the multiple signal lines connected to the second register; Figure 11 A schematic diagram of a partial structure of a display panel provided in the present application; Figure 12 Equivalent circuit diagrams corresponding to different shift registers; Figure 13 A timing diagram of the signals transmitted by the multiple signal lines connected to the third register; Figure 14 Equivalent circuit diagrams corresponding to the second register and the fourth register, respectively; Figure 15 An equivalent circuit diagram corresponding to the fifth register; Figure 16 A timing diagram of the partial position potentials and the signals transmitted by the partial signal lines in the shift register of the display panel shown in FIG. 6; Figure 17 A schematic diagram of a display device provided in the present application. DETAILED DESCRIPTION

[0016] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0017] It should be noted that the embodiments described are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0018] The terms used in the embodiments of the present application are only for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0019] It should be understood that the term "and / or" used herein only describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0020] Figure 1 Equivalent circuit diagram of part of the structure of the gate drive circuit in the related art.

[0021] Under the existing design, the gate potential of the plurality of transistors in the pixel circuit is usually adjusted by the gate control signal output by the gate drive circuit 01', as shown in Figure 1 The output end 01a' of the gate drive circuit 01' can output the gate control signal, and the gate control signal includes an enabled state and a disabled state (the gate control signal in the enabled state can control the transistor to be turned on, and the gate control signal in the disabled state can control the transistor to be turned off). Specifically, when the transistor receiving the gate control signal is a P-type transistor, the voltage value corresponding to the gate control signal in the enabled state can be lower than the voltage value corresponding to the gate control signal in the disabled state.

[0022] When the first output transistor T1 of the gate drive circuit 01' is turned on, the low-level electrical signal transmitted by the first signal line VGL is output through the output end 01a', and the low-level electrical signal can be the gate control signal in the enabled state; when the second output transistor T2 of the gate drive circuit 01' is turned on, the high-level electrical signal transmitted by the second signal line VGH is output through the output end 01a', and the high-level electrical signal can be the gate control signal in the disabled state.

[0023] The gate drive circuit 01' can also include a plurality of transistors T4, T5, T6, T7, T8, T9, T10, T1a, T1b, T1c, etc., and a plurality of capacitors C11, C12, etc. In addition, the connection mode between the above-mentioned circuit structures and the connection mode between the gate drive circuit 01' and each signal line are described in detail in Figure 1As shown, details are not repeated here.

[0024] It should be noted that in the process of switching the gate control signal from a high-level electrical signal to a low-level electrical signal, it is difficult for the gate control signal to complete the switching of the high and low levels in a short time, that is, the gate control signal needs a certain time (hereinafter referred to as the transition time) to switch from high level to target low level. The existence of the transition time easily leads to the difficulty of timely switching of the gate control signal, thereby affecting the opening and closing states of some transistors in the pixel circuit, and thus affecting the working state of the pixel circuit and reducing the display effect.

[0025] Figure 2 For Figure 1 The timing diagram of part of the electrical signals corresponding to the gate drive circuit is shown as follows for the convenience of understanding, Figure 2 The potential changes of the control end of the first output transistor and the output end of the gate drive circuit under the transmission of the electrical signals of the first signal line, the second level signal, the first clock signal line, the second clock signal line and the input signal line are shown in the following.

[0026] The reasons for the above-mentioned difficulty of timely switching of the gate control signal are as follows: in combination with Figure 1 and Figure 2 When the gate control signal starts to switch from a high-level signal to a low-level signal, the second output transistor T2 is closed, the first clock signal line CK transmits a low-level signal, the first transistor T3 is opened, and there is a low-level signal transmitted by the input signal line IN to the control end 11a' of the first output transistor T1. Considering the load problem of the first clock signal line CK (usually one first clock signal line CK can provide a clock signal to multiple circuits), the process fluctuation problem and the temperature influence, the threshold voltage of some transistors (for example, the first transistor T3 and the first output transistor T2) in the gate drive circuit 01' is easy to deviate, specifically, it takes a long time for the low-level signal transmitted by the input signal line IN to pull down the potential of the control end 11a' to the target low potential, which leads to the difficulty of the first output transistor T2 to completely open, and affects the high and low levels of the output signal. To solve this problem, the self-falling effect of the first capacitor C10 is selected in the existing design to further pull down the potential of the control end 11a', and in this process, the low-level signal transmitted by the second clock signal line XCK is used to pull down the potential of one end of the first capacitor C10, so that the time when the potential of the control end 11a' is further pulled down (which can be regarded as the time when the first output transistor T2 is completely opened) occurs near the falling edge of the second clock signal line XCK (delayed). It should be noted that the above-mentioned transition time required for switching the gate control signal from a high-level signal to a target low-level signal can be regarded as the time corresponding to the start of writing the low-level signal transmitted by the input signal line IN to the control end 11a' of the first output transistor T2 to the completion of further pulling down the potential of the control end 11a'. For example,Figure 2 As shown, in the current case, the length of the transition time is affected by the time interval Δt between the falling edge of the signal transmitted by the first clock signal line CK and the falling edge of the signal transmitted by the second clock signal line XCK. The larger the time interval Δt, the longer the transition time, and the greater the impact on the working state of the pixel circuit. However, the first clock signal line CK and the second clock signal line XCK usually also provide electrical signals for other circuits (such as pixel circuits), and the time interval Δt between the two clock signals must have a certain size. Therefore, the existing design is difficult to meet the demand of shortening the transition process of the gate control signal while maintaining the size of the above-mentioned time interval Δt, and usually the transition time is sacrificed to ensure the normal operation of the circuit.

[0027] Figure 3 A schematic diagram of a partial structure of a display panel provided by the present application is shown in Figure 4 A schematic diagram of a partial structure of a display panel provided by the present application is shown in Figure 3 An equivalent circuit diagram of a shift register in the display panel shown in Figure 5 An equivalent circuit diagram of a shift register in the display panel shown in Figure 3 An equivalent circuit diagram of a pixel circuit in the display panel shown in

[0028] To solve the above problems, the present application provides a display panel 10, which combines Figure 3 An equivalent circuit diagram of a shift register in the display panel shown in Figure 4 The display panel 10 includes a plurality of gate drive circuits 01, and each gate drive circuit 01 includes a plurality of cascaded shift registers 11. The output end 11a0 of the shift register 11 is electrically connected to the scan signal line 02. The scan signal output by the shift register 11 can be transmitted to the pixel circuit 03 through the scan signal line 02, and used to participate in the working process of the pixel circuit 03 to generate a light-emitting driving current. Specifically, in combination with Figure 3 An equivalent circuit diagram of a shift register in the display panel shown in Figure 5 The scan signal output by the shift register 11 can be transmitted to the control end of part of the transistors in the pixel circuit 03, so as to control the on-off state of the transistors. Therefore, the accuracy of the timing of the above-mentioned scan signal can affect the working state of the pixel circuit 03.

[0029] Specifically, as shown in Figure 5As shown, the pixel circuit 03 can include a driving transistor M0, a data writing transistor M1, a first light emitting control transistor M2, a second light emitting control transistor M3, a threshold value grabbing transistor M4, a first reset transistor M5, a second reset transistor M6, and a storage capacitor C11. In addition, the pixel circuit 03 can also be electrically connected to a power voltage signal line VDD, a data line Data, a first reset line Vref1, a second reset line Vref2, and the like. The control end of part of the transistors in the pixel circuit 03 can also be electrically connected to part of the scan lines 02 (including a first scan line 021, a second scan line 022, a third scan line 023, a fourth scan line 024, and a fifth scan line 025). It can be clearly seen that the scan signal output by the shift register 11 can be used to control the on-off state of part of the transistors in the pixel circuit 03, thereby affecting the light emitting driving current generated by the pixel circuit 03. Therefore, the timing accuracy of the scan signal output by the shift register 11 is related to whether the light emitting state of the light emitting device is good or not. The connection relationship between the above-mentioned signal lines and the transistors in the pixel circuit 03 will be described in detail below. Figure 5 Here, no longer be described.

[0030] As shown in Figure 4 , the shift register 11 includes a first output unit 111 and a second output unit 112. The first end of the first output unit 111 is electrically connected to the first signal line 04, and the first end of the second output unit 112 is electrically connected to the second signal line 05. The second end of the first output unit 111 and the second end of the second output unit 112 are both electrically connected to the scan signal line 02. The first output unit 111 and the second output unit 112 can be opened in time difference, that is, when the first output unit 111 is opened, the second output unit 112 is closed, and when the first output unit 111 is closed, the second output unit 112 is opened. Therefore, the electrical signals transmitted by the first signal line 04 and the second signal line 05 are transmitted to the output end 11a0 in time difference.

[0031] Figure 6 For the timing diagram of the potential at part of the positions in the shift register and the electrical signals transmitted by part of the signal lines, for the convenience of understanding, Figure 6 , the timing changes of the electrical signals transmitted by the first signal line, the second signal line, the input signal line, the first clock signal line, the second clock signal line, the first voltage adjustment signal line, and the like are shown. In addition, the potential changes at the output end of the shift register and the control end of the first output unit are also shown.

[0032] As shown in Figure 6As shown, the signal level transmitted by the first signal line 04 is lower than the signal level transmitted by the second signal line 05. The first signal line 04 can transmit a low-level signal, and the second signal line 05 can transmit a high-level signal. Therefore, during the output of the scan signal from the shift register 11, the scan signal can switch between high and low levels. The time required for the scan signal to switch between high and low levels can affect the timing of the switching on and off of the transistors in the pixel circuit 03 controlled by the scan signal (this can refer to the characteristic of measuring whether the transistors turn on or off in a timely manner).

[0033] like Figure 4 As shown, the shift register 11 also includes a first control unit 113 and a second control unit 114.

[0034] The first control unit 113 includes an adjusting capacitor C1, a first adjusting transistor T31, a first transmission transistor T32, and a first input transistor T33. The first terminal of the first input transistor T33 is electrically connected to the input signal line O61, and the second terminal of the first input transistor T33 is electrically connected to the first terminal of the first transmission transistor T32. The second terminal of the first transmission transistor T32 is electrically connected to the first plate of the adjusting capacitor C1, the control terminal of the first adjusting transistor T31, and the control terminal 110 of the first output unit 111 (the control terminal of the first output transistor T11). The second terminal of the first adjusting transistor T31 is electrically connected to the second plate of the adjusting capacitor C1. In this case, the electrical signal output by the first adjusting transistor T31 can cooperate with the electrical signal transmitted through the input signal line O61, and combined with the self-derating characteristic of the adjusting capacitor C1, the potential of the control terminal of the first output transistor T11 can be further lowered.

[0035] The output terminal of the second control unit 114 is electrically connected to the control terminal of the second output unit 112 (the control terminal of the second output transistor T21).

[0036] like Figure 3 As shown, the plurality of gate driving circuits 01 includes a first gate driving circuit 101. The shift register 11 in the first gate driving circuit 101 is a first type register 11a, and the i-th level first type register 11a is a first register 11a1, where i ≥ 1 and i is an integer. When i > 1, the i-th level first type register 11a can receive the scan signal output by the (i-1)-th level first type register 11a through the input signal line 061; that is, the scan signal can be regarded as the input signal received by the i-th level first type register 11a.

[0037] The control end of the first input transistor T33 is electrically connected to the first clock signal line 062, and part of the transistors in the second control unit 114 are electrically connected to the second clock signal line 063. Specifically, the second clock signal line 063 can be electrically connected to the second adjusting transistor T41 and the third transistor T42 in the second control unit 114, and the detailed connection mode can be referred to Figure 4

[0038] The first end of the first adjusting transistor T31 is electrically connected to the first voltage regulating signal line 091, and at this time, the voltage regulating signal transmitted by the first voltage regulating signal line 091 can cooperate with the input signal written to the control end 110 by the input signal line 061 to realize the self-falling effect of the adjusting capacitor C1.

[0039] As Figure 6 indicated, the enabling switching time of the signal transmitted by the first clock signal line 062 is the first time t1, the enabling switching time of the signal transmitted by the second clock signal line 063 is the second time t2, and the enabling switching time of the signal transmitted by the first voltage regulating signal line 091 is the third time t3. The enabling switching time is the time when the electrical signal starts to switch from the non-enabling signal to the enabling signal. It should be noted that in this application, the case of "low level as enabling signal and high level as non-enabling signal" is taken as an example to explain the scheme of this application, but it does not mean that the scheme of this application is limited to the example. That is, the scheme of this application can also include the case of "high level as enabling signal and low level as non-enabling signal" (at this time, the corresponding structure in the shift register 11 can be adaptively adjusted according to the logic of the scheme of this application).

[0040] In the first stage t01, the first time t1 is earlier than the second time t2 and the third time t3, and the time interval Δta between the first time t1 and the third time t3 is less than the time interval Δtb between the first time t1 and the second time t2.

[0041] ​In the embodiment of the present application, by introducing the first voltage regulating signal line 091, the voltage regulating signal transmitted thereby can be used in cooperation with the input signal transmitted by the input signal line 061, in combination with the self-discharging effect of the adjusting capacitor C1, to further lower the potential of the control end 110 of the first output unit 111, so as to facilitate the target low level of the gate control signal after the high-low level switching. In addition, the timing design of the present application realizes that Δta is less than Δtb, which means that, compared with the existing design which uses the clock signals transmitted by the two clock signal lines for self-discharging adjustment of the capacitor, the design of the present application which uses the voltage regulating signal in cooperation with the input signal can reduce or even eliminate the time interval between the falling edges of the two cooperating signals (the signals written to the two poles of the adjusting capacitor C1), thereby helping to reduce the jump time of the gate control signal, so as to realize the timely switching of the potential of the gate control signal, further improve the working state of the pixel circuit 03, and maintain good display effect.

[0042] In combination with Figure 4 and Figure 5 , multiple shift registers 11 can include multiple types, and different types of shift registers 11 can respectively transmit different scanning signals to the multiple transistor control ends in the pixel circuit 03 through the multiple scanning signal lines shown in Figure 5 . Among them, the equivalent circuit structures respectively corresponding to the multiple types of shift registers 11 can all be as shown in Figure 4 .

[0043] In a possible implementation manner, the scanning signal line 02 to which the shift register 11 is electrically connected can be a first scanning line 021, and the circuit structure thereof can refer to Figure 4 . The shift register 11 can transmit scanning signals to the first light-emitting control transistor M2 and the second light-emitting control transistor M3 through the first scanning line 021.

[0044] In a possible implementation manner, the scanning signal line 02 to which the shift register 11 is electrically connected can be a second scanning line 022, and the circuit structure thereof can refer to Figure 4 . The shift register 11 can transmit scanning signals to the first reset transistor M5 through the second scanning line 022.

[0045] In a possible implementation manner, the scanning signal line 02 to which the shift register 11 is electrically connected can be a third scanning line 023, and the circuit structure thereof can refer to Figure 4 . The shift register 11 can transmit scanning signals to the threshold capture transistor M4 through the third scanning line 023.

[0046] Figure 7 Another timing diagram for the potential size of the partial position in the shift register and the electrical signal transmitted by the partial signal line is shown in FIG. 17 for ease of understanding.Figure 7 The timing changes of the electrical signals transmitted by the first signal line, the second signal line, the input signal line, the first clock signal line, the second clock signal line, the first voltage regulating signal line, and the potential changes at the structures such as the output end of the shift register and the control end of the first output unit are shown in the figure In an embodiment of the present application, as shown in Figure 7 The first time t1 coincides with the third time t3.

[0047] In the embodiment of the present application, the first voltage regulating signal line 091 can be a specific signal line added separately relative to the existing design and participating in regulating the potential of the control end 110 of the first output unit 111. The electrical signal transmitted by the specific signal line can be set individually according to the requirements of the shift register 11. Specifically, the signal timing of the specific signal line can be adjusted individually, that is, the timing position of the third time t3 is adjusted so that t1 coincides with t3, and the time difference between the enable switching time corresponding to the clock signal of the first clock signal line 062 and the enable switching time corresponding to the voltage regulating signal of the first voltage regulating signal line 091 is eliminated. This design can shorten or even eliminate the above-mentioned jump time as much as possible, without affecting the timing state of other clock signals, maintaining the normal working state of the pixel circuit 03, and improving the display effect.

[0048] In a possible implementation, the first voltage regulating signal line 091 can transmit a clock signal, and the first voltage regulating signal line 091 and the first clock signal line 062 can transmit the same electrical signal. This design means that the same electrical signal can be output to the shift register 11 through the first voltage regulating signal line 091 and the first clock signal line 062. This is beneficial to reducing the types of electrical signals needed to be provided on the premise of shortening or eliminating the above-mentioned jump time, and further saving the chip computing power.

[0049] In an embodiment of the present application, as shown in Figure 4 The first control unit 113 further includes a first transistor T34 and a second transistor T35. The control end of the first transistor T34 is electrically connected with the second end of the first input transistor T33, and the first end of the second transistor T35 is electrically connected with the first signal line 04.

[0050] The second control unit 114 further includes a second input transistor T43, a first capacitor C2, a second regulating transistor T41, and a third transistor T42. The first end of the second input transistor T43 is electrically connected to the second signal line 05, the second end of the first transistor T34, and the second end of the second transistor T35. The second end of the second input transistor T43 is electrically connected to the first plate of the first capacitor C2 and the control end of the second regulating transistor T41. The control end of the second input transistor T43 is electrically connected to the first signal line 04. The second end of the second regulating transistor T41 is electrically connected to the second plate of the first capacitor C1 and the first end of the third transistor T42. The second end of the third transistor T42 is electrically connected to the control end of the second output unit 112 (the control end of the second output transistor T21).

[0051] In addition, the second control unit 114 can further include a fourth transistor T44, a fifth transistor T45, and a second capacitor C3. The connection mode between the above structures is described in detail in Figure 4 , which will not be described here.

[0052] In the first register 11a1, the first end of the first transistor T34 and the control end of the second transistor T35 are both electrically connected to the first clock signal line 062. The first end of the second regulating transistor T41 is electrically connected to the second clock signal line 063. The control end of the third transistor T42 is electrically connected to the second clock signal line 063.

[0053] In the embodiment of the present application, the second clock signal line 063 only provides clock signals to part of the structures in the second control unit 114 in the first register 11a1. The clock signals transmitted by the second clock signal line 063 no longer serve to adjust the control end potential of the first output unit 111, so the problem of excessively long jump time caused by the timing difference between the two clock signals does not occur. In addition, in the design of the present embodiment, the high-level signal transmitted by the second signal line 05 is no longer used to participate in the adjustment process of the control end potential of the first output unit 111, thereby simplifying the wiring complexity.

[0054] Figure 8 A schematic diagram of part of a display panel provided in the present application.

[0055] In an embodiment of the present application, in combination with Figure 5 and Figure 8 , the display panel 10 further includes a pixel circuit 03, which includes a driving transistor M0, a first light-emitting control module d1 (including a first light-emitting control transistor M2), a second light-emitting control module d2 (including a second light-emitting control transistor M3), a threshold value capturing module d3 (including a threshold value capturing transistor M4), and a first reset module d4 (including a first reset transistor M5).

[0056] The second end of the first light-emitting control module d1 is electrically connected with the first end of the driving transistor M0, the second end of the driving transistor M0 is electrically connected with the first end of the second light-emitting control module d2 and the first end of the threshold value capturing module d3, the second end of the threshold value capturing module d3 is electrically connected with the control end of the driving transistor M0, and the second end of the first reset module d4 is electrically connected with the control end of the driving transistor M0.

[0057] The scanning signal line electrically connected with the control end of the first light-emitting control module d1 and the control end of the second light-emitting control module d2 is a light-emitting control line (which can be a first scanning line 021), and the scanning signal line electrically connected with the control end of the threshold value capturing module d3 is a first control line (which can be a third scanning line 023).

[0058] As shown in Figure 8 The shift register 11 in the second gate drive circuit 102 is a second type of register 11b, and the i-th stage of the second type of register 11b is a second register 11b1.

[0059] The output end of the first type of register 11a is electrically connected with the light-emitting control line (which can be the first scanning line 021), and the output end of the second type of register 11b is electrically connected with the first control line (which can be the third scanning line 023). The scanning signals respectively output by the first type of register 11a and the second type of register 11b can correspond to different scanning signal lines respectively and act on different transistors in the pixel circuit 03, so that it can be determined that the scanning signals respectively transmitted by the first type of register 11a and the second type of register 11b can be different.

[0060] Figure 9 For the equivalent circuit diagram corresponding to different shift registers, for the convenience of understanding, Figure 9 The equivalent circuit diagram corresponding to the first register and the second register is shown, and the connection relationship between the two register circuits and different clock signal lines is specifically shown.

[0061] As shown in Figure 9As shown, in the second register 11b1, the control end of the first input transistor T33 is electrically connected to the third clock signal line 064, part of the transistors in the second control unit 114 are electrically connected to the fourth clock signal line 065, and the first end of the first adjusting transistor T31 is electrically connected to the first clock signal line 062. That is, the first adjusting transistor T31 in the second register 11b1 can receive the clock signal of the first clock signal line 062 connected to the first register 11a1. It needs to be clear that since the first gate drive circuit 101 and the second gate drive circuit 102 are adjacent along the first direction X, based on the transmission rule of the clock signal in the display panel 10, the clock signal transmitted by the first clock signal line 062 and the clock signal transmitted by the third clock signal line 064 exhibit a small time interval (which can be called a first signal transmission time difference) in time sequence. At this time, the design of the present embodiment selects to adjust the control end potential of the first output unit 111 (in the second register 11b1) by the clock signal of the third clock signal line 064 and the clock signal of the first clock signal line 062. The above-mentioned feature that the first signal transmission time difference is small can be understood as the transition time of the scan signal output by the output end 11a0 of the second register 11b1 is also short.

[0062] Figure 10 The timing diagrams of the signals respectively transmitted by the plurality of signal lines connected to the second register are shown for the convenience of understanding, Figure 10 The timing changes of the signals respectively transmitted by the first clock signal line, the third clock signal line, and the fourth clock signal line are shown, and the timing changes of the electrical signals of the third scan line connected to the second register are also shown.

[0063] In combination with Figure 9 and Figure 10 , the enabling switching moment of the signal transmitted by the third clock signal 064 is the fourth moment t4, and the enabling switching moment of the signal transmitted by the fourth clock signal line 065 is the fifth moment t5.

[0064] Among them, in the first stage t01, the fourth moment t4 is earlier than the fifth moment t5 and the first moment t1, and the time interval Δtc between the fourth moment t4 and the first moment t1 is smaller than the time interval Δtd between the fourth moment t4 and the fifth moment t5.

[0065] In the embodiment of the present application, the timing design that Δtc is less than Δtd means that the design of cooperating the clock signals respectively transmitted by the third clock signal 064 and the first clock signal line 062 can reduce the time interval between the falling edges of the two cooperating signals (the signals respectively written to the two poles of the adjusting capacitor C1), thereby helping to reduce the transition time of the gate control signal, so as to realize that the potential of the gate control signal can be switched in time, further improve the working state of the pixel circuit 03, and maintain good display effect. In addition, in the embodiment, the clock signal transmitted by the first clock signal line 062 is used as one of the cooperating signals for adjusting the potential of the control end of the first output unit 111 in the second register 11b1, which reasonably utilizes the first signal transmission time difference between the clock signals respectively transmitted by the first clock signal 062 and the third clock signal 064, simplifies the wiring setting, shortens the transition time of the gate control signal of the second register 11b1, and does not need to additionally set a separate signal line to participate in the adjustment process of the control end potential of the first output unit 111, thereby saving cost.

[0066] Figure 11 A schematic diagram of a partial structure of a display panel is provided in the present application.

[0067] In one embodiment of the present application, as shown in Figure 5 , the scan signal line electrically connected to the control end of the first reset module d4 is the second control line (which can be the second scan line 022).

[0068] As shown in Figure 11 , the plurality of gate drive circuits 01 further includes a third gate drive circuit 103. Along the first direction X, the third gate drive circuit 103 is adjacent to the second gate drive circuit 102, and the second gate drive circuit 102 is located between the first gate drive circuit 101 and the third gate drive circuit 103; the shift register 11 in the third gate drive circuit 103 is a third type of register 11c, and the i-th third type of register 11c is a third register 11c1; the output end of the third type of register 11c is electrically connected to the second control line (which can be the second scan line 022).

[0069] The scan signals respectively output by the first type of register 11a, the second type of register 11b and the third type of register 11c can correspond to different scan signal lines respectively, and act on different transistors in the pixel circuit 03 respectively, so that it can be determined that the scan signals respectively transmitted by the first type of register 11a, the second type of register 11b and the third type of register 11c can be different.

[0070] Figure 12 For the equivalent circuit diagram corresponding to different shift registers, for the convenience of understanding, Figure 12The first register, the second register and the third register respectively correspond to the equivalent circuit schematic situation, and the connection relationship between the three register circuits and different clock signal lines is specifically shown.

[0071] As shown in Figure 12 , in the third register 11c1, the control end of the first input transistor T33 is electrically connected to the fifth clock signal line 066, part of the transistors in the second control unit 114 are electrically connected to the sixth clock signal line 067, and the first end of the first adjusting transistor T31 is electrically connected to the third clock signal line 064. That is, the first adjusting transistor T31 in the third register 11c1 can receive the clock signal connected to the third clock signal line 064 of the second register 11b1. It should be noted that since the second gate drive circuit 102 and the third gate drive circuit 103 are arranged adjacent along the first direction X, based on the transmission rule of the clock signal in the display panel 10, the clock signal transmitted by the third clock signal line 064 and the clock signal transmitted by the fifth clock signal line 066 have a small time interval (which can be called a second signal transmission time difference) in time sequence. At this time, the design of the present embodiment selects to adjust the control end potential of the first output unit 111 (in the third register 11c1) by using the clock signal of the third clock signal line 064 and the clock signal of the fifth clock signal line 066. The above-mentioned second signal transmission time difference is small, which can be understood as the transition time of the scan signal output by the output end 11a0 of the third register 11c1 is also short.

[0072] Figure 13 The time sequence diagram of the signals respectively transmitted by the plurality of signal lines connected to the third register is shown in Figure 13 , which shows the time sequence change of the signals respectively transmitted by the third clock signal line, the fifth clock signal line and the sixth clock signal line, and also shows the time sequence change of the electrical signal of the second scan line connected to the third register.

[0073] As shown in Figure 13 , the enable switching time of the signal transmitted by the fifth clock signal line 066 is the sixth time t6, and the enable switching time of the signal transmitted by the sixth clock signal line 067 is the seventh time t7.

[0074] Among them, in the first stage t01, the sixth time t6 is earlier than the seventh time t7 and the fourth time t4, and the time interval Δte between the sixth time t6 and the fourth time t4 is less than the time interval Δtf between the sixth time t6 and the seventh time t7.

[0075] In the embodiment of the present application, the timing design that Δte is less than Δtf means that the design of cooperating the clock signals respectively transmitted by the third clock signal line 064 and the fifth clock signal line 066 can reduce the time interval between the falling edges of the two cooperating signals (the signals respectively written to the two poles of the adjusting capacitor C1), thereby helping to reduce the transition time of the gate control signal, so as to realize that the potential of the gate control signal can be switched in time, further improve the working state of the pixel circuit 03, and maintain good display effect. In addition, in the embodiment, the clock signal transmitted by the third clock signal line 064 is used as one of the cooperating signals for adjusting the potential of the control end of the first output unit 111 in the third register 11c1, and the second signal transmission time difference between the clock signals respectively transmitted by the fifth clock signal line 066 and the third clock signal line 064 is reasonably utilized, which simplifies the wiring setting while shortening the transition time of the gate control signal of the third register 11c1, without the need to additionally set a separate signal line to participate in the adjustment process of the potential of the control end of the first output unit 111, thereby saving cost.

[0076] In an embodiment of the present application, in the first stage t01, the time interval between the sixth time t6 and the fourth time t4 is Δte, and the time interval between the fourth time t4 and the first time t1 is Δtc.

[0077] 0≤Δte≤5us, 0≤Δtc≤5us.

[0078] In the embodiment of the present application, the clock signals respectively transmitted by the third clock signal line 064 and the first clock signal line 062 are cooperated to adjust the potential of the control end of the first output unit 111 in the second register 11b1, and the design that the time interval Δtc satisfies “0≤Δtc≤5us” is beneficial to reduce the transition time of the gate control signal output by the second register 11b1. The clock signals respectively transmitted by the third clock signal line 064 and the fifth clock signal line 066 are cooperated to adjust the potential of the control end of the first output unit 111 in the third register 11c1, and the design that the time interval Δte satisfies “0≤Δte≤5us” is beneficial to reduce the transition time of the gate control signal output by the third register 11c1.

[0079] In an embodiment of the present application, Δte≥Δtc.

[0080] In the embodiment of the present application, Δte=Δtc, so the time interval between the enabling switching time of the third clock signal line 064 and the first clock signal line 062 is equal to the time interval between the enabling switching time of the third clock signal 064 and the fifth clock signal line 066, which facilitates timing design. It should be noted that since the scan signal output by the third register 11c1 is used to control the opening and closing of the first reset module d4, and the scan signal output by the second register 11b1 is used to control the opening and closing of the threshold capture module d3, the enabling switching time of the signal transmitted by the second scan line 022 can be approximately regarded as the opening time of the first reset module d4 (at this moment, the control terminal of the driving transistor M0 starts to be reset), and the enabling switching time of the signal transmitted by the third scan line 023 can be approximately regarded as the opening time of the threshold capture module d3 (at this moment, the control terminal of the driving transistor M0 starts to be written or other). The above Δte>Δtc can be regarded as the period Δte between the opening of the first reset module d4 and the opening of the threshold capture module d3 being longer, and this period Δte can be regarded as the corresponding length of the reset phase. Considering that the reset phase is a necessary phase, the design of larger Δte can be understood as the guarantee of the reset effect.

[0081] Figure 14 The equivalent circuit diagram corresponding to the second register and the fourth register.

[0082] In one embodiment of the present application, as shown in Figure 8 , the i+1 level second type register 11b is the fourth register 11b2.

[0083] In combination with Figure 8 and Figure 14 , in the fourth register 11b2, the control terminal of the first input transistor T33 is electrically connected to the fourth clock signal line 065, part of the transistors in the second control unit 114 are electrically connected to the third clock signal line 064, and the first end of the first adjusting transistor T31 is electrically connected to the second clock signal line 063.

[0084] In this embodiment, the second register 11b1 and the fourth register 11b2 are adjacent cascaded registers. The control terminal of the first input transistor T33 in the fourth register 11b2 is electrically connected to a portion of the transistors in the second control unit 114 in the second register 11b1 via the same clock signal line. Similarly, a portion of the transistors in the second control unit 114 in the fourth register 11b2 are electrically connected to the control terminal of the first input transistor T33 in the second register 11b1 via the same clock signal line. This design conforms to the connection rules of cascaded bit registers 11 and clock signal lines, facilitating wiring. Furthermore, the clock signal lines connected to the first adjustment transistor T31 in both the second register 11b1 and the fourth register 11b2 also provide clock signals to other register circuits. This can be understood as both register circuits being externally connected to the clock signal lines corresponding to other registers to adjust the potential of the control terminal of the first output unit 111. Based on this, this embodiment is designed so that the clock signal lines externally connected to the second register 11b1 and the fourth register 11b2 also satisfy the connection rules of cascaded bit registers 11 and clock signal lines, which helps reduce wiring difficulty and saves manufacturing costs.

[0085] Figure 15 The equivalent circuit diagram for the fifth register is shown below. Figure 16 This is a timing diagram showing the magnitude of the position potentials within the fifth register and the electrical signals transmitted on some signal lines. For ease of understanding, Figure 16 The diagram shows the timing changes of the signals transmitted by the second clock signal line, the first clock signal line, the second voltage regulation signal line, etc., as well as the potential changes at the output terminal of the fifth register, the control terminal of the first output unit, and other structures.

[0086] In one embodiment of this application, combined with Figure 8 and Figure 15 The first type register 11a of the (i+1)th level is the fifth register 11a2.

[0087] In the fifth register 11a2, the control terminal of the first input transistor T33 is electrically connected to the second clock signal line 063, some transistors in the second control unit 114 are electrically connected to the first clock signal line 062, the first terminal of the first regulating transistor T31 is electrically connected to the second voltage regulating signal line 092, and the enable switching time of the signal transmitted by the second voltage regulating signal line 092 is the eighth time t8.

[0088] like Figure 16 As shown, in the second stage t02, the second time t2 is earlier than the first time t1 and the eighth time t8, and the time interval Δtg between the second time t2 and the eighth time t8 is less than the time interval Δth between the second time t2 and the first time t1.

[0089] In this embodiment, by introducing a second voltage regulation signal line 092, the voltage regulation signal transmitted by it can be coordinated with the input signal transmitted by the input signal line 061. Combined with the self-dropout effect of the regulating capacitor C1, the potential of the control terminal 110 of the first output unit 111 is further pulled down, so as to promote the gate control signal output by the fifth register 11a2 to reach the target low level after the high-low level switching. In addition, the design of Δtg < Δth means that compared with the scheme of using the signals transmitted by the first clock signal line 062 and the second clock signal line 063 as two coordinating signals, the scheme of using the signals transmitted by the second voltage regulation signal line 092 and the second clock signal line 063 as two coordinating signals in this embodiment is more advantageous. This scheme has a better reduction in the transition time corresponding to the gate control signal of the fifth register 11a2, which is conducive to further improving the working state of the pixel circuit 03 and maintaining a good display effect. It should be noted that, unlike the first voltage regulation signal line 091, the second voltage regulation signal line 092 can be another separately configured signal line. The signal transmitted by the second voltage regulation signal line 092 can be different from the signal transmitted by the first voltage regulation signal line 091 (this difference can be manifested as a difference in signal timing). In this design, the voltage regulation signal lines connected to the adjacent cascaded first register 11a1 and fifth register 11a2 can be different, which conforms to the line connection rules between cascaded shift registers and facilitates wiring.

[0090] Figure 17 This is a schematic diagram of a display device provided in this application.

[0091] This application provides a display device 20, such as... Figure 17 As shown, the display device 20 includes the display panel 10 provided in the above embodiments. The display device 20 can be a mobile phone, or it can be an electronic device such as a computer or television.

[0092] The pixel circuit 03 in the display device 20 provided in this application embodiment can output a preset size of light-emitting driving current in a relatively timely manner, and the display effect of each area in the display device 20 is significantly improved.

[0093] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A display panel, characterized in that, It includes multiple gate driving circuits; the gate driving circuit includes multiple cascaded shift registers, and the output of the shift registers is electrically connected to the scan signal line; The shift register includes a first output unit and a second output unit; a first terminal of the first output unit is electrically connected to a first signal line, a first terminal of the second output unit is electrically connected to a second signal line, and the second terminals of both the first and second output units are electrically connected to the scan signal line; the level of the signal transmitted by the first signal line is lower than the level of the signal transmitted by the second signal line. The shift register further includes a first control unit and a second control unit; The first control unit includes an adjustment capacitor, a first adjustment transistor, a first transmission transistor, and a first input transistor; The first terminal of the first input transistor is electrically connected to the input signal line, and the second terminal of the first input transistor is electrically connected to the first terminal of the first transmission transistor; the second terminal of the first transmission transistor is electrically connected to the first plate of the regulating capacitor, the control terminal of the first regulating transistor, and the control terminal of the first output unit, and the control terminal of the first transmission transistor is electrically connected to the first signal line; the second terminal of the first regulating transistor is electrically connected to the second plate of the regulating capacitor. The output terminal of the second control unit is electrically connected to the control terminal of the second output unit; The plurality of gate driving circuits includes a first gate driving circuit, wherein the shift register in the first gate driving circuit is a first type of register, and the i-th level of the first type of register is a first register; i ≥ 1 and i is an integer; In the first register, the control terminal of the first input transistor is electrically connected to the first clock signal line, some transistors in the second control unit are electrically connected to the second clock signal line, and the first terminal of the first regulating transistor is electrically connected to the first voltage regulation signal line. The enable switching time of the signal transmitted by the first clock signal line is the first moment, the enable switching time of the signal transmitted by the second clock signal line is the second moment, and the enable switching time of the signal transmitted by the first voltage regulation signal line is the third moment; the enable switching time is the moment when the electrical signal begins to switch from a non-enable signal to an enable signal. In the first stage, the first moment is earlier than the second moment and the third moment, and the time interval between the first moment and the third moment is less than the time interval between the first moment and the second moment.

2. The display panel according to claim 1, characterized in that, The first time point coincides with the third time point.

3. The display panel according to claim 1, characterized in that, The first control unit further includes a first transistor and a second transistor; the control terminal of the first transistor is electrically connected to the second terminal of the first input transistor; the first terminal of the second transistor is electrically connected to the first signal line. The second control unit further includes a second input transistor, a first capacitor, a second regulating transistor, and a third transistor; the first terminal of the second input transistor is electrically connected to the second signal line, the second terminal of the first transistor, and the second terminal of the second transistor; the second terminal of the second input transistor is electrically connected to the first plate of the first capacitor and the control terminal of the second regulating transistor; the control terminal of the second input transistor is electrically connected to the first signal line; the second terminal of the second regulating transistor is electrically connected to the second plate of the first capacitor and the first terminal of the third transistor; the second terminal of the third transistor is electrically connected to the control terminal of the second output unit. In the first register, the first terminal of the first transistor and the control terminal of the second transistor are both electrically connected to the first clock signal line; the first terminal of the second regulating transistor is electrically connected to the second clock signal line; and the control terminal of the third transistor is electrically connected to the second clock signal line.

4. The display panel according to claim 1, characterized in that, The display panel further includes a pixel circuit, which includes a driving transistor, a first light-emitting control module, a second light-emitting control module, a threshold capture module, and a first reset module. The second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving transistor. The second terminal of the driving transistor is electrically connected to the first terminal of the second light-emitting control module and the first terminal of the threshold grasping module. The second terminal of the threshold grasping module is electrically connected to the control terminal of the driving transistor. The second terminal of the first reset module is electrically connected to the control terminal of the driving transistor. The scanning signal line electrically connected to the control terminal of the first light-emitting control module and the control terminal of the second light-emitting control module is the light-emitting control line, and the scanning signal line electrically connected to the control terminal of the threshold grasping module is the first control line; The plurality of gate driving circuits further includes a second gate driving circuit, which is adjacent to the first gate driving circuit along the first direction; the shift register in the second gate driving circuit is a second type register, and the i-th stage of the second type register is a second register; the output terminal of the first type register is electrically connected to the light emission control line, and the output terminal of the second type register is electrically connected to the first control line; In the second register, the control terminal of the first input transistor is electrically connected to the third clock signal line, some transistors in the second control unit are electrically connected to the fourth clock signal line, and the first terminal of the first regulating transistor is electrically connected to the first clock signal line. The enable switching time of the signal transmitted by the third clock signal line is the fourth time, and the enable switching time of the signal transmitted by the fourth clock signal line is the fifth time. In the first stage, the fourth moment is earlier than the fifth moment and the first moment, and the time interval between the fourth moment and the first moment is less than the time interval between the fourth moment and the fifth moment.

5. The display panel according to claim 4, characterized in that, The scan signal line electrically connected to the control terminal of the first reset module is the second control line; The plurality of gate driving circuits further includes a third gate driving circuit. Along the first direction, the third gate driving circuit is adjacent to the second gate driving circuit, and the second gate driving circuit is located between the first gate driving circuit and the third gate driving circuit. The shift register in the third gate driving circuit is a third type register, and the i-th stage of the third type register is a third register. The output terminal of the third type register is electrically connected to the second control line. In the third register, the control terminal of the first input transistor is electrically connected to the fifth clock signal line, some transistors in the second control unit are electrically connected to the sixth clock signal line, and the first terminal of the first regulating transistor is electrically connected to the third clock signal line. The enable switching time of the signal transmitted by the fifth clock signal line is the sixth time, and the enable switching time of the signal transmitted by the sixth clock signal line is the seventh time. In the first stage, the sixth time point is earlier than the seventh time point and the fourth time point, and the time interval between the sixth time point and the fourth time point is less than the time interval between the sixth time point and the seventh time point.

6. The display panel according to claim 5, characterized in that, Within the first stage, the time interval between the sixth time and the fourth time is Δte, and the time interval between the fourth time and the first time is Δtc. Where 0≤Δte≤5us, 0≤Δtc≤5us.

7. The display panel according to claim 6, characterized in that, Δte≥Δtc.

8. The display panel according to claim 4, characterized in that, The second type of register at level i+1 is the fourth register; In the fourth register, the control terminal of the first input transistor is electrically connected to the fourth clock signal line, some transistors in the second control unit are electrically connected to the third clock signal line, and the first terminal of the first regulating transistor is electrically connected to the second clock signal line.

9. The display panel according to claim 1, characterized in that, The first type of register in the (i+1)th level is the fifth register; In the fifth register, the control terminal of the first input transistor is electrically connected to the second clock signal line, some transistors in the second control unit are electrically connected to the first clock signal line, the first terminal of the first regulating transistor is electrically connected to the second voltage regulating signal line, and the enable switching time of the signal transmitted by the second voltage regulating signal line is the eighth time. During the second phase, the second moment is earlier than the first moment and the eighth moment, and the time interval between the second moment and the eighth moment is less than the time interval between the second moment and the first moment.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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