Chip packaging structure and preparation method of chip packaging structure
By filling the non-wired area of the substrate with a reinforcing ring and combining it with a heat dissipation cap, the warping problem of large-size chip packaging structure was solved, improving the overall yield and heat dissipation efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-27
AI Technical Summary
Large-size chip packaging structures may experience defects due to warping during the manufacturing process, affecting the overall yield.
A groove is made in the non-trace area of the substrate and filled with a first reinforcing ring. A second reinforcing ring or a heat sink is connected to the first reinforcing ring to enhance the rigidity of the substrate structure and reduce warping.
It effectively reduces warpage, minimizes defects, and improves the overall yield and heat dissipation efficiency of chip packaging structures.
Smart Images
Figure CN121752082A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a chip packaging structure and a method for preparing the chip packaging structure. Background Technology
[0002] Currently, during the fabrication of large-size chip packaging structures, the inherent warpage problem is significant due to the large size of their internal structures (e.g., the substrate). Subsequent fabrication processes on this substrate (e.g., flip-chip bonding or component placement) can lead to various defects due to warpage, thus affecting the overall yield of the chip packaging structure. Therefore, effectively reducing the warpage phenomenon in large-size chip packaging structures during fabrication has become a pressing technical problem for those skilled in the art. Summary of the Invention
[0003] To overcome the technical problems mentioned in the background, this application provides a chip packaging structure, which includes: A substrate, the substrate including a trace area and a non-trace area surrounding the trace area, the substrate including a first side and a second side opposite to each other, on the first side, the non-trace area of the substrate having a groove surrounding the trace area; A first reinforcing part, the first reinforcing part including a first reinforcing ring, the first reinforcing ring filling the groove; At least one chip is disposed on a first side of the wiring area, and the pins of the chip are connected to the wiring in the substrate; The second reinforcement part is disposed on the first side of the substrate and is connected to the first reinforcement part. The second reinforcement part includes a second reinforcement ring or a heat dissipation cover.
[0004] In one possible implementation, when the second reinforcement part is the second reinforcement ring, the second reinforcement ring is disposed on the first side of the non-wiring area, and one side of the second reinforcement ring is connected to the first reinforcement ring. When the second reinforcement is the heat dissipation cover, the heat dissipation cover covers the first side of the trace area and at least part of the non-trace area. The heat dissipation cover is connected to the first reinforcement ring, wherein the orthographic projection of the chip and the first reinforcement ring on the substrate is located within the orthographic projection of the heat dissipation cover on the substrate.
[0005] In one possible implementation, the heat dissipation cover includes a heat dissipation top plate and a heat dissipation side plate extending along the heat dissipation top plate toward the substrate, wherein the side of the heat dissipation side plate away from the heat dissipation top plate is connected to the first reinforcing ring.
[0006] In one possible implementation, the groove includes a groove bottom, and the chip packaging structure further includes a first adhesive layer disposed between the groove bottom and the first reinforcing ring; When the second reinforcing part is the second reinforcing ring, the chip packaging structure further includes a second adhesive layer, which is disposed between the first reinforcing ring and the second reinforcing ring; When the second reinforcement part is the heat dissipation cover, the chip packaging structure further includes a third adhesive layer and a fourth adhesive layer. The chip includes a back side opposite to the pins. The third adhesive layer is disposed between the inner side of the heat dissipation top plate and the back side of the chip. The fourth adhesive layer is disposed between the side of the heat dissipation side plate away from the heat dissipation top plate and the first reinforcement ring.
[0007] In one possible implementation, the orthographic projection shape of the first reinforcing ring on the substrate includes a rectangle, and the orthographic projection shape of the second reinforcing ring on the substrate also includes a rectangle. The orthographic projection shape of the heat sink on the substrate includes a rectangle.
[0008] In one possible implementation, the materials of the first reinforcing ring, the second reinforcing ring, and the heat dissipation cover include thermally conductive materials.
[0009] In one possible implementation, the chip package structure further includes components disposed on a first side of the wiring area of the substrate, and the components are connected to the wiring in the substrate. The number of the components is multiple, and the multiple components are disposed on both sides of the chip.
[0010] Another objective of this application is to provide a method for fabricating a chip packaging structure, the method comprising: A substrate is provided, wherein the substrate includes a trace area and a non-trace area surrounding the trace area, and the substrate includes opposing first and second sides; A groove is formed around the wiring area on the first side of the non-wiring area; A first reinforcing portion is filled into the groove, wherein the first reinforcing portion includes a first reinforcing ring; At least one chip is disposed on the first side of the wiring area, wherein the pins of the chip are connected to the wiring in the substrate; A second reinforcing part is disposed on the first side of the substrate and connected to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover.
[0011] In one possible implementation, when the second reinforcing part is the second reinforcing ring, the step of disposing the second reinforcing part on the first side of the substrate and connecting the second reinforcing part to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover, includes: The second reinforcing ring is placed on the first side of the non-trace area, and one side of the second reinforcing ring is connected to the first reinforcing ring.
[0012] In one possible implementation, when the second reinforcing part is the heat dissipation cover, the step of disposing the second reinforcing part on the first side of the substrate and connecting the second reinforcing part to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover, includes: The heat sink covers the first side of the trace area and at least part of the non-trace area, and connects the heat sink to the first reinforcing ring, wherein the orthographic projection of the chip and the first reinforcing ring on the substrate is located within the orthographic projection of the heat sink on the substrate.
[0013] Based on any of the above aspects, embodiments of this application provide a chip packaging structure and a method for fabricating the chip packaging structure. The chip packaging structure includes a substrate, a first reinforcing portion, at least one chip, and a second reinforcing portion. The substrate includes a wiring area and a non-wiring area, and includes a first side and a second side opposite to each other. On the first side, a groove surrounding the wiring area is formed in the non-wiring area. The first reinforcing portion includes a first reinforcing ring, which fills the groove. The chip is disposed on the first side of the wiring area, and the chip's pins are connected to the wiring in the substrate. The second reinforcing portion is disposed on the first side of the substrate and connected to the first reinforcing portion. The second reinforcing portion includes a second reinforcing ring or a heat sink. The first reinforcing portion in the above structure can reduce the warping phenomenon during the fabrication process, thereby reducing the occurrence of defects. Furthermore, the combination of the first reinforcing portion and the second reinforcing portion can further control the overall warping phenomenon of the chip packaging structure, ensuring the overall yield of the chip packaging structure. Attached Figure Description
[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 This is one of the schematic diagrams of a chip packaging structure provided in this embodiment; Figure 2This is a second schematic diagram of a chip packaging structure provided in this embodiment; Figure 3 This is a schematic diagram of the steps involved in fabricating a chip packaging structure according to this embodiment; Figure 4 for Figure 3 One of the corresponding process flow diagrams; Figure 5 for Figure 3 The second corresponding manufacturing process diagram.
[0016] Icons: Chip package structure-1; Substrate-10; First reinforcement-11; First reinforcement ring-110; Chip-12; Pin-120; Back side-121; Second reinforcement-13; Second reinforcement ring-130; Heat sink cover-131; Heat sink top plate-1310; Heat sink side plate-1311; First adhesive layer-14; Second adhesive layer-15; Third adhesive layer-16; Fourth adhesive layer-17; Components-18; Groove-100; Groove bottom-101. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0018] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0020] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0021] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.
[0022] In order to solve the technical problems mentioned in the background art, the inventors have innovatively designed the following technical solutions, and the specific implementation scheme of this application will be described in detail below with reference to the accompanying drawings.
[0023] Please see Figure 1 and Figure 2 , Figure 1 This is one of the schematic diagrams of a chip packaging structure 1 provided in this embodiment. Figure 2 This is a second schematic diagram of a chip packaging structure 1 provided in this embodiment. The chip packaging structure 1 includes a substrate 10, a first reinforcing portion 11, at least one chip 12, and a second reinforcing portion 13. The substrate 10 includes a wiring area AA1 and a non-wiring area AA2 surrounding the wiring area AA1. The substrate 10 includes a first side and a second side opposite to each other. On the first side, the non-wiring area AA2 of the substrate 10 has a groove 100 surrounding the wiring area AA1. The chip 12 is disposed on the first side of the wiring area AA1, and the pins 120 of the chip 12 are connected to the wiring in the substrate 10. The first reinforcing portion 11 includes a first reinforcing ring 110, which fills the groove 100.
[0024] In this embodiment, the large-size chip package structure typically includes a large-size substrate 10, which provides mechanical support and electrical interconnection for the entire chip package structure 1. The substrate 10 at the wiring area AA1 has a precision circuit structure, and internal devices such as the chip 12 or components 18 are all located on the substrate 10 at the wiring area AA1 and connected to the wiring within the substrate 10. The non-wiring area AA2 located outside the wiring area AA1 is the outermost ineffective area, and creating a groove 100 there will not affect the electrical function of the chip package structure 1. In addition, if the top view of the substrate 10 at the wiring area AA1 is rectangular, then the top view of the substrate 10 at the non-wiring area AA2 is also rectangular, and the groove 100 is a rectangular groove. The size of the first reinforcing ring 110 filled in the groove 100 must match the size of the groove 100 to ensure that the first reinforcing ring 110 is flush with the surface of the substrate 10. The first reinforcing ring 110 can be prefabricated or directly fabricated within the groove 100. When the first reinforcing ring 110 is pre-made, the pre-made first reinforcing ring 110 with matching dimensions is simply embedded and filled into the groove 100.
[0025] It is worth noting that the depth of the groove 100 is not specifically limited here and can be set according to the actual situation.
[0026] In the above-described scheme, due to the excessive size of the large-size substrate 10, subsequent fabrication processes (such as flip-chip 12 or component 18) on the substrate 10 may lead to various defects due to warping. For example, this may result in poor mounting of the chip 12 or component 18 to the substrate 10 or poor bottom filling of the chip 12. In this embodiment, the subsequent fabrication processes of the chip packaging structure 1 are performed based on the first reinforcing part 11. Thus, the first reinforcing part 11 (i.e., the first reinforcing ring 110) significantly enhances the overall structural rigidity of the substrate 10, reduces warping during the fabrication of the chip packaging structure 1, thereby reducing the occurrence of defects and ensuring the overall yield of the chip packaging structure 1.
[0027] In this embodiment, the second reinforcing part 13 is disposed on the first side of the substrate 10, and the second reinforcing part 13 is connected to the first reinforcing part 11. The second reinforcing part 13 includes a second reinforcing ring 130 or a heat dissipation cover 131. Thus, the combination of the first reinforcing part 11 and the second reinforcing part 13 can reduce the overall warping phenomenon of the chip packaging structure 1, further ensure the overall yield of the chip packaging structure 1, and ensure the reliability of subsequent processes.
[0028] Furthermore, the second reinforcement part 13 of this embodiment includes two implementations. For one implementation of this embodiment, please refer to... Figure 1 When the second reinforcing part 13 is a second reinforcing ring 130, the second reinforcing ring 130 is disposed on the first side of the non-trace area AA2, and one side of the second reinforcing ring 130 is connected to the first reinforcing ring 110. In this embodiment, the second reinforcing ring 130 is vertically stacked on the first reinforcing ring 110. The second reinforcing ring 130 and the first reinforcing ring 110 can have the same size. In this way, the combination of the first reinforcing ring 110 and the second reinforcing ring 130 can further control the overall warpage of the chip package structure 1, thereby ensuring the overall yield of the chip package structure 1 and ensuring the reliability of subsequent processes. Furthermore, when the materials of the first reinforcing ring 110 and the second reinforcing ring 130 are thermally conductive materials (e.g., metal materials), the metal ratio of the chip package structure 1 is increased, thereby improving heat dissipation efficiency.
[0029] In another embodiment of this example, please refer to Figure 2The second reinforcement 13 is a heat dissipation cover 131, which covers the first side of the wiring area AA1 and at least part of the non-wiring area AA2. The heat dissipation cover 131 is connected to the first reinforcement ring 110, wherein the orthographic projection of the chip 12 and the first reinforcement ring 110 on the substrate 10 lies within the orthographic projection of the heat dissipation cover 131 on the substrate 10. In this embodiment, the heat dissipation cover 131 covers all devices on the first side of the wiring area AA1, forming a "rigid cover" on the first side of the substrate 10. Thus, the combination of the heat dissipation cover 131 and the first reinforcement ring 110 can further control the overall warpage of the chip package structure 1, thereby ensuring the overall yield of the chip package structure 1. Furthermore, the materials of the first reinforcement ring 110 and the heat dissipation cover 131 are thermally conductive materials (e.g., metal materials), which can increase the metal ratio of the chip package structure 1, thereby improving the heat dissipation efficiency.
[0030] Furthermore, please see again Figure 2 The heat dissipation cover 131 includes a heat dissipation top plate 1310 and a heat dissipation side plate 1311 extending from the heat dissipation top plate 1310 toward the substrate 10. The side of the heat dissipation side plate 1311 away from the heat dissipation top plate 1310 is connected to the first reinforcing ring 110. In this embodiment, the heat dissipation top plate 1310 and the heat dissipation side plate 1311 form a covering space, and all devices on the first side of the wiring area AA1 of the substrate 10 are located within this covering space. It is worth noting that the extension direction of the heat dissipation top plate 1310 is the same as the extension direction of the substrate 10, and the angle formed between the heat dissipation top plate 1310 and the heat dissipation side plate 1311 can be 45 degrees, 90 degrees, etc., and is not specifically limited here. When the angle formed between the heat dissipation top plate 1310 and the heat dissipation side wall is 90 degrees, the cross-sectional shape of the heat dissipation cover 131 and the substrate 10 is rectangular.
[0031] Further, please see Figure 1 and Figure 2 The groove 100 includes a groove bottom 101, and the chip packaging structure 1 also includes a first adhesive layer 14, which is disposed between the groove bottom 101 and the first reinforcing ring 110. In this embodiment, during the fabrication process of the chip packaging structure 1, the first adhesive layer 14 is first disposed on the groove bottom 101, and then the first reinforcing ring 110 is embedded and filled into the groove 100. The first adhesive layer 14 connects to the groove bottom 101 to achieve a stable connection between the first reinforcing ring 110 and the groove 100.
[0032] It is worth noting that the first adhesive layer 14 includes AD adhesive.
[0033] In this embodiment, when the second reinforcing part 13 is the second reinforcing ring 130, please refer to... Figure 1The chip packaging structure 1 also includes a second adhesive layer 15, which is disposed between the first reinforcing ring 110 and the second reinforcing ring 130. During the fabrication of the chip packaging structure 1, the substrate 10 exposes the first reinforcing ring 110. The second adhesive layer 15 is first disposed on the first reinforcing ring 110, and then one side of the second reinforcing ring 130 is connected to the first reinforcing ring 110 through the second adhesive layer 15 to achieve a stable connection between the first reinforcing ring 110 and the second reinforcing ring 130, thereby ensuring the reliability of the internal device connections of the chip packaging structure 1.
[0034] It is worth noting that the second adhesive layer 15 includes AD adhesive.
[0035] When the second reinforcing part 13 is a heat dissipation cover 131, please refer to Figure 2 The chip package structure 1 further includes a third adhesive layer 16 and a fourth adhesive layer 17. The chip 12 includes a back surface 121 opposite to the pins 120. The third adhesive layer 16 is disposed between the inner side of the heat dissipation top plate 1310 and the back surface 121 of the chip 12. The fourth adhesive layer 17 is disposed between the side of the heat dissipation side plate 1311 away from the heat dissipation top plate 1310 and the first reinforcing ring 110. In this embodiment, during the fabrication process of the chip package structure 1, the fourth adhesive layer 17 is first disposed on the first reinforcing ring 110 and the third adhesive layer 16 is disposed on the back surface 121 of the chip 12. Then, the heat dissipation cover 131 is connected to the chip 12 and the first reinforcing ring 110 through the third adhesive layer 16 and the fourth adhesive layer 17 to achieve a stable connection between the heat dissipation cover 131 and the chip 12 and the first reinforcing ring 110.
[0036] It is worth noting that the third adhesive layer 16 includes TIM adhesive, and the fourth adhesive layer 17 includes AD adhesive.
[0037] Further, please see Figure 1 and Figure 2 In this embodiment, the orthographic projection shape of the first reinforcing ring 110 on the substrate 10 includes a rectangle, and the orthographic projection shape of the groove 100 on the substrate 10 also includes a rectangle. The orthographic projection shape of the second reinforcing ring 130 on the substrate 10 also includes a rectangle, and the orthographic projection shape of the heat dissipation cover 131 on the substrate 10 also includes a rectangle. It is worth noting that the orthographic projection shapes of the first reinforcing ring 110, the second reinforcing ring 130, and the heat dissipation cover 130 on the substrate 10 include rounded rectangles.
[0038] In this embodiment, the orthographic projection shapes of the first reinforcing ring 110, the second reinforcing ring 130, and the heat dissipation cover 131 on the substrate 10 include, but are not limited to, the shapes described above. For example, the orthographic projection shape of the first reinforcing ring 110 on the substrate 10 can be annular, and the orthographic projection shape of the groove 100 on the substrate 10 can also be annular. The orthographic projection shape of the second reinforcing ring 130 on the substrate 10 can be annular, and the orthographic projection shape of the heat dissipation cover 131 on the substrate 10 can be circular.
[0039] Furthermore, the materials of the first reinforcing ring 110, the second reinforcing ring 130, and the heat sink 131 include thermally conductive materials, such as metal materials. In this embodiment, when both the first reinforcing ring 110 and the second reinforcing ring 130 are made of metal materials, or when both the first reinforcing ring 110 and the heat sink 131 are made of metal materials, while ensuring further control over warpage, the overall metal ratio of the chip package structure 1 is increased, thereby improving the heat dissipation effect.
[0040] Further, please see Figure 1 and Figure 2 The chip packaging structure 1 in this embodiment also includes components 18, which are disposed on the first side of the trace area AA1 of the substrate 10 and connected to the traces in the substrate 10. Components 18 include, but are not limited to, decoupling capacitors, resistors, inductors, etc., and can be mounted around the chip 12 by SMT process. They usually play the functions of filtering and voltage regulation to ensure the stable operation of the chip 12.
[0041] In this embodiment, there are multiple components 18, which are disposed on both sides of the chip 12. The number of components 18 is not specifically limited here and can be set according to the actual situation.
[0042] Based on the same inventive concept, please see Figure 3 , Figure 4 and Figure 5 , Figure 3 This is a schematic flowchart of the fabrication method of a chip packaging structure 1 provided in this embodiment. Figure 4 for Figure 3 One of the corresponding process diagrams, Figure 5 for Figure 3 According to the second corresponding process diagram, this application embodiment also provides a method for fabricating a chip packaging structure 1, the method including: Step S11, a substrate 10 is provided, wherein the substrate 10 includes a trace area AA1 and a non-trace area AA2 surrounding the trace area AA1, and the substrate 10 includes a first side and a second side opposite to each other.
[0043] In this step, the substrate 10 needs to undergo strict incoming material inspection to ensure that it is free from physical damage and has good electrical performance.
[0044] Step S12: A groove 100 surrounding the wiring area AA1 is opened on the first side of the non-wiring area AA2.
[0045] In this step, a groove 100 of a specific depth can be created using mechanical or laser processes.
[0046] Step S13: Fill the groove 100 with the first reinforcing part 11, wherein the first reinforcing part 11 includes the first reinforcing ring 110.
[0047] In this step, the first reinforcing ring 110 can be prefabricated or directly fabricated within the groove 100. If the first reinforcing ring 110 is prefabricated, simply insert and fill the groove 100 with the prefabricated, size-matched first reinforcing ring 110.
[0048] Step S14: At least one chip 12 is disposed on the first side of the wiring area AA1, wherein the pins 120 of the chip 12 are connected to the wiring in the substrate 10.
[0049] In this step, the pins 120 of the chip 12 are first aligned with the substrate 10. Then, the pins 120 are precisely aligned with the corresponding pads at the trace area AA1. Next, a reliable connection with the substrate 10 is formed through a reflow soldering process. Finally, underfill adhesive is applied between the chip 12 and the substrate 10 to protect the solder joints formed between the pins 120 and the pads while reducing the impact of mechanical or thermal stress.
[0050] Step S15: The second reinforcing part 13 is disposed on the first side of the substrate 10 and connected to the first reinforcing part 11. The second reinforcing part 13 includes a second reinforcing ring 130 or a heat dissipation cover 131.
[0051] In the above scheme, for the large-size chip packaging structure 1, this embodiment first sets a first reinforcing ring 110 during the fabrication process of the chip packaging structure 1, and then performs subsequent fabrication processes of the chip packaging structure 1 based on the first reinforcing ring 110 (e.g., step S14). Thus, the first reinforcing part 11 (i.e., the first reinforcing ring 110) significantly enhances the overall structural rigidity of the substrate 10, reducing the warping phenomenon that occurs during the fabrication of the chip packaging structure 1, thereby reducing the occurrence of defects and ensuring the overall yield of the chip packaging structure 1. Furthermore, setting a second reinforcing part 13 based on the first reinforcing part 11 can reduce the overall warping phenomenon of the chip packaging structure 1, further ensuring the overall yield of the chip packaging structure 1 and ensuring the reliability of subsequent processes.
[0052] Furthermore, when the second reinforcing part 13 is the second reinforcing ring 130, step S15 can be implemented in the following way.
[0053] The second reinforcing ring 130 is placed on the first side of the non-wiring area AA2, and one side of the second reinforcing ring 130 is connected to the first reinforcing ring 110.
[0054] In this embodiment, a second adhesive layer 15 is first provided on the first reinforcing ring 110 exposed on the substrate 10, and then one side of the second reinforcing ring 130 is connected to the first reinforcing ring 110 through the second adhesive layer 15 to achieve a stable connection between the first reinforcing ring 110 and the second reinforcing ring 130.
[0055] Furthermore, when the second reinforcement part 13 is a heat dissipation cover 131, step S15 can also be implemented in the following way.
[0056] A heat sink 131 is placed over the first side of the trace area AA1 and at least part of the non-trace area AA2, and the heat sink 131 is connected to the first reinforcing ring 110, wherein the orthographic projection of the chip 12 and the first reinforcing ring 110 on the substrate 10 is located within the orthographic projection of the heat sink 131 on the substrate 10.
[0057] In this embodiment, the heat sink 131 includes a heat sink top plate 1310 and a heat sink side plate 1311 extending along the heat sink top plate 1310 toward the substrate 10. First, a third adhesive layer 16 is provided on the back side 121 of the chip 12 and a fourth adhesive layer 17 is provided on the first reinforcing ring 110. Then, the heat sink 131 is connected to the chip 12 and the first reinforcing ring 110 through the third adhesive layer 16 and the fourth adhesive layer 17 to achieve a stable connection between the heat sink 131 and the chip 12 and the first reinforcing ring 110.
[0058] Furthermore, in step S14, component 18 is placed on the first side of the trace area AA1. In this embodiment, component 18 can be mounted around chip 12 using SMT technology to ensure stable operation of chip 12.
[0059] In summary, this application provides a chip packaging structure and a method for fabricating the chip packaging structure. The chip packaging structure includes a substrate, a first reinforcing portion, at least one chip, and a second reinforcing portion. The substrate includes a wiring area and a non-wiring area, and includes a first side and a second side opposite to each other. On the first side, a groove surrounding the wiring area is formed in the non-wiring area. The first reinforcing portion includes a first reinforcing ring, which fills the groove. The chip is disposed on the first side of the wiring area, and the chip's pins are connected to the wiring in the substrate. The second reinforcing portion is disposed on the first side of the substrate and connected to the first reinforcing portion. The second reinforcing portion includes a second reinforcing ring or a heat sink. The first reinforcing portion in the above structure can reduce warping during the fabrication process, thereby reducing the occurrence of defects. Furthermore, the combination of the first reinforcing portion and the second reinforcing portion can further control the overall warping of the chip packaging structure, ensuring the overall yield of the chip packaging structure.
[0060] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A chip packaging structure, characterized in that, The chip packaging structure includes: A substrate, the substrate including a trace area and a non-trace area surrounding the trace area, the substrate including a first side and a second side opposite to each other, on the first side, the non-trace area of the substrate having a groove surrounding the trace area; A first reinforcing part, the first reinforcing part including a first reinforcing ring, the first reinforcing ring filling the groove; At least one chip is disposed on a first side of the wiring area, and the pins of the chip are connected to the wiring in the substrate; The second reinforcement part is disposed on the first side of the substrate and is connected to the first reinforcement part. The second reinforcement part includes a second reinforcement ring or a heat dissipation cover.
2. The chip packaging structure as described in claim 1, characterized in that, When the second reinforcement part is the second reinforcement ring, the second reinforcement ring is disposed on the first side of the non-wiring area, and one side of the second reinforcement ring is connected to the first reinforcement ring; When the second reinforcement is the heat dissipation cover, the heat dissipation cover covers the first side of the trace area and at least part of the non-trace area. The heat dissipation cover is connected to the first reinforcement ring, wherein the orthographic projection of the chip and the first reinforcement ring on the substrate is located within the orthographic projection of the heat dissipation cover on the substrate.
3. The chip packaging structure as described in claim 2, characterized in that, The heat dissipation cover includes a heat dissipation top plate and a heat dissipation side plate extending along the heat dissipation top plate toward the substrate, wherein the side of the heat dissipation side plate away from the heat dissipation top plate is connected to the first reinforcing ring.
4. The chip packaging structure as described in claim 3, characterized in that, The groove includes a bottom, and the chip packaging structure further includes a first adhesive layer, which is disposed between the bottom of the groove and the first reinforcing ring. When the second reinforcing part is the second reinforcing ring, the chip packaging structure further includes a second adhesive layer, which is disposed between the first reinforcing ring and the second reinforcing ring; When the second reinforcement part is the heat dissipation cover, the chip packaging structure further includes a third adhesive layer and a fourth adhesive layer. The chip includes a back side opposite to the pins. The third adhesive layer is disposed between the inner side of the heat dissipation top plate and the back side of the chip. The fourth adhesive layer is disposed between the side of the heat dissipation side plate away from the heat dissipation top plate and the first reinforcement ring.
5. The chip packaging structure as described in claim 1, characterized in that, The orthographic projection shape of the first reinforcing ring on the substrate includes a rectangle, and the orthographic projection shape of the second reinforcing ring on the substrate also includes a rectangle; The orthographic projection shape of the heat sink on the substrate includes a rectangle.
6. The chip packaging structure as described in claim 1, characterized in that, The materials of the first reinforcing ring, the second reinforcing ring, and the heat dissipation cover include thermally conductive materials.
7. The chip packaging structure as described in claim 1, characterized in that, The chip packaging structure also includes components, which are disposed on the first side of the wiring area of the substrate and are connected to the wiring in the substrate. The number of the components is multiple, and the multiple components are disposed on both sides of the chip.
8. A method for fabricating a chip packaging structure, characterized in that, The method includes: A substrate is provided, wherein the substrate includes a trace area and a non-trace area surrounding the trace area, and the substrate includes opposing first and second sides; A groove is formed around the wiring area on the first side of the non-wiring area; A first reinforcing portion is filled into the groove, wherein the first reinforcing portion includes a first reinforcing ring; At least one chip is disposed on the first side of the wiring area, wherein the pins of the chip are connected to the wiring in the substrate; A second reinforcing part is disposed on the first side of the substrate and connected to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover.
9. The method for fabricating the chip packaging structure as described in claim 8, characterized in that, When the second reinforcing part is the second reinforcing ring, the step of disposing the second reinforcing part on the first side of the substrate and connecting the second reinforcing part to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover, includes: The second reinforcing ring is placed on the first side of the non-trace area, and one side of the second reinforcing ring is connected to the first reinforcing ring.
10. The method for fabricating the chip packaging structure as described in claim 8, characterized in that, When the second reinforcing part is the heat dissipation cover, the step of disposing the second reinforcing part on the first side of the substrate and connecting the second reinforcing part to the first reinforcing part, wherein the second reinforcing part includes a second reinforcing ring or a heat dissipation cover, includes: The heat sink covers the first side of the trace area and at least part of the non-trace area, and connects the heat sink to the first reinforcing ring, wherein the orthographic projection of the chip and the first reinforcing ring on the substrate is located within the orthographic projection of the heat sink on the substrate.