Shift register and driving method thereof, gate driving circuit and display device

Abstract

The embodiment of the invention provides a shift register and a driving method thereof, a gate driving circuit and a display device. A shift register comprises an input circuit, a first control circuit, a reset circuit, a holding circuit, a second control circuit, a third control circuit, a first output circuit and a second output circuit. The first output circuit is coupled to a fourth node, a second voltage end, a first signal output end, a third node and a third voltage end, and is configured to provide a first output signal through the first signal output end according to the voltage of the fourth node, the second voltage, the voltage of the third node and the third voltage. The second output circuit is coupled to a fourth node, a third voltage terminal, a second signal output terminal, a third node and a fourth voltage terminal, and is configured to provide a second output signal through the second signal output terminal according to the voltage of the fourth node, the third voltage, the voltage of the third node, and a fourth voltage from the fourth voltage terminal.

Description

Shift registers and their driving methods, gate driving circuits and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to shift registers and their driving methods, gate driving circuits, and display devices. Background Technology

[0002] Gate Driver on Array (GOA) technology fabricates the gate driver circuitry on the array substrate, enabling row-by-row scanning of pixels. The gate driver circuitry may include multiple cascaded shift registers. Scan signals are output from the shift registers to drive the pixels, and cascaded transfer signals can be simultaneously output to drive the next-level shift register.

[0003] In the display field, Organic Light-Emitting Diode (OLED) displays are widely used due to their wide viewing angles and fast response times. OLED displays utilize the driving current provided by the driving transistors in the pixel circuits to drive the light-emitting devices to emit light.

[0004] Summary of the Invention

[0005] Embodiments of this disclosure provide a shift register and its driving method, a gate driving circuit, an array substrate, and a display device.

[0006] According to a first aspect of this disclosure, a shift register is provided. It includes an input circuit, a first control circuit, a reset circuit, a holding circuit, a second control circuit, a third control circuit, a first output circuit, and a second output circuit. The input circuit is coupled to an input signal terminal, a first clock signal terminal, and a first node, and is configured to provide an input signal from the input signal terminal to the first node according to a first clock signal from the first clock signal terminal. The first control circuit is coupled to a first voltage terminal, a second clock signal terminal, a second voltage terminal, the input signal terminal, and the second node, and is configured to control the voltage of the second node according to a first voltage from the first voltage terminal, a second clock signal, a second voltage from the second voltage terminal, and the input signal. The reset circuit is coupled to the second node, the second voltage terminal, the second clock signal terminal, and the first node, and is configured to reset the first node according to the voltage of the second node, the second clock signal from the second clock signal terminal, and the second voltage from the second voltage terminal. The holding circuit is coupled to the second clock signal and the second node, and is configured to hold the voltage of the second node according to the second clock signal. A second control circuit is coupled to a second node, a second clock signal terminal, a second voltage terminal, a first node, and a fourth node, and is configured to control the voltage of the fourth node based on the voltage of the first node, the voltage of the second node, the second clock signal, and the second voltage. A third control circuit is coupled to a first node, a third node, and a third voltage terminal, and is configured to control the voltage of the third node based on the third voltage and the voltage of the first node. A first output circuit is coupled to a fourth node, a second voltage terminal, a first signal output terminal, a third node, and the third voltage terminal, and is configured to provide a first output signal through the first signal output terminal based on the voltage of the fourth node, the second voltage, the voltage of the third node, and the third voltage. A second output circuit is coupled to a fourth node, a third voltage terminal, a second signal output terminal, a third node, and a fourth voltage terminal, and is configured to provide a second output signal through the second signal output terminal based on the voltage of the fourth node, the voltage of the third node, the third voltage, and the fourth voltage from the fourth voltage terminal.

[0007] In embodiments of this disclosure, the first output signal is used as a cascade transmission signal, and the second output signal is used as a scanning signal.

[0008] In embodiments of this disclosure, the shift register alternatively includes an input circuit, a first control circuit, a reset circuit, a second control circuit, a third control circuit, a first output circuit, and a second output circuit. The first control circuit is alternatively coupled to a third voltage terminal, a second clock signal terminal, a second voltage terminal, an input signal terminal, and a second node, and is configured to control the voltage of the second node based on the third voltage, the second clock signal, the second voltage, and the input signal. The second control circuit is alternatively coupled to the first node, the second node, and the second voltage terminal, and is configured to control the voltage of the second node based on the voltage of the first node and the second voltage. The second node coincides with a fourth node.

[0009] In embodiments of this disclosure, the first voltage and the third voltage are high-level voltages, and the first voltage is greater than or equal to the third voltage; the second voltage and the fourth voltage are low-level voltages, and the second voltage is less than or equal to the fourth voltage.

[0010] In embodiments of this disclosure, the first voltage is approximately 14V, the second voltage is approximately -9V, the third voltage is approximately 8V, and the fourth voltage is approximately -6V.

[0011] In embodiments of this disclosure, the input circuit includes a first transistor, the control electrode of the first transistor is coupled to a first clock signal terminal, the first electrode of the first transistor is coupled to an input signal terminal, and the second electrode of the first transistor is coupled to a first node.

[0012] In embodiments of this disclosure, the first control circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to an input signal terminal, the first electrode of the second transistor is coupled to a second voltage terminal, and the second electrode of the second transistor is coupled to a second node. The control electrode of the third transistor is coupled to a second clock signal terminal, the first electrode of the third transistor is coupled to a first voltage terminal, and the second electrode of the third transistor is coupled to a second node.

[0013] In an embodiment of this disclosure, the first control circuit includes a second transistor, a third transistor, and a fourth capacitor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the seventh node. The control electrode of the third transistor is coupled to the seventh node, the first electrode of the third transistor is coupled to the third voltage terminal, and the second electrode of the third transistor is coupled to the second node. The first plate of the fourth capacitor is coupled to the second clock signal terminal, and the second plate of the fourth capacitor is coupled to the seventh node.

[0014] In embodiments of this disclosure, the reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to a second node, the first electrode of the fourth transistor is coupled to a second voltage terminal, the second electrode of the fourth transistor is coupled to a fifth node, the control electrode of the fifth transistor is coupled to a second clock signal terminal, the first electrode of the fifth transistor is coupled to a fifth node, and the second electrode of the fifth transistor is coupled to a first node.

[0015] In an embodiment of this disclosure, the holding circuit includes a first capacitor, a first plate of the first capacitor being coupled to a third voltage terminal, and a second plate of the first capacitor being coupled to a second node.

[0016] In embodiments of this disclosure, the second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the sixth node. The control electrode of the seventh transistor is coupled to the second clock signal terminal, the first electrode of the seventh transistor is coupled to the sixth node, and the second electrode of the seventh transistor is coupled to the fourth node. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the fourth node.

[0017] In embodiments of this disclosure, the second control circuit includes an eighth transistor. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second clock signal terminal, and the second electrode of the eighth transistor is coupled to the second node.

[0018] In embodiments of this disclosure, the third control circuit includes a ninth transistor. The control terminal of the ninth transistor is coupled to a third voltage terminal, the first terminal of the ninth transistor is coupled to a first node, and the second terminal of the ninth transistor is coupled to a third node.

[0019] In embodiments of this disclosure, the control electrode of the ninth transistor is alternatively coupled to the first voltage terminal.

[0020] In an embodiment of this disclosure, the first output circuit includes a tenth transistor, an eleventh transistor, and a second capacitor. The control electrode of the tenth transistor is coupled to a fourth node, the first electrode of the tenth transistor is coupled to a second voltage terminal, the second electrode of the tenth transistor is coupled to a first signal output terminal, the control electrode of the eleventh transistor is coupled to a third node, the first electrode of the eleventh transistor is coupled to a third voltage terminal, the second electrode of the eleventh transistor is coupled to the first signal output terminal, the first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to a third node.

[0021] In an embodiment of this disclosure, the first output circuit includes a tenth transistor, an eleventh transistor, a second capacitor, and a fifth capacitor. The control electrode of the tenth transistor is coupled to a second node, the first electrode of the tenth transistor is coupled to a second voltage terminal, the second electrode of the tenth transistor is coupled to a first signal output terminal, the control electrode of the eleventh transistor is coupled to a third node, the first electrode of the eleventh transistor is coupled to a third voltage terminal, the second electrode of the eleventh transistor is coupled to the first signal output terminal, the first plate of the second capacitor is coupled to the first signal output terminal, the second plate of the second capacitor is coupled to a third node, the first plate of the fifth capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to a second node.

[0022] In embodiments of this disclosure, the tenth transistor is a dual-gate transistor.

[0023] In embodiments of this disclosure, the tenth transistor includes a third terminal, and the first output circuit further includes a fourteenth transistor, wherein the control terminal of the fourteenth transistor is coupled to a first signal output terminal, the first terminal of the fourteenth transistor is coupled to a first voltage terminal, and the second terminal of the fourteenth transistor is coupled to the third terminal of the tenth transistor.

[0024] In an embodiment of this disclosure, the tenth transistor has a bottom control electrode coupled to a fifth voltage terminal, wherein a fifth voltage from the fifth voltage terminal is lower than a second voltage and the second voltage is lower than a fourth voltage.

[0025] In embodiments of this disclosure, the second output circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor. The control electrode of the twelfth transistor is coupled to a fourth node, the first electrode of the twelfth transistor is coupled to a fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to a second signal output terminal. The control electrode of the thirteenth transistor is coupled to a third node, the first electrode of the thirteenth transistor is coupled to a third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal. The first plate of the third capacitor is coupled to the second signal output terminal, and the second plate of the third capacitor is coupled to a third node.

[0026] In an embodiment of this disclosure, the second output circuit includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to a second node, the first electrode of the twelfth transistor is coupled to a fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to a second signal output terminal. The control electrode of the thirteenth transistor is coupled to a third node, the first electrode of the thirteenth transistor is coupled to a third voltage terminal, and the second electrode of the thirteenth transistor is coupled to a second signal output terminal.

[0027] In embodiments of this disclosure, the input circuit includes a first transistor, the control electrode of the first transistor is coupled to a first clock signal terminal, the first electrode of the first transistor is coupled to an input signal terminal, and the second electrode of the first transistor is coupled to a first node.

[0028] The first control circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the second node. The control electrode of the third transistor is coupled to the second clock signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node.

[0029] The reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, the second electrode of the fourth transistor is coupled to the fifth node, the control electrode of the fifth transistor is coupled to the second clock signal terminal, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the first node.

[0030] The holding circuit includes a first capacitor, the first plate of the first capacitor being coupled to a third voltage terminal, and the second plate of the first capacitor being coupled to a second node;

[0031] The second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the sixth node. The control electrode of the seventh transistor is coupled to the second clock signal terminal, the first electrode of the seventh transistor is coupled to the sixth node, and the second electrode of the seventh transistor is coupled to the fourth node. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the fourth node.

[0032] The third control circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to a third voltage terminal, the first electrode of the ninth transistor is coupled to a first node, and the second electrode of the ninth transistor is coupled to a third node.

[0033] The first output circuit includes a tenth transistor, an eleventh transistor, and a second capacitor. The control electrode of the tenth transistor is coupled to a fourth node, the first electrode of the tenth transistor is coupled to a second voltage terminal, and the second electrode of the tenth transistor is coupled to a first signal output terminal. The control electrode of the eleventh transistor is coupled to a third node, the first electrode of the eleventh transistor is coupled to a third voltage terminal, and the second electrode of the eleventh transistor is coupled to the first signal output terminal. The first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to a third node.

[0034] The second output circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor. The control electrode of the twelfth transistor is coupled to the fourth node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal. The first plate of the third capacitor is coupled to the second signal output terminal, and the second plate of the third capacitor is coupled to the third node to hold the first capacitor of the circuit. The first plate of the first capacitor is coupled to the third voltage terminal, and the second plate of the first capacitor is coupled to the second node.

[0035] In embodiments of this disclosure, the input circuit includes a first transistor, the control electrode of the first transistor is coupled to a first clock signal terminal, the first electrode of the first transistor is coupled to an input signal terminal, and the second electrode of the first transistor is coupled to a first node.

[0036] The first control circuit includes a second transistor, a third transistor, and a fourth capacitor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the seventh node. The control electrode of the third transistor is coupled to the seventh node, the first electrode of the third transistor is coupled to the third voltage terminal, and the second electrode of the third transistor is coupled to the second node. The first plate of the fourth capacitor is coupled to the second clock signal terminal, and the second plate of the fourth capacitor is coupled to the seventh node.

[0037] The reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, the second electrode of the fourth transistor is coupled to the fifth node, the control electrode of the fifth transistor is coupled to the second clock signal terminal, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the first node.

[0038] The second control circuit includes an eighth transistor, the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the second node.

[0039] The third control circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to a third voltage terminal, the first electrode of the ninth transistor is coupled to a first node, and the second electrode of the ninth transistor is coupled to a third node.

[0040] The first output circuit includes a tenth transistor, an eleventh transistor, a second capacitor, and a fifth capacitor. The control electrode of the tenth transistor is coupled to a second node, the first electrode of the tenth transistor is coupled to a second voltage terminal, and the second electrode of the tenth transistor is coupled to a first signal output terminal. The control electrode of the eleventh transistor is coupled to a third node, the first electrode of the eleventh transistor is coupled to a third voltage terminal, and the second electrode of the eleventh transistor is coupled to the first signal output terminal. The first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to a third node. The first plate of the fifth capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to a second node.

[0041] The second output circuit includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal.

[0042] According to a second aspect of this disclosure, a gate drive circuit is provided. The gate drive circuit includes a plurality of cascaded shift registers as described in any one of the first aspects of this disclosure.

[0043] According to a third aspect of this disclosure, a display device is provided. The display device includes a gate driving circuit as described in a second aspect of this disclosure.

[0044] According to a fourth aspect of this disclosure, a method for driving a shift register as described in any of the first aspects of this disclosure is provided. The method includes: in a first stage, providing a first voltage to a second node, storing and preserving a first voltage difference related to the voltage of the second node; in a second stage, maintaining the first voltage difference, continuously outputting a second voltage as a first output signal at a first output signal terminal, and continuously outputting a fourth voltage as a second output signal at a second signal output terminal; in a third stage, providing the second voltage to the first node and a third node to reset the first node and the third node; and in a fourth stage, providing an input signal to the first node and the third node, providing the second voltage to the second node and the fourth node to reset the second node and the fourth node, and outputting a third voltage as a first output signal at a first output signal terminal, and outputting the third voltage as a second output signal at a second signal output terminal. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure. In the drawings:

[0046] Figure 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

[0047] Figure 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure;

[0048] Figure 3 shows an exemplary circuit diagram of the shift register shown in Figure 1 according to an embodiment of the present disclosure;

[0049] Figure 4 shows an exemplary circuit diagram of a shift register as shown in Figure 2 according to an embodiment of the present disclosure;

[0050] Figure 5 shows an exemplary circuit diagram of the shift register shown in Figure 1 according to another embodiment of the present disclosure;

[0051] Figure 6 shows an exemplary circuit diagram of the shift register shown in Figure 2 according to another embodiment of the present disclosure;

[0052] Figure 7 shows an exemplary circuit diagram of the shift register shown in Figure 1 according to another embodiment of the present disclosure;

[0053] Figure 8 shows an exemplary circuit diagram of the shift register shown in Figure 2 according to another embodiment of the present disclosure;

[0054] Figure 9 shows an exemplary circuit diagram of the shift register shown in Figure 1 according to another embodiment of the present disclosure;

[0055] Figure 10 shows an exemplary circuit diagram of the shift register shown in Figure 2 according to another embodiment of the present disclosure;

[0056] Figure 11 shows the timing diagram of each signal during the operation of the shift register shown in Figure 3;

[0057] Figure 12 shows a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0058] Figure 13 shows a schematic diagram of a display device according to an embodiment of the present disclosure; and

[0059] Figure 14 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure. Detailed Implementation

[0060] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the described embodiments, all other embodiments obtained by those skilled in the art without creative effort are also within the scope of this disclosure.

[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. The terms “connection,” “coupled,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, which can be direct connections or indirect connections via an intermediate medium.

[0062] As previously described, each shift register in a GOA can provide a scan signal to a pixel row to achieve row-by-row scanning, while simultaneously outputting a cascade pass signal to drive the next-stage shift register. In a typical shift register, only one output signal is provided. This output signal is provided to the corresponding pixel row as a scan signal and then to the next-stage shift register as a cascade pass signal. Since the scan signal is used to drive the pixels to emit light, load can cause the scan signal level to decrease. This decrease may lead to cascade pass signal failure. To address this problem, the shift register provided in the embodiments of this disclosure solves the aforementioned cascade failure problem by separating the scan signal and the cascade pass signal.

[0063] This disclosure provides embodiments of a shift register and its driving method, a gate driving circuit, and a display device. The embodiments and examples of this disclosure are described in detail below with reference to the accompanying drawings.

[0064] Figure 1 shows a schematic block diagram of a shift register 5 according to an embodiment of the present disclosure. As shown in Figure 1, the shift register 5 includes an input circuit 100, a first control circuit 200, a reset circuit 300, a holding circuit 400, a second control circuit 500, a third control circuit 600, a first output circuit 700, and a second output circuit 800. It will now be described in detail with reference to the accompanying drawings.

[0065] In embodiments of this disclosure, the input circuit 100 is coupled to a signal input terminal, a first clock signal terminal, and a first node N1, and can provide an input signal STV from the signal input terminal to the first node N1 based on a first clock signal CK from the first clock signal terminal. In this embodiment, the input circuit 100 is coupled to the first clock signal terminal to receive the first clock signal CK. The input circuit 100 is coupled to the signal input terminal to receive the input signal STV. The input circuit 100 can provide the received input signal STV to the first node N1 based on the received first clock signal CK1.

[0066] A first control circuit 200 is coupled to a first voltage terminal, a second clock signal terminal, an input signal terminal, and a second node N2, and controls the voltage of the second node N2 based on a first voltage V1 from the first voltage terminal, a second clock signal CB, a second voltage V2 from the second voltage terminal, and an input signal STV. In an embodiment, the first control circuit 200 is coupled to the first voltage terminal to receive the first voltage V1. The first control circuit 200 is coupled to the second voltage terminal to receive the first voltage V2. The first control circuit 200 is coupled to the second clock signal terminal to receive the second clock signal CB. The first control circuit 200 controls the voltage of the second node N2 based on the received first clock signal CB, the first voltage V1, the second voltage V2, and the voltage of the first node N1. In embodiments of this disclosure, the first voltage V1 can be a high-level voltage, for example, about 14V. The second voltage V2 can be a low-level voltage, for example, about -9V. In an embodiment, the voltage fluctuation value can be ±0.1V. The first voltage V1 can be in the range of 13.9V to 14.1V. The second voltage V2 can be in the range of -9.1V to -8.9V.

[0067] A reset circuit 300 is coupled to a second node N2, a second voltage terminal, a second clock signal terminal, and a first node N1, and is configured to reset the first node N1 based on the voltage of the second node N2, a second clock signal CB from the second clock signal terminal, and a second voltage V2. In an embodiment, the reset circuit 300 is coupled to the second voltage terminal to receive the second voltage V2. The reset circuit 300 is coupled to the second clock signal terminal to receive the second clock signal CB. In an embodiment, the second clock signal CB has the same frequency as the first clock signal CK and is 180 degrees out of phase.

[0068] The holding circuit 400 is coupled to the third voltage terminal and the second node N2, and is configured to maintain the voltage of the second node N2 according to the third voltage V3 received from the third voltage terminal. In an embodiment, the holding circuit 400 is coupled to the third voltage terminal to receive the third voltage V3. In an embodiment, the third voltage V3 is a high-level voltage and is less than or equal to the first voltage V1. The third voltage V3 can be in the range of 0V-25V, for example, the third voltage V3 can be about 8V. Similarly, in an embodiment, the voltage fluctuation value can be ±0.1V. The third voltage V3 can be in the range of 7.9V to 8.1V.

[0069] The second control circuit 500 is coupled to the second node N2, the second clock signal terminal, the second voltage terminal, the first node N1, and the fourth node N4, and is configured to control the voltage of the fourth node N4 with the voltage of the first node N1, the voltage of the second node N2, the second clock signal CB, and the second voltage V2. In an embodiment, the second control circuit 500 is coupled to the second clock signal terminal to receive the second clock signal CB. The second control circuit 500 is coupled to the second voltage terminal to receive the second voltage V2.

[0070] The third control circuit 600 is coupled to the first node N1, the third node N3, and a third voltage terminal, and is configured to control the voltage of the third node N3 based on the third voltage V3 and the voltage of the first node N1. In an embodiment, the third control circuit 600 is coupled to the third voltage terminal to receive the third voltage V3.

[0071] The first output circuit 700 is coupled to the fourth node N4, the second voltage terminal, the first signal output terminal, the third node N3, and the third voltage terminal, and is configured to provide a first output signal OUTPUT1 through the first signal output terminal based on the voltage of the fourth node N4, the second voltage V2, the voltage of the third node N3, and the third voltage V3. In an embodiment, the first output signal OUTPUT1 can be used as a cascade pass signal. In an embodiment, the first output circuit 700 is coupled to the second voltage terminal to receive the second voltage V2. The first output circuit 700 is coupled to the third voltage terminal to receive the third voltage V3. In embodiments of this disclosure, the cascade pass signal refers to a signal provided by the previous stage shift register to the next stage shift register as an input signal for driving the next stage shift register in a gate drive circuit for any two cascaded shift registers. The cascade pass signal can also be provided to the previous stage shift register as a reset signal for resetting the shift register.

[0072] The second output circuit 800 is coupled to the fourth node N4, the third voltage terminal, the second signal output terminal, the third node N3, and the fourth voltage terminal, and is configured to provide a second output signal OUTPUT2 through the second signal output terminal based on the voltage of the fourth node N4, the third voltage V3, the voltage of the third node N3, and the fourth voltage V4 from the fourth voltage terminal. In an embodiment, the second output signal OUTPUT2 can be used as a scan signal. In an embodiment, the second output circuit 800 is coupled to the third voltage terminal to receive the third voltage V3. The second output circuit 800 is coupled to the fourth voltage terminal to receive the fourth voltage V4. In an embodiment, the fourth voltage V4 is a low-level voltage, and the fourth voltage V4 is greater than or equal to the second voltage V2. The fourth voltage V4 can be in the range of -25V to 0V, for example, the fourth voltage V4 can be about -6V. Similarly, in an embodiment, the voltage fluctuation value can be ±0.1V. The fourth voltage V4 can be in the range of -6.1V to -5.9V.

[0073] Alternatively, in other embodiments of this disclosure, the third control circuit 600 may be coupled to the first voltage terminal V1.

[0074] The shift register 5 prevents step-by-step failure of the gate drive circuit caused by load by separating the cascade pass signal from the scan signal.

[0075] This disclosure also provides another shift register 10. The shift register 10 alternatively includes an input circuit 100, a first control circuit 200, a reset circuit 300, a second control circuit 500, a third control circuit 600, a first output circuit 700, and a second output circuit 800. The shift register 10 will now be described in detail with reference to FIG2.

[0076] Figure 2 shows a schematic block diagram of a shift register 10 according to another embodiment of the present disclosure. As shown in Figure 2, the shift register 10 differs from the shift register 5 in that: a first control circuit 200 is alternatively coupled to a third voltage terminal V3, a second clock signal terminal, a second voltage terminal, an input signal terminal, and a second node N2, and is configured to control the voltage of the second node N2 according to the third voltage V3, the second clock signal CB, the second voltage V2, and the input signal STV; and a second control circuit 500 is alternatively coupled to a first node N1, a second node N2, and a second voltage terminal, and is configured to control the voltage of the second node N2 according to the voltage of the first node N1 and the second voltage V2. In the shift register 10, the second node N2 coincides with the fourth node N4. The input circuit 100, the reset circuit 300, the third control circuit 600, the first output circuit 700, and the second output circuit 800 are similar to those in Figure 1 and will not be described again here.

[0077] Similar to shift register 5, shift register 10 can also prevent cascading failure of the gate drive circuit caused by load by separating the cascade pass signal from the scan signal. The circuit diagram of shift register 5 is described in detail below with reference to FIG3.

[0078] Figure 3 shows an example circuit diagram of the shift register 15 shown in Figure 1 according to an embodiment of the present disclosure. As shown in Figure 3, the shift register 15 includes first transistors T1 to thirteenth transistors T13 and first capacitors C1 to third capacitors C3.

[0079] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors or field-effect transistors (e.g., low-temperature poly-silicon transistors and oxide thin-film transistors) or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. The gate of the transistor can be referred to as the control terminal. Furthermore, according to the characteristics of the transistor, transistors can be divided into N-type and P-type transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage and the turn-off voltage is a high-level voltage. When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage and the turn-off voltage is a low-level voltage.

[0080] Additionally, it should be noted that the transistors used in the shift registers provided in the embodiments of this disclosure are all N-type transistors as an example. The embodiments of this disclosure include, but are not limited to, at least some of the transistors in the shift register may also be P-type transistors.

[0081] The input circuit 100 includes a first transistor T1. The control electrode of the first transistor T1 is coupled to a first clock signal terminal, the first electrode of the first transistor T1 is coupled to a signal input terminal, and the second electrode of the first transistor T1 is coupled to a first node N1.

[0082] The first control circuit 200 includes a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is coupled to the signal input terminal, the first electrode of the second transistor T2 is coupled to the second voltage terminal, and the second electrode of the second transistor T2 is coupled to the second node N2. The control electrode of the third transistor T3 is coupled to the second clock signal terminal, the first electrode of the third transistor T3 is coupled to the first voltage terminal, and the second electrode of the third transistor T3 is coupled to the second node N2.

[0083] The reset circuit 300 includes a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is coupled to the second node N2, the first electrode of the fourth transistor T4 is coupled to the second voltage terminal, and the second electrode of the fourth transistor T4 is coupled to the fifth node N5. The control electrode of the fifth transistor T5 is coupled to the second clock signal terminal, the first electrode of the fifth transistor T5 is coupled to the fifth node N5, and the second electrode of the fifth transistor T5 is coupled to the first node N1.

[0084] The holding circuit 400 includes a first capacitor C1. The first plate of the first capacitor C1 is coupled to the third voltage terminal, and the second plate of the first capacitor C1 is coupled to the second node N2.

[0085] The second control circuit 500 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The control electrode of the sixth transistor T6 is coupled to the second node N2, the first electrode of the sixth transistor T6 is coupled to the second clock signal terminal, and the second electrode of the sixth transistor T6 is coupled to the sixth node N6. The control electrode of the seventh transistor T7 is coupled to the second clock signal terminal, the first electrode of the seventh transistor T7 is coupled to the sixth node N6, and the second electrode of the seventh transistor T7 is coupled to the fourth node N4. The control electrode of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the second voltage terminal, and the second electrode of the eighth transistor T8 is coupled to the fourth node N4.

[0086] The third control circuit 600 includes a ninth transistor T9. The control terminal of the ninth transistor T9 is coupled to the third voltage terminal, the first terminal of the ninth transistor T9 is coupled to the first node N1, and the second terminal of the ninth transistor T9 is coupled to the third node N3.

[0087] The first output circuit 700 includes a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2. The control electrode of the tenth transistor T10 is coupled to the fourth node N4, the first electrode of the tenth transistor T10 is coupled to the second voltage terminal, and the second electrode of the tenth transistor T10 is coupled to the first signal output terminal. The control electrode of the eleventh transistor T11 is coupled to the third node N3, the first electrode of the eleventh transistor T11 is coupled to the third voltage terminal, and the second electrode of the eleventh transistor T11 is coupled to the first signal output terminal. The first plate of the second capacitor C2 is coupled to the first signal output terminal, and the second plate of the second capacitor C2 is coupled to the third node N3.

[0088] The second output circuit 800 includes a twelfth transistor T12, a thirteenth transistor T13, and a third capacitor C3. The control electrode of the twelfth transistor T12 is coupled to the fourth node N4, the first electrode of the twelfth transistor T12 is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor T12 is coupled to the second signal output terminal. The control electrode of the thirteenth transistor T13 is coupled to the third node N3, the first electrode of the thirteenth transistor T13 is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor T13 is coupled to the second signal output terminal. The first plate of the third capacitor C3 is coupled to the second signal output terminal, and the second plate of the third capacitor C3 is coupled to the third node N3.

[0089] Alternatively, in other embodiments of this disclosure, the control electrode of the ninth transistor T9 may be coupled to the first voltage terminal.

[0090] Figure 4 shows an exemplary circuit diagram of the shift register shown in Figure 2 according to an embodiment of the present disclosure. The shift register 20 shown in Figure 4 includes first transistors T1 to fifth transistors T5, eighth transistors T8 to thirteenth transistors T13, a second capacitor C2, and a fifth capacitor C5. The shift register 20 differs from the shift register 15 shown in Figure 3 in that: the first control circuit 200 includes a second transistor T2, a third transistor T3, and a fourth capacitor C4. The control electrode of the second transistor T2 is coupled to the input signal terminal, the first electrode of the second transistor T2 is coupled to the second voltage terminal, and the second electrode of the second transistor T2 is coupled to the seventh node N7. The control electrode of the third transistor T3 is coupled to the seventh node N7, the first electrode of the third transistor T3 is coupled to the third voltage terminal V3, and the second electrode of the third transistor T3 is coupled to the second node N2. The first plate of the fourth capacitor C4 is coupled to the second clock signal terminal, and the second plate of the fourth capacitor C4 is coupled to the seventh node N7. The second control circuit 500 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is coupled to the first node N1, the first electrode of the eighth transistor T8 is coupled to the second voltage terminal, and the second electrode of the eighth transistor T8 is coupled to the second node N2. The first output circuit 700 includes a tenth transistor T10, an eleventh transistor T11, a second capacitor C2, and a fifth capacitor C5. The control electrode of the tenth transistor T10 is coupled to the second node N2, the first electrode of the tenth transistor T10 is coupled to the second voltage terminal, and the second electrode of the tenth transistor T10 is coupled to the first signal output terminal. The control electrode of the eleventh transistor T11 is coupled to the third node N3, the first electrode of the eleventh transistor T11 is coupled to the third voltage terminal V3, and the second electrode of the eleventh transistor T11 is coupled to the first signal output terminal. The first plate of the second capacitor C2 is coupled to the first signal output terminal, and the second plate of the second capacitor C2 is coupled to the third node N3. The first plate of the fifth capacitor C5 is coupled to the first signal output terminal, and the second plate of the second capacitor C2 is coupled to the second node N2. In the shift register 20, the second node N2 overlaps with the fourth node N4. The input circuit 100, reset circuit 300, third control circuit 600 and second output circuit 800 in shift register 20 are similar to those in shift register 15 in Figure 3, and will not be described again here.

[0091] Figure 5 shows an exemplary circuit diagram of shift register 5 as shown in Figure 1 according to another embodiment of the present disclosure. As shown in Figure 5, the difference between shift register 25 and shift register 15 is that the tenth transistor T10 is a dual-gate transistor. The tenth transistor T10 includes a third electrode. The first output circuit 700 further includes a fourteenth transistor T14. The control electrode of the fourteenth transistor T14 is coupled to a first signal output terminal, the first electrode of the fourteenth transistor T14 is coupled to a first voltage terminal, and the second electrode of the fourteenth transistor T14 is coupled to the third electrode of the tenth transistor T10. In embodiments of the present disclosure, the third electrode of the dual-gate transistor refers to the same electrode that serves as the source and drain relative to the two gates, respectively.

[0092] Figure 6 shows an exemplary circuit diagram of shift register 10 as shown in Figure 2 according to another embodiment of the present disclosure. As shown in Figure 6, the difference between shift register 30 and shift register 20 is that the tenth transistor T10 is a dual-gate transistor. The coupling relationship and function of the tenth transistor T10 are similar to those in Figure 5, and will not be described again here.

[0093] Figure 7 shows an exemplary circuit diagram of shift register 5 as shown in Figure 1 according to another embodiment of the present disclosure. As shown in Figure 7, shift register 35 differs from shift register 15 in that the tenth transistor T10 has a bottom control electrode. The transistor has a substrate and an active layer located on the substrate. The active layer includes a channel region corresponding to the gate and a portion opposite to the channel region. The bottom control electrode is coupled to this portion. The bottom control electrode of the tenth transistor T10 is coupled to a fifth voltage terminal. The fifth voltage V5 from the fifth voltage terminal can be a low level, and the fifth voltage V5 is less than the second voltage V2. For example, the fifth voltage V5 can be -12V. Similarly, in the embodiment, the voltage fluctuation value can be ±0.1V. The fifth voltage V5 can be in the range of -12.1V to -11.9V. The bottom control electrode allows the tenth transistor T10 to increase the current carrying capacity of the transistor when it is turned on without changing the voltage difference between its first and second electrodes. Furthermore, in the embodiment, the tenth transistor T10 can be an oxide thin-film transistor. Oxide-film transistors (OTCs) are prone to negative bias at the threshold voltage, which can lead to leakage current in the circuit. By adding a bottom control electrode, the output characteristic curve of the OTC can be adjusted to reduce or counteract the effect of the negatively biased threshold voltage, thus preventing leakage current and circuit failure.

[0094] Figure 8 shows an exemplary circuit diagram of shift register 10 as shown in Figure 2 according to another embodiment of the present disclosure. As shown in Figure 8, the difference between shift register 40 and shift register 20 is that the tenth transistor T10 has a bottom control electrode. The coupling relationship and function of the dual-gate transistor tenth transistor T10 are similar to those in Figure 7, and will not be described again here.

[0095] Figure 9 shows an exemplary circuit diagram of the shift register 5 shown in Figure 1 according to another embodiment of the present disclosure. As shown in Figure 9, the shift register 45 differs from the shift register 15 shown in Figure 3 in that the shift register 45 further includes a fifteenth transistor T15. The control electrode and the second electrode of the fifteenth transistor T15 are both coupled to the third node N3, and the first electrode of the fifteenth transistor T15 is coupled to the first voltage terminal. This configuration can maintain the high level of the voltage of the third node N3 when the voltage of the third node N3 is high, thereby maintaining the driving capability of the first output signal OUTPUT1 and the second output signal OUTPUT2.

[0096] Figure 10 shows an exemplary circuit diagram of shift register 10 as shown in Figure 2 according to another embodiment of the present disclosure. As shown in Figure 10, the difference between shift register 25 and shift register 20 shown in Figure 4 is that shift register 50 further includes a fifteenth transistor T15. The coupling relationship and function of the fourteenth transistor T15 are similar to those in Figure 9, and will not be described again here.

[0097] The operation of the shift register 15 shown in Figure 3 will be described below with reference to the signal timing diagram in Figure 11. In this embodiment, the first voltage V1 is approximately high (14V), the second voltage V2 is approximately low (-9V), the third voltage V3 is approximately high (8V), and the fourth voltage V4 is approximately low (-6V). The first clock signal CK and the second clock signal CB have the same frequency and are 180 degrees out of phase. Similarly, in this embodiment, the voltage fluctuation can be ±0.1V. The first voltage V1 can be in the range of 13.9V to 14.1V. The second voltage V2 can be in the range of -9.1V to -8.9V. The third voltage V3 can be in the range of 7.9V to 8.1V. The fourth voltage V4 can be in the range of -6.1V to -5.9V.

[0098] As shown in Figure 11, shift register 15 receives a low-level input signal STV and a first clock signal CK, as well as a high-level second clock signal CB. The third transistor T3 is turned on, and the received high-level first voltage V1 is provided to the second node N2. The first capacitor C1 stores the first voltage difference associated with the second node N2. In this embodiment, the first voltage difference refers to the voltage difference between the third voltage V3 and the high-level voltage of the second node N2. The fourth transistor T4 is turned on, and the received low-level second voltage V2 is provided to the fifth node N5. The fifth transistor T5 is turned on, and the received low-level voltage of the fifth node N5 is provided to the first node N1. The sixth transistor T6 is turned on, and the received high-level second clock signal CB is provided to the sixth node N6. The seventh transistor T7 is turned on, and the received high-level voltage of the sixth node N6 is provided to the fourth node N4. The ninth transistor T9 is turned on, and the low-level voltage of the first node N1 is provided to the third node N3. The tenth transistor T10 is turned on, and the received low-level second voltage V2 is provided to the first signal output terminal as the first output signal OUTPUT1. The twelfth transistor T12 is turned on, and the low-level second voltage V2 is provided to the second signal output terminal as the second output signal OUTPUT2. The first transistor T1, the second transistor T2, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0099] In the second stage t2, shift register 15 receives a high-level first clock signal CK, and a low-level input signal STV and a second clock signal CB. First transistor T1 turns on, and the received low-level input signal STV is provided to first node N1. Due to the first voltage difference stored in first capacitor C1, the voltage at second node N2 remains high. Fourth transistor T4 turns on, and the received low-level second voltage V2 is provided to fifth node N5. Sixth transistor T6 turns on, and the received low-level second clock signal CB is provided to sixth node N6. The voltage at fourth node N4 remains high. Ninth transistor T9 turns on, and the low-level voltage at first node N1 is provided to third node N3. Tenth transistor T10 turns on, and the received low-level second voltage V2 is provided to the first signal output terminal as the first output signal OUTPUT1. Twelfth transistor T12 turns on, and the low-level second voltage V2 is provided to the second signal output terminal as the second output signal OUTPUT2. The second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the seventh transistor T7, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0100] In the third stage t3, shift register 15 receives a low-level input signal STV and a first clock signal CK, as well as a high-level second clock signal CB. The third transistor T3 turns on, and the received high-level first voltage V1 is provided to the second node N2. The first capacitor C1 stores the first voltage difference associated with the second node N2. In this embodiment, the first voltage difference refers to the voltage difference between the third voltage V3 and the high-level voltage of the second node N2. The fourth transistor T4 turns on, and the received low-level second voltage V2 is provided to the fifth node N5. The fifth transistor T5 turns on, and the received low-level voltage of the fifth node N5 is provided to the first node N1. The sixth transistor T6 turns on, and the received high-level second clock signal CB is provided to the sixth node N6. The seventh transistor T7 turns on, and the received high-level voltage of the sixth node N6 is provided to the fourth node N4. The ninth transistor T9 turns on, and the low-level voltage of the first node N1 is provided to the third node N3. The tenth transistor T10 is turned on, and the received low-level second voltage V2 is provided to the first signal output terminal as the first output signal OUTPUT1. The twelfth transistor T12 is turned on, and the low-level second voltage V2 is provided to the second signal output terminal as the second output signal OUTPUT2. The first transistor T1, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0101] In stage t4, shift register 15 receives a high-level input signal STV and a first clock signal CK, as well as a low-level second clock signal CB. First transistor T1 turns on, and the received high-level input signal STV is provided to first node N1. Second transistor T2 turns on, and the received low-level second voltage V2 is provided to second node N2. Due to the first voltage difference stored in first capacitor C1, the voltage at second node N2 remains high and then goes low. Eighth transistor T8 turns on, and the received low-level second voltage V2 is provided to fourth node N4. Ninth transistor T9 turns on, and the received high-level voltage from first node N1 is provided to third node N3. Eleventh transistor T11 turns on, and the received high-level third voltage V3 is provided to the first signal output terminal as the first output signal OUTPUT1. Thirteenth transistor T13 turns on, and the received high-level third voltage V3 is provided to the second signal output terminal as the second output signal OUTPUT2. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off.

[0102] Embodiments of this disclosure also provide a gate drive circuit composed of shift registers. FIG12 shows a schematic diagram of a gate drive circuit 55 according to an embodiment of this disclosure. As shown in FIG12, the gate drive circuit 55 may include a plurality of shift registers. Any one or more shift registers may adopt the structure of shift registers 5, 15, 20, 25, 30, 45 or 50 provided in the embodiments of this disclosure or variations thereof. FIG12 only schematically shows the first three shift registers, namely, the first shift register SR_1 corresponding to the first row of pixels, the second shift register SR_2 corresponding to the second row of pixels, and the third shift register SR_3 corresponding to the third row of pixels.

[0103] The first signal output of the Nth stage shift register is coupled to the signal input of the (N+1)th stage shift register, where N is a positive integer. As shown in Figure 12, the signal input of the first shift register SR_1 receives the input signal STV_1 from the input signal line INPUT. The first signal output of the first shift register SR_1 is coupled to the signal input of the second shift register SR_2 to provide the input signal STV_2. The first signal output of the second shift register SR_2 is coupled to the signal input of the shift register SR_3 to provide the input signal STV_3.

[0104] In embodiments of this disclosure, the gate drive circuit 55 further includes a first clock signal line CLK_A, a second clock signal line CLK_B, a first voltage line VG1, a second voltage line VL1, a third voltage line VG2, and a fourth voltage line VL2. For odd-row shift registers, the first clock signal line CLK_A is coupled to the first clock signal terminal of the shift register to provide a first clock signal CK. The second clock signal line CLK_B is coupled to the second clock signal terminal of the shift register to provide a second clock signal CB. For even-row shift registers, the first clock signal line CLK_A is coupled to the second clock signal terminal of the shift register to provide a second clock signal CB. The second clock signal line CLK_B is coupled to the first clock signal terminal of the shift register to provide the first clock signal CK. Those skilled in the art should understand that the coupling relationship between the odd-row and even-row shift registers and the clock signal terminals can be interchanged. Additionally, the first voltage line VG1 is coupled to the first voltage terminal of all shift registers to provide a first voltage V1. The second voltage line VL1 is coupled to the second voltage terminal of all shift registers to provide the second voltage V2. The third voltage line VG2 is coupled to the third voltage terminal of all shift registers to provide the third voltage V3. The fourth voltage line VL2 is coupled to the fourth voltage terminal of all shift registers to provide the fourth voltage V4.

[0105] Alternatively, in other embodiments of this disclosure, the gate drive circuit 55 includes a plurality of shift registers 35 or 40. The gate drive circuit further includes a fifth voltage line VL3 to provide a fifth voltage V3.

[0106] Embodiments of this disclosure also provide a display device including the gate driving circuit described above. FIG13 illustrates a display device according to an embodiment of this disclosure. As shown in FIG13, the display device 60 includes a gate driving circuit 55. In embodiments, the display device can be any product or component with display function, such as a liquid crystal panel, liquid crystal television, monitor, OLED panel, OLED television, electronic paper display device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, etc.

[0107] Furthermore, embodiments of this disclosure also provide a method for driving a shift register. Figure 14 shows a schematic flowchart of a method for driving a shift register according to an embodiment of this disclosure. The shift register can be any applicable shift register based on embodiments of this disclosure.

[0108] In step 1100, in the first stage t1, a first voltage V1 is provided to the second node N2, and a first voltage difference related to the voltage of the second node N2 is stored and saved. According to the second clock signal CB, a second voltage V2 is provided to the first node N1 and the third node N3. In an embodiment, the first control circuit 200 provides a high-level first voltage V1 to the second node N2. The first voltage difference is the voltage difference between the third voltage V3 and the high-level voltage of the second node N2. In some embodiments of this disclosure, for example, the shift register is one of the shift registers 5, 15, 25, 35, and 45 described above, and the first voltage difference can be the voltage difference between the third voltage V3 and the second node N2. The first signal output terminal can output the second voltage V2 as the first output signal OUTPUT1. The second signal output terminal can output a fourth voltage V4 as the second output signal OUTPUT2. In an embodiment, the first output signal OUTPUT1 is used as a cascade transmission signal, and the second output signal OUTPUT2 is used as a scan signal.

[0109] In step 1200, in the second stage t2, maintaining the first voltage difference, a second voltage V2 is output at the first output signal terminal as the first output signal OUTPUT1, and a fourth voltage V4 is output at the second signal output terminal as the second output signal OUTPUT2. In some embodiments of this disclosure, for example, the shift register is one of the shift registers 5, 15, 25, 35, and 45 described above, and the voltage of the second node N2 is maintained at a high level. The voltage of the fourth node N4 is maintained at a high level. The first signal output terminal can continuously output the second voltage V2 as the first output signal. The second signal output terminal can continuously output the fourth voltage V4 as the second output signal OUTPUT2.

[0110] In step 1300, at the third stage t3, the second voltage V2 is provided to the first node N1 and the third node N3 to reset them. In this embodiment, the first signal output terminal can continuously output the second voltage V2 as the first output signal OUTPUT1. The second signal output terminal can continuously output the fourth voltage V4 as the second output signal OUTPUT2.

[0111] In step 1400, the input signal STV is provided to the first node N1 and the third node N3, and the second voltage V2 is provided to the second node N2 and the fourth node N4 to reset the second node N2 and the fourth node N4. The third voltage V3 is then output at the first output signal terminal as the first output signal OUTPUT1, and at the second signal output terminal as the second output signal OUTPUT2. In this embodiment, the first control circuit 200 provides the low-level second voltage V2 to the second node N2, and the second control circuit 500 provides the second voltage V2 to the fourth node N4.

[0112] Those skilled in the art will understand that although the above steps are described in sequence, they do not constitute a limitation on the order of the methods, and the embodiments of this disclosure can also be implemented in any other suitable order.

[0113] The foregoing has described several embodiments of this disclosure in detail, but the scope of protection of this disclosure is not limited thereto. Obviously, those skilled in the art can make various modifications, substitutions, or variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A shift register, comprising an input circuit, a first control circuit, a reset circuit, a holding circuit, a second control circuit, a third control circuit, a first output circuit, and a second output circuit, wherein: The input circuit is coupled to an input signal terminal, a first clock signal terminal, and a first node, and is configured to provide an input signal from the input signal terminal to the first node according to a first clock signal from the first clock signal terminal; The first control circuit is coupled to a first voltage terminal, a second clock signal terminal, a second voltage terminal, the input signal terminal, and a second node, and is configured to control the voltage of the second node based on a first voltage from the first voltage terminal, the second clock signal, a second voltage from the second voltage terminal, and the input signal. The reset circuit is coupled to the second node, the second voltage terminal, the second clock signal terminal and the first node, and is configured to reset the first node according to the voltage of the second node, the second clock signal from the second clock signal terminal and the second voltage; The holding circuit is coupled to the second clock signal terminal and the second node, and is configured to hold the voltage of the second node according to the second clock signal; The second control circuit is coupled to the second node, the second clock signal terminal, the second voltage terminal, the first node, and the fourth node, and is configured to control the voltage of the fourth node according to the voltage of the first node, the voltage of the second node, the second clock signal, and the second voltage. The third control circuit is coupled to the first node, the third node and the third voltage terminal, and is configured to control the voltage of the third node according to the third voltage and the voltage of the first node; The first output circuit is coupled to the fourth node, the second voltage terminal, the first signal output terminal, the third node, and the third voltage terminal, and is configured to provide a first output signal through the first signal output terminal based on the voltage of the fourth node, the second voltage, the voltage of the third node, and the third voltage; The second output circuit is coupled to the fourth node, the third voltage terminal, the second signal output terminal, the third node, and the fourth voltage terminal, and is configured to provide a second output signal through the second signal output terminal based on the voltage of the fourth node, the third voltage, the voltage of the third node, and the fourth voltage from the fourth voltage terminal.

2. The shift register according to claim 1, wherein, The first output signal is used as a cascade transmission signal, and the second output signal is used as a scan signal.

3. The shift register according to claim 2, wherein the shift register alternatively includes the input circuit, the first control circuit, the reset circuit, the second control circuit, the third control circuit, the first output circuit, and the second output circuit, wherein: The first control circuit is alternatively coupled to the third voltage terminal, the second clock signal terminal, and the second voltage terminal. The input signal terminal and the second node are configured to control the voltage of the second node based on the third voltage, the second clock signal, the second voltage, and the input signal. The second control circuit is alternatively coupled to the first node, the second node and the second voltage terminal, and is configured to control the voltage of the second node according to the voltage of the first node and the second voltage. as well as The second node coincides with the fourth node.

4. The shift register according to any one of claims 1 to 3, wherein the first voltage and the third voltage are high-level voltages, and the first voltage is greater than or equal to the third voltage, and the second voltage and the fourth voltage are low-level voltages, and the second voltage is less than or equal to the fourth voltage.

5. The shift register according to claim 4, wherein, The first voltage is approximately 14V, the second voltage is approximately -9V, the third voltage is approximately 8V, and the fourth voltage is approximately -6V.

6. The shift register according to any one of claims 1 to 3, wherein, The input circuit includes a first transistor, the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the first node.

7. The shift register according to claim 1, wherein, The first control circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the second node. The control electrode of the third transistor is coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node.

8. The shift register according to claim 3, wherein, The first control circuit includes a second transistor, a third transistor, and a fourth capacitor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the seventh node. The control electrode of the third transistor is coupled to the seventh node, the first electrode of the third transistor is coupled to the third voltage terminal, and the second electrode of the third transistor is coupled to the second node. The first plate of the fourth capacitor is coupled to the second clock signal terminal, and the second plate of the fourth capacitor is coupled to the seventh node.

9. The shift register according to any one of claims 1 to 3, wherein, The reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, the second electrode of the fourth transistor is coupled to the fifth node, the control electrode of the fifth transistor is coupled to the second clock signal terminal, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the first node.

10. The shift register according to claim 1, wherein, The holding circuit includes a first capacitor, a first plate of the first capacitor being coupled to the third voltage terminal, and a second plate of the first capacitor being coupled to the second node.

11. The shift register according to claim 1, wherein, The second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor. The control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the sixth node. The control electrode of the seventh transistor is coupled to the second clock signal terminal, the first electrode of the seventh transistor is coupled to the sixth node, and the second electrode of the seventh transistor is coupled to the fourth node. The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the fourth node.

12. The shift register according to claim 2, wherein, The second control circuit includes an eighth transistor, the control electrode of which is coupled to the first node, the first electrode of which is coupled to the second clock signal terminal, and the second electrode of which is coupled to the second node.

13. The shift register according to any one of claims 1 to 3, wherein, The third control circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to the third voltage terminal, the first electrode of the ninth transistor is coupled to the first node, and the second electrode of the ninth transistor is coupled to the third node.

14. The shift register according to claim 13, wherein, The control electrode of the ninth transistor is alternatively coupled to the first voltage terminal.

15. The shift register according to claim 1, wherein, The first output circuit includes a tenth transistor, an eleventh transistor, and a second capacitor. The control electrode of the tenth transistor is coupled to the fourth node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the first signal output terminal. The control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the third voltage terminal, and the second electrode of the eleventh transistor is coupled to the first signal output terminal. The first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to the third node.

16. The shift register according to claim 2, wherein, The first output circuit includes a tenth transistor, an eleventh transistor, a second capacitor, and a fifth capacitor. The control electrode of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the first signal output terminal. The control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the third voltage terminal, and the second electrode of the eleventh transistor is coupled to the first signal output terminal. The first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to the third node. The first plate of the fifth capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to the second node.

17. The shift register according to claim 15 or 16, wherein, The tenth transistor is a dual-gate transistor.

18. The shift register according to claim 17, wherein, The tenth transistor includes a third terminal, and the first output circuit further includes a fourteenth transistor, wherein the control terminal of the fourteenth transistor is coupled to the first signal output terminal, the first terminal of the fourteenth transistor is coupled to the first voltage terminal, and the second terminal of the fourteenth transistor is coupled to the third terminal of the tenth transistor.

19. The shift register according to claim 15 or 16, wherein, The tenth transistor has a bottom control electrode coupled to a fifth voltage terminal, wherein a fifth voltage from the fifth voltage terminal is lower than the second voltage and the second voltage is lower than the fourth voltage.

20. The shift register according to claim 1, wherein, The second output circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor. The control electrode of the twelfth transistor is coupled to the fourth node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal. The first plate of the third capacitor is coupled to the second signal output terminal, and the second plate of the third capacitor is coupled to the third node.

21. The shift register according to claim 2, wherein, The second output circuit includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal.

22. The shift register according to claim 1, wherein: The input circuit includes a first transistor, the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the first node. The first control circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the second node. The control electrode of the third transistor is coupled to the second clock signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node. The reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the fifth node. Point coupling: the control terminal of the fifth transistor is coupled to the second clock signal terminal; the first terminal of the fifth transistor is coupled to the fifth node; and the second terminal of the fifth transistor is coupled to the first node. The holding circuit includes a first capacitor, a first plate of the first capacitor being coupled to the third voltage terminal, and a second plate of the first capacitor being coupled to the second node; The second control circuit includes a sixth transistor, a seventh transistor, and an eighth transistor, wherein the control electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the sixth node; the control electrode of the seventh transistor is coupled to the second clock signal terminal, the first electrode of the seventh transistor is coupled to the sixth node, and the second electrode of the seventh transistor is coupled to the fourth node; the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second voltage terminal, and the second electrode of the eighth transistor is coupled to the fourth node. The third control circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to the third voltage terminal, the first electrode of the ninth transistor is coupled to the first node, and the second electrode of the ninth transistor is coupled to the third node; The first output circuit includes a tenth transistor, an eleventh transistor, and a second capacitor. The control electrode of the tenth transistor is coupled to the fourth node; the first electrode of the tenth transistor is coupled to the second voltage terminal; the second electrode of the tenth transistor is coupled to the first signal output terminal; the control electrode of the eleventh transistor is coupled to the third node; the first electrode of the eleventh transistor is coupled to the third voltage terminal; the second electrode of the eleventh transistor is coupled to the first signal output terminal; the first plate of the second capacitor is coupled to the first signal output terminal; and the second plate of the second capacitor is coupled to the third node. The second output circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor. The control electrode of the twelfth transistor is coupled to the fourth node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal. The first plate of the third capacitor is coupled to the second signal output terminal, and the second plate of the third capacitor is coupled to the third node. The first plate of the first capacitor is coupled to the third voltage terminal, and the second plate of the first capacitor is coupled to the second node.

23. The shift register according to claim 3, wherein, The input circuit includes a first transistor, the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the first node. The first control circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the input signal terminal, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the seventh node. The control electrode of the third transistor is coupled to the seventh node, the first electrode of the third transistor is coupled to the third voltage terminal, and the second electrode of the third transistor is coupled to the second node. The first plate of the fourth capacitor is coupled to the second clock signal terminal, and the second plate of the fourth capacitor is coupled to the seventh node. The reset circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, the second electrode of the fourth transistor is coupled to the fifth node, the control electrode of the fifth transistor is coupled to the second clock signal terminal, the first electrode of the fifth transistor is coupled to the fifth node, and the second electrode of the fifth transistor is coupled to the first node. The second control circuit includes an eighth transistor, the control electrode of which is coupled to the first node, the first electrode of which is coupled to the second voltage terminal, and the second electrode of which is coupled to the second node; The third control circuit includes a ninth transistor, the control electrode of the ninth transistor is coupled to the third voltage terminal, the first electrode of the ninth transistor is coupled to the first node, and the second electrode of the ninth transistor is coupled to the third node; The first output circuit includes a tenth transistor, an eleventh transistor, a second capacitor, and a fifth capacitor. The control electrode of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the first signal output terminal. The control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the third voltage terminal, and the second electrode of the eleventh transistor is coupled to the first signal output terminal. The first plate of the second capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to the third node. The first plate of the fifth capacitor is coupled to the first signal output terminal, and the second plate of the second capacitor is coupled to the second node. as well as The second output circuit includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the second node, the first electrode of the twelfth transistor is coupled to the fourth voltage terminal, and the second electrode of the twelfth transistor is coupled to the second signal output terminal. The control electrode of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the third voltage terminal, and the second electrode of the thirteenth transistor is coupled to the second signal output terminal.

24. A gate driving circuit comprising a plurality of cascaded shift registers as described in any one of claims 1 to 23, wherein the signal output terminal of the Nth-stage shift register is coupled to the input terminal of the (N+1)th-stage shift register, wherein, N is a positive integer.

25. A display device comprising the gate driving circuit as described in claim 24.

26. A method for driving a shift register as described in any one of claims 1 to 23 comprises: In the first stage, a first voltage is provided to the second node, and the first voltage difference related to the voltage of the second node is stored and saved; In the second stage, the first voltage difference is maintained, a second voltage is output at the first output signal terminal as the first output signal, and a fourth voltage is output at the second signal output terminal as the second output signal. In the third stage, the second voltage is supplied to the first node and the third node to reset the first node and the third node; as well as In the fourth stage, the input signal is provided to the first node and the third node, the second voltage is provided to the second node and the fourth node to reset the second node and the fourth node, and the third voltage is output at the first output signal terminal as the first output signal, and the third voltage is output at the second signal output terminal as the second output signal.

Images