Storage and calculation integrated electroencephalogram fatigue real-time feature extraction sensor device

Abstract

The invention relates to the technical field of biomedical signal detection and processing, particularly discloses a storage and calculation integrated electroencephalogram fatigue real-time feature extraction sensor device, and aims to solve the problems of high system delay, insufficient durability of a resistive random access memory and large power consumption volume caused by dependence on an additional chip in the prior art. The device comprises an electroencephalogram signal acquisition and preprocessing module, a storage and calculation integrated feature extraction array module, a specific frequency band filter coefficient write-in module, a self-adaptive durability enhancement control module and a feature judgment and output interface module. The EEG features are calculated in parallel in a simulation domain through the storage and calculation integrated core module, the operation parameters of the resistive random access memory are dynamically optimized in combination with the self-adaptive control module, real-time feature extraction lower than 10 ms is achieved, the durability of the device is improved to more than ten millions of times, and the power consumption and the size of the system are remarkably reduced.

Description

Technical Field

[0001] This invention belongs to the field of biomedical signal detection and processing technology, specifically relating to a storage-computing integrated EEG fatigue real-time feature extraction sensor device. Background Technology

[0002] Electroencephalogram (EEG) signal processing and neuromorphic computing are important research directions at the intersection of biomedical engineering and artificial intelligence. Their core objective is to achieve efficient and real-time analysis and feature extraction of bioelectrical signals such as EEG by simulating the information processing mechanisms of biological nervous systems. Among these, in-memory computing architectures based on resistive random access memory (RRAM) are becoming a key technological path to overcome the bottlenecks of traditional von Neumann architectures due to their potential in integrating parallel computing and data storage.

[0003] Among these applications, real-time EEG fatigue detection for scenarios such as driver fatigue and neurological disease monitoring is a specific and crucial technological direction within the aforementioned fields. This technology aims to achieve immediate early warning of transient events such as microsleep by continuously monitoring changes in fatigue-related features in EEG signals. Its basic objective is to rapidly and accurately extract key fatigue indicators, such as the theta / alpha wave power ratio, from non-stationary, low signal-to-noise ratio raw EEG signals.

[0004] Existing technologies primarily employ a discrete "acquisition-processing-storage" architecture. This means that after EEG signals are acquired via electrodes, they sequentially undergo analog front-end amplification, analog-to-digital conversion, microcontroller feature calculation, and finally, are written to an independent memory. This architecture suffers from significant technical bottlenecks: First, the serial processing across multiple stages results in excessively high system latency, with measured total latency exceeding 100ms. However, the window for EEG feature changes related to microsleep events lasts only a few hundred milliseconds, making instantaneous capture difficult with traditional methods, leading to a high false negative rate. Second, although resistive random access memory (RRAM) is introduced as a storage medium, its durability is severely insufficient when frequently writing non-stationary EEG signals, with the number of write cycles far below practical application requirements. Furthermore, existing solutions rely on digital filters to suppress noise such as electromyography (EMG), requiring additional digital signal processing chips, increasing system power consumption and size, and limiting their application in wearable devices. Therefore, a sensor device for extracting EEG fatigue features that deeply integrates signal processing and storage, fundamentally improving real-time performance and device durability, is desired. Summary of the Invention

[0005] The purpose of this invention is to provide a memory-in-memory integrated EEG fatigue real-time feature extraction sensor device to solve the technical contradictions of existing discrete architectures in processing EEG signals, such as excessive system latency, insufficient durability of resistive random access memory, and increased power consumption and size due to reliance on additional digital processing chips.

[0006] The technical solution of the present invention is a storage-computing integrated EEG fatigue real-time feature extraction sensor device, the device comprising:

[0007] The EEG signal acquisition and preprocessing module is used to acquire raw EEG signals from the scalp of an organism and perform primary physical conditioning and noise suppression on the signals.

[0008] The in-memory computing feature extraction array module is used to receive the preprocessed analog signal output by the EEG signal acquisition and preprocessing module, and based on the physical characteristics of the resistive random access memory cross array, it performs signal transformation and feature calculation in parallel in the analog domain, and directly outputs fatigue feature values ​​in digital form.

[0009] The specific frequency band filter coefficient writing module is used to precisely write a set of conductance values ​​corresponding to the filter coefficients of a specific frequency band into a designated resistive random access memory unit through electrical pulse programming.

[0010] An adaptive durability enhancement control module is used to monitor the working status of the in-memory computing feature extraction array module in real time and dynamically adjust the operating parameters of its internal resistive switching memory to optimize its durability.

[0011] The feature decision and output interface module is used to receive fatigue feature values ​​output by the in-memory computing feature extraction array module, make state decisions based on preset fatigue thresholds, and generate corresponding control or warning signals for external output.

[0012] Furthermore, the EEG signal acquisition and preprocessing module includes a high-impedance input stage, a programmable gain amplifier, and an analog domain common-mode noise suppression unit.

[0013] The high-impedance input stage is directly connected to the dry or wet electrode, and its input impedance is greater than 1 GΩ, which is used to reduce signal pickup attenuation.

[0014] The programmable gain amplifier has an adjustable gain range from 100x to 10,000x, and is used to amplify EEG signals from the µV level to the V level.

[0015] The analog domain common-mode noise suppression unit adopts active shielding drive technology. It generates a cancellation signal in phase with the common-mode noise through a feedback loop and injects it into the reference ground, thereby directly suppressing 50Hz power frequency interference and common-mode electromyographic noise at the analog front end. This unit can improve the common-mode rejection ratio to over 120dB.

[0016] Furthermore, the in-memory computing feature extraction array module is the core computing unit of the device, and its core is a 32x32 resistive random access memory (RRAM) in-memory computing crossover array. The row and column lines of this crossover array are connected via gating transistors, and each crossover point represents a RRAM cell. The specific operation of this module is as follows:

[0017] The pre-processed simulated EEG signal is used as the input voltage and applied to a specific row line WL of the cross array. The cross array is pre-programmed with electrical pulses via a specific frequency band filter coefficient writing module, precisely writing a set of conductance values ​​corresponding to the specific frequency band filter coefficients into designated resistive random access memory (RRAM) cells. When the input voltage is applied, the current flowing through each column line BL is the sum of the product of the input voltage and the conductance values ​​of all corresponding cells in the activated rows of that column. This physical process directly performs the convolution operation between the input signal and the filter coefficients in the analog domain. Specifically, to extract the power ratio of theta waves to alpha waves, a key indicator of EEG fatigue, this module incorporates two parallel subarrays.

[0018] The conductance mode of the first subarray is configured to be equivalent to a 4Hz to 8Hz bandpass filter for extracting the theta wave component.

[0019] The conductance mode of the second subarray is configured to be equivalent to an 8Hz to 13Hz bandpass filter for extracting the alpha wave component.

[0020] The total current signal output from each column is converted into a voltage signal by a transimpedance amplifier integrated at the end of the array, then the instantaneous power is obtained by an analog multiplier circuit, and finally integrated by an analog integrator within a 250ms time window to obtain the average power values ​​of the θ wave and α wave.

[0021] The two power values ​​are fed into an analog divider circuit, which directly calculates and outputs the digital characteristic value of the power ratio θ / α. The entire process from signal input to characteristic value output is completed continuously in the analog domain, with a calculation delay of less than 10ms.

[0022] Furthermore, the adaptive durability enhancement control module includes an operating parameter dynamic adjustment unit and a state monitoring feedback unit. The state monitoring feedback unit continuously monitors the write verification current and read current fluctuations, as well as the cumulative number of operations, of the resistive switching memory cells in the in-memory computing feature extraction array module. Based on the data from the state monitoring feedback unit, the operating parameter dynamic adjustment unit dynamically adjusts the write pulse parameters used when programming the conductance value of the resistive switching memory. Specifically, the adjustment strategy is as follows: when the cumulative number of operations is less than 1 million, a standard amplitude of 3V and a pulse width of 100ns is used for the write pulse. After the cumulative number of operations reaches 1 million, for every 100,000 operations, the amplitude of the write pulse is reduced by 0.05V, while the pulse width is increased by 10ns. This strategy aims to gradually adopt gentler programming conditions as the device ages, reducing the electrical stress impact on the resistive switching dielectric layer, thereby increasing the effective durability of the device from less than 100,000 operations to over 10 million operations.

[0023] Furthermore, the feature decision and output interface module includes a digital comparator, a state latch, and a standard communication interface. The digital comparator compares the real-time θ / α power ratio value output by the in-memory feature extraction array module with a preset fatigue threshold, which is set to 2.5. When the θ / α power ratio continuously exceeds this threshold for 500ms, the digital comparator outputs a high-level trigger signal. The state latch receives this trigger signal and latches it as a fatigue state flag. The standard communication interface is a low-power Bluetooth module or a serial peripheral interface, used to package the fatigue state flag and the original θ / α power ratio data into a data frame conforming to a standard protocol and send it to an external host or display alarm unit.

[0024] Furthermore, as an embodiment of the present invention, the analog multiplier circuit in the in-memory computing feature extraction array module is implemented using a four-quadrant multiplier structure based on the subthreshold characteristics of field-effect transistors. This structure utilizes the exponential relationship between the gate-source voltage and leakage current of paired transistors in the subthreshold region, and through a voltage addition circuit configuration, achieves an approximate calculation of the product of two input voltages, thereby completing the power calculation function under extremely low operating current. Furthermore, as an embodiment of the present invention, the EEG signal acquisition and preprocessing module also includes an analog high-pass filter unit with a cutoff frequency set to 0.5Hz, used to filter out slow baseline drift signals caused by electrode contact with skin. This high-pass filter unit is implemented using a Saleen-Kai topology structure composed of a passive resistor-capacitor network and an operational amplifier, ensuring the elimination of low-frequency interference in the early stages of the analog domain.

[0025] Furthermore, as one embodiment of the present invention, the device is integrated using system-in-package (SiP) technology. The analog circuitry of the EEG signal acquisition and preprocessing module and the in-memory computing feature extraction array module is fabricated on the same chip using a 40nm CMOS process. The resistive random access memory (RRAM) cross-array in the in-memory computing feature extraction array module is integrated between metal interconnect layers using a back-end process. The digital circuitry of the adaptive durability enhancement control module and the feature decision and output interface module is fabricated on another chip using a 55nm CMOS process. These two chips are stacked in three dimensions and vertically interconnected using through-silicon via (TSV) technology, and are jointly packaged within a ball grid array package with a size no larger than 5mm x 5mm, forming a complete miniaturized sensor system.

[0026] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0027] By constructing a memory-based feature extraction array module with a resistive random access memory (RRAM) crossover array at its core, the feature extraction computation of EEG signals is transformed from traditional serial processing in the digital domain to parallel processing in the analog domain using physical laws. The pre-processed signal is directly input into this module, where analog multiplication, addition, and transformation are performed using pre-programmed conductance modes, and digital feature values ​​are directly output via integrated analog circuitry. This architecture completely eliminates the latency caused by multiple serial steps such as analog-to-digital conversion, digital filtering, and microcontroller computation, reducing the total latency of feature extraction from over 100ms to less than 10ms. This order-of-magnitude improvement enables the device to capture and respond in real time to transient EEG feature changes related to microsleep events, lasting only a few hundred milliseconds, fundamentally solving the problem of high false negative rates caused by excessive latency in existing technologies.

[0028] A dedicated adaptive durability enhancement control module was designed to proactively address the durability challenges of resistive random access memory (RRAM) when frequently writing non-stationary EEG signals through a closed-loop control mechanism of state monitoring and dynamic parameter adjustment. This module optimizes the amplitude and pulse width of the write pulses in real time based on the cumulative number of operations performed on the device. Standard parameters are used in the early stages of the device's lifespan to ensure programming accuracy, while automatically switching to gentler programming conditions as the device ages to reduce electrical stress damage. This adaptive strategy significantly improves the effective durability of the RRAM cell in EEG signal processing applications from less than 100,000 cycles to over 10 million cycles, meeting the application requirements for long-term, continuous monitoring and solving the core bottleneck of insufficient memory durability in existing technologies.

[0029] The EEG signal acquisition and preprocessing module integrates an analog domain common-mode noise suppression unit and an analog high-pass filter unit, which directly suppress power frequency interference, baseline drift and common-mode electromyography noise at the very front of the signal chain, i.e. in the analog domain.

[0030] This design eliminates the reliance on subsequent digital signal processing chips, significantly reducing the overall power consumption and size of the system while ensuring high common-mode rejection ratio and effective filtering. By combining system-in-package (SiP) technology to integrate analog, in-memory computing, and digital control units in three dimensions, a miniaturized, low-power integrated sensor device is ultimately realized, providing a feasible technical path for achieving high-performance real-time EEG fatigue monitoring in space- and power-constrained scenarios such as wearable devices and implantable medical devices. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall technical architecture of the in-memory computing integrated EEG fatigue real-time feature extraction sensor device proposed in this invention.

[0032] Figure 2 This is a schematic diagram of the core principle framework of the in-memory computing integrated feature extraction array module in this invention; Detailed Implementation

[0033] The overall technical architecture of the in-memory computing integrated EEG fatigue real-time feature extraction sensor device proposed in this invention is shown in the attached figure. Figure 1 As shown, the device consists of five highly coupled modules: an EEG signal acquisition and preprocessing module, a storage-and-computation integrated feature extraction array module, a specific frequency band filter coefficient writing module, an adaptive durability enhancement control module, and a feature decision and output interface module. These modules are tightly connected via analog or digital signal paths, forming a complete closed-loop processing chain from raw bioelectrical signal input to fatigue state determination output. The entire system achieves integrated signal acquisition, feature computation, and state decision-making at the physical level, eliminating the need for external general-purpose processors or dedicated digital signal processing chips, thus achieving significant optimizations in latency, power consumption, and size.

[0034] First, the EEG signal acquisition and preprocessing module, as the front-end unit of the system, directly establishes an electrical connection with the dry or wet electrodes attached to the scalp of the organism. The core task of this module is to acquire, amplify, and perform preliminary noise suppression of the weak raw EEG signals before they enter the subsequent processing stages.

[0035] Because EEG signal amplitudes are typically in the range of 10µV to 100µV and have extremely high source impedance, this module must have extremely high input impedance to avoid signal attenuation. Therefore, its high-impedance input stage employs a differential input structure based on field-effect transistors, with an input impedance design value greater than 1GΩ, ensuring a signal pickup efficiency of no less than 99% under typical electrode-skin contact impedance (typically 5kΩ to 50kΩ). The common-mode input range of this input stage covers 0 to 3.3V to be compatible with electrode bias conditions under different power supply environments.

[0036] Following the high-impedance input stage is the programmable gain amplifier. This amplifier employs a multi-stage chopper-stabilized operational amplifier architecture to suppress 1 / f noise and improve DC accuracy. Its gain can be adjusted in 6dB steps within the range of 100 to 10000 times via a digital control word, corresponding to a 7-bit binary gain control code. The gain selection logic is determined by the characteristic decision and output interface module based on dynamic feedback of the current signal-to-noise ratio: when the detected signal amplitude is consistently below 50µV, the gain is automatically increased to 10000 times; when the signal amplitude exceeds 500µV, the gain is gradually reduced to prevent saturation in subsequent stages. The amplified signal amplitude is stabilized within the range of 0.5V to 2.5V, adapting to the dynamic range requirements of subsequent analog processing circuits.

[0037] After signal amplification, the analog domain common-mode noise suppression unit immediately intervenes. This unit employs active shielding drive technology, with its core being a high-bandwidth differential instrumentation amplifier coupled with a negative feedback loop. This loop detects the common-mode components of the two input signals in real time and generates a cancellation voltage with the same phase and amplitude, which is injected into the reference ground node through a low-output-impedance buffer. This mechanism effectively disrupts the propagation path of common-mode noise in the signal path, showing a significant suppression effect, especially against 50Hz power frequency interference and its harmonics. In actual testing, under conditions with 1V peak-to-peak common-mode interference, this unit can improve the common-mode rejection ratio to over 120dB, far exceeding the 80dB level of traditional passive shielding solutions.

[0038] In addition, the module integrates an analog high-pass filter unit with a precisely set cutoff frequency of 0.5Hz to filter out slow baseline drift caused by electrode polarization or sweat diffusion. This high-pass filter employs a Salen-Kay second-order topology, consisting of two precisely matched operational amplifiers, four thin-film resistors, and two high-stability multilayer ceramic capacitors. Its passband ripple is less than 0.1dB, and its stopband attenuation reaches -40dB at 0.1Hz, ensuring that low-frequency physiological information such as delta waves (0.5Hz to 4Hz) is preserved while completely eliminating the effects of DC offset.

[0039] The analog signal processed as described above is sent to the in-memory computing feature extraction array module. This module is the core technology of this invention, and its internal structure and principle are shown in the attached figure. Figure 2 As shown, this module is built upon a resistive random access memory (RRAM) crossover array with a size of 32 rows × 32 columns. Each crossover point integrates an independent RRAM cell. These cells are connected to the row and column lines respectively via gating transistors, which are manufactured using a low-leakage-current deep submicron CMOS process, with a turn-off leakage current of less than 1 pA. During system initialization, two sets of preset filter coefficients are written into two independent subarray regions via external programming pulses. The first subarray is configured as an equivalent 4Hz to 8Hz bandpass filter for extracting the theta wave component; the second subarray is configured as an equivalent 8Hz to 13Hz bandpass filter for extracting the alpha wave component. The quantization precision of the filter coefficients is 8 bits, corresponding to a programming resolution of 256 levels for the RRAM conductance values, with a conductance range covering 1 µS to 100 µS.

[0040] When the preprocessed simulated EEG signal is applied as an input voltage to a specific row, the total current flowing through each column is the algebraic sum of the products of the conductance values ​​of all activated cells in that column and the input voltage, thus realizing the convolution operation between the input signal and the filter coefficients. For example, if at a certain moment, a voltage V_in(t) is applied to the i-th row, then the output current I_j(t) of the j-th column can be expressed as:

[0041]

[0042] Where G_{ij} is the conductance value of the resistive random access memory cell in the i-th row and j-th column.

[0043] The analog current signal output from each column is then fed into a transimpedance amplifier integrated at the end of the array. This amplifier employs a folded cascode structure, with a feedback resistor being a precision laser-tuned polysilicon resistor with a resistance of 1MΩ. It linearly converts the current signal into a voltage signal with a conversion gain of 1V / uA.

[0044] The converted voltage signal is fed into an analog multiplier circuit. This circuit is based on the exponential current-voltage characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) in the subthreshold region. Specifically, a four-quadrant multiplier is constructed using four matched N-type MOSFETs, where the gates of two transistors receive the voltage signal to be squared, and the gates of the other two transistors receive a fixed bias. By subtracting the drain currents and converting the result to voltage via a load resistor, an output proportional to the square of the input voltage can be obtained. This structure can achieve squaring operations within an input range of 0.1mV to 1V with a nonlinearity error of less than 2%, under conditions of a power supply voltage of 1.8V and a quiescent current of only 200nA.

[0045] The squared instantaneous power signal is fed into an analog integrator. This integrator employs a Miller integrator architecture, with a high-density metal-insulator-metal capacitor of 10 pF. The integration time constant is dynamically set by a digitally controlled switched capacitor network. In this embodiment, the integration window is fixed at 250 f, corresponding to the standard timescale of fatigue assessment. The integrator resets every 250 ms, with the reset signal provided synchronously by the feature decision and output interface module to ensure time alignment of the theta and alpha wave power calculations. The integrated outputs are the average power values ​​within this time window, denoted as P_θ and P_α, respectively.

[0046] P_θ and P_α are fed into an analog divider circuit. This circuit is also built based on the logarithmic-anti-logarithmic characteristics of subthreshold transistors, and performs the division operation by first taking the logarithm of the two inputs, subtracting them, and then taking the anti-logarithm. Its output is the θ / α power ratio, a key fatigue indicator.

[0047] The output of the analog divider is connected to a high-speed comparator analog-to-digital converter (ADC). This converter is a 6-bit resolution, 4kHz sampling rate successive approximation register structure that quantizes the analog θ / α ratio into a digital value and outputs it as a serial data stream to the feature decision and output interface module. The entire processing chain from analog signal input to digital feature value output is completed continuously in the analog domain. The end-to-end calculation delay has been measured to be less than 10ms, meeting the real-time requirements.

[0048] Meanwhile, the adaptive durability enhancement control module continuously monitors the health status of the in-memory computing feature extraction array module. This module comprises two sub-units: a status monitoring feedback unit and an operating parameter dynamic adjustment unit. The status monitoring feedback unit collects three key parameters in real time through sensing circuits embedded around the cross array: the verification current after each write operation, the standard deviation of current fluctuations during periodic read operations, and the cumulative number of operations for each resistive switching memory cell. The verification current is used to determine whether programming is successful, and its target value is set within ±5% of the corresponding target conductance value; the standard deviation of current fluctuations reflects the stability of the device state, and if it exceeds 10%, it is considered an early failure symptom; the cumulative number of operations is recorded by a 32-bit counter, which increments after each write pulse is applied.

[0049] The dynamic parameter adjustment unit dynamically adjusts the amplitude and pulse width of the write pulse based on the aforementioned monitoring data. Initially, the write pulse is a standard square wave with an amplitude of 3V and a pulse width of 100ns. When the cumulative number of operations of any unit reaches 1 million, the system activates an adaptive strategy: thereafter, for every additional 100,000 operations, the write pulse amplitude decreases by 0.05V, while the pulse width increases by 10ns. For example, at 1.1 million cumulative operations, the pulse parameters are adjusted to 2.95V and 110ns; at 2 million operations, they are adjusted to 2.5V and 200ns, and so on. The physical basis of this strategy is that as the resistive switching dielectric layer undergoes multiple electrochemical migrations, its defect state density increases, making it easier for conductive filaments to form under the same electric field. Therefore, reducing the electric field strength (by reducing the voltage) and extending the action time (by increasing the pulse width) can significantly reduce the risk of dielectric breakdown while maintaining a sufficient programming window. Accelerated life testing has verified that, with this strategy, the effective durability of the resistive random access memory (RRAM) unit in EEG signal feature extraction applications has increased from less than 100,000 cycles in traditional solutions to more than 10 million cycles, which is sufficient to support the device to work continuously for more than 5 years.

[0050] Finally, the feature decision and output interface module receives the digital value of the θ / α power ratio from the in-memory feature extraction array module. This module incorporates a digital comparator whose reference threshold is permanently set to 2.5 via a fuse tuning circuit. This threshold is selected based on statistical analysis of a large clinical EEG database; a sustained θ / α ratio above 2.5 indicates significant fatigue in the subject. The digital comparator not only performs instantaneous comparisons but also integrates a 500ms duration determination logic. Specifically, the comparator outputs a high-level trigger signal only when the θ / α ratio remains above 2.5 for 500ms or longer. This design effectively filters out misjudgments caused by transient artifacts (such as blinking or electromyographic bursts).

[0051] The trigger signal is fed into a D-type state latch. Upon receiving a valid trigger, the latch sets its output high and maintains this state until an external clear command is received. The latch's output is the final fatigue state flag. In addition, the module buffers the θ / α ratio sequence for the most recent second, with a sampling rate of 4Hz, totaling four data points. This data, along with the fatigue state flag, is packaged into a standard data frame by a protocol encapsulation engine. The data frame format conforms to the Bluetooth Low Energy 4.2 specification and includes a synchronization header, device address, data type identifier, payload, and cyclic redundancy check (CRC) code. The encapsulated data frame is transmitted externally through a standard communication interface. This interface supports two physical layers: one is a Bluetooth Low Energy module operating in the 2.4GHz band with a maximum transmit power of 0dB milliwatts and a standby current of less than 1uA; the other is a serial peripheral interface with a clock frequency up to 10MHz, supporting full-duplex communication. Users can choose one according to their application scenario. In wearable devices, Bluetooth Low Energy is typically used to enable wireless data upload; in embedded medical systems, a serial peripheral interface may be used to enable high-speed direct connection with the main control chip.

[0052] The entire device achieves high integration using system-in-package (SiP) technology. The analog circuitry (including transimpedance amplifiers, analog multipliers, integrators, dividers, and analog-to-digital converters) in the EEG signal acquisition and preprocessing module and the in-memory computing feature extraction array module is fabricated on the same silicon chip using a 40nm CMOS process. The resistive random access memory (RRAM) cross-array in the in-memory computing feature extraction array module is deposited on the top metal interconnect layer of this chip using a back-end integration process, achieving vertical electrical connection to the underlying transistors via tungsten plugs. The digital logic (including counters, comparators, latches, and protocol engines) in the adaptive durability enhancement control module and the feature decision and output interface module is fabricated on another independent digital chip using a 55nm CMOS process. These two chips are stacked in three dimensions using through-silicon via (TSV) technology. The TSVs have a diameter of 5µm, a spacing of 40µm, and are filled with copper, achieving high-speed, low-latency vertical interconnection between the chips. Finally, the entire stacked structure is packaged within a 5mm × 5mm ball grid array (BGA) package, with a package thickness not exceeding 1mm. The device has 48 pins, including power, ground, electrode interfaces, communication interfaces, and test pins. This miniaturized design allows the device to be directly embedded in the temples of smart glasses, headphone pads, or flexible patches, making it suitable for long-term, non-invasive EEG fatigue monitoring.

[0053] In summary, this embodiment deeply integrates signal acquisition, analog domain feature calculation, durability management, and state decision-making to construct a truly in-memory computing-integrated real-time EEG fatigue feature extraction sensor device. Its technical advantages are reflected in three dimensions: First, by utilizing the physical computing power of the resistive random access memory (RRAM) cross-array, the feature extraction delay is compressed to less than 10ms, enabling real-time capture of transient fatigue events; second, through a closed-loop adaptive control mechanism, the effective durability of the RRAM is improved by two orders of magnitude, solving the long-term reliability bottleneck; and third, through front-end analog noise suppression and three-dimensional system integration, miniaturization and low power consumption are achieved, providing an engineering-feasible solution for wearable EEG monitoring.

[0054] Based on the foregoing embodiments, this embodiment extends the filter configuration and feature extraction logic of the in-memory computing feature extraction array module to support more refined fatigue state classification. This embodiment still follows the appendix. Figure 1 The overall architecture is shown, but within the in-memory feature extraction array module, the cross array is divided into three parallel sub-arrays instead of two. The first sub-array is still configured with a 4Hz to 8Hz bandpass filter for extracting the θ wave; the second sub-array is configured with an 8Hz to 13Hz bandpass filter for extracting the α wave; and the third sub-array is configured with a 13Hz to 30Hz bandpass filter for extracting the β wave component. The introduction of the β wave enables the system to calculate the θ / (α+β) ratio, which is more discriminative than the simple θ / α ratio under deep fatigue conditions.

[0055] Correspondingly, the number of analog multiplier circuits, integrators, and analog dividers has increased to three sets, respectively handling power calculations for the θ, α, and β frequency bands. Ultimately, two characteristic values ​​are output simultaneously: the θ / α ratio and the θ / (α+β) ratio. The digital comparator in the characteristic decision and output interface module has also been upgraded to multi-threshold decision logic. Specifically, the system defines three fatigue states: mild fatigue (θ / α > 2.5 and θ / (α+β) < 1.8), moderate fatigue (θ / α > 2.5 and 1.8 ≤ θ / (α+β) < 2.2), and severe fatigue (θ / α > 2.5 and θ / (α+β) ≥ 2.2). Each state corresponds to a different warning level, which is sent via the communication interface in data packets of different priorities. For example, a severe fatigue state triggers a high-priority interrupt and sets an emergency flag in the data frame, prompting an immediate response from the external host.

[0056] Furthermore, the strategy of the adaptive durability enhancement control module has been optimized. Due to the introduction of a third subarray, the write operation frequency is increased by approximately 50%. To compensate for this effect, the adjustment step size of the dynamic parameter adjustment unit has been refined: after the cumulative number of operations reaches 1 million, parameter adjustments are performed every 50,000 operations, with the amplitude decreasing by 0.03V and the pulse width increasing by 6ns. This finer adjustment strategy ensures that the durability target of over 10 million operations can still be maintained under higher loads.

[0057] The EEG signal acquisition and preprocessing module has also been adapted accordingly. The upper limit gain of the programmable gain amplifier has been increased to 15,000 times to cope with the typically lower amplitude of beta waves. At the same time, the cutoff frequency of the analog high-pass filter has been fine-tuned to 0.3Hz to better preserve delta wave information and assist in sleep stage determination. While maintaining the same 5mm×5mm package size, the entire system successfully accommodated the newly added analog circuit units by optimizing the wiring density and power distribution network.

[0058] Clinically validated, this embodiment improves the accuracy of distinguishing between mild inattention and severe cognitive decline by 12% compared to Embodiment 1, and is particularly suitable for graded early warning in high-risk work scenarios (such as long-distance driving and air traffic control).

Claims

1. A storage-based, real-time brainwave fatigue feature extraction sensor device, characterized in that, include: The EEG signal acquisition and preprocessing module is used to acquire raw EEG signals from the scalp of an organism and perform primary physical conditioning and noise suppression on the signals. The in-memory computing feature extraction array module is used to receive the preprocessed analog signal output by the EEG signal acquisition and preprocessing module, and based on the physical characteristics of the resistive random access memory cross array, it performs signal transformation and feature calculation in parallel in the analog domain, and directly outputs fatigue feature values ​​in digital form. The specific frequency band filter coefficient writing module is used to precisely write a set of conductance values ​​corresponding to the filter coefficients of a specific frequency band into a specified resistive switching memory unit through electrical pulse programming. An adaptive durability enhancement control module is used to monitor the working status of the in-memory computing feature extraction array module in real time and dynamically adjust the operating parameters of its internal resistive switching memory to optimize its durability. The feature decision and output interface module is used to receive fatigue feature values ​​output by the in-memory computing feature extraction array module, make state decisions based on preset fatigue thresholds, and generate corresponding control or warning signals for external output.

2. The in-memory computing integrated EEG fatigue real-time feature extraction sensor device according to claim 1, characterized in that, The in-memory computing integrated feature extraction array module includes: An analog-in-memory computing crossover array based on metal-oxide resistive switching memory; the row lines and column lines of the crossover array are connected by gating transistors, and each crossover point is a resistive switching memory cell; In this cross array, a set of conductance values ​​corresponding to filter coefficients of a specific frequency band are pre-programmed by electrical pulses and written into designated resistive switching memory cells. When the preprocessed analog EEG signal is applied as an input voltage to a specific row of the cross array, the current flowing through each column is the sum of the product of the input voltage and the conductance values ​​of all the corresponding cells in the activated rows of that column, thus completing the convolution operation between the input signal and the filter coefficients in the analog domain.

3. The in-memory computing integrated EEG fatigue real-time feature extraction sensor device according to claim 2, characterized in that, The in-memory computing integrated feature extraction array module has two built-in parallel sub-arrays, including: The conductance mode of the first subarray is configured to be equivalent to a 4Hz to 8Hz bandpass filter for extracting the theta wave component. The conductance mode of the second subarray is configured to be equivalent to an 8Hz to 13Hz bandpass filter for extracting alpha wave components. The total current signal output from each column is converted into a voltage signal by a transimpedance amplifier integrated at the end of the array, and then the instantaneous power is obtained by an analog multiplier circuit. Finally, it is integrated by an analog integrator within a 250ms time window to obtain the average power values ​​of the θ wave and the α wave. The two power values ​​are fed into an analog divider circuit to directly calculate and output the digital characteristic value of the θ / α power ratio.

4. The in-memory computing integrated EEG fatigue real-time feature extraction sensor device according to claim 1, characterized in that, The adaptive durability enhancement control module includes a state monitoring feedback unit and an operation parameter dynamic adjustment unit. The state monitoring feedback unit continuously monitors the write verification current, read current fluctuations, and cumulative operation count of the resistive random access memory (RRAM) cells in the in-memory computing feature extraction array module. The operation parameter dynamic adjustment unit dynamically adjusts the write pulse parameters used when programming the conductance value of the RRAM based on the data from the state monitoring feedback unit. The specific adjustment strategy is as follows: When the cumulative number of operations is less than 1 million, a write pulse with a standard amplitude of 3V and a pulse width of 100ns is used. When the cumulative number of operations reaches 1 million, the system will reduce the amplitude of the write pulse by 0.05V and increase the pulse width by 10ns for every 100,000 operations.

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