Implementation method of PCIe transaction layer completion timeout
By introducing a hardware mechanism at the PCIe transaction layer, allocating a storage entry (Entry) for each request transaction and using an internal timer for timeout management, the problems of high CPU usage and increasing area and power consumption with the number of IDs in the prior art are solved, achieving low power consumption, high precision timeout management and error recovery.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN PENGTI TECHNOLOGY CO LTD
- Filing Date
- 2025-12-22
- Publication Date
- 2026-07-10
AI Technical Summary
The existing PCIe transaction layer timeout mechanism suffers from high CPU usage, poor real-time performance, and linear growth in area and power consumption with the number of IDs. This is especially true in scenarios with large ID spaces and low-power standby, where it becomes a bottleneck limiting the area, power consumption, and performance of PCIe IPs.
It adopts a hardware mechanism integrated into the PCIe transaction layer, allocates a unique storage entry Entry to each request transaction through the entry management module, and uses an internal timer to periodically accumulate the time by step value, supporting multiple concurrent requests and error reporting, and realizing timeout management and resource reclamation.
It reduces software complexity, improves system reliability and debugging capabilities, achieves high-precision timeout management with low area and low power consumption, and supports multi-request concurrency and transaction representation ID management.
Smart Images
Figure CN121764733B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-speed serial communication technology, and in particular to a method for implementing PCIe transaction layer timeout. Background Technology
[0002] The PCIe specification requires all functions (Root Complex, Endpoint, PCIe-PCI Bridge) that may issue Non-Posted requests to implement a completion timeout (CTO) mechanism at the transaction layer to prevent the Requester from encountering an error due to waiting for completion for an extended period. The specification only provides the following three requirements: a programmable range of 9 increments (50µs-64s), an enable / disable bit (Device Control 2[4]), and setting the Internal Completion Status[15:12] to 0x9 after the timeout. No specific circuit implementation is specified.
[0003] Early FPGAs / ASICs, to save area, directly reused firmware / driver layer timers: when a request was issued, the software recorded a timestamp, and timeouts were checked via interrupts or polling. After a timeout, a "Vendor-Defined Error" was reported in the configuration space. The main problems with this approach are: high interrupt frequency (>1 kHz / queue) → CPU usage 5-15%; in high-concurrency I / O scenarios (NVME, GPU computing), software traversal of the ID table becomes a bottleneck; in virtualized environments, the overhead of timer thread context switching is amplified a second time as the number of virtual functions surges. Most commercial IPs (Synopsys, Cadence, Xilinx) provide 1-2 global 24-bit counters shared by all IDs. Although this approach uses a shared counter mechanism, because the bit width of each ID is the same as the global counter, the area increases with the number of managed IDs. Power consumption issues: When all timers toggle simultaneously, the peak current is 30-40 mA, which brings the risk of IR-drop; Timing issues: Multiple IDs time out simultaneously, generating "avalanche interrupts", the interrupt controller needs a deep FIFO buffer, adding 0.8-1.2 kB of additional SRAM.
[0004] In summary, existing timeout implementations either rely on software timers, leading to high CPU usage and poor real-time performance, or employ shared or fully parallel hardware timers, resulting in a contradiction where area and power consumption increase linearly with the number of IDs. This is particularly problematic when supporting large ID spaces, multiple virtual functions, and low-power standby scenarios, becoming a key bottleneck limiting the area, power consumption, and performance of PCIe IP. Therefore, there is an urgent need for a low-area, low-power, scalable, and high-precision hardware mechanism for completing timeouts to solve these technical challenges. Summary of the Invention
[0005] In view of the above-mentioned problems, the present invention is proposed.
[0006] Therefore, the problem to be solved by this invention is how to propose a completion timeout hardware mechanism integrated into the PCIe transaction layer to realize timeout management of Non-Posted requests, support multiple concurrent requests, transaction representation ID management, error reporting and recovery mechanisms, and improve system reliability and debugging capabilities.
[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0008] In a first aspect, embodiments of the present invention provide a method for implementing PCIe transaction layer timeout, including: after the PCIe bus completes the enumeration operation, configuring available space information, configuring the step size control module in the system management software, setting the time unit for timeout calculation, and determining 9 register values that conform to the 9 timeout time ranges of the PCIe protocol according to the timeout time calculation principle;
[0009] When the hardware system receives a Non-Posted request transaction sent by the requester, it allocates a unique storage entry Entry for the PCIe request message in the entry management module and generates a corresponding index identifier Entry ID; it sets the valid bits of the index identifier Entry ID to be valid to start the corresponding timeout timing process; when all valid bits in the entry are invalid, the timing process is paused.
[0010] The entry management corresponding to the index identifier Entry ID is a set of timing information, which is maintained by the timeout management module. The timeout management module periodically accumulates the time by step value through an internal timer. When the accumulated count reaches the software preset threshold, it updates the timing information corresponding to the storage entry Entry and performs timeout statistics on the next storage entry Entry in a polling manner.
[0011] When a normal completion message is received for the request transaction corresponding to the storage entry Entry, the request information, timing information and validity flag in the storage entry Entry are cleared, the storage entry Entry is restored to its initial state, and the timeout timing process of the storage entry Entry is terminated.
[0012] When the timing information of a storage entry reaches its maximum value, the request is deemed to have timed out. After the timeout is triggered, a completion message conforming to the PCIe protocol requirements is constructed based on the original request information stored in the storage entry and the requester is replied to. At the same time, an interrupt message is triggered to notify the HOST software. If a timeout is triggered, all information corresponding to the storage entry is initialized to the initial state, and resource reclamation is completed.
[0013] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, the system management software configures the step size control module, including:
[0014] The step size control module is used to determine the timeout calculation step size value based on software configuration or hardware adaptive mechanism;
[0015] When the software needs to customize the step size, the system management software updates the timeout calculation step size value and writes it directly to the register; when the software does not configure the step size, the hardware automatically sets the timeout calculation step size value and adaptively adjusts it according to the PCIe link rate; wherein, the hardware reads the link speeds register in the configuration space, obtains the link rate information, and automatically selects the timeout calculation step size value corresponding to the link rate information.
[0016] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, the time unit for timeout calculation includes:
[0017] The timeout period is calculated as follows:
[0018] Set the timeout period = hardware-selected time threshold TH × depth of storage entry N × maximum number of rounds; if there is an error in the timeout period, the maximum error is the timeout period divided by the maximum number of rounds.
[0019] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, nine register values conforming to the nine timeout time ranges of the PCIe protocol are determined, including:
[0020] The system management software sets register values in the hardware configuration space for the nine timeout ranges defined by the corresponding PCIe protocol. The hardware system selects a hardware-selected time threshold TH from the nine register values based on the current configuration space status for timeout counting. The hardware-selected time threshold TH and the timer step size value together determine the final timeout time.
[0021] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, the table entry management module includes: a request transaction information processing unit, used to receive and store key information of the request transaction;
[0022] The transaction information processing unit is used to match completion messages and release the corresponding storage entry resources.
[0023] The Entry Validation Control Unit is used to control the setting and clearing of the valid bit in the Entry storage entry.
[0024] The Entry Request Information Control Unit stores request information fields according to PCIe protocol version requirements.
[0025] The timeout sending management unit is used to generate a completion message and return it to the requester after a timeout is triggered.
[0026] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, the timeout management module includes:
[0027] The timeout scan calculation unit is used to start a time counter t when any storage entry Entry is marked as valid.
[0028] The Entry timing information control unit stores the round count value and updates it periodically based on the scan calculation results. The time counter increments by a step value after each clock cycle T, where t = t + step value. When t exceeds the hardware-selected time threshold TH, the round count value of the current Entry is incremented by 1, and the pointer moves to the next Entry for polling. When the round count value of an entry reaches its maximum value, a timeout is triggered, the valid flag is cleared, a completion message is generated, and an interrupt signal is triggered.
[0029] As a preferred embodiment of the PCIe transaction layer timeout implementation method of the present invention, the entry management corresponding to EntryID manages a set of timing information, including: using M≥4 bits to record and store the entry timing information, the timeout time has an error, and the relationship between the error and the timing information M is: error = set time - error coefficient * set time, where the error coefficient = -(1 / 2) M ).
[0030] As a preferred embodiment of the PCIe transaction layer completion timeout implementation method of the present invention, the simultaneous triggering of an interrupt message to notify the HOST software includes:
[0031] When a timeout is detected, an interrupt message is generated by the interrupt control module and reported to the HOST software. The interrupt control module generates an interrupt based on the interrupt control register in the PCIe configuration space. At most one timeout event is generated per clock cycle, and only one interrupt is triggered.
[0032] In a second aspect, embodiments of the present invention provide a computer device, including a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program instructions are executed by the processor, they implement the steps of the PCIe transaction layer completion timeout implementation method as described in the first aspect of the present invention.
[0033] Thirdly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program instructions, when executed by a processor, implement the steps of the PCIe transaction layer completion timeout implementation method as described in the first aspect of the present invention.
[0034] The beneficial effects of this invention are as follows: This invention proposes a completion timeout hardware mechanism integrated into the PCIe transaction layer, which realizes timeout management for Non-Posted requests, supports multiple concurrent requests, transaction representation ID management, error reporting and recovery mechanisms, improves system reliability and debugging capabilities, greatly reduces software complexity, and enables PCIe devices to manage completion timeouts through simple configuration. Attached Figure Description
[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 A flowchart illustrating the implementation method for timeout handling in the PCIe transaction layer;
[0037] Figure 2 A schematic diagram of the step size control flow for implementing timeout in the PCIe transaction layer;
[0038] Figure 3 A schematic diagram of the table entry management module and timeout management module for implementing timeout in the PCIe transaction layer;
[0039] Figure 4 A schematic diagram of the completion timeout management system structure for implementing timeouts in the PCIe transaction layer;
[0040] Figure 5 A schematic diagram of the software configuration step size flow for implementing timeout in the PCIe transaction layer;
[0041] Figure 6 A diagram illustrating the timeout management process for implementing timeouts in the PCIe transaction layer. Detailed Implementation
[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0043] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0044] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.
[0045] Example 1
[0046] Reference Figures 1-3 This is the first embodiment of the present invention, which provides a method for implementing PCIe transaction layer completion timeout, including:
[0047] S1: After the enumeration operation is completed on the PCIe bus, the available space information is configured. The system management software configures the step size control module, sets the time unit for timeout calculation, and determines the 9 register values that conform to the 9 timeout ranges of the PCIe protocol according to the timeout calculation principle.
[0048] Furthermore, the step size control module is used to determine the timeout calculation step size value based on software configuration or hardware adaptive mechanism; when the software needs to customize the step size, the system management software updates the step size value and writes it directly into the register; when the software does not configure the step size, the hardware automatically sets the step size value and adaptively adjusts it according to the PCIe link rate; wherein, the hardware reads the link speeds register in the configuration space to obtain the link rate information and automatically selects the timeout calculation step size value corresponding to the link rate information.
[0049] Furthermore, the timeout period is calculated as follows:
[0050] Set the timeout period = hardware-selected time threshold TH × depth of storage entry N × maximum number of rounds; if there is an error in the timeout period, the maximum error is the timeout period divided by the maximum number of rounds.
[0051] Furthermore, the system management software sets register values in the hardware configuration space for the nine timeout ranges defined by the PCIe protocol. The hardware system selects a hardware-selected time threshold TH from the nine register values based on the current configuration space status for timeout counting. The hardware-selected time threshold TH and the timer step size value together determine the final timeout time.
[0052] S2: When the hardware system receives a Non-Posted request transaction sent by the requester, it allocates a unique storage entry Entry for the PCIe request message in the entry management module and generates a corresponding index identifier Entry ID; it sets the valid bits of the Entry ID identifier to be valid to start the corresponding timeout timing process; when all valid bits in the entry are invalid, the timing process is paused.
[0053] Furthermore, the entry management module includes: a request transaction information processing unit, used to receive and store key information of the request transaction; a completion transaction information processing unit, used to match the completion message and release the corresponding storage entry resource; a storage entry valid flag control unit, used to control the setting and clearing of the valid bit of the storage entry; a storage entry request information control unit, used to store the request information field according to the PCIe protocol version requirements; and a timeout sending management unit, used to generate a completion message and return it to the requester after a timeout is triggered.
[0054] It should be noted that the request transaction information processing unit: In this invention, information that can be used to generate a completion timeout is stored in the storage entry Entry request information;
[0055] Complete transaction information processing unit: In this invention, the request information stored in the table has obtained the EntryID, and the corresponding matched table entry is initialized and cleaned.
[0056] Entry validity control unit: When an entry's ID is used by a requested transaction, the entry is marked as valid, i.e., valid=1; when a normal completion message is received or a timeout occurs, valid needs to be marked as invalid, i.e., valid=0, indicating that the entry has been released;
[0057] Storage Entry Request Information Control Unit: Stores the information of the request transaction, and then, upon receiving the completion message, matches the information in the completion message with the request information. This invention suggests that the matching rules should comply with the requirements of different versions of the PCIe protocol. The request information typically includes: Transaction ID, BC, ATTR, and other fields.
[0058] Timeout Sending Management Unit: After a timeout is triggered, an additional completion message needs to be generated to reply to the requester according to the information in the request message and the PCIe protocol requirements. This invention considers extreme cases where, if a timeout is triggered just as a completion message is received, the additionally generated completion message will be discarded.
[0059] S3: The entry management system corresponding to the Entry ID manages a set of timing information, which is maintained by the timeout management module. The timeout management module uses an internal timer to periodically accumulate the time by step value. When the accumulated count reaches the software-preset threshold, it updates the timing information corresponding to the Entry and performs timeout statistics on the next stored entry Entry in a polling manner.
[0060] Furthermore, the timeout scan calculation unit is used to start a time counter t when any storage entry Entry is marked as valid;
[0061] The Entry timing information control unit stores the round count value and updates it periodically based on the scan calculation results. The time counter increments by a step value after each clock cycle T, where t = t + step value. When t exceeds the hardware-selected time threshold TH, the round count value of the current Entry is incremented by 1, and the pointer moves to the next Entry for polling. When the round count value of an entry reaches its maximum value, a timeout is triggered, the valid flag is cleared, a completion message is generated, and an interrupt signal is triggered.
[0062] Furthermore, M≥4 bits are used to record and store the entry timing information. There is an error in the timeout period. The relationship between the error and the timing information M is: Error = Set Time - Error Coefficient * Set Time, where the error coefficient = -(1 / 2) M When M=4, the error is 6.25%. The timing accuracy can be further improved by increasing the number of bits.
[0063] It should be noted that the timeout scan calculation unit uses a timer t in hardware. The timer starts working when at least one valid flag is valid. After each hardware clock cycle, the timer value t = t + step size. When the timer t exceeds the hardware-selected time threshold TH, the round count value of the current Entry ID record is incremented by 1, and the ID pointer pointing to the current Entry ID points to the next Entry ID. The Entry ID pointer cyclically polls and scans the entire Entry ID entry. If the round count value within the current Entry ID is the maximum value, a timeout is triggered. After the timeout, the valid flags need to be cleared, a CPL message is generated, and an interrupt is triggered simultaneously. To further optimize power consumption, the timer is paused when all stored Entry entries are invalid (valid = 0).
[0064] S4: When it is detected that the request transaction corresponding to the Entry has received a normal completion message, the request information, timing information and validity flag in the stored Entry are cleared, the entry is restored to its initial state, and the timeout timing process of the entry is terminated.
[0065] S5: When the timing information of the storage entry Entry reaches the maximum value, the request is determined to have timed out. After the timeout is triggered, a completion message conforming to the PCIe protocol requirements is constructed based on the original request information stored in the entry and replied to the requester. At the same time, an interrupt message is triggered to notify the HOST software. If a timeout is triggered, all information corresponding to the storage entry Entry is initialized to the initial state, and resource reclamation is completed.
[0066] Furthermore, when a timeout is detected, an interrupt message is generated by the interrupt control module and reported to the HOST software. The interrupt control module generates an interrupt based on the interrupt control register in the PCIe configuration space. At most one timeout event is generated per clock cycle, and only one interrupt is triggered.
[0067] Example 2
[0068] Reference Figures 4-6 This is the second embodiment of the present invention, specifically including:
[0069] like Figure 4As shown, ① indicates that the generation information of PCIe GenX is obtained from the configuration space, which is used by the hardware to automatically select the software configuration preset value as the step size value; ② indicates whether the software configuration step size uses the hardware value or the software value. If the software value is used, the software also needs to directly configure the step size value; ③ indicates that the final step size value is sent to the timeout management module; ④ the software configures 9 sets of time thresholds to correspond to the 9 sets of timeout ranges in the PCIe protocol configuration space. The hardware will select one of them as the hardware-selected time threshold TH according to the configuration space; ⑤ indicates that after receiving the request transaction, the request information is stored in the storage entry Entry involved in this invention according to the PCIe protocol requirements; ⑥ indicates that after managing the timeout, the configuration space capability information used by the solution of this invention includes the configuration registers of the 9 sets of timeout ranges and related capabilities; ⑦ indicates that after normal completion, a matching search needs to be performed in the table. After a successful match, the current Entry ID entry information needs to be cleared; ⑧ indicates that when normal completion occurs, this invention needs to suppress the timeout completion generated by the timeout management module at the same time; ⑨ indicates that after a timeout occurs, the timeout Entry will be... The ID entry information is cleaned up; ⑩ indicates that after a timeout, the information stored in the timeout Entry ID needs to be read according to the PCIe protocol requirements, and a completion message is constructed and returned to the requester; the depth of the Entry needs to be set according to the maximum processing capacity that the system can accept. The depth will affect the system resources. The completioner needs to set it according to its own ability to accept requests. This invention does not allocate a counter for each Entry, but uses a timeout counter. In this way, the resource consumption of the counter is not affected by the depth factor. Therefore, the timeout setting method of this invention uses this feature to optimize and control the counting resources; ⑪ indicates the interrupt control information of the configuration space, which is used for the system to control PCIe interrupts; ⑫ indicates that an interrupt is triggered when a timeout occurs; ⑬ indicates that an interrupt notification software is generated.
[0070] It should be noted that if the hardware clock cycle is 1ns and the configured spatial link rate is PCIe Gen7, the step size is 1. The round count is recorded using 4 bits. The timeout is set to 4 seconds; that is, if a completion message is not correctly generated within 4 seconds of receiving a request, the 4-bit record value is the maximum value, automatically triggering the timeout mechanism. In this way, the software can control the hardware to generate a timeout at a specific time based on a time threshold, with an error of 1 / 16. Users can design a suitable timeout recovery mechanism based on this principle.
[0071] Error issue: The target timeout is 4 seconds. If the timer pointer just passed the entry in the previous moment and the first round of timeout scanning has just begun, the error is 0. A timeout will occur after 16 rounds of scanning. If the timer pointer just points to the entry, since the entry is marked as valid (1), the number of rounds immediately returns to 1, and a timeout will occur after only 15 rounds of scanning. The actual timeout is 3.75 seconds. Therefore, the timeout range is [3.75s, 4s].
[0072] Software settings: The premises are as follows: clock cycle 1ns, step size 1, entry depth 100, round count using 4 bits (16 rounds timeout), target timeout 4 seconds, and error 0. Based on the principle, the target timeout of 4 seconds = hardware-selected time threshold TH × entry depth 100 × number of timeout rounds 16. Therefore, the software-set threshold TH = target timeout ÷ (entry depth × number of timeout rounds). The software-set threshold TH represents to the hardware how many steps (time) from 0 are needed to reach the target timeout.
[0073] like Figure 5 As shown, this invention applies to any function in the PCIe tree structure that implements a timeout method. This function is defined in the PCIe protocol and is not limited to any specific device type, thus possessing broad applicability. Software and hardware personnel in this field can follow the specific procedures below for practical application. The software needs to decide whether to configure the step size. If software configuration is required, the software directly configures the step size value. If hardware configuration of the step size is required, the software needs to configure the step size values corresponding to Gen1 to Gen7. Then, the hardware selects the corresponding step size value based on the actual operating speed: the step size value represents the accumulated value of the hardware in each cycle. The hardware will periodically accumulate the step size to achieve the timing effect. If the Gen7 clock cycle is 1ns, the corresponding step size is 1; if the Gen6 clock cycle is 1ns, the corresponding step size is 1; if the Gen5 clock cycle is 2ns, the corresponding step size is 2. Here, a reference configuration method is provided to set the PCIe Gen7 clock cycle to T and the step size to 1. If the clock cycle is N×T, the step size is also N×1. Finally, the software needs to select a time threshold TH based on the different hardware within the nine ranges of the PCIe protocol settings to ultimately constrain the target timeout time. Target timeout time = software-set threshold TH × Entry depth × maximum number of timeout rounds.
[0074] like Figure 6As shown in the diagram, the hardware implements timeout management in parallel according to the following process. Specifically, if a request message is received, an entry is created. When the entry is not empty, a time counter starts counting in steps until it reaches the threshold TH set by the software. Afterward, it continues to poll for the next stored entry, while the Entry ID is incremented by 1 to indicate the round number. When the round number reaches its maximum and the Entry marker is not cleared, the hardware determines a timeout, clears the entry information, and triggers an interrupt to end the process. If a completion message corresponding to the request is received, the entry is immediately cleared. Since the Entry marker is invalid after clearing, the Entry will not trigger a timeout, and the process ends.
[0075] This embodiment also provides a computer device applicable to the implementation method of PCIe transaction layer completion timeout, including a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute computer-executable instructions to implement the PCIe transaction layer completion timeout implementation method as proposed in the above embodiment.
[0076] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.
[0077] This embodiment also provides a storage medium on which a computer program is stored. When the program is executed by a processor, it implements the PCIe transaction layer completion timeout implementation method as proposed in the above embodiments.
[0078] In summary, this invention proposes a hardware mechanism for completion timeout integrated into the PCIe transaction layer, enabling timeout management for Non-Posted requests. It supports concurrent multi-request handling, transaction representation ID management, error reporting and recovery mechanisms, thereby improving system reliability and debugging capabilities. It significantly reduces software complexity, as software does not need to participate in the process; PCIe device management of completion timeouts can be achieved through simple configurations such as enable / disable switches and thresholds.
[0079] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A method for implementing PCIe transaction layer completion timeout, characterized in that, include: After the enumeration operation is completed on the PCIe bus, the available space information is configured. The system management software configures the step size control module, sets the time unit for timeout calculation, and determines the 9 register values that conform to the 9 timeout ranges of the PCIe protocol according to the timeout calculation principle. When the hardware system receives a Non-Posted request transaction from the requester, it allocates a unique storage entry Entry for the PCIe request message in the entry management module and generates a corresponding index identifier Entry ID; Set the valid bits of the index identifier Entry ID to be valid to start the corresponding timeout timing process. When all valid bits in the table entry are invalid, pause the timing process. The entry management corresponding to the index identifier Entry ID is a set of timing information, which is maintained by the timeout management module. The timeout management module periodically accumulates the time by step value through an internal timer. When the accumulated count reaches the software preset threshold, it updates the timing information corresponding to the storage entry Entry and performs timeout statistics on the next storage entry Entry in a polling manner. When a normal completion message is received for the request transaction corresponding to the storage entry Entry, the request information, timing information and validity flag in the storage entry Entry are cleared, the storage entry Entry is restored to its initial state, and the timeout timing process of the storage entry Entry is terminated. When the timing information of a storage entry reaches its maximum value, the request is deemed to have timed out. After the timeout is triggered, a completion message conforming to the PCIe protocol requirements is constructed based on the original request information stored in the storage entry and the requester is replied to. At the same time, an interrupt message is triggered to notify the HOST software. If a timeout is triggered, all information corresponding to the storage entry is initialized to the initial state, and resource reclamation is completed.
2. The method for implementing PCIe transaction layer timeout as described in claim 1, characterized in that, The system management software configures the step size control module, including: The step size control module is used to determine the timeout calculation step size value based on software configuration or hardware adaptive mechanism; When the software needs to customize the step size, the system management software updates the timeout calculation step size value and writes it directly to the register; when the software does not configure the step size, the hardware automatically sets the timeout calculation step size value and adjusts it adaptively according to the PCIe link rate. Specifically, the hardware reads the link speeds register in the configuration space to obtain link speed information and automatically selects the timeout calculation step size value corresponding to the link speed information.
3. The method for implementing PCIe transaction layer timeout as described in claim 1, characterized in that, The time unit for setting the timeout calculation includes: The timeout period is calculated as follows: Set timeout = hardware-selected time threshold TH × depth of storage entry N × maximum number of rounds; If there is an error in the timeout period, the maximum error is the timeout period divided by the maximum value of the number of rounds.
4. The method for implementing PCIe transaction layer timeout as described in claim 1, characterized in that, The determination of the nine register values that conform to the nine timeout ranges of the PCIe protocol includes: The system management software sets register values in the hardware configuration space for the nine timeout ranges defined by the corresponding PCIe protocol. The hardware system selects a hardware-selected time threshold TH from the nine register values based on the current configuration space status for timeout counting. The hardware-selected time threshold TH and the timer step size value together determine the final timeout time.
5. The method for implementing PCIe transaction layer timeout as described in claim 1, characterized in that, The table entry management module includes: The request transaction information processing unit is used to receive and store key information of the request transaction; The transaction information processing unit is used to match completion messages and release the corresponding storage entry resources. The Entry Validation Control Unit is used to control the setting and clearing of the valid bit in the Entry storage entry. The Entry Request Information Control Unit stores request information fields according to PCIe protocol version requirements. The timeout sending management unit is used to generate a completion message and return it to the requester after a timeout is triggered.
6. The method for implementing PCIe transaction layer completion timeout as described in claim 1, characterized in that, The timeout management module includes: The timeout scan calculation unit is used to start a time counter t when any storage entry Entry is marked as valid. The Entry timing information control unit stores the number of rounds and updates it periodically based on the scan calculation results; The time counter increments by a step value after each clock cycle T, where t = t + step value. When t exceeds the hardware-selected time threshold TH, the round count of the current storage entry Entry is incremented by 1, and the pointer moves to the next storage entry Entry for polling. When the round count of an entry reaches its maximum value, a timeout is triggered, the valid flag is cleared, a completion message and an interrupt signal are generated.
7. The method for implementing PCIe transaction layer completion timeout as described in claim 1, characterized in that, The entry corresponding to the Entry ID manages a set of timing information, including: The timing information of an entry is stored using M≥4 bits. There is an error in the timeout period. The relationship between the error and the timing information M is: Error = Set Time - Error Coefficient * Set Time, where the error coefficient = -(1 / 2) M ).
8. The method for implementing PCIe transaction layer completion timeout as described in claim 1, characterized in that, The simultaneous triggering of an interrupt message to notify the HOST software includes: When a timeout is detected, an interrupt message is generated by the interrupt control module and reported to the HOST software. The interrupt control module generates an interrupt based on the interrupt control register in the PCIe configuration space. At most one timeout event is generated per clock cycle, and only one interrupt is triggered.
9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the PCIe transaction layer completion timeout implementation method according to any one of claims 1 to 8.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the PCIe transaction layer completion timeout implementation method according to any one of claims 1 to 8.