NorFlash and array structure oriented to AI reasoning and compiling method and application of NorFlash and array structure

Abstract

The invention discloses a NorFlash and array structure oriented to AI reasoning and a compiling method and application of the NorFlash and array structure, and relates to the technical field of integrated circuit memories, and the NorFlash is a 2T structure formed by connecting a selection transistor ST and a floating gate type memory transistor MT in series. A storage array architecture is also formed through the NorFlash, and the NorFlash is particularly suitable for computing equipment such as an AI server and the like which have strict requirements on programming power consumption and speed. Source and drain currents in the programming process are thoroughly eliminated or remarkably reduced, so that ultralow-power-consumption programming is achieved, the number of units capable of being programmed in parallel within the same time is increased based on the ultralow-power-consumption programming, and finally the total programming time of the NorFlash chip is greatly shortened.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit memory technology, and more specifically, to a NorFlash array structure for AI inference, its compilation method, and its application. Background Technology

[0002] In AI inference servers, computing units such as GPUs and NPUs need to quickly load microcode, configuration information, or boot code from Nor Flash. Nor Flash is the preferred choice due to its fast random access capabilities. However, traditional Nor Flash uses a channel hot electron injection (CHE) programming mechanism, the core problem of which is the excessive programming current (typically tens to hundreds of microamps per cell). This leads to two serious bottlenecks: power consumption limitation: due to the limitation of the chip's total current budget, the programmer cannot program a large number of memory cells simultaneously, and must perform programming in batches, which seriously slows down the programming (burning) speed of the entire chip. This problem is particularly prominent when AI servers need to update the firmware of multiple hardware modules in batches; area overhead: in order to withstand the large programming current, the bit lines and source lines must be designed to be wider, and the driving capability of the memory transistors must also be stronger, both of which increase the cell area and are not conducive to improving storage density. While existing technologies attempt to improve accuracy by optimizing the programming voltage waveform or employing Incremental Step Pulse Programming (ISPP), they have not fundamentally solved the high current problem inherent in the CHE mechanism. Therefore, a new Nor Flash cell structure and programming method are urgently needed to significantly reduce programming power consumption, thereby enabling a higher degree of parallel programming. Summary of the Invention To address the aforementioned issues, the present invention aims to provide a novel Nor Flash memory cell structure and its programming method, which aims to completely eliminate or significantly reduce source and leakage currents during the programming process, thereby achieving ultra-low power programming and increasing the number of cells that can be programmed in parallel at the same time, ultimately significantly shortening the total programming time of the Nor Flash chip. To achieve the above technical objectives, this application provides a NorFlash for AI inference, consisting of a 2T structure composed of a select transistor ST and a floating-gate memory transistor MT connected in series. Preferably, the gate of the transistor ST is connected to the word line WL, and the source is connected to the bit line BL. Preferably, the gate of the floating gate type memory transistor MT is connected to the control line CG, its source and the drain of the select transistor ST share a node S', and its drain is connected to the common source line SL. Preferably, the common source line SL is no longer grounded during programming, but can be subjected to a negative voltage. Based on the same inventive concept, this invention provides a NorFlash compilation method for AI inference, comprising the following steps: During the preparation period, all lines are kept in standby mode. During setup, the control source line SL is pulled down to a negative voltage V_sl_neg, while a negative voltage V_neg is applied to the word line WL to turn off the select transistor ST, and a positive voltage V_bl is applied to the bit line BL. During the programming pulse period, a high positive programming voltage V_prog is applied to the control gate line CGL. During this period, a strong electric field is generated between the floating gate of the memory transistor MT and the source terminal Node S', which triggers FN tunneling and electrons are injected into the floating gate. During the recovery period, the voltage of control CGL is reduced to 0V, and then the voltages of WL, BL and SL are gradually restored to the standby state. Preferably, when programming the selected cell, the selected word line WL_sel is selected by applying a negative voltage V_neg to ensure that the selected transistor ST is strongly inverted and completely turned off, thereby physically cutting off the current path from the bit line BL to the node S', wherein the negative voltage V_neg is between -2V and -4V. Preferably, when programming a selected cell, the selected bit line BL_sel is selected: a positive programming voltage V_prog is applied, wherein the positive programming voltage V_prog is between 5V and 8V; Select control line CG_sel: Apply a high programming voltage V_cg to inject electrons into the floating gate of the memory tube MT, wherein the high programming voltage V_cg is between 9V and 12V; Common source line SL: Apply a negative voltage V_sl_neg, where the negative voltage V_sl_neg is between -4V and -8V. Based on the same inventive concept, this invention utilizes NorFlash for AI inference to form a storage array architecture. Based on the same inventive concept, this invention provides a parallel programming method for memory array architectures, comprising the following steps: Parallel programming groups: The array is divided into multiple independent "parallel programming groups", each containing a number of bit lines and word lines; Negative voltage generation circuit: The chip integrates a high-efficiency negative charge pump circuit to provide the required negative voltage for word line drivers and source line drivers; Programming operation: Within the same programming cycle, the chip simultaneously applies programming voltage to several units distributed in different "parallel programming groups". The present invention discloses the following technical effects: 1. Revolutionary low power consumption: It fundamentally eliminates programming current, reducing the programming power consumption of a single unit to an extremely low level. 2. Extremely high programming speed: Extremely low unit power consumption allows for large-scale parallel programming, thereby reducing the total programming time of the chip to 1 / 10 or even less of the traditional method, greatly improving the efficiency of AI server firmware updates. 3. High density potential: Since there is no need to consider the large current carrying capacity, the size of bit lines and transistors can be made smaller, which is conducive to increasing storage density and reducing costs. 4. High reliability: FN tunneling is a uniform and gentle injection mechanism that causes less damage to the tunnel oxide layer than intense hot electron injection, which helps improve the endurance of the memory. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 This is a schematic diagram of the 2T storage unit circuit described in this invention; Figure 2 This is the programming operation timing and voltage configuration diagram described in this invention. Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. like Figures 1-2 As shown, this invention provides a Nor-type flash memory (NorFlash) storage cell structure, its programming method, and a corresponding storage array architecture, which is particularly suitable for computing devices such as AI servers with stringent requirements for programming power consumption and speed. Specifically, it includes the following: 1. Core storage unit structure, such as Figure 1 As shown, it possesses: ST (Select Transistor): Its on / off state is controlled by the word line (WL) voltage. During programming, a negative voltage (e.g., -3V) is applied to WL to ensure that ST is completely turned off, cutting off the DC current path; MT (Floating Gate Storage Transistor): The amount of charge in its floating gate determines the threshold voltage of the cell, thereby storing data '0' or '1'; Node S': The internal connection point between ST and MT, which is the key location where the FN tunneling effect occurs. Voltage configuration: such as Figure 1 It shows the voltage state of each port during programming, which is fundamental to understanding "zero current" programming and source-side FN tunneling. The basic memory cell proposed in this invention consists of a selection transistor (ST) and a floating-gate memory transistor (MT) connected in series (2T structure). Among them, the gate of the select transistor (ST) is connected to the word line (WL), and the source is connected to the bit line (BL). The gate of the memory transistor (MT) is connected to the control line (CG), its source shares a node (NodeS') with the drain of the select transistor (ST), and its drain is connected to the common source line (SL). The key difference from a traditional 1T unit is that the common source line (SL) is no longer grounded during programming, but can instead be subjected to a negative voltage. 2. Low-power programming methods (see...) Figure 2 (Programming operation timing and voltage configuration diagram) Timing description: t0-t1 (preparation period): All lines are in standby mode (usually 0V or positive voltage). t1-t2 (Setup Phase): First, the source line (SL) is pulled low to a negative voltage V_sl_neg (e.g., -8V). Simultaneously, the word line (WL) is applied a negative voltage V_neg (e.g., -3V) to turn off the select transistor (ST). The bit line (BL) is applied a positive voltage V_bl (e.g., 2.5V). t2-t3 (Programming Pulse Period): A high positive programming voltage V_prog (e.g., 12V) is applied to the control gate line (CGL). During this period, a strong electric field is generated between the floating gate and the source terminal (Node S') of the memory transistor (MT), inducing FN tunneling, and electrons are injected into the floating gate. t3-t4 (Recovery Period): First, the CGL voltage drops to 0V. Subsequently, the voltages of WL, BL, and SL gradually recover to standby state. This ramp-down helps stabilize the programming state. When programming a selected unit, the voltage configuration for each terminal is as follows: (1) Select word line (WL_sel): Apply a negative voltage V_neg (e.g., -2V to -4V). This negative voltage ensures that the select transistor (ST) is strongly inverted and completely turned off, thereby physically cutting off the current path from the bit line (BL) to node S'. (2) Select bit line (BL_sel): Apply a positive programming voltage V_prog (e.g., 5V to 8V). (3) Select control line (CG_sel): Apply a high programming voltage V_cg (e.g., 9V to 12V) to inject electrons into the floating gate of the memory tube (MT). (4) Common source line (SL): Apply a negative voltage V_sl_neg (e.g. -4V to -8V). Working principle: Since the select transistor (ST) is completely turned off by the negative gate voltage, the path from the bit line (BL) to node S' is blocked, and the traditional programming current from BL through ST and MT to SL does not exist. At this time, the programming mechanism of the memory transistor (MT) changes to the "source-side Fowler-Nordheim tunneling effect". The high control gate voltage V_cg and the negative source-side voltage V_sl_neg generate an extremely high electric field on the tunnel oxide layer of the memory transistor MT. This electric field forces electrons to be injected from the source end of MT (node ​​S') into the floating gate through the FN tunneling effect, thus completing the programming. Because the FN tunnel current is extremely small (typically in the pA to nA range), the programming power consumption of a single unit is reduced by 2-3 orders of magnitude compared to the traditional CHE mechanism. 3. Memory array architecture and parallel programming: Based on the aforementioned low-power units, this invention designs an array that supports large-scale parallel programming: Parallel programming groups: The array is divided into multiple independent "parallel programming groups", each containing a number of bit lines and word lines. Negative voltage generation circuit: The chip integrates a high-efficiency negative charge pump circuit to provide the required negative voltage (V_neg, V_sl_neg) for word line drivers and source line drivers. Programming operation: Because the programming current of each unit is extremely low, the chip can simultaneously apply programming voltage to hundreds or even thousands of units distributed in different "parallel programming groups" within the same programming cycle. This is equivalent to increasing the programming throughput by several orders of magnitude. Example: The present invention provides a novel Nor Flash memory cell structure and its compilation method, the specific implementation process of which is as follows: 1. Circuit implementation: Design a negative voltage charge pump with input voltage VCC=3.3V and output voltages V_neg = -3V and V_sl_neg=-6V. The word line driver is designed as a level shifting circuit that can output a voltage from V_neg (-3V, used for programming shutdown) to VCC (3.3V, used for reading on). Bit line drivers and control line drivers also need to support high voltage output. 2. Operating Procedures: Programming: As mentioned above, a specific combination of negative and high pressure is applied to perform FN tunnel programming on multiple selected units in parallel, with a pulse width of approximately 1-2 ms. Read: Apply VCC (e.g., 3.3V) to the word line (WL), apply VCC to the control line (CG), precharge the bit line (BL) to 1V, and ground the source line (SL). The threshold voltage of the memory transistor MT is determined by sensing the bit line current, thereby reading the stored data ('0' or '1'). Erasure: Using a uniform block erase or sector erase, the control line (CG) is grounded, the bit line (BL) is floating, and a high voltage (e.g., 10V) is applied to the source line (SL). Electrons are pulled back from the floating gate to the substrate through the FN tunneling effect. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes. In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A NorFlash for AI inference, characterized in that, A 2T structure consisting of a selection transistor ST and a floating-gate memory transistor MT connected in series.

2. The NorFlash for AI inference according to claim 1, characterized in that: The gate of the selected transistor ST is connected to the word line WL, and the source is connected to the bit line BL.

3. The NorFlash for AI inference according to claim 2, characterized in that: The gate of the floating gate type memory transistor MT is connected to the control line CG, and its source and the drain of the select transistor ST share a node S', and its drain is connected to the common source line SL.

4. The NorFlash for AI inference according to claim 3, characterized in that: The common source line SL is no longer grounded during programming; instead, a negative voltage can be applied.

5. A NorFlash compilation method for AI inference according to any one of claims 1-4, characterized in that, Includes the following steps: During the preparation period, all lines are kept in standby mode. During setup, the control source line SL is pulled down to a negative voltage V_sl_neg, while a negative voltage V_neg is applied to the word line WL to turn off the select transistor ST, and a positive voltage V_bl is applied to the bit line BL. During the programming pulse period, a high positive programming voltage V_prog is applied to the control gate line CGL. During this period, a strong electric field is generated between the floating gate of the memory transistor MT and the source terminal Node S', which triggers FN tunneling and electrons are injected into the floating gate. During the recovery period, the voltage of control CGL is reduced to 0V, and then the voltages of WL, BL and SL are gradually restored to the standby state.

6. The compilation method according to claim 5, characterized in that: When programming a selected cell, the selected word line WL_sel: applies a negative voltage V_neg to ensure that the select transistor ST is strongly inverted and completely turned off, thereby physically cutting off the current path from the bit line BL to the node S', where the negative voltage V_neg is between -2V and -4V.

7. The compilation method according to claim 6, characterized in that: When programming a selected cell, select bit line BL_sel: apply a positive programming voltage V_prog, where the positive programming voltage V_prog is between 5V and 8V; Select control line CG_sel: Apply a high programming voltage V_cg to inject electrons into the floating gate of the memory tube MT, wherein the high programming voltage V_cg is between 9V and 12V; Common source line SL: Apply a negative voltage V_sl_neg, where the negative voltage V_sl_neg is between -4V and -8V.

8. A storage array architecture consisting of NorFlash for AI inference as described in any one of claims 1-4.

9. The parallel programming method for the storage array architecture according to claim 8, characterized in that, Includes the following steps: Parallel programming groups: The array is divided into multiple independent "parallel programming groups", each containing a number of bit lines and word lines; Negative voltage generation circuit: The chip integrates a high-efficiency negative charge pump circuit to provide the required negative voltage for word line drivers and source line drivers; Programming operation: Within the same programming cycle, the chip simultaneously applies programming voltage to several units distributed in different "parallel programming groups".

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