A chip data efficient processing method for a burning process

Abstract

This invention relates to the field of data processing technology, specifically to an efficient chip data processing method for the programming process. The method involves: obtaining the suspected anomaly level of page addresses based on differences in the number of write failures and the difference in write time between page addresses; identifying suspected abnormal page addresses based on the suspected anomaly level; clustering these suspected abnormal page addresses based on their distribution characteristics within the chip to obtain different page address sets; and obtaining the true anomaly level based on the state characteristics of neighboring page addresses, the discrete distribution characteristics of their respective page address sets, and the differences in the number of write failures and write time between the suspected abnormal page address and other suspected abnormal page addresses within the same set. This invention obtains the chip programming anomaly level based on the true anomaly level of suspected abnormal page addresses, the number of write failures, and the write time; and detects the chip programming status based on the programming anomaly level, thus improving the accuracy of assessing latent defects in the chip.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a method for efficient processing of chip data during the programming process. Background Technology

[0002] Chip programming refers to the process of writing compiled program code, configuration parameters, or firmware data into the non-volatile memory inside a chip, enabling the chip to have its intended functions and operate independently. Current technologies only evaluate whether the programming process passed, such as whether all address blocks were completely written. However, they cannot assess latent defects, potentially leading to lifespan risks for the programmed chip and low utilization efficiency of the programmed data. Therefore, there is an urgent need for a method to assess latent defects in chips, improve the utilization efficiency of programmed data, and obtain more complete chip programming information. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a method for efficient chip data processing during the programming process. The specific technical solution adopted is as follows:

[0004] Obtain the number of write failures and write time for all page addresses in the chip;

[0005] The degree of suspected anomaly of page addresses is obtained based on the differences in the number of write failures and the differences in write time between page addresses; suspected abnormal page addresses are obtained based on the degree of suspected anomaly; and different page address sets are obtained by clustering based on the distribution characteristics of the suspected abnormal page addresses in the chip.

[0006] The true degree of abnormality is obtained based on the state characteristics of the neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set.

[0007] The degree of chip programming anomaly is obtained based on the actual degree of anomaly of the suspected abnormal page address, the number of write failures, and the write time; the chip programming status is detected based on the degree of programming anomaly.

[0008] Furthermore, the step of obtaining the suspected anomaly level of a page address based on the differences in the number of write failures and the differences in write times between page addresses includes:

[0009] Calculate the average number of write failures for all page addresses in the chip to obtain the average number of failures; calculate the average write time for all page addresses in the chip to obtain the average time; calculate the difference between the number of write failures for any page address and the average number of failures, and normalize it to obtain a first value; calculate the difference between the write time for any page address and the average time, and normalize it to obtain a second value; calculate the sum of the first value and the second value to obtain the suspected anomaly level of the arbitrary page address.

[0010] Furthermore, the step of obtaining the address of the suspected abnormal page based on the degree of suspected abnormality includes:

[0011] Page addresses whose suspected anomaly level exceeds a preset first threshold are designated as suspected abnormal page addresses.

[0012] Furthermore, the step of clustering based on the distribution characteristics of the suspected abnormal page addresses in the chip to obtain different sets of page addresses includes:

[0013] Based on the address numbers of the suspected abnormal page addresses, the K-means clustering algorithm is used to cluster all the suspected abnormal page addresses to obtain different sets of page addresses.

[0014] Furthermore, the step of obtaining the true degree of abnormality based on the state characteristics of the neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set includes:

[0015] In the formula, R represents the actual abnormality level of any suspected abnormal page address, and K represents the number of adjacent page addresses that are suspected abnormal page addresses. Let N represent an exponential function with the natural constant as its base, and let N represent the number of page addresses in the set of page addresses containing any suspected abnormal page address. Let M represent the average number of page address intervals between the nth suspected abnormal page address and its two nearest adjacent suspected abnormal page addresses; let M represent the number of other suspected abnormal page addresses in the page address set containing the given suspected abnormal page address; and let S represent the normalized value of the number of writes to the given suspected abnormal page address. Let T represent the normalized value of the number of writes to the m-th other suspected abnormal page address, and let T represent the normalized value of the write time to any of the suspected abnormal page addresses. This represents the normalized value of the write time of the m-th other suspected abnormal page address.

[0016] Furthermore, the step of obtaining the chip's programming anomaly level based on the actual anomaly level of the suspected abnormal page address, the number of write failures, and the write time includes:

[0017] In the formula, W represents the degree of programming error, and H represents the number of suspected abnormal page addresses. This indicates the true degree of abnormality of the h-th suspected abnormal page address. This represents the normalized value of the number of writes to the h-th suspected abnormal page address. This represents the normalized value of the write time of the h-th suspected abnormal page address.

[0018] Furthermore, the step of detecting the chip programming status based on the degree of programming anomaly includes:

[0019] When the degree of programming abnormality exceeds a preset second threshold, the chip programming status is manually re-inspected.

[0020] The present invention has the following beneficial effects:

[0021] In this invention, obtaining the suspected anomaly level can initially determine page addresses that may have programming anomalies based on the number of write failures and write times. Obtaining suspected abnormal page addresses can pinpoint the location of potentially abnormal page addresses within the chip. Obtaining the page address set can determine the cause of anomalies in the programming process based on the distribution characteristics of suspected abnormal page addresses, further improving the accuracy of latent defect assessment. The true anomaly level is obtained based on the state characteristics of neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses within the set. This can determine the type of cause leading to the suspected abnormal page address, avoiding interference from external factors during the programming process. Obtaining the programming anomaly level can characterize the likelihood of latent defects in the chip, and ultimately, the programming status of the chip is detected based on the programming anomaly level, improving the accuracy of detection and assessment. Attached Figure Description

[0022] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a method for efficient chip data processing during the programming process, provided as an embodiment of the present invention. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a chip data efficient processing method for the programming process proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0026] The following description, in conjunction with the accompanying drawings, details a specific scheme for an efficient chip data processing method provided by the present invention for the programming process.

[0027] Please see Figure 1 The diagram illustrates a flowchart of an efficient chip data processing method for the programming process according to an embodiment of the present invention. The method includes the following steps:

[0028] Step S1: Obtain the number of write failures and the write time for all page addresses in the chip.

[0029] In this embodiment of the invention, the implementation scenario is to assess potential hidden defects in chip programming and improve the accuracy of programming defect assessment. The chip is connected via an interface, and data is written according to the memory address sequence. For a specified page address, data is written to that page, and the process waits for completion. If writing fails, the process is repeated. The programmer polls to check if writing is complete; if so, the address is incremented, and the writing process is repeated until all page addresses are written. If a timeout occurs, the chip programming is considered a failure. For chips where all page addresses are fully written, the programming data is analyzed to obtain the number of writing failures and the writing time for each page address as programming information for that page address. The number of writing failures represents the number of times the page address was repeatedly written, and the writing time represents the total writing time for that page address.

[0030] Step S2: Based on the differences in the number of write failures and the differences in write time between page addresses, obtain the degree of suspected anomaly of the page addresses; obtain suspected abnormal page addresses based on the degree of suspected anomaly; and cluster the suspected abnormal page addresses in the chip to obtain different sets of page addresses.

[0031] Since the tested chip is a fully written chip with no surface abnormalities, its basic quality is acceptable, and there are no major chip quality defects. Therefore, most of the written address blocks are normal address blocks, and address blocks with potential hidden defects should only account for a small portion. Thus, the suspected abnormality level of a page address can be initially obtained based on the differences in the number of write failures and the differences in write time between page addresses. Preferably, in this embodiment of the invention, the step of obtaining the suspected abnormality level includes: calculating the average number of write failures for all page addresses in the chip to obtain the average number; since most page addresses in the chip are normal page addresses, the average number is closer to the number of normal page addresses. Calculating the average write time for all page addresses in the chip to obtain the average time; the average time is closer to the time of normal page addresses. Calculating the difference between the number of write failures for any page address and the average number, and normalizing it to obtain a first value; the larger the first value, the higher the number of write failures for that page address is above the average level, and the more likely the page address's programming process is to be abnormal. The difference between the write time and the average time for any page address is calculated and normalized to obtain a second value. A larger second value indicates that the write time for that page address is higher than the average, and the more likely the page address's programming process is to be abnormal. In this embodiment, the normalization method is maximum-minimum value normalization. The sum of the first and second values ​​is calculated to obtain the suspected abnormality level of the arbitrary page address; a larger suspected abnormality level indicates that the page address's programming process is more likely to be abnormal.

[0032] Furthermore, the value range of the suspected anomaly level of page addresses is from 0 to 2. The page address more likely to have an anomaly during the burning process has a suspected anomaly level closer to 2, while the page address less likely to have an anomaly during the burning process has a suspected anomaly level closer to 0. These two cases are distributed at opposite ends of the value range. Therefore, suspected abnormal page addresses can be obtained based on the suspected anomaly level. Specifically, page addresses with a suspected anomaly level exceeding a preset first threshold are considered suspected abnormal page addresses. In this embodiment of the invention, the median value of the value range is used as the first threshold, thereby obtaining suspected abnormal page addresses more accurately. The implementer can determine the preset first threshold according to the implementation scenario. Suspected abnormal page addresses indicate that they may have burning anomalies. It is not only the chip's own quality factors that affect the burning of some page addresses. Various external interferences during the writing process can also cause data writing anomalies, such as transmission voltage fluctuations and unstable interface contact, which can lead to page address writing failures or excessively long writing times. Therefore, it is necessary to further analyze suspected abnormal page addresses to obtain page addresses that more accurately correspond to actual chip quality anomalies, thereby improving the accuracy of chip burning effect evaluation. Then, based on the distribution characteristics of suspected abnormal page addresses in the chip, clustering is performed to obtain different page address sets. Preferably, in this embodiment of the invention, the step of obtaining the page address set includes: clustering all suspected abnormal page addresses according to their address numbers using a K-means clustering algorithm to obtain different page address sets. It should be noted that the K-means clustering algorithm is existing technology, and the specific steps will not be described in detail. Clustering can group similar suspected abnormal page addresses into a single cluster.

[0033] Step S3: Obtain the true degree of abnormality based on the state characteristics of neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set.

[0034] Abnormal page address distribution caused by chip quality issues is relatively concentrated. This is because a defect in one part of the chip affects the performance of all memory addresses on that chip. Since page addresses within the same region of the chip are generally adjacent, suspected abnormal page addresses exhibit a dense distribution with few gaps between them. If the page address write anomaly is caused by external device problems, such as voltage fluctuations or unstable interface contact, such interference is uncontrollable, highly random, and the disconnection is instantaneous. Therefore, the distribution of suspected abnormal page addresses caused by this type of situation is relatively discrete and random. Furthermore, write anomalies at addresses within the same defective region often show high similarity, resulting in relatively high similarity of written data within the same page address set. External environmental interference, such as voltage fluctuations, can lead to different write anomalies during page address writing, such as varying numbers of write failures and significant differences in write duration. Therefore, the true degree of anomaly is obtained based on the state characteristics of neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in write failure counts and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set. Preferably, in this embodiment of the invention, the step of obtaining the true degree of anomaly includes:

[0035]

[0036] In the formula, R represents the actual abnormality level of any suspected abnormal page address, and K represents the number of adjacent page addresses that are also suspected abnormal page addresses. This indicates that the quantity is normalized when... A value of 1 indicates that both adjacent page addresses of any suspected abnormal page address are suspected abnormal page addresses, meaning that a programming abnormality has occurred simultaneously in the same area on the chip, which is a strong indication of chip quality abnormality. Let N represent an exponential function with base to the natural constant, and let N represent the number of page addresses in the set of page addresses containing the arbitrary suspected abnormal page address. This represents the average number of page address intervals between the nth suspected abnormal page address and its two nearest adjacent suspected abnormal page addresses. A smaller number of intervals indicates a denser distribution of suspected abnormal page addresses within that page address set. The larger the value, the more indicative it is of chip quality abnormalities. M represents the number of other suspected abnormal page addresses in the same page address set as any suspected abnormal page address, and S represents the normalized value of the number of writes to that suspected abnormal page address. Let represent the normalized value of the number of writes to the m-th other suspected abnormal page address, and T represent the normalized value of the write time to that arbitrary suspected abnormal page address. This represents the normalized value of the write time for the m-th other suspected faulty page address. The smaller the difference in write time and the difference in the number of write failures between suspected faulty page addresses within the page address set, the better. The larger the value, the more similar the programmed information within that page address, and the more likely it is to be a chip quality anomaly. Therefore, the greater the actual degree of anomaly, the greater the probability of a chip quality anomaly. The normalized value is obtained by normalizing the maximum and minimum values.

[0037] Step S4: Obtain the chip's programming anomaly level based on the actual anomaly level of the suspected abnormal page address, the number of write failures, and the write time; detect the chip programming status based on the programming anomaly level.

[0038] After obtaining the actual anomaly level corresponding to all suspected abnormal page addresses, the programming information of page addresses with higher actual anomaly levels is more reliable. Therefore, the programming anomaly level of the chip can be obtained based on the actual anomaly level of the suspected abnormal page addresses, the number of write failures, and the write time. Preferably, in this embodiment of the invention, the step of obtaining the programming anomaly level includes:

[0039]

[0040] In the formula, W represents the degree of programming error, and H represents the number of suspected abnormal page addresses. This indicates the true degree of abnormality of the h-th suspected abnormal page address. This represents the normalized value of the number of writes to the h-th suspected abnormal page address. This represents the normalized value of the write time for the h-th suspected abnormal page address. More write failures and longer write times indicate a more abnormal programming process. Furthermore, a greater degree of actual abnormality suggests that the programming anomaly is more likely due to chip quality issues, and its contribution to the programming information is greater. Therefore, a higher degree of programming anomaly increases the likelihood of latent defects in the chip after programming, and the more likely anomalies will occur during subsequent use. The chip programming status is then detected based on the degree of programming anomaly. Specifically, when the degree of programming anomaly exceeds a preset second threshold, the chip programming status is manually re-inspected. The implementer can determine the preset second threshold based on the implementation scenario. The more likely the chip has latent defects, the more precise the re-inspection of the programmed chip is needed to determine its fate. Thus, calculating the degree of programming anomaly improves the accuracy of latent defect detection during chip programming, resulting in higher accuracy in chip programming evaluation.

[0041] In summary, this invention provides an efficient chip data processing method for the programming process. It obtains the suspected anomaly level of page addresses based on the differences in the number of write failures and the differences in write times between page addresses; identifies suspected abnormal page addresses based on the suspected anomaly level; clusters these suspected abnormal page addresses based on their distribution characteristics within the chip to obtain different page address sets; and obtains the true anomaly level based on the state characteristics of neighboring page addresses, the discrete distribution characteristics of their respective page address sets, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses within the same set. This invention obtains the chip programming anomaly level based on the true anomaly level of suspected abnormal page addresses, the number of write failures, and the write time; and detects the chip programming status based on the programming anomaly level, thus improving the accuracy of assessing latent defects in the chip.

[0042] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0043] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. A method for efficient processing of chip data during the programming process, characterized in that, The method includes the following steps: Obtain the number of write failures and write time for all page addresses in the chip; The degree of suspected anomaly of page addresses is obtained based on the differences in the number of write failures and the differences in write time between page addresses; suspected abnormal page addresses are obtained based on the degree of suspected anomaly; and different page address sets are obtained by clustering based on the distribution characteristics of the suspected abnormal page addresses in the chip. The true degree of abnormality is obtained based on the state characteristics of the neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set. The degree of chip programming anomaly is obtained based on the actual anomaly level of the suspected abnormal page address, the number of write failures, and the write time; the chip programming status is detected based on the degree of programming anomaly. The step of obtaining the suspected anomaly level of a page address based on the differences in the number of write failures and the differences in write time between page addresses includes: Calculate the average number of write failures for all page addresses in the chip to obtain the average number of failures; calculate the average write time for all page addresses in the chip to obtain the average time; calculate the difference between the number of write failures for any page address and the average number of failures, and normalize it to obtain a first value; calculate the difference between the write time for any page address and the average time, and normalize it to obtain a second value; calculate the sum of the first value and the second value to obtain the suspected abnormality level of the arbitrary page address. The step of obtaining the true degree of abnormality based on the state characteristics of the neighboring page addresses of the suspected abnormal page address, the discrete distribution characteristics of the page address set, and the differences in the number of write failures and write times between the suspected abnormal page address and other suspected abnormal page addresses in the page address set includes: In the formula, R represents the actual abnormality level of any suspected abnormal page address, and K represents the number of adjacent page addresses that are suspected abnormal page addresses. Let N represent an exponential function with the natural constant as its base, and let N represent the number of page addresses in the set of page addresses containing any suspected abnormal page address. Let M represent the average number of page address intervals between the nth suspected abnormal page address and its two nearest adjacent suspected abnormal page addresses; let M represent the number of other suspected abnormal page addresses in the page address set containing the given suspected abnormal page address; and let S represent the normalized value of the number of writes to the given suspected abnormal page address. Let T represent the normalized value of the number of writes to the m-th other suspected abnormal page address, and let T represent the normalized value of the write time to any of the suspected abnormal page addresses. This represents the normalized value of the write time of the m-th other suspected abnormal page address; The step of obtaining the chip programming anomaly level based on the actual anomaly level of the suspected abnormal page address, the number of write failures, and the write time includes: In the formula, W represents the degree of programming error, and H represents the number of suspected abnormal page addresses. This indicates the true degree of abnormality of the h-th suspected abnormal page address. This represents the normalized value of the number of writes to the h-th suspected abnormal page address. This represents the normalized value of the write time of the h-th suspected abnormal page address.

2. The method for efficient chip data processing during the programming process according to claim 1, characterized in that, The step of obtaining the suspected abnormal page address based on the suspected abnormality level includes: Page addresses whose suspected anomaly level exceeds a preset first threshold are designated as suspected abnormal page addresses.

3. The method for efficient chip data processing during the programming process according to claim 1, characterized in that, The step of clustering the suspected abnormal page addresses in the chip to obtain different sets of page addresses includes: Based on the address numbers of the suspected abnormal page addresses, the K-means clustering algorithm is used to cluster all the suspected abnormal page addresses to obtain different sets of page addresses.

4. The method for efficient chip data processing during the programming process according to claim 1, characterized in that, The step of detecting the chip programming status based on the degree of programming abnormality includes: When the degree of programming abnormality exceeds a preset second threshold, the chip programming status is manually re-inspected.

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