A Real-Time Redundant Fault-Tolerant Communication System Based on Dual RS-485 Links

Abstract

This application proposes a real-time redundant fault-tolerant communication system based on dual RS-485 links, belonging to the field of industrial communication and real-time control technology. It includes: two electrically independent but logically coordinated RS-485 physical links, at least one master node, and multiple slave nodes. The first RS-485 link is used for the master node to send data frames to the slave nodes, and the second RS-485 link is used for the slave nodes to send feedback frames to the master node. The two links form a parallel or alternating pipelined communication relationship in time. The feedback frame includes two timestamps: the first timestamp records the time when the slave node receives the data frame, and the second timestamp records the time when the slave node sends the feedback frame. This application's system has a simple structure, low cost, strong real-time performance, and high reliability, making it suitable for real-time systems such as industrial control, robotics, and motion control. It is a low-cost alternative to real-time Ethernet.

Description

Technical Field

[0001] This invention belongs to the field of industrial communication and real-time control technology, specifically relating to a real-time redundant fault-tolerant communication system based on dual RS-485 links. Background Technology

[0002] In real-time control fields such as industrial automation, robot control, motion control, and CNC systems, communication buses not only need to meet the requirements of high-speed data transmission, but also need to possess key characteristics such as deterministic timing, high-precision time synchronization, high reliability, and real-time feedback. Among these, deterministic timing requires predictable communication delays with low jitter; high-precision time synchronization requires support for accurate clock synchronization between distributed nodes; high reliability means that the system must have redundancy and fault tolerance capabilities; and real-time feedback requires the system to support status confirmation and closed-loop control.

[0003] Traditional RS-485 buses are widely used in industrial settings due to their simple structure, strong anti-interference capabilities, long transmission distances, and low costs. However, with the ever-increasing performance requirements of real-time control systems, existing RS-485 communication systems are facing increasingly severe technical bottlenecks. First, traditional RS-485 uses a half-duplex operating mode, requiring time-division multiplexing of transmission and reception on the same physical link. This necessitates frequent communication direction switching, introducing additional bus arbitration delays and direction-switching waiting times, making it difficult to meet the stringent requirements of microsecond-level deterministic real-time communication. Second, traditional RS-485 protocols lack a hard real-time time synchronization mechanism. Timestamps are typically transmitted as ordinary data fields at the application layer, and their timing accuracy is heavily influenced by factors such as communication scheduling, frame intervals, and bus arbitration, resulting in significant time synchronization jitter and failing to meet the extremely high time accuracy requirements of applications such as high-precision motion control. While RS-422 buses support full-duplex (four-wire), their physical layer definition is fixed as unidirectional transmission (one pair of wires transmits only, and the other pair receives only). If the transmitting wire pair breaks, the RS-422 cannot convert the receiving wire pair back into a transmitting wire pair, lacking link-level reconfiguration and redundancy capabilities. Furthermore, although some dual-bus redundancy solutions exist in the industry (such as redundant CAN buses), most of these solutions employ a master-slave hot-standby structure, using only one link for data transmission under normal operating conditions, while the other link remains idle. This not only results in low physical resource utilization but also increases the complexity of system implementation due to the intricate switching mechanism. Finally, due to the inherent characteristics of half-duplex communication, data transmission and feedback acknowledgment cannot be performed in parallel, leading to bus utilization typically below 50%, severely limiting the overall system performance.

[0004] To address real-time performance and time synchronization issues, various real-time Ethernet technologies have been developed in the industrial sector, such as EtherCAT, PROFINET IRT, POWERLINK, Ethernet / IP, and SERCOS III. These advanced technologies achieve nanosecond-level time synchronization accuracy by implementing complex clock synchronization protocols (such as IEEE 1588 PTP), and have been widely used in high-end industrial automation. However, while pursuing high performance, real-time Ethernet technology has also revealed many limitations. These systems require multi-layered protocol stacks, leading to significantly increased software complexity and high development and maintenance costs. At the hardware level, real-time Ethernet typically requires dedicated real-time Ethernet controller chips or FPGAs to implement time-critical functions, with hardware costs far exceeding those of traditional communication solutions. Furthermore, real-time Ethernet places high demands on processor performance and storage resources, requiring nodes to possess powerful computing capabilities and sufficient memory. The complexity of system integration and debugging is also a prominent issue, often requiring long development cycles and specialized technical support. More importantly, for small to medium-sized application scenarios with a small number of nodes and simple topologies, deploying real-time Ethernet is often not cost-effective, resulting in wasted resources. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application proposes a real-time redundant fault-tolerant communication system based on dual RS-485 links. By implementing alternating parallel transmission of data frames and feedback / synchronization frames between two electrically isolated but logically coordinated RS-485 physical links, it is suitable for applications such as industrial automation, motion control, and robot control that have strict requirements for real-time performance, reliability, and time synchronization accuracy.

[0006] This invention provides a real-time redundant fault-tolerant communication system based on dual RS-485 links, comprising:

[0007] The first RS-485 physical link includes: differential signal line A1, differential signal line B1, a first terminating resistor and a first transceiver chip, wherein the differential signal line A1 and differential signal line B1 form a first differential signal pair;

[0008] The second RS-485 physical link includes: differential signal line A2, differential signal line B2, a second terminating resistor and a second transceiver chip, wherein the differential signal line A2 and differential signal line B2 form a second differential signal pair;

[0009] At least one master node is connected to a first RS-485 physical link and a second RS-485 physical link respectively, and is used to schedule the first RS-485 physical link and the second RS-485 physical link, publish time base, send data frames and master node commands to slave nodes, and process the feedback frames of slave nodes.

[0010] Multiple slave nodes are connected to a first RS-485 physical link and a second RS-485 physical link, respectively, and are used to respond to master node commands, execute control instructions, and send feedback frames. The feedback frame includes two timestamps: the first timestamp records the time when the slave node receives the data frame, and the second timestamp records the time when the slave node sends the feedback frame.

[0011] The feedback frame includes: a frame start identifier, an associated frame sequence number, a source address, a first timestamp, a second timestamp, an execution status code, an error flag, status data, security authentication information, and a cyclic redundancy check code for the feedback frame.

[0012] The data frame includes: a frame start identifier, frame type, frame sequence number, target address, data payload length, time reference information, data payload, and cyclic redundancy check code of the data frame.

[0013] Both timestamps are automatically latched by the hardware circuit when the start-of-frame identifier is detected.

[0014] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes:

[0015] The master node is also used to automatically latch data frames in hardware when transmitting them on the first RS-485 physical link, and to receive the transmission time T transmitted by the hardware. mastersend ;

[0016] The slave node is also configured to automatically latch the data upon receiving the start-of-frame identifier of a data frame, and to receive the reception time T transmitted by the hardware. slaverecv Receive time T slaverecv Stored within the first timestamp;

[0017] The slave node is also used to automatically latch the data while sending a feedback frame on the second RS-485 physical link, and to receive the transmission time T transmitted by the hardware. slavesend Sending time T slavesend Stored in the second timestamp, the feedback frame is sent to the master node;

[0018] The master node is also used to automatically latch the received feedback frame in hardware, and the master node receives the reception time T transmitted by the hardware. masterrecv .

[0019] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes:

[0020] The master node is also used to determine the transmission time T. mastersend Reception time T slaverecv Sending time Tslavesend and the receiving time T masterrecv Calculate round-trip time and clock skew;

[0021] The slave node is further configured to adjust its local clock based on the time reference information and clock offset sent by the master node in the data frame, so as to achieve time synchronization between the slave node and the master node. The time reference information is the transmission time T. mastersend .

[0022] The round-trip time is calculated as follows:

[0023] RTT = (T masterrecv - T mastersend ) - (T2 - T1);

[0024] Where RTT is the round-trip time, T masterrecv The receiving time of the master node, T mastersend T1 is the time when the master node sends the data, T2 is the time saved in the second timestamp, and T1 is the time saved in the second timestamp.

[0025] The clock offset is calculated as follows:

[0026] Clock offset = [(T1 - T mastersend ) - (T masterrecv - T2)] / 2;

[0027] Among them, Clock offset For clock skew, T masterrecv The receiving time of the master node, T mastersend T1 is the time when the master node sends the data, T2 is the time saved in the second timestamp, and T1 is the time saved in the second timestamp.

[0028] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: the first RS-485 physical link and the second RS-485 physical link operating in a dual-link parallel mode, including:

[0029] The first RS-485 physical link and the second RS-485 physical link work in parallel. One RS-485 physical link is used to transmit data frames, and the other RS-485 physical link is used to transmit feedback frames.

[0030] Each slave node simultaneously monitors the communication quality of the first RS-485 physical link and the second RS-485 physical link;

[0031] If the communication quality does not meet the preset value, the first RS-485 physical link or the second RS-485 physical link will be reconstructed.

[0032] The real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: when the first RS-485 physical link is in a fault state, reconstructing the second RS-485 physical link into a half-duplex working mode, the master node sends data frames through the second RS-485 physical link, and the slave node returns a feedback frame on the second RS-485 physical link after receiving the data frame, adjusting the communication cycle of the second RS-485 physical link and increasing the direction switching time; when the second RS-485 physical link is in a fault state, reconstructing the first RS-485 physical link into a half-duplex working mode, the master node sends data frames through the first RS-485 physical link, and the slave node returns a feedback frame on the first RS-485 physical link after receiving the data frame, adjusting the communication cycle of the first RS-485 physical link and increasing the direction switching time.

[0033] The real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: arbitrarily selecting one RS-485 physical link from the first and second RS-485 physical links for transmitting command information, and selecting the other RS-485 physical link for transmitting authentication information; the master node includes a random challenge code in the data frame; and the slave node returns a response code calculated based on the challenge code and the shared key in the feedback frame.

[0034] Beneficial effects:

[0035] This application proposes a real-time redundant fault-tolerant communication system based on dual RS-485 links. Regarding communication efficiency, this application achieves a fundamental breakthrough overcoming the traditional RS-485 half-duplex bottleneck through a dual-link parallel transmission mechanism. By allowing data frames and feedback frames to be transmitted in parallel on two independent links, the direction switching waiting time is completely eliminated, resulting in a 50%-100% improvement in communication efficiency compared to traditional solutions. This performance improvement is not only reflected in the increased data throughput, but more importantly, it achieves true full-duplex communication, providing more ample communication bandwidth for real-time control systems. Attached Figure Description

[0036] Figure 1 An embodiment of the present invention provides a real-time redundant fault-tolerant communication system based on dual RS-485 links;

[0037] Figure 2 Schematic diagram of data frame and feedback frame formats according to an embodiment of the present invention;

[0038] Figure 3 Pipeline communication timing diagram of an embodiment of the present invention;

[0039] Figure 4Schematic diagram of the time synchronization mechanism in this invention embodiment;

[0040] Figure 5 Redundancy and fault tolerance flowchart of an embodiment of the present invention. Detailed Implementation

[0041] The specific implementation methods of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0042] Example 1:

[0043] This embodiment provides a real-time redundant fault-tolerant communication system based on dual RS-485 links, such as... Figure 1 As shown, it includes:

[0044] The first RS-485 physical link includes: differential signal line A1, differential signal line B1, a first terminating resistor and a first transceiver chip, wherein the differential signal line A1 and differential signal line B1 form a first differential signal pair;

[0045] In this embodiment, the differential signal line A1 and differential signal line B1 are twisted pairs.

[0046] The second RS-485 physical link includes: differential signal line A2, differential signal line B2, a second terminating resistor and a second transceiver chip, wherein the differential signal line A2 and differential signal line B2 form a second differential signal pair;

[0047] In this embodiment, differential signal line A2 and differential signal line B2 are twisted pairs.

[0048] At least one master node is connected to a first RS-485 physical link and a second RS-485 physical link respectively, and is used to schedule the first RS-485 physical link and the second RS-485 physical link, publish time base, send data frames and master node commands to slave nodes, and process the feedback frames of slave nodes.

[0049] Multiple slave nodes are connected to a first RS-485 physical link and a second RS-485 physical link, respectively, and are used to respond to master node commands, execute control instructions, and send feedback frames. The feedback frame includes two timestamps: the first timestamp records the time when the slave node receives the data frame, and the second timestamp records the time when the slave node sends the feedback frame.

[0050] In this embodiment, the master node includes: RS485 transmitter 1, RS485 transmitter 2, RS485 receiver 1 and RS485 receiver 2, wherein RS485 transmitter 1 and RS485 receiver 1 are respectively transmitting and receiving information in the first RS-485 physical link, and RS485 transmitter 2 and RS485 receiver 2 are respectively transmitting and receiving information in the second RS-485 physical link.

[0051] The slave node N (N is a positive integer) includes: RS485 transmitter 1, RS485 transmitter 2, RS485 receiver 1, RS485 receiver 2, and slave controller N.

[0052] The core innovation of this embodiment lies in the effective organization and coordination of the two RS-485 physical links. The first and second RS-485 physical links are completely isolated at the electrical level, each with independent differential signal pairs, independent transceiver circuits, and independent terminating resistor configurations. This electrical isolation design not only provides inherent hardware redundancy but also lays the foundation for subsequent fault detection and isolation. Logically, these two physically independent links do not operate independently but are managed by a unified communication protocol and precise timing control, forming a collaborative organic whole. Each node (including the master node and all slave nodes) is simultaneously connected to both RS-485 physical links and possesses dual-channel synchronous transmission and reception capabilities. This fully symmetrical connection method allows the system to flexibly allocate link functions and perform fault switching, which is a key foundation for achieving high reliability and high performance.

[0053] RS-485 physical link function allocation and alternating transmission mechanism:

[0054] Under normal system operation, the two RS-485 physical links operate in a functionally separated, time-interleaved mode, such as... Figure 3 As shown:

[0055] (1) Within the first time period:

[0056] The first RS-485 physical link: The master node broadcasts or sends data frames Data[n] to the slave node, which contain information such as control commands, parameter settings, and time references;

[0057] The second RS-485 physical link: The slave node sends a feedback frame Ack[n-1] to the master node for the previous data frame Data[n-1], which includes information such as execution status, timestamp, and verification result.

[0058] (2) During the second time period:

[0059] First RS-485 physical link: The master node sends a new data frame Data[n+1] to the slave node;

[0060] Second RS-485 physical link: The slave node sends a feedback frame Ack[n] to the master node for the current data frame Data[n].

[0061] Regarding the organization of time windows, the timing relationship between the first time period (i.e., the first time window) and the second time period (i.e., the second time window) can be flexibly configured according to system requirements. When the two windows completely overlap, data frames and feedback frames are transmitted in complete parallel time, maximizing communication concurrency. When the two windows partially overlap, the system maintains a certain degree of parallelism while reserving the necessary time margin for link switching and synchronization, forming an efficient pipelined communication mode. Even with a configuration where the two windows are adjacent but do not overlap, the system can still achieve sequential execution without idle waiting, ensuring full utilization of communication resources.

[0062] This pipelined communication characteristic fundamentally changes the working mode of traditional half-duplex communication. Because data frames and feedback frames are transmitted on different physical links, similar to the pipelined working mechanism of a computer CPU, the system completely eliminates the waiting time caused by direction switching in traditional half-duplex communication, achieving true communication pipelined operation. The duration of each communication cycle is strictly fixed, and timing parameters such as data frame transmission time, feedback frame transmission time, and frame interval are all deterministic constants, making communication latency completely predictable and meeting the stringent timing determinism requirements of hard real-time systems. More importantly, the bandwidth doubling effect generated by the simultaneous operation of two physical links makes the total system communication bandwidth twice that of a single link, achieving higher data throughput at the same physical rate and providing ample communication capacity support for complex control applications.

[0063] The data frame, such as Figure 2 As shown, the data frame includes: frame start identifier, frame type, frame sequence number, destination address, data payload length, time reference information, data payload, and cyclic redundancy check code, as shown in Table 1.

[0064] The feedback frame, such as Figure 2 As shown, the feedback frame includes: frame start identifier, associated frame sequence number, source address, first timestamp, second timestamp, execution status code, error flag, status data, security authentication information, and cyclic redundancy check code, as shown in Table 2.

[0065] Table 1 Data Frame Structure:

[0066] ;

[0067] In this embodiment, the frame start identifier is used for frame synchronization; the frame sequence number is used for frame association and frame loss detection; the target address indicates the target slave node; the time reference information includes the master node's hardware timestamp; the data payload includes control commands or parameters; and the check field is used for error detection. At the same time the master node sends a data frame, the hardware circuit automatically latches a high-precision timestamp. This timestamp's precision can reach the level of physical layer bit time, for example, 100ns at a 10Mbps communication rate. This hardware-level timestamp mechanism completely avoids the impact of software processing delays and scheduling uncertainties, laying a solid foundation for subsequent accurate time synchronization. In this embodiment, the hardware circuit can be implemented using common hardware circuits such as an RTC real-time clock, which will not be described in detail here.

[0068] The frame sequence number mechanism provides the system with powerful frame association and integrity detection capabilities. Each data frame is assigned a unique, cyclically incrementing sequence number, and feedback frames establish a one-to-one correspondence with the corresponding data frames by referencing this sequence number. This explicit association not only supports advanced functions such as out-of-order confirmation and selective retransmission, but also enables the system to accurately detect anomalies such as frame loss and duplicate frames, significantly improving communication reliability.

[0069] The scalable design of the frame structure ensures that the system can adapt to different application requirements and future functional expansions. By supporting optional fields (such as security authentication codes, priority identifiers, extended data types, etc.), the system can flexibly add new functionalities according to specific application scenarios while maintaining the stability of core functions. This design philosophy reserves ample room for the long-term evolution of the system.

[0070] Table 2 Feedback Frame Structure:

[0071] ;

[0072] In this embodiment, the associated frame sequence number indicates the corresponding data frame; the first timestamp is the hardware latch time for the slave node to receive the data frame; the second timestamp is the hardware latch time for the slave node to send the feedback frame; the execution status information indicates the instruction execution result; the error detection field contains the verification result or error flag; and the verification field is used for error detection. The dual timestamp mechanism used in the feedback frame is one of the key innovations in achieving high-precision time synchronization in this embodiment. The first timestamp T1 records the precise moment when the slave node receives the data frame, and the second timestamp T2 records the precise moment when the slave node sends the feedback frame. Both timestamps are automatically latched by the hardware circuit at the moment the start of frame (SOF) is detected, completely eliminating the uncertainty caused by software processing. By comprehensively analyzing its own sending timestamp, receiving timestamp, and the T1 and T2 fed back by the slave node, the master node can accurately calculate the round-trip transmission delay of the signal and the clock deviation between the master and slave nodes. This bidirectional time measurement method based on four hardware timestamps can achieve sub-microsecond time synchronization accuracy on a standard RS-485 physical layer, and its performance level is comparable to that of real-time Ethernet systems using complex clock synchronization protocols.

[0073] The associated frame sequence number field plays a crucial role in the feedback frame, explicitly indicating which data frame the feedback frame corresponds to. This explicit association mechanism enables the system to support more flexible communication strategies, such as allowing feedback frames to arrive out of order, supporting selective acknowledgment, and implementing advanced functions such as priority-based retransmission, greatly enhancing the system's adaptability under complex operating conditions.

[0074] Multi-dimensional status feedback capabilities transform feedback frames from simple response signals into information-rich status report carriers. Beyond basic execution result confirmation, feedback frames can carry data such as real-time sensor readings, equipment operating status, diagnostic information, and error codes. Timely feedback of this information provides the necessary feedback channel for the master node to achieve true closed-loop control, enabling the entire system to respond promptly to changes in the field, achieving precise dynamic adjustment and fault early warning.

[0075] Both timestamps are automatically latched by the hardware circuit when the start-of-frame identifier is detected.

[0076] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes:

[0077] The master node is also used to automatically latch data frames in hardware when transmitting them on the first RS-485 physical link, and to receive the transmission time T transmitted by the hardware. mastersend ;

[0078] The slave node is also configured to automatically latch the data upon receiving the start-of-frame identifier of a data frame, and to receive the reception time T transmitted by the hardware. slaverecv Receive time T slaverecv Stored within the first timestamp;

[0079] The slave node is also used to automatically latch the data while sending a feedback frame on the second RS-485 physical link, and to receive the transmission time T transmitted by the hardware. slavesend Sending time T slavesend Stored in the second timestamp, the feedback frame is sent to the master node;

[0080] The master node is also used to automatically latch the received feedback frame in hardware, and the master node receives the reception time T transmitted by the hardware. masterrecv .

[0081] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes:

[0082] The master node is also used to determine the transmission time T. mastersend Reception time T slaverecv Sending time T slavesend and the receiving time T masterrecv Calculate round-trip time and clock skew;

[0083] The slave node is also used to adjust its local clock based on the time reference information and clock deviation sent by the master node in the data frame, so as to achieve time synchronization between the slave node and the master node.

[0084] Deterministic time synchronization mechanism:

[0085] In this embodiment, under high-speed deterministic communication scenarios, traditional broadcast synchronization frames can only achieve application-layer synchronization and cannot eliminate the propagation delay caused by signal transmission on the physical link. Since electrical signals have a transmission delay of approximately 5 ns / m in twisted-pair cables, for long-distance buses, there is a significant deviation in the absolute time at which slave nodes closer to the master node receive the broadcast frame compared to those at the far end. This embodiment aims to incorporate physical layer propagation delay into the compensation scope by calculating the round-trip time (RTT), thereby achieving sub-microsecond time alignment across physical distance limitations.

[0086] This embodiment achieves high-precision time synchronization through hardware timestamps and bidirectional time measurement, such as... Figure 4 As shown, the specific process is as follows:

[0087] (1) Timestamp latching:

[0088] While the master node is sending data frames on the first RS-485 physical link, the hardware automatically latches the transmission time T. mastersend The master node sends Data[n], which includes the master node's time reference.

[0089] Master node propagation delay ;

[0090] When a slave node receives the start-of-frame identifier of a data frame, the hardware automatically latches the reception time T. slaverecv (i.e., T1);

[0091] Processing latency from the node That is, T2 - T1;

[0092] While the slave node sends the feedback frame on the second RS-485 physical link, the hardware automatically latches the transmission time T. slavesend (i.e., T2);

[0093] Send Ack[n] (including T2 and T1) from the node;

[0094] Delay from node propagation ;

[0095] When the master node receives a feedback frame, the hardware automatically latches the receiving time T. masterrecv .

[0096] (2) Calculation of round-trip time delay:

[0097] The master node calculates the round-trip latency based on the four timestamps mentioned above:

[0098] The round-trip time is calculated as follows:

[0099] RTT = (T masterrecv - T mastersend ) - (T2 - T1);

[0100] Where RTT is the round-trip time, T masterrecv The receiving time of the master node, T mastersend T1 is the sending time of the master node, T2 is the time stored in the second timestamp, T1 is the time stored in the second timestamp, and (T2 - T1) is the processing delay of the slave node (known or measurable).

[0101] The one-way transmission delay is RTT / 2.

[0102] (3) Clock deviation estimation:

[0103] The master node estimates the clock skew between the master and slave nodes based on the round-trip time and a known link delay model:

[0104] The clock offset is calculated as follows:

[0105] Clock offset = [(T1 - T mastersend ) - (T masterrecv - T2)] / 2;

[0106] Among them, Clock offset For clock skew, T masterrecv The receiving time of the master node, T mastersend T1 is the time when the master node sends the data, T2 is the time saved in the second timestamp, and T1 is the time saved in the second timestamp.

[0107] (4) Clock calibration:

[0108] The slave node adjusts its local clock based on the time reference information sent by the master node in the data frame and the calculated clock offset, thereby achieving time synchronization with the master node.

[0109] The specific synchronization process is as follows: Figure 4 As shown:

[0110] In this embodiment, the timestamp latch, implemented entirely in hardware, is the cornerstone of this system's high-precision time synchronization. The entire timestamp latching process is completed automatically by the hardware circuitry. From detecting the start of the frame marker to the latch counter value, no software intervention is involved. Its accuracy can reach the level of physical layer bit time, completely unaffected by software factors such as operating system scheduling and interrupt response delays. This hardware-level implementation reduces the uncertainty of time measurement to the nanosecond level, providing a reliable guarantee for achieving high-precision time synchronization.

[0111] The closed-loop synchronization mechanism endows the system with the ability to continuously adapt and correct itself. By continuously receiving timestamp information from feedback frames, the master node can construct a complete time synchronization closed loop, and monitor and evaluate the clock deviation and drift trend between the master and slave nodes in real time. Based on this real-time feedback information, the system can dynamically adjust synchronization parameters and actively compensate for clock drift, thereby maintaining a stable and high-precision time synchronization state throughout the entire system operation.

[0112] The deterministic nature of communication delay is another key element in achieving high-precision time synchronization. Because the system uses a fixed communication period and strictly controlled frame length, the delay for each data transmission is a predictable constant, eliminating the delay jitter caused by contention arbitration and random backoff mechanisms found in traditional Ethernet. This deterministic delay characteristic simplifies the clock skew calculation model, improves the accuracy and convergence speed of the synchronization algorithm, and enables the system to reach a stable synchronization state in a shorter time.

[0113] The low jitter characteristic brought by dual-link parallel transmission further improves the stability of time synchronization. In traditional half-duplex communication systems, the uncertainty of direction switching introduces significant time jitter. However, this invention completely eliminates this source of uncertainty by transmitting data frames and feedback frames on two independent links, reducing time synchronization jitter to an almost negligible level and providing an ideal communication foundation for application scenarios requiring stable timing.

[0114] Synchronization accuracy analysis:

[0115] At a communication rate of 10 Mbps, with a bit time of 100 ns, the hardware timestamp accuracy can reach ±100 ns. Considering the deterministic and symmetric nature of link delay, the system time synchronization accuracy can reach the sub-microsecond level, far superior to the millisecond-level synchronization accuracy of traditional RS-485 systems.

[0116] Dynamic function switching and refactoring mechanism:

[0117] In a preferred embodiment, the functional allocation of the first RS-485 physical link and the second RS-485 physical link is not fixed, but can be dynamically adjusted according to a preset strategy or system operating status. This flexibility significantly enhances the robustness and maintainability of the system.

[0118] To balance the load distribution and physical wear of the two links, the system can implement a periodic function switching strategy. Under this strategy, the functional roles of the two links are swapped according to a predetermined cycle. For example, during odd-numbered communication cycles, the first RS-485 physical link is responsible for transmitting data frames while link 2 is responsible for transmitting feedback frames. During even-numbered communication cycles, the opposite occurs: link 1 transmits feedback frames while the second RS-485 physical link transmits data frames. This role-switching mechanism not only maintains a balanced workload between the two links and extends hardware lifespan, but also continuously verifies the operational status of the two links during long-term operation, allowing for early detection of potential performance degradation issues.

[0119] Another important feature is the system's fault-adaptive reconfiguration capability. When the system detects an anomaly in the first RS-485 physical link (such as a physical disconnection, short circuit, or bit error rate exceeding a set threshold), the control logic automatically reconfigures the second RS-485 physical link into a half-duplex mode, enabling it to simultaneously carry the transmission of data frames and feedback frames. Similarly, when an anomaly is detected in the second RS-485 physical link, the system reconfigures the first RS-485 physical link into a half-duplex mode. This automatic reconfiguration mechanism ensures that even in the event of a single-link failure, the system can continue normal communication, although the communication cycle will increase accordingly to accommodate the direction switching time. More importantly, when both links return to normal operation, the system can automatically detect this change and gradually restore to the dual-link parallel operation mode using a smooth transition strategy. The entire recovery process does not cause communication interruption to upper-layer applications.

[0120] In addition, the system supports dynamically adjusting the transmission priority and bandwidth allocation ratio of data frames and feedback frames according to actual application needs. This flexible resource scheduling capability enables the system to adapt to different working scenarios and performance requirements.

[0121] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: the first RS-485 physical link and the second RS-485 physical link operating in a dual-link parallel mode, including:

[0122] The first RS-485 physical link and the second RS-485 physical link work in parallel. One RS-485 physical link is used to transmit data frames, and the other RS-485 physical link is used to transmit feedback frames.

[0123] Each slave node simultaneously monitors the communication quality of the first RS-485 physical link and the second RS-485 physical link;

[0124] If the communication quality does not meet the preset value, the first RS-485 physical link or the second RS-485 physical link will be reconstructed.

[0125] In this embodiment, the dual-link architecture inherently possesses redundancy capabilities, and the specific fault tolerance strategy is as follows:

[0126] (1) Normal working mode:

[0127] Two RS-485 physical links operate simultaneously, transmitting data frames and feedback frames respectively;

[0128] Each node simultaneously monitors the communication quality of two links, including metrics such as bit error rate, frame loss rate, and latency jitter.

[0129] (2) Single-link fault detection:

[0130] A link failure is determined when the following abnormal conditions are detected:

[0131] N consecutive frames of CRC check failure (N is a configurable threshold, typically 3, based on a balance between false detection rate and detection latency);

[0132] No signal on the link (carrier detection failed);

[0133] Frame timeout (the expected frame was not received within the specified time window);

[0134] Frame sequence numbers are not consecutive (frames are dropped).

[0135] (3) Automatic reconfiguration mechanism:

[0136] Scenario 1: First RS-485 physical link failure:

[0137] (a) The system automatically reconfigures the second RS-485 physical link into a half-duplex working mode;

[0138] (b) The master node sends a data frame through the second link, and the slave node receives it and returns a feedback frame on the same link;

[0139] The communication cycle is adjusted accordingly, increasing the direction switching time.

[0140] Scenario 2: Second RS-485 physical link failure:

[0141] (a) The system automatically reconfigures the first RS-485 physical link into a half-duplex working mode;

[0142] (b) The master node sends data frames and receives feedback frames through the first link.

[0143] Scenario 3: Single-link recovery:

[0144] (a) When the faulty link returns to normal, the system automatically detects and gradually restores the dual-link parallel working mode;

[0145] (b) The recovery process employs a smooth transition strategy to avoid communication interruption.

[0146] (4) Fault isolation and reporting:

[0147] (a) The faulty link is logically isolated, which does not affect the communication of the normal link;

[0148] (b) The master node reports link status changes and redundancy mode switching events to the upper-layer application;

[0149] (c) Supports fault logging and remote diagnostics.

[0150] The system has a communication rate of 1Mbps-10Mbps, a bit time of 100ns-1μs, and a time synchronization accuracy at the bit time level, supporting deterministic real-time communication at the microsecond or submicrosecond level.

[0151] like Figure 5 As shown, the specific redundancy and fault tolerance process includes:

[0152] Step S1: Initialize dual links, including: a first RS-485 physical link and a second RS-485 physical link;

[0153] Step S2: The dual links are in normal communication mode;

[0154] Step S3: Monitor link status;

[0155] Step S4: Detect whether the link has failed;

[0156] Step S5: If both links fail, stop immediately and report the fault.

[0157] Step S6: If the first RS-485 physical link fails and there is no response for N consecutive frames, the second RS-485 physical link is reconstructed into half-duplex mode. The transmission period of the second RS-485 physical link is extended. When the first RS-485 physical link is restored, it smoothly transitions to the normal dual-link communication mode.

[0158] Step S7: If the second RS-485 physical link fails and there is no response for N consecutive frames, the first RS-485 physical link is reconstructed into half-duplex mode, and the transmission period of the first RS-485 physical link is extended. When the second RS-485 physical link is restored, it smoothly transitions to the normal dual-link communication mode.

[0159] The system described in this example supports at least one of the following topologies: bus topology; star topology; hybrid topology; and each node is connected to two RS-485 physical links simultaneously, providing dual-channel transmit and receive capabilities.

[0160] In the field of mobile robot technology, mobile robots include wheeled or legged mobile mechanisms with multiple drive joints and sensor nodes; dual RS-485 physical links adopt a vibration-resistant connection method to adapt to the vibration and shock environment of the mobile platform; the system supports a hierarchical architecture, with the bottom layer real-time control using a dual RS-485 system and the upper layer non-real-time communication using industrial Ethernet or wireless communication; dual-link redundancy ensures uninterrupted communication during movement, with a fault switching time of less than 100 microseconds, meeting the continuity requirements of motion control.

[0161] This embodiment supports hot-swapping and dynamic node discovery, including: each slave node has a unique identifier (UID) containing chip serial number, product type, and manufacturer identifier; the master node discovers online nodes through broadcast scan commands, collects UIDs, and automatically assigns communication addresses; the master node continuously monitors the response status of slave nodes, and automatically reallocates communication time slots when a node is detected to be offline, and completes address allocation and communication establishment within 200ms when a new node connects; slave nodes adopt a random delayed response mechanism based on UID hashing to avoid conflicts caused by multiple nodes responding simultaneously.

[0162] This embodiment supports encrypted communication, including: the payloads of data frames and feedback frames are encrypted using a symmetric encryption algorithm (AES or ChaCha20), and a message authentication code (HMAC or Poly1305) is attached to prevent tampering; the initialization vector is generated by combining the frame sequence number and timestamp to prevent replay attacks; utilizing the physical isolation characteristics of dual RS-485 links, control commands and authentication information are transmitted on the two links respectively and encrypted using different keys, providing dual security protection; it supports a hardware encryption accelerator, with encryption overhead less than 1% of the communication cycle, having minimal impact on real-time performance; and it supports two key management modes: pre-shared key (PSK) and dynamic key negotiation (ECDH, Elliptic Curve Diffie–Hellman key Exchange).

[0163] In this embodiment, the system's fault detection capability is built upon a multi-layered, fine-grained real-time monitoring mechanism. Through frame-level checksum and sequence number monitoring, the system can complete fault detection in an extremely short time (typically only a few frames of transmission time, equivalent to tens of microseconds). This rapid detection capability is a prerequisite for achieving seamless switching. The detection mechanism not only focuses on single errors but also accurately distinguishes between sporadic interference and persistent faults by statistically analyzing the number of consecutive error frames and error patterns, thus avoiding misjudgments and unnecessary mode switching caused by transient interference.

[0164] Seamless switching capability ensures business continuity in the face of link failures. The entire link reconstruction process is completely transparent to upper-layer applications, allowing applications to smoothly switch between normal and redundant modes without modifying any code. Through a carefully designed state machine and buffering mechanism, the system ensures that no data is lost during mode switching and that there is no communication interruption. Users only experience a slight increase in communication cycle time, while core functions remain unaffected.

[0165] The bidirectional redundancy feature endows the system with extremely high flexibility and reliability. Unlike traditional primary-backup redundancy schemes, the two links in this system are completely equidistant. Either link can serve as both the primary channel for data transmission and the backup channel for redundancy protection. This symmetrical design not only simplifies the system logic and reduces implementation complexity, but also enables the system to fully utilize the transmission capacity of both links, doubling the bandwidth under normal conditions and providing reliable communication guarantees in fault conditions.

[0166] Hot-swappable capability significantly improves system maintainability and availability. When a link is repaired due to maintenance or failure, the system can automatically detect the link recovery and gradually reinstate it without interrupting communication. The entire recovery process employs a smooth transition strategy, using progressive state migration and verification mechanisms to ensure the link's operational stability before full activation, avoiding frequent switching caused by link instability. This achieves true online repair and recovery without requiring system restarts or downtime maintenance.

[0167] The aforementioned real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: initializing a first RS-485 physical link (i.e., link 1) and a second RS-485 physical link (i.e., link 2). Both links operate normally in parallel mode. Link 1 sends data; the master node sends Data[n], and the slave node receives and stores it as T1. Link 2 receives data; the slave node sends Ack[n-1], and the master node receives and synchronizes. When the first RS-485 physical link is in a fault state (link 1 fails, no response for 3 consecutive frames, i.e., only link 2 is normal, single-link mode 2 is initiated), the second RS-485 physical link is reconstructed into a half-duplex working mode, corresponding to an extended cycle. The master node sends data frames through the second RS-485 physical link, and the slave node... After receiving the data frame, a feedback frame is returned on the second RS-485 physical link, adjusting the communication cycle of the second RS-485 physical link and increasing the direction switching time. After link 1 recovers, it smoothly transitions to normal operation of dual links. When the second RS-485 physical link is in a fault state (link 2 is faulty, no response for 3 consecutive frames, i.e. only link 1 is normal, and single link mode 1 is started), the first RS-485 physical link is reconstructed into a half-duplex working mode, and the corresponding cycle is extended. The master node sends data frames through the first RS-485 physical link, and after receiving the data frame, the slave node returns a feedback frame on the first RS-485 physical link, adjusting the communication cycle of the first RS-485 physical link and increasing the direction switching time. After link 2 recovers, it smoothly transitions to normal operation of dual links.

[0168] The real-time redundant fault-tolerant communication system based on dual RS-485 links further includes: arbitrarily selecting one RS-485 physical link from the first and second RS-485 physical links for transmitting command information, and selecting the other RS-485 physical link for transmitting authentication information; the master node includes a random challenge code in the data frame; and the slave node returns a response code calculated based on the challenge code and the shared key in the feedback frame.

[0169] Security enhancement mechanisms:

[0170] In application scenarios with special security requirements, this embodiment supports the following security enhancement functions:

[0171] (1) Security strategy of physical link isolation:

[0172] Sensitive command information and critical authentication information are transmitted on two separate physical links.

[0173] Attackers need to eavesdrop on or tamper with two physical links simultaneously to obtain complete information, significantly increasing the difficulty of the attack.

[0174] (2) Message Authentication Code (MAC):

[0175] The data frame and the feedback frame contain a message authentication code based on the shared key;

[0176] The receiver verifies the MAC address to confirm message integrity and the sender's identity.

[0177] (3) Challenge-Response Mechanism:

[0178] The master node includes a random challenge code in the data frame;

[0179] The node returns a response code calculated based on the challenge code and the shared key in the feedback frame;

[0180] The master node verifies the correctness of the response code to prevent replay attacks.

[0181] (4) Timestamp protection:

[0182] Utilize hardware timestamps to detect abnormal latency and identify potential man-in-the-middle attacks;

[0183] Frames that time out or have abnormal latency are rejected.

[0184] (5) Encryption protection (optional):

[0185] Lightweight encryption (such as AES-128) is applied to the data payload;

[0186] The key is pre-distributed or dynamically updated through a secure channel.

[0187] Compared with existing technologies, as shown in Table 3.

[0188] Table 3: Comparison with Existing Technologies

[0189] ;

[0190] Advantages in specific application scenarios:

[0191] In the field of collaborative robots: the communication system cost of this embodiment is only 20-25% of that of real-time Ethernet solutions, which can significantly reduce the selling price of collaborative robots, and this is of great significance to the market for medium- and low-cost collaborative robots. At the same time, dual-link redundancy naturally meets the dual-channel monitoring requirements of the functional safety standard (ISO 10218), simplifying the safety certification process.

[0192] In the field of mobile robotics: The high anti-interference capability of differential signals is particularly suitable for the strong electromagnetic interference environment of AGVs / AMRs (high-current motor drives, PWM inverters, etc.). Lightweight cabling (60% less than Ethernet) has a positive impact on the energy consumption and load capacity of mobile platforms. Two-wire cabling simplifies cable chain design and reduces maintenance costs.

[0193] In the field of biomimetic robotics, multi-jointed biomimetic robots (humanoid, quadrupedal, etc.) typically contain 20-50 control nodes, making traditional solutions prohibitively expensive. This invention, through a multi-bus parallel architecture, keeps costs within a manageable range, making it affordable for R&D startups and consumer-grade products. The simple protocol stack (compared to real-time Ethernet) significantly shortens the development cycle, making it suitable for rapid iteration in robot development.

[0194] Advantages of intelligence and security:

[0195] Hot-swappable and plug-and-play: The system supports hot-swapping of nodes, achieving automatic discovery and address allocation through a unique identifier (UID). New nodes are configured within 200ms after connection. In applications such as collaborative robot quick-change tools and AGV modular configuration, users can replace modules without manual configuration, significantly improving usability and maintenance efficiency.

[0196] Topology Adaptive Capability: The system can dynamically adjust communication scheduling based on the online status of nodes, and automatically reallocate time slots when nodes are added or removed, ensuring efficient utilization of communication resources. It supports various topologies such as daisy chain and star, and can switch between them online.

[0197] Advanced security protection: Supports AES-128 / ChaCha20 encryption and HMAC / Poly1305 message authentication to prevent data eavesdropping and tampering. Utilizing dual-link physical isolation, it implements a dual-channel independent encryption strategy, improving security by 100 times compared to single-channel encryption. Hardware encryption acceleration reduces encryption overhead to <1μs, with minimal impact on real-time performance. Supports challenge-response authentication and dynamic key negotiation, meeting industrial network security standards such as IEC 62443.

[0198] Cost-feature ratio advantage: Compared to real-time Ethernet, this embodiment provides advanced features such as hot-plugging and encryption at only 20-25% of the cost, enabling small and medium-sized devices to obtain enterprise-level features at a low cost.

[0199] To more clearly describe the application of this embodiment in specific scenarios, some examples are listed below:

[0200] Example 1: 10Mbps Dual RS-485 Real-time Motion Control System;

[0201] (1) Application scenarios:

[0202] This example applies to a multi-axis motion control system, which includes one main controller and eight servo drive nodes.

[0203] System requirements: Control cycle: 250μs; Position synchronization accuracy: <1μs; Communication reliability: >99.99%; Support for fault diagnosis and redundancy switching.

[0204] (2) Hardware configuration:

[0205] Physical layer parameters: RS-485 communication rate: 10Mbps; bit time: 100ns; two independent RS-485 differential physical links (A1 / B1 and A2 / B2); terminating resistor: 120Ω; maximum bus length: 50m (10Mbps).

[0206] Node configuration:

[0207] Each node includes: a dual-channel RS-485 transceiver or two single-channel RS-485 transceivers; an FPGA or high-performance MCU (such as STM32H7 or Cortex-M7) hardware timestamp module (based on a high-precision timer with a resolution of 100ns); and a CRC check hardware accelerator.

[0208] (3) Topology:

[0209] A bus topology is adopted, with the master node located at one end of the bus, eight slave nodes distributed along the bus, and two RS-485 links wired in parallel.

[0210] Frame format definition. As shown in Tables 4 and 5.

[0211] Table 4: Data Frame Definitions for Example 1

[0212] ;

[0213] Table 5: Data frame definition for Example 1:

[0214] ;

[0215] (4) Communication timing:

[0216] (a) Single-cycle communication sequence (250 μs):

[0217] Time T0:

[0218] Link A1 / B1: Master node → Slave node 1 (Data[n], 10.4μs);

[0219] Link A2 / B2: From node 1 to master node (Ack[n-1], 8.8μs);

[0220] Time T0+25μs:

[0221] Link A1 / B1: Master node → Slave node 2 (Data[n], 10.4μs);

[0222] Link A2 / B2: From node 2 to master node (Ack[n-1], 8.8μs);

[0223] Time T0+50μs:

[0224] Link A1 / B1: Master node → Slave node 3 (Data[n], 10.4μs);

[0225] Link A2 / B2: From node 3 to master node (Ack[n-1], 8.8μs);

[0226] Time T0+175μs:

[0227] Link A1 / B1: Master node → Slave node 8 (Data[n], 10.4μs);

[0228] Link A2 / B2: Slave node 8 → Master node (Ack[n-1], 8.8μs); ...

[0230] Time interval T0+200μs-T0+250μs: Reserved time for clock synchronization and fault detection.

[0231] (b) Time budget analysis:

[0232] Total time for transmitting data frames from 8 nodes: 8 × 10.4μs = 83.2μs;

[0233] Total time for receiving feedback frames from 8 nodes: 8 × 8.8μs = 70.4μs;

[0234] Frame interval: 8 × (25μs - 10.4μs) = 116.8μs;

[0235] Reserved time: 250μs - 83.2μs - 70.4μs = 96.4μs;

[0236] Time margin: 96.4μs / 250μs = 38.6%.

[0237] (c) Assembly line effect:

[0238] Since data frames are transmitted on link A1 / B1 and feedback frames are transmitted on link A2 / B2, the two can be transmitted in parallel, which is equivalent to using two highways at the same time. The overall communication efficiency is close to twice the theoretical value.

[0239] (5) Time synchronization is achieved:

[0240] (a) Timestamp latching mechanism:

[0241] The master node FPGA latches a 64-bit hardware counter value as T on the rising edge of the SOF data frame. mastersend ;

[0242] When the FPGA at the slave node detects the rising edge of the data frame SOF, it latches the local counter value as T1.

[0243] On the rising edge of the SOF feedback frame sent by the slave node FPGA, the local counter value is latched as T2.

[0244] When the master node FPGA detects the rising edge of the feedback frame SOF, it latches the local counter value as T. masterrecv .

[0245] (b) Round-trip delay calculation:

[0246] Processing delay from node: Δt = T2 - T1 ≈ 5μs (fixed value);

[0247] Round-trip transmission delay: RTT = (T masterrecv - T mastersend ) – Δt;

[0248] One-way transmission delay: propagation_delay = RTT / 2 ≈ 2μs (50m bus);

[0249] (c) Clock skew estimation and correction:

[0250] In this example, if the RTT calculation is omitted and only broadcast frames are used, a fixed phase error of approximately 250 ns will be introduced on the 50m bus, which cannot be eliminated by software. The RTT measurement formula described in this invention, RTT = (T...), addresses this issue. masterrecv -T mastersend (T2 - T1) allows the master node to obtain the independent latency characteristics of each slave node. This data is used not only for time calibration but also for fine-tuning the "acknowledgment lead" in pipelined communication. This ensures that when multiple slave nodes transmit data back on the second link (A2 / B2), they can be closely arranged with a very high duty cycle without collisions or invalid gaps, thereby increasing bus utilization to over 85%.

[0251] Clock offset: offset = T1 - T mastersend - propagation delay ;

[0252] Clock correction from node: T slave = T local + offset;

[0253] Among them, propagation delay For clock delay correction, T local T represents the time value before the node is calibrated. slave This is the clock correction time for the slave node.

[0254] The master node calculates the clock skew once per communication cycle, and the slave node uses a low-pass filter to smooth the correction value to avoid clock jitter.

[0255] (d) Synchronization accuracy verification:

[0256] Hardware timestamp accuracy: ±100ns; Transmission delay symmetry error: ±50ns; Clock drift rate: <10ppm;

[0257] Synchronization accuracy: <500ns; this accuracy meets the position synchronization requirement of <1μs in multi-axis motion control.

[0258] (6) Redundancy and fault tolerance verification:

[0259] (a) Fault injection test:

[0260] Test 1: Disconnect link A1 / B1;

[0261] The system detected three consecutive frames of no response (75μs) on link A1 / B1; automatically switched to half-duplex mode on link A2 / B2; the communication period was extended to 350μs (increasing the direction switching time); communication was not interrupted during the switching process.

[0262] Test 2: Disconnect link A2 / B2;

[0263] The system detects no feedback frames on link A2 / B2; it automatically switches to half-duplex mode on link A1 / B1; the communication period is extended to 350μs; communication is uninterrupted during the switching process;

[0264] Test 3: Link Recovery;

[0265] After the faulty link was repaired, the system automatically detected signal recovery; smoothly transitioned back to dual-link parallel mode; and the communication cycle was restored to 250μs.

[0266] (b) Reliability statistics:

[0267] Normal mode MTBF (Mean Time Between Failures): >10,000 hours; Single-link failure mode MTBF: >5,000 hours; Failover time: <100μs; System availability: 99.95%.

[0268] The performance test results are shown in Table 6.

[0269] Table 6: Performance Test Results;

[0270] ;

[0271] Example 2: 1Mbps dual RS-485 long-distance monitoring system;

[0272] (1) Application scenarios:

[0273] This example is applied to a remote monitoring system for factory automation, which includes one master station and 32 distributed I / O nodes, with a bus length of up to 1200m.

[0274] (2) System configuration:

[0275] (a) Physical layer parameters: RS-485 communication rate: 1Mbps; bit time: 1μs; maximum bus length: 1200m; maximum distance between nodes: 40m.

[0276] (b) Frame format: Data frame length: 160 bits, transmission time 160 μs; Feedback frame length: 96 bits, transmission time 96 μs; Communication period: 10 ms (100 Hz);

[0277] (3) Features: The lower communication rate is suitable for long-distance transmission, reducing signal attenuation and reflection effects; the longer communication cycle is suitable for I / O monitoring applications, reducing real-time requirements; dual-link redundancy improves the reliability of long-distance communication.

[0278] (4) Performance verification: Bit error rate at a distance of 1200m: <10 9 Time synchronization accuracy: <10μs; The system continues to operate in the event of a single link failure, with the communication cycle extended to 15ms; Bus utilization: ~75%.

[0279] This example demonstrates the applicability of the present invention in low-speed, long-distance, multi-node scenarios.

[0280] Example 3: Dual RS-485 system supporting security authentication;

[0281] (1) Application scenarios:

[0282] This example is applied to critical control systems with high safety requirements, such as nuclear power plant auxiliary systems and aviation ground equipment.

[0283] (2) Security enhancement implementation:

[0284] (a) Message Authentication Code (MAC): Both data frames and feedback frames contain a 32-bit HMAC-SHA256 truncated code; calculated based on the pre-shared key (PSK); the receiver verifies the MAC, and discards the frame if it does not match.

[0285] (b) Challenge-Response: The master node includes a 32-bit random challenge code in the data frame; the slave node returns a response code calculated based on the challenge code and PSK in the feedback frame; the master node verifies the response code to prevent replay attacks.

[0286] (c) Timestamp protection: Hardware timestamps are used to detect abnormal delays; frames that exceed the normal transmission delay by ±20% are rejected.

[0287] (d) Physical link isolation: Control commands are transmitted on link A1 / B1, and authentication information is transmitted on link A2 / B2; an attacker needs to eavesdrop on both links simultaneously to obtain complete information.

[0288] (3) Safety assessment:

[0289] Anti-eavesdropping capability: It requires eavesdropping on two physical links simultaneously, which increases the difficulty;

[0290] Anti-tampering capability: MAC verification failure rate >99.99%;

[0291] Anti-replay attack: timestamp window ±100μs, replay detection rate >99.9%;

[0292] Anti-injection attack: Injection frames without a valid MAC address are 100% rejected.

[0293] This embodiment verifies the effectiveness of the present invention in safety-critical applications.

[0294] Example 4: Supports hot-plugging and dynamic discovery;

[0295] This example demonstrates the system's hot-plugging and auto-discovery capabilities.

[0296] Unique Node Identifier: Each slave node is programmed with a unique identifier (UID), including the chip serial number, product type, and manufacturer ID. The master node collects the UIDs of all online nodes via broadcast scan commands and automatically assigns communication addresses.

[0297] Hot-plugging: The master node monitors the slave node's response status every communication cycle. If three consecutive cycles of no response are detected, the node is marked offline and a new communication time slot is allocated. When a new node joins, the master node receives the node's join request in an idle time slot, allocates an address, and then notifies the node to enter normal communication mode. The entire process is completed within 200ms and is transparent to upper-layer applications.

[0298] Application Value: In the application of quick-change tools for collaborative robots, no manual configuration is required after changing the end effector. The system automatically identifies the tool type and loads the corresponding parameters, significantly improving ease of use.

[0299] Example 5: Enhanced Encrypted Communication;

[0300] This example demonstrates the system's security encryption capabilities.

[0301] Encryption scheme: The data payload is encrypted using AES-128-CTR mode, and message authentication is provided using HMAC-SHA256. The initialization vector is generated by XORing the frame sequence number and timestamp to prevent replay attacks.

[0302] Performance optimization: By utilizing the hardware AES accelerator of MCUs such as STM32H7, the encryption overhead is <1μs, accounting for <1% of the communication cycle, and has minimal impact on real-time performance.

[0303] Dual-link security isolation: Utilizing the physical isolation of dual RS-485 links, a dual-channel independent encryption strategy is implemented. Control commands and authentication information are transmitted on two separate links and encrypted with different keys. Attackers need to simultaneously eavesdrop on and crack both links to obtain complete information, improving security by more than 100 times compared to single-link security.

[0304] Key Management: Supports both Pre-Shared Key (PSK) and Dynamic Key Negotiation (ECDH) modes. In security-critical applications, nodes negotiate session keys via ECDH upon joining and support periodic updates, providing forward security protection.

[0305] Application scenarios: Suitable for safety-critical fields such as nuclear power plant auxiliary systems, medical robots, and aviation ground equipment, meeting the requirements of industrial network security standards such as IEC 62443.

[0306] This embodiment represents a significant breakthrough in several technical aspects.

[0307] Performance advantages:

[0308] In terms of communication efficiency, this embodiment achieves a fundamental breakthrough over the bottleneck of traditional RS-485 half-duplex communication through a dual-link parallel transmission mechanism. Traditional RS-485 half-duplex communication systems introduce a delay of 5-50 microseconds with each direction switch. This seemingly small delay accumulates into a significant performance bottleneck in high-frequency communication scenarios. This embodiment completely eliminates the direction switch waiting time by transmitting data frames and feedback frames in parallel on two independent links, resulting in a 50%-100% improvement in communication efficiency compared to traditional solutions. This performance improvement is not only reflected in the increased data throughput but, more importantly, in achieving true full-duplex communication, providing more ample communication bandwidth for real-time control systems.

[0309] In terms of real-time performance, the system employs a fixed communication cycle and strictly controlled frame length design to ensure complete predictability of communication latency. All timing parameters within each communication cycle are predetermined constants, eliminating any randomness or uncertainty. The system's smallest time granularity can be accurate to the physical layer bit time level, for example, reaching 100 nanoseconds at a 10Mbps communication rate. This ultra-high time resolution, combined with deterministic latency characteristics, allows the system's latency jitter to be reduced to the sub-microsecond level, fully meeting the requirements of applications with extremely stringent hard real-time performance demands, such as motion control and robot control.

[0310] Time synchronization capability is another significant performance breakthrough in this embodiment. Unlike the "open-loop synchronization" in existing technologies that rely solely on unidirectional broadcast frames, this embodiment constructs a "closed-loop synchronization" mechanism by transmitting feedback frames back via a second link and calculating the RTT. This mechanism not only compensates for static physical cable delays but also monitors and mitigates clock drift caused by changes in ambient temperature. This RTT-based dynamic closed-loop correction is the technical guarantee for the system to achieve sub-microsecond synchronization accuracy without relying on a dedicated PTP chip. Through a bidirectional time measurement mechanism based on hardware timestamps, the system can achieve sub-microsecond time synchronization accuracy without implementing a complex IEEE 1588 PTP protocol stack. Compared to the millisecond-level synchronization accuracy that traditional RS-485 systems can generally only achieve, this embodiment achieves an order-of-magnitude improvement in accuracy. This level of synchronization accuracy is comparable to or even surpasses some real-time Ethernet systems, providing an ideal communication infrastructure for applications requiring high-precision time coordination, such as distributed motion control and multi-axis linkage.

[0311] In terms of bandwidth utilization, the parallel transmission mode with two physical links operating simultaneously doubles the total system bandwidth compared to a single link. For example, at a physical rate of 10 Mbps, the effective throughput of the system can reach nearly 20 Mbps. This bandwidth doubling effect not only improves data transmission capability but, more importantly, provides sufficient channel resources for the system to simultaneously process control command issuance and status feedback uploads under normal operating conditions, avoiding the problem in traditional half-duplex systems where data transmission and feedback confirmation need to compete for the same physical channel.

[0312] Reliability advantages:

[0313] The system's redundancy and fault tolerance stem from its meticulously designed dual-link architecture and intelligent fault handling mechanism. Two electrically isolated physical links operate collaboratively under normal conditions. If either link fails, the system can detect the fault within milliseconds and automatically switch to a single-link half-duplex mode, maintaining communication continuity throughout the switchover process, completely transparent to the application layer. This rapid response to fault detection and switching minimizes the impact of short-term failures, while long-term failures are effectively handled by the backup link. Compared to traditional passive primary / backup solutions, this proactive redundancy strategy not only improves resource utilization but also significantly shortens fault recovery time, enabling the system to maintain a stable availability of over 99.9%, meeting the stringent reliability requirements of critical control applications.

[0314] Real-time status confirmation and closed-loop control capabilities are another crucial guarantee of system reliability. Feedback frames are not merely simple confirmations of reception; they carry rich, multi-dimensional status information, including command execution status, error flags, real-time sensor readings, and equipment operating parameters. By continuously receiving and analyzing this feedback information, the master node can monitor the working status and execution of each slave node in real time, and take immediate action upon detecting any anomalies. This closed-loop control mechanism based on real-time feedback not only improves the system's control accuracy but, more importantly, enables rapid fault location and diagnosis, allowing maintenance personnel to quickly identify problematic nodes and their causes, significantly reducing the system's mean time to repair (MTBL).

[0315] The system employs a multi-layered verification mechanism to provide layered protection for data integrity and communication reliability. The frame sequence number mechanism ensures the integrity of the communication sequence and can accurately detect anomalies such as frame loss, duplication, or out-of-order delivery. CRC check provides robust error detection capabilities for each data frame and feedback frame, capable of identifying the vast majority of bit errors occurring during transmission. Timestamp check provides an additional verification dimension from a timing perspective, capable of identifying issues such as abnormal delays and timing discrepancies. These three protection mechanisms work together to form a complete error detection system, enabling the system to achieve an error detection rate of over 99.99%. Simultaneously, the system also supports frame loss detection and automatic retransmission mechanisms based on frame sequence numbers, further improving communication reliability and robustness.

[0316] Security advantages:

[0317] Physical layer security isolation:

[0318] Critical information is transmitted across two physical links, reducing the risk of eavesdropping.

[0319] Supports security mechanisms such as message authentication codes and challenge-response mechanisms;

[0320] The timestamp mechanism can detect replay attacks and man-in-the-middle attacks.

[0321] Cost and implementation advantages:

[0322] The simplicity of the system architecture is its greatest cost advantage. This embodiment is entirely based on mature RS-485 physical layer technology, eliminating the need for dedicated real-time Ethernet controller chips or complex FPGA solutions. It can be implemented using standard RS-485 transceiver chips in conjunction with ordinary microcontrollers or processors. Hardware costs can be reduced by 50%-80% compared to real-time Ethernet solutions. This significant cost advantage makes the system particularly suitable for large-scale deployments and cost-sensitive applications. Furthermore, due to the use of standardized hardware components, the system boasts strong supply chain stability, eliminating the procurement risks and long-term supply issues associated with dedicated chips. This is a crucial advantage for industrial systems requiring long-term operation and maintenance. In addition, the simple hardware architecture reduces maintenance and spare parts management costs, allowing ordinary maintenance personnel to perform routine maintenance without requiring highly specialized technical support.

[0323] In terms of ease of implementation, the system's protocol design prioritizes simplicity and practicality, avoiding the multi-layered protocol stacks and complex configuration management common in real-time Ethernet. The software implementation complexity is relatively low, allowing developers to quickly grasp the system principles and implementation methods, significantly shortening the product development cycle. The system maintains good compatibility with existing RS-485 hardware platforms. For applications already deploying RS-485 communication systems, a relatively simple upgrade process allows for a smooth migration to the new system, fully protecting existing user investments. The system also supports multiple topologies, including traditional bus topologies and flexible star topologies, and can even be combined to form hybrid topologies based on site conditions. This topological flexibility enables the system to adapt to various complex field cabling environments. The number of nodes can be easily expanded to dozens according to actual needs, meeting the requirements of small and medium-sized distributed control systems.

[0324] In terms of application scope, the system demonstrates broad applicability and excellent scalability potential. In industrial automation, it can be applied to various scenarios such as production line control, process control, and building automation. In robot control, its high real-time performance and precise time synchronization capabilities make it particularly suitable for applications with stringent timing requirements, such as multi-joint robots and collaborative robots. In motion control, it supports complex motion control functions such as multi-axis synchronous control, electronic cams, and flying shears. In CNC systems, it can function as a servo bus to enable high-speed real-time communication between the controller and the driver. For embedded systems with limited computing resources and power consumption, this embodiment offers significant advantages over real-time Ethernet solutions, reducing system cost and power consumption while maintaining performance. In certain application scenarios, this embodiment can even serve as a low-cost alternative to real-time Ethernet, providing users with a more cost-effective option.

[0325] In terms of communication architecture, this embodiment completely eliminates the direction switching delay in traditional RS-485 half-duplex mode through a dual-link parallel working mechanism, achieving true parallelism between data transmission and feedback reception, and fundamentally breaking through the performance bottleneck of half-duplex communication. Regarding time synchronization, without relying on complex real-time Ethernet protocols, the system achieves deterministic time synchronization at the microsecond or even sub-microsecond level through an innovative hardware-level timestamp mechanism, significantly improving the timing coordination capability between distributed nodes.

[0326] In terms of system resource utilization, the simultaneous operation of two physical links forms a pipelined communication mode, enabling bandwidth utilization to reach twice the theoretical value and significantly improving communication efficiency. Simultaneously, the dual-link redundancy design ensures that the system can automatically reconstruct the communication path in the event of a link failure, guaranteeing uninterrupted communication and significantly enhancing the system's fault tolerance and reliability. Compared to the fixed-direction full-duplex of RS-422, this embodiment adopts a "dual-half-duplex" physical architecture. Under normal conditions, it simulates full-duplex; in the event of a fault, either link can independently handle transmission and reception tasks, resulting in significantly higher reliability than RS-422.

[0327] In terms of real-time control, this embodiment integrates multi-dimensional information such as timestamps, execution status, and verification results into the feedback frame, achieving true real-time status confirmation and closed-loop control capabilities, providing a complete control feedback mechanism for upper-layer applications. Because it eliminates the need for a dedicated PTP (Precision Time Protocol) chip, microsecond-level synchronization can be achieved using frame interrupts from an RS-485 transceiver, resulting in lower costs compared to real-time Ethernet. Regarding security, the system supports a security enhancement mechanism based on physical link isolation. By distributing critical information across two independent links, it significantly reduces the risk of communication being eavesdropped on, tampered with, or subjected to injection attacks.

[0328] More importantly, this embodiment maintains its low-cost advantage, being entirely based on mature RS-485 technology. It requires no dedicated controller chip and its implementation cost is far lower than that of real-time Ethernet solutions, making it an ideal choice for resource-constrained systems and small to medium-sized application scenarios.

[0329] The various embodiments in this application are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0330] The scope of protection of this application is not limited to the embodiments described above. Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from the scope and spirit of this disclosure. If such modifications and variations fall within the scope of equivalent technology of this disclosure, then the intent of this disclosure also includes such modifications and variations.

Claims

1. A real-time redundant fault-tolerant communication system based on dual RS-485 links, characterized in that, include: The first RS-485 physical link includes: differential signal line A1, differential signal line B1, a first terminating resistor and a first transceiver chip, wherein the differential signal line A1 and differential signal line B1 form a first differential signal pair; The second RS-485 physical link includes: differential signal line A2, differential signal line B2, a second terminating resistor and a second transceiver chip, wherein the differential signal line A2 and differential signal line B2 form a second differential signal pair; At least one master node is connected to a first RS-485 physical link and a second RS-485 physical link respectively, and is used to schedule the first RS-485 physical link and the second RS-485 physical link, publish time base, send data frames and master node commands to slave nodes, and process the feedback frames of slave nodes. Multiple slave nodes are connected to a first RS-485 physical link and a second RS-485 physical link, respectively, and are used to respond to master node commands, execute control instructions, and send feedback frames. The feedback frame includes two timestamps: the first timestamp records the time when the slave node receives the data frame, and the second timestamp records the time when the slave node sends the feedback frame. It also includes: the first RS-485 physical link and the second RS-485 physical link are in dual-link parallel operation mode, including: The first RS-485 physical link and the second RS-485 physical link work in parallel. One RS-485 physical link is used to transmit data frames, and the other RS-485 physical link is used to transmit feedback frames. Each slave node simultaneously monitors the communication quality of the first RS-485 physical link and the second RS-485 physical link; If the communication quality does not meet the preset value, the first RS-485 physical link or the second RS-485 physical link will be reconstructed.

2. The real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, The feedback frame includes: a frame start identifier, an associated frame sequence number, a source address, a first timestamp, a second timestamp, an execution status code, an error flag, status data, security authentication information, and a cyclic redundancy check code for the feedback frame. The data frame includes: a frame start identifier, frame type, frame sequence number, target address, data payload length, time reference information, data payload, and cyclic redundancy check code of the data frame.

3. The real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, Both timestamps are automatically latched by the hardware circuit when the start-of-frame identifier is detected.

4. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, Also includes: The master node is also used to automatically latch data frames in hardware when transmitting them on the first RS-485 physical link, and to receive the transmission time T transmitted by the hardware. mastersend ; The slave node is also configured to automatically latch the data upon receiving the start-of-frame identifier of a data frame, and to receive the reception time T transmitted by the hardware. slaverecv Receive time T slaverecv Stored within the first timestamp; The slave node is also used to automatically latch the data while sending a feedback frame on the second RS-485 physical link, and to receive the transmission time T transmitted by the hardware. slavesend Sending time T slavesend Stored in the second timestamp, the feedback frame is sent to the master node; The master node is also used to automatically latch the received feedback frame in hardware, and the master node receives the reception time T transmitted by the hardware. masterrecv .

5. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, Also includes: The master node is also used to determine the transmission time T. mastersend Reception time T slaverecv Sending time T slavesend and the receiving time T masterrecv Calculate round-trip time and clock skew; The slave node is further configured to adjust its local clock based on the time reference information and clock offset sent by the master node in the data frame, so as to achieve time synchronization between the slave node and the master node. The time reference information is the transmission time T. mastersend .

6. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 5, characterized in that, The round-trip time is calculated as follows: RTT = (T masterrecv - T mastersend ) - (T2 - T1); Where RTT is the round-trip time, T masterrecv The receiving time of the master node, T mastersend T1 is the time when the master node sends the data, T2 is the time saved in the second timestamp, and T1 is the time saved in the second timestamp.

7. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 5, characterized in that, The clock offset is calculated as follows: Clock offset = [(T1 - T mastersend ) - (T masterrecv - T2)] / 2; Among them, Clock offset For clock skew, T masterrecv The receiving time of the master node, T mastersend T1 is the time when the master node sends the data, T2 is the time saved in the second timestamp, and T1 is the time saved in the second timestamp.

8. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, Also includes: When the first RS-485 physical link is faulty, the second RS-485 physical link is reconfigured into a half-duplex working mode. The master node sends data frames through the second RS-485 physical link, and the slave node returns a feedback frame on the second RS-485 physical link after receiving the data frame. The communication cycle of the second RS-485 physical link is adjusted, increasing the direction switching time. When the second RS-485 physical link is faulty, the first RS-485 physical link is reconfigured into a half-duplex working mode. The master node sends data frames through the first RS-485 physical link, and the slave node returns a feedback frame on the first RS-485 physical link after receiving the data frame. The communication cycle of the first RS-485 physical link is adjusted, increasing the direction switching time.

9. A real-time redundant fault-tolerant communication system based on dual RS-485 links according to claim 1, characterized in that, Also includes: In the first RS-485 physical link and the second RS-485 physical link, one RS-485 physical link is randomly selected for transmitting command information, and the other RS-485 physical link is selected for transmitting authentication information. The master node includes a random challenge code in the data frame; the slave node returns a response code calculated based on the challenge code and the shared key in the feedback frame.

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