A trench gate electrode self-alignment forming method
By employing the growth and etching of first and second mask sidewalls in the trench gate MOSFET, the problems of over-etching or under-etching in the etching process are solved, achieving effective protection of the gate electrode and improving device reliability, making it suitable for mass production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING THIRD GENERATION SEMICON TECH INNOVATION CENT CO LTD
- Filing Date
- 2026-03-03
- Publication Date
- 2026-06-05
AI Technical Summary
In the traditional trench gate MOSFET manufacturing process, the etching process is prone to over-etching or under-etching, which affects the uniformity and reliability of the device threshold voltage, and the photolithography overlay precision limits the reduction of the device cell size.
By using the growth and etching of the first and second mask sidewalls, and taking advantage of the self-alignment of the sidewall process, the gate electrode in the trench is effectively protected and the gate electrode at the mesa is fully etched, thus avoiding the impact on photolithography accuracy.
It achieves effective protection of the gate electrode in the trench and sufficient etching of the gate electrode at the mesa, improving the reliability of the device and allowing for reduction in unit cell size, making it suitable for mass production line applications.
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Figure CN121772309B_ABST