Flip-chip LED chip and method for manufacturing the same
By employing wet etching technology and anti-etching layer materials in flip-chip LEDs, combined with a specific sidewall design, the problem of etching damage was solved, luminous efficiency and reliability were improved, operating voltage was reduced, and efficient ohmic contact and stability were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-06-05
AI Technical Summary
Traditional etching processes for flip-chip LEDs can damage the metal electrodes and gallium nitride-based semiconductors, leading to decreased luminous efficiency and reliability. Furthermore, dry etching technology lacks selectivity in etching the dielectric layer and metal electrodes, affecting device performance.
Contact holes are formed using a wet etching process, with Cr, Ni, Pt, Au, Ti and other materials used as anti-etching layers. Combined with a specific sidewall tilt angle and spacing design, the etching process is designed to ensure that the underlying structure is not damaged. The etching ratio is controlled by BOE etching solution to achieve complete removal of the dielectric layer.
It improves luminous efficiency, reduces operating voltage, enhances device reliability and yield, and ensures the stability of contact resistance and the integrity of ohmic contacts.
Smart Images
Figure CN122161237A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a flip-chip LED and its fabrication method. Background Technology
[0002] In traditional flip-chip LED manufacturing processes, after depositing a dielectric layer such as silicon dioxide as a passivation protective layer above the metal electrodes, contact holes must be formed through etching to achieve external electrical connections. The quality of these contact holes is crucial to device performance. Insufficient etching will result in residual dielectric material inside the holes, causing increased contact resistance and deterioration of operating voltage; while excessive etching may damage the underlying metal electrodes and even the gallium nitride-based semiconductor material, directly reducing the device's luminous efficiency and reliability. Currently, mainstream dry etching techniques, such as reactive ion etching, have significant limitations when applied to plasma-sensitive gallium nitride devices: First, high-energy plasma can damage the crystal structure of the active region, forming non-radiative recombination centers, leading to a decrease in internal quantum efficiency; second, this method lacks sufficient selectivity in etching the dielectric layer and metal electrodes, easily causing electrode surface damage and deterioration of ohmic contact characteristics. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a flip-chip LED with high luminous efficiency, low operating voltage and high reliability.
[0004] Accordingly, the present invention also provides a method for preparing the above-mentioned flip-chip LED.
[0005] To solve the above-mentioned technical problems, the present invention provides a flip-chip LED, comprising: a substrate, an epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer and an N-type pad layer stacked on the substrate; The third insulating layer covers the P-type metal interconnect layer and the N-type metal interconnect layer, and forms a first contact hole exposing the P-type metal interconnect layer and a second contact hole exposing the N-type metal interconnect layer. The P-type pad layer is connected to the P-type metal interconnect layer through the first contact hole, and the N-type pad layer is connected to the N-type metal interconnect layer through the second contact hole. Both the first contact hole and the second contact hole are formed by a wet etching process. The P-type metal interconnect layer includes a first bottom layer and a first etch-resistant layer sequentially stacked on the second insulating layer; the N-type metal interconnect layer includes a second bottom layer and a second etch-resistant layer sequentially stacked on the second insulating layer. Both the first anti-etching layer and the second anti-etching layer are made of one or more of Cr, Ni, Pt, Au, and Ti.
[0006] As an improvement to the above technical solution, both the first anti-etching layer and the second anti-etching layer include a first Cr layer, a first Pt layer and a first Ti layer stacked sequentially. The thickness of the first Cr layer is 20nm~100nm, the thickness of the first Pt layer is 100nm~200nm, and the thickness of the first Ti layer is 4nm~15nm.
[0007] As an improvement to the above technical solution, both the first anti-etching layer and the second anti-etching layer include a first Ni layer, a second Cr layer and a second Ti layer stacked sequentially. The thickness of the first Ni layer is 10nm~50nm, the thickness of the second Cr layer is 100nm~200nm, and the thickness of the second Ti layer is 4nm~15nm.
[0008] As an improvement to the above technical solution, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer is ≥10°. The inclination angle of the sidewall of the third insulating layer near the N-type pad layer is ≥10°; The minimum distance between the sidewall of the third insulating layer near the P-type pad layer and the sidewall of the P-type pad layer is ≥500nm. The minimum spacing between the sidewall of the third insulating layer near the N-type pad layer and the sidewall of the N-type pad layer is ≥500nm.
[0009] As an improvement to the above technical solution, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer is 10°~20°. The inclination angle of the sidewall of the third insulating layer near the N-type pad layer is 10°~20°; The minimum distance between the sidewall of the third insulating layer near the P-type pad layer and the sidewall of the P-type pad layer is 500nm~2000nm. The minimum spacing between the sidewall of the third insulating layer near the N-type pad layer and the sidewall of the N-type pad layer is 500nm~2000nm.
[0010] As an improvement to the above technical solution, both the first bottom layer and the second bottom layer are made of one or more of Cr, Al, Cu, Ti, Ni, Pt, Au, and Ag; and / or The first insulating layer is a SiO2 layer and / or SiN. x Layers with a thickness of 400nm~600nm; and / or The second insulating layer is a SiO2 layer and / or SiN. x Layers with a thickness of 600nm~1000nm; and / or The third insulating layer is a SiO2 layer and / or SiN. x The layer has a thickness of 600nm~1000nm.
[0011] As an improvement to the above technical solution, both the first bottom layer and the second bottom layer include a third Cr layer, a first AlCu layer, a third Ti layer, a second AlCu layer, a fourth Ti layer, and a third AlCu layer stacked sequentially; the thickness of the third Cr layer is 2nm~8nm, the thickness of the first AlCu layer is 300nm~800nm, and its Cu content is 5wt%~20wt%; the thickness of the third Ti layer is 50nm~200nm; the thickness of the second AlCu layer is 300nm~800nm, and its Cu content is 5wt%~20wt%; the thickness of the fourth Ti layer is 50nm~200nm; and the thickness of the third AlCu layer is 300nm~800nm, and its Cu content is 5wt%~20wt%.
[0012] As an improvement to the above technical solution, the flip-chip LED further includes a current diffusion layer disposed between the epitaxial layer and the first insulating layer; the current diffusion layer is an ITO layer, an IZO layer, an IGO layer, or an IGZO layer, with a thickness of 100nm~300nm; and / or The flip-chip LED further includes a passivation layer disposed below the second insulating layer. The passivation layer is an Al2O3 layer with a thickness of 100nm~150nm; and / or The reflective layer comprises a DBR reflective layer, a metal reflective layer, and a conductive anti-diffusion layer sequentially stacked on the first insulating layer; the DBR reflective layer is a SiO2 / TiO2 type DBR layer, a MgF2 / TiO2 type DBR layer, or a SiO2 / Ti2O5 type DBR layer; the thickness of the DBR reflective layer is 0.5μm~5μm; The metal reflective layer is made of one or more of Ag, Al or Au, and its thickness is 100nm~300nm; the conductive anti-diffusion layer is made of one or more of Ti, Ni, Cr, Au, TiW, PtPd, and its thickness is 200nm~500nm.
[0013] Accordingly, the present invention also discloses a method for preparing a flip-chip LED, which includes: An epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, and a third insulating layer are formed on a substrate. The first and second contact holes are formed on the third insulating layer using a wet etching process. A P-type pad layer is formed in the first contact hole; an N-type pad layer is formed in the second contact hole.
[0014] As an improvement to the above technical solution, BOE etching solution is used to perform wet etching on the third insulating layer to form the first contact hole and the second contact hole. The volume ratio of NH4F aqueous solution to HF aqueous solution in the BOE etching solution is 6:1 to 10:1, the etching temperature is 20℃ to 30℃, and the etching time is 800s to 1000s. The etching ratio of the BOE etching solution to the third insulating layer and the P-type or N-type metal interconnect layer is ≥100:1.
[0015] Implementing this invention has the following beneficial effects: A flip-chip LED in one embodiment of the present invention includes: a substrate, an epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer, and an N-type pad layer stacked on the substrate; the third insulating layer has a first contact hole exposing the P-type metal interconnect layer and a second contact hole exposing the N-type metal interconnect layer, both the first and second contact holes being formed by a wet etching process; the P-type metal interconnect layer includes a first bottom layer and a first anti-etching layer stacked sequentially; the N-type metal interconnect layer includes a second bottom layer and a second anti-etching layer stacked sequentially; the first and second anti-etching layers are both made of one or more of Cr, Ni, Pt, Au, and Ti. In this application, both the first and second contact holes are formed by a wet etching process, which effectively avoids damage to the underlying metal structure and the epitaxial layer, ensuring that the etching process does not damage the light-emitting layer and improving luminous efficiency. Furthermore, the wet etching process can completely remove the third insulating layer in the first and second contact holes, preventing residues from increasing contact resistance. Furthermore, the first and second anti-etching layers of this application can effectively resist the erosion of the P-type and N-type metal interconnect layers during wet etching to form the first and second contact holes. This not only ensures the complete removal of the third insulating layer, but also protects the structural integrity of the P-type and N-type metal interconnect layers, ensuring low-resistance and stable ohmic contact, reducing the operating voltage, and improving reliability and yield. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of a flip-chip LED in one embodiment of the present invention; Figure 2 yes Figure 1 A magnified view of a section at point A in the middle; Figure 3 This is a schematic diagram of the structure of a P-type metal interconnect layer in one embodiment of the present invention; Figure 4This is a schematic diagram of the structure of an N-type metal interconnect layer in one embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the P-type metal interconnect layer in another embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an N-type metal interconnect layer in another embodiment of the present invention; Figure 7 These are partial SEM images of the flip-chip LEDs obtained in Embodiments 1 and 2 of this invention; Figure 8 These are partial SEM images of the flip-chip LEDs obtained in Embodiments 3 to 5 of this invention; In the diagram, 100 is the substrate, 210 is the N-type semiconductor layer, 220 is the light-emitting layer, 230 is the P-type semiconductor layer, 240 is the N-type conductive step, 250 is the isolation trench, 260 is the light-emitting structure, 270 is the current diffusion layer, 300 is the first insulating layer, 310 is the first via, 320 is the second via, 400 is the reflective layer, 410 is the DBR reflective layer, 411 is the third via, 412 is the fourth via, 420 is the metal reflective layer, 430 is the conductive anti-diffusion layer, 510 is the passivation layer, 520 is the second insulating layer, 530 is the fifth via, 540 is the sixth via, 600 is the P-type metal interconnect layer, and 610 is the first bottom layer. 611 is the third Cr layer, 612 is the first AlCu layer, 613 is the third Ti layer, 614 is the second AlCu layer, 615 is the fourth Ti layer, 616 is the third AlCu layer, 620 is the first etch resist layer, 621 is the first Cr layer, 622 is the first Pt layer, 623 is the first Ti layer, 624 is the first Ni layer, 625 is the second Cr layer, 626 is the second Ti layer, 700 is the N-type metal interconnect layer, 710 is the second bottom layer, 720 is the second etch resist layer, 800 is the third insulating layer, 810 is the first contact hole, 820 is the second contact hole, 910 is the P-type pad layer, and 920 is the N-type pad layer. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.
[0018] Please see Figure 1 , Figure 2An embodiment of the present invention provides a flip-chip LED, which includes a substrate 100, an epitaxial layer, a first insulating layer 300, a reflective layer 400, a second insulating layer 520, a P-type metal interconnect layer 600, an N-type metal interconnect layer 700, a third insulating layer 800, a P-type pad layer 910, and an N-type pad layer 920.
[0019] In the vertical direction (i.e., the thickness direction of the substrate 100), the epitaxial layer includes an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 sequentially stacked on the substrate 100. A light-emitting structure 260, an isolation trench 250, and an N-type conductive step 240 are formed on the epitaxial layer. The isolation trench 250 is used to separate the substrate 100 and the epitaxial layer to form multiple flip-chip LEDs. Specifically, the inclination angle of the sidewall of the isolation trench 250 is 45°~55°. The N-type conductive step 240 is located on one side of the light-emitting structure 260, exposing the N-type semiconductor layer 210, and is used to form an electrical connection with the N-type metal interconnect layer 700 and the N-type pad layer 920. The light-emitting structure 260 emits light, and its top is a P-type semiconductor layer 230, which is used to form an electrical connection with the P-type metal interconnect layer 600 and the P-type pad layer 910. Specifically, the tilt angle of the sidewall of the light-emitting structure 260 is 30°~50°.
[0020] Specifically, the substrate 100 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. The N-type semiconductor layer 210 can be an N-type GaAs layer, an N-type GaN layer, or an N-type AlGaN layer, but is not limited to these. The light-emitting layer 220 can be an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, an AlGaN-AlGaN type multiple quantum well layer, or an AlGaInP-AlGaInP type multiple quantum well layer, but is not limited to these. The P-type semiconductor layer 230 can be a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited to these. Preferably, in some embodiments, the substrate 100 is a patterned sapphire substrate, the N-type semiconductor layer 210 is an N-type GaN layer, the light-emitting layer 220 is an InGaN-GaN type multiple quantum well layer, and the P-type semiconductor layer 230 is a P-type GaN layer.
[0021] The first insulating layer 300 covers the sidewalls and bottom wall of the N-type conductive step 240, the isolation trench 250, and the light-emitting structure 260. A first through-hole 310 is provided at the N-type conductive step 240 to expose it, and a second through-hole 320 is provided above the P-type semiconductor layer 230 to expose it. For a single flip-chip LED, the number of first through-holes 310 and second through-holes 320 can be one or more. The inclination angle between the sidewalls of the first through-hole 310 and the second through-hole 320 is 20° to 40°. The first insulating layer 300 covers the surfaces exposed during the etching process to form the light-emitting structure 260, the isolation trench 250, and the N-type conductive step 240, effectively passivating the dangling bonds formed during etching and improving the reliability of the flip-chip LED.
[0022] Specifically, the first insulating layer 300 is composed of SiO2 and SiN. x It may be made of one or more of Al2O3, but is not limited thereto. The thickness of the first insulating layer 300 is 300 nm to 800 nm. Preferably, in some embodiments, the first insulating layer 300 is a SiO2 layer and / or SiN. x The first insulating layer 300 has a thickness of 400 nm to 600 nm. More preferably, the first insulating layer 300 is a SiO2 layer.
[0023] The reflective layer 400 is used to reflect the light emitted by the light-emitting layer 220 so that the light is emitted from one side of the substrate 100. In order to achieve effective light reflection, the reflective layer 400 should at least cover the light-emitting structure 260, that is, the outer edge of the orthogonal projection of the reflective layer 400 on the substrate 100 should be outside the outer edge of the orthogonal projection of the light-emitting layer 220 on the substrate 100, or at least the two should coincide.
[0024] Specifically, the reflective layer 400 can be a metal reflective layer or a DBR-type reflective layer. Preferably, in some embodiments, the reflective layer 400 includes a DBR reflective layer 410, a metal reflective layer 420, and a conductive anti-diffusion layer 430 sequentially stacked on the first insulating layer 300. This composite structure of the DBR reflective layer 410 and the metal reflective layer 420 significantly improves reflectivity and suppresses the diffusion of metal ions into the semiconductor layer, thereby improving light extraction efficiency and reliability.
[0025] Specifically, the DBR reflective layer 410 covers the first insulating layer 300. That is, the DBR reflective layer 410 is disposed on the sidewalls of the N-type conductive step 240, the isolation groove 250, and the light-emitting structure 260. This not only reflects light but also enhances the passivation effect, further reduces the surface state density, and improves the luminous efficiency of the flip-chip LED. Specifically, the DBR reflective layer 410 can be a SiO2 / TiO2 type DBR layer, a MgF2 / TiO2 type DBR layer, or a SiO2 / Ti2O5 type DBR layer, but is not limited to these. The thickness of the DBR reflective layer 410 is 0.5μm to 5μm, preferably 1.5μm to 4.5μm.
[0026] Specifically, a third via 411 exposing an N-type conductive step 240 and a fourth via 412 exposing a P-type semiconductor layer 230 are provided on the DBR reflective layer 410. The two vias correspond to the first via 310 and the second via 320 respectively, ensuring that the electrode lead-out path is continuous and reliable. The tilt angle of the sidewalls of the third via 411 and the fourth via 412 is controlled between 10° and 30° to balance photolithography accuracy and metal filling uniformity.
[0027] Specifically, the metal reflective layer 420 and the conductive anti-diffusion layer 430 are located above the light-emitting structure 260, meaning they only cover the area corresponding to the light-emitting structure 260 and do not cover the N-type conductive step 240 and the isolation trench 250, thereby avoiding the risk of short circuits. More preferably, the metal reflective layer 420 only partially covers the top of the light-emitting structure 260, meaning that the outer edge of its orthogonal projection on the substrate 100 is located inside the outer edge of the orthogonal projection of the P-type semiconductor layer 230 on the substrate 100. Based on this control, leakage caused by metal propagation in the metal reflective layer 420 can be avoided.
[0028] Specifically, the metal reflective layer 420 is made of one or more of Ag, Al, or Au, with a thickness of 100 nm to 300 nm and a sidewall angle of 25° to 35° to ensure the stepped coverage capability of the metal layer within the via. Preferably, the metal reflective layer 420 is an Ag layer with a thickness of 200 nm to 300 nm.
[0029] Specifically, the conductive anti-diffusion layer 430 is made of one or more of Ti, Ni, Cr, Au, TiW alloy, and PtPd alloy, and its thickness is 200 nm to 500 nm. Preferably, in some embodiments, the conductive anti-diffusion layer 430 is a TiW layer with a thickness of 200 nm to 400 nm.
[0030] The second insulating layer 520 covers the first insulating layer 300 and the reflective layer 400. A fifth via 530 exposing the N-type conductive step 240 and a sixth via 540 exposing the conductive anti-diffusion layer 430 (or the P-type semiconductor layer 230) are formed on the second insulating layer 520. Specifically, the fifth via 530 can correspond to the first via 310 and the third via 411 to ensure current conduction from the N-type metal interconnect layer 700. The sixth via 540 can correspond to the second via 320 and the fourth via 412, or it can be partially offset from the second via 320 and the fourth via 412. Especially when the reflective layer 400 includes a stacked structure of a metal reflective layer 420 and a conductive anti-diffusion layer 430, the offset arrangement can optimize the uniformity of current distribution and improve luminous brightness and reliability. The sidewall inclination angles of the fifth through hole 530 and the sixth through hole 540 are controlled between 15° and 25° to improve the filling quality and interface contact reliability of the N-type metal interconnect layer 700 and the P-type metal interconnect layer 600 in the through holes.
[0031] Specifically, the second insulating layer 520 is composed of SiO2 and SiN. x It is made of one or more of Al2O3, but is not limited thereto. The thickness of the second insulating layer 520 is 600 nm to 1200 nm. Preferably, in some embodiments, the second insulating layer 520 includes a SiO2 layer and / or a SiN layer. x The second insulating layer 520 has a thickness of 600 nm to 1000 nm. More preferably, the second insulating layer 520 is a SiO2 layer.
[0032] Please refer to Figures 3-6 Both the P-type metal interconnect layer 600 and the N-type metal interconnect layer 700 are disposed above the second insulating layer 520. The P-type metal interconnect layer 600 is connected to the reflective layer 400 through the sixth through-hole 540, and the N-type metal interconnect layer 700 is in contact with the conductive step through the fifth through-hole 530.
[0033] Specifically, the P-type metal interconnect layer 600 includes a first bottom layer 610 and a first etch-resistant layer 620 sequentially stacked on the second insulating layer 520; the N-type metal interconnect layer 700 includes a second bottom layer 710 and a second etch-resistant layer 720 sequentially stacked on the second insulating layer 520. The first bottom layer 610 and the second bottom layer 710 are both common single-layer or multi-layer metal structures in the art, and can be made of one or more of Cr, Al, Cu, Ti, Ni, Pt, Au, and Ag, but are not limited thereto.
[0034] Preferably, in some embodiments, both the first bottom layer 610 and the second bottom layer 710 include a third Cr layer 611, a first AlCu layer 612, a third Ti layer 613, a second AlCu layer 614, a fourth Ti layer 615, and a third AlCu layer 616 stacked sequentially; the thickness of the third Cr layer 611 is 2nm~8nm, the thickness of the first AlCu layer 612 is 300nm~800nm, and its Cu content is 5wt%~20wt%; the thickness of the third Ti layer 613 is 50nm~200nm; the thickness of the second AlCu layer 614 is 300nm~800nm, and its Cu content is 5wt%~20wt%; the thickness of the fourth Ti layer 615 is 50nm~200nm; and the thickness of the third AlCu layer 616 is 300nm~800nm, and its Cu content is 5wt%~20wt%. In the above multilayer structure, the Cr layer can effectively improve adhesion, the Ti layer can improve thermal stability, and the AlCu layer can improve reflectivity while ensuring good conductivity and anti-electromigration ability. The synergistic effect of these layers enables the overall structure to maintain excellent interfacial stability and electrical performance under high temperature and high humidity environments, improving reliability and light extraction efficiency.
[0035] Specifically, the first anti-etching layer 620 and the second anti-etching layer 720 are both made of one or more of Cr, Ni, Pt, Au, and Ti. These first and second anti-etching layers 620 and 720 effectively resist the erosion of the P-type metal interconnect layer 600 and the N-type metal interconnect layer 700 during wet etching to form the first contact hole 810 and the second contact hole 820. This not only ensures the complete removal of the third insulating layer 800 but also protects the structural integrity of the P-type and N-type metal interconnect layers 600, ensuring low-resistance, stable ohmic contacts, reducing operating voltage, and improving reliability and yield. Specifically, the thicknesses of the first and second anti-etching layers 620 and 720 are controlled between 100 nm and 500 nm, respectively.
[0036] Preferably, in some embodiments, both the first etch-resistant layer 620 and the second etch-resistant layer 720 include a first Cr layer 621, a first Pt layer 622, and a first Ti layer 623 stacked sequentially; the thickness of the first Cr layer 621 is 20nm~100nm, the thickness of the first Pt layer 622 is 100nm~200nm, and the thickness of the first Ti layer 623 is 4nm~15nm. This three-layer structure can effectively improve brightness, reduce operating voltage, and improve the luminous efficiency of the device.
[0037] Preferably, in other embodiments, both the first etch-resistant layer 620 and the second etch-resistant layer 720 comprise a first Ni layer 624, a second Cr layer 625, and a second Ti layer 626 stacked sequentially; the thickness of the first Ni layer 624 is 10 nm to 50 nm, the thickness of the second Cr layer 625 is 100 nm to 200 nm, and the thickness of the second Ti layer 626 is 4 nm to 15 nm. This three-layer structure synergistically improves brightness, reduces operating voltage, enhances device luminous efficiency, and reduces production costs.
[0038] The third insulating layer 800 covers the P-type metal interconnect layer 600, the N-type metal interconnect layer 700, and the second insulating layer 520. A first contact hole 810 exposing the P-type metal interconnect layer 600 and a second contact hole 820 exposing the N-type metal interconnect layer 700 are formed on the third insulating layer 800. Both the first contact hole 810 and the second contact hole 820 are formed using a wet etching process. This process effectively avoids damage to the underlying metal structure and epitaxial layer, ensuring that the etching process does not damage the light-emitting layer 220 and improving luminous efficiency. Furthermore, the wet etching process can completely remove the third insulating layer 800 from the first contact hole 810 and the second contact hole 820, preventing residue from increasing contact resistance. Specifically, in this application, the minimum spacing (L1) between the sidewall of the third insulating layer 800 near the P-type pad layer 910 and the sidewall of the P-type pad layer 910 is ≥500nm; the minimum spacing between the sidewall of the third insulating layer 800 near the N-type pad layer 920 and the sidewall of the N-type pad layer 920 is ≥500nm, with no third insulating layer 800 covering between them. Based on this, sufficient wiring space is provided for the N-type pad layer 920 and the P-type pad layer 910, facilitating alignment and connection in subsequent wire bonding processes, while reducing the risk of short circuits and improving reliability. Preferably, in some embodiments, the minimum spacing between the sidewall of the third insulating layer 800 near the P-type pad layer 910 and the sidewall of the P-type pad layer 910 is 500nm~2000nm. The minimum spacing between the sidewall of the third insulating layer 800 near the N-type pad layer 920 and the sidewall of the N-type pad layer 920 is 500nm~2000nm. It should be noted that the minimum spacing refers to the distance between the bottom of the sidewall of the third insulating layer 800 near the P-type pad layer 910 and the bottom of the sidewall of the P-type pad layer 910. Alternatively, it refers to the distance between the bottom of the sidewall of the third insulating layer 800 near the N-type pad layer 920 and the bottom of the sidewall of the N-type pad layer 920.
[0039] Specifically, the third insulating layer 800 is composed of SiO2 and SiN. x It is made of one or more of Al2O3, but is not limited thereto. The thickness of the third insulating layer 800 is 500 nm to 1200 nm. Preferably, in some embodiments, the third insulating layer 800 is a SiO2 layer and / or SiN.x The third insulating layer 800 has a thickness of 600 nm to 1000 nm. More preferably, the third insulating layer 800 is a SiO2 layer.
[0040] Specifically, after wet etching, the tilt angle (α) of the sidewall of the third insulating layer 800 near the P-type pad layer 910 (i.e., the sidewall of the first contact hole 810) is ≥10°; the tilt angle of the sidewall of the third insulating layer 800 near the N-type pad layer 920 (i.e., the sidewall of the second contact hole 820) is ≥10°. By controlling the tilt angle, the interfacial bonding strength between the pad layer and the metal interconnect layer can be enhanced, thereby improving reliability. More preferably, the tilt angle of the sidewall of the third insulating layer 800 near the P-type pad layer 910 is 10°~20°; the tilt angle of the sidewall of the third insulating layer 800 near the N-type pad layer 920 is 10°~20°.
[0041] In this design, the P-type pad layer 910 is positioned above the P-type metal interconnect layer 600, with its edge completely falling within the range of the first contact hole 810. Similarly, the N-type pad layer 920 is positioned above the N-type metal interconnect layer 700, with its edge completely falling within the range of the second contact hole 820. This design not only ensures sufficient and stable ohmic contact between the pad layer and the underlying metal interconnect layer but also effectively prevents the risk of insulation layer breakdown caused by lateral pad creep.
[0042] Specifically, the P-type pad layer 910 and the N-type pad layer 920 are common metal pad structures in the art, such as a stacked structure composed of one or more of Ti, Sn, Ni, and Au, but are not limited thereto. Preferably, both the P-type pad layer 910 and the N-type pad layer 920 are Ti / Al / Ti / Pt / Ti / Ni / Au stacked structures, and the thicknesses of each layer are 0.1nm~5nm, 1000nm~2000nm, 50nm~200nm, 100nm~300nm, 20nm~100nm, 800nm~1500nm, and 20nm~200nm, respectively.
[0043] Specifically, the tilt angle (β) of the sidewall of the P-type pad layer 910 is 50°~70°, and the tilt angle of the sidewall of the N-type pad layer 920 is 50°~70°. Based on the above tilt angles, the pad layer can form a good coating state.
[0044] Preferably, in some embodiments, the flip-chip LED further includes a current diffusion layer 270, which is disposed above the P-type semiconductor layer 230, more specifically between the P-type semiconductor layer 230 and the first insulating layer 300. The current diffusion layer 270 is an ITO layer, an IZO layer, an IGO layer, or an IGZO layer, but is not limited to these. The thickness of the current diffusion layer 270 is 100nm~300nm. The projection of the current diffusion layer 270 on the substrate 100 is located inside the projection of the P-type semiconductor layer 230 on the substrate 100, that is, there is a predetermined distance between the sidewall of the current diffusion layer 270 and the sidewall of the light-emitting structure 260.
[0045] Preferably, in some embodiments, the flip-chip LED further includes a passivation layer 510, which is disposed below the second insulating layer 520, and more specifically, between the second insulating layer 520 and the DBR reflective layer 410 / conductive anti-diffusion layer 430. The passivation layer 510 is an Al2O3 layer with a thickness of 100nm~150nm.
[0046] Accordingly, the present invention also discloses a method for preparing a flip-chip LED, which specifically includes the following steps: S1: An epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, and a third insulating layer are formed on the substrate; Specifically, step S1 includes: S11: An epitaxial layer is formed on the substrate; Specifically, an epitaxial layer is obtained by sequentially forming an N-type semiconductor layer 210, a light-emitting layer 220, and a P-type semiconductor layer 230 on a substrate 100 using methods such as MOCVD, MBE, and PVD.
[0047] S12: Etching forms multiple N-type conductive steps and isolation trenches that expose the N-type semiconductor layer, forming multiple light-emitting structures on the substrate; Specifically, a mask (photoresist layer or SiO2 layer) can be formed on the epitaxial layer first, and then the P-type semiconductor layer 230, the light-emitting layer 220 and the N-type semiconductor layer 210 of a preset thickness in the preset area can be removed by wet etching or dry etching to form an N-type conductive step 240, an isolation trench 250 and a light-emitting structure 260, but it is not limited to this.
[0048] S13: A first insulating layer and a DBR reflective layer are formed on the N-type conductive step, the isolation groove, and the light-emitting structure; Specifically, in some embodiments, a first insulating layer 300 and a DBR reflective layer 410 are formed by PECVD, and then a third via 411 and a fourth via 412 are formed on the DBR reflective layer 410 by a dry etching process. Finally, a first via 310 and a second via 320 are formed at corresponding positions on the first insulating layer 300 by a wet etching process.
[0049] S14: A metal reflective layer and a conductive anti-diffusion layer are formed on the DBR reflective layer to obtain the first intermediate; Specifically, a metal stack can be formed through electron beam evaporation or PVD processes to obtain a metal reflective layer 420 and a conductive anti-diffusion layer 430, but it is not limited to these methods.
[0050] Preferably, in some embodiments, a photoresist layer is first formed on the DBR reflective layer 410, then the photoresist layer in the preset area above the light-emitting structure 260 is removed by exposure and development, then multiple metals are sequentially deposited by electron beam evaporation, and finally the metals located on the photoresist layer are removed by blue film stripping process. Finally, the photoresist layer is removed, that is, a metal reflective layer 420 and a conductive anti-diffusion layer 430 are formed in the preset area above the light-emitting structure 260.
[0051] S15: A passivation layer and a second insulating layer are formed on the first intermediate body, and a sixth through hole is formed to expose the conductive anti-diffusion layer and a fifth through hole is formed to expose the N-type conductive step. Specifically, a passivation layer 510 and a second insulating layer 520 can be formed through processes such as ALD, PECVD, and LPCVD, and then a fifth through hole 530 and a sixth through hole 540 can be formed by etching, but it is not limited to these processes.
[0052] Preferably, in some embodiments, a passivation layer 510 is first formed on the first intermediate by ALD, and then a second insulating layer 520 is formed on the passivation layer 510 by PECVD. Then, a fifth via 530 and a sixth via 540 are formed by dry etching.
[0053] S16: A P-type metal interconnect layer and an N-type metal interconnect layer are formed on the first insulating layer to obtain a second intermediate; Specifically, metal stacks can be formed through electron beam evaporation or PVD processes to obtain a P-type metal interconnect layer 600 and an N-type metal interconnect layer 700, but are not limited to these.
[0054] Preferably, in some embodiments, a photoresist layer is first formed in the second insulating layer 520, the fifth via 530, and the sixth via 540. Then, the photoresist layer in the preset area is removed by exposure and development. Then, a metal stack is deposited by electron beam evaporation to form a P-type metal interconnect layer 600 and an N-type metal interconnect layer 700. Then, the metal on the photoresist layer is removed by blue film stripping. Finally, the photoresist is removed to obtain the second intermediate.
[0055] S17: Form a third insulating layer on the second intermediate; Specifically, the third insulating layer 800 can be formed by processes such as ALD, PECVD, and LPCVD, but is not limited thereto. Preferably, in some embodiments, the third insulating layer 800 is formed by PECVD.
[0056] S2: The first and second contact holes are formed on the third insulating layer using a wet etching process; Specifically, a wet etching solution containing HF can be used to wet etch the third insulating layer 800 to form the first contact hole 810 and the second contact hole 820.
[0057] Preferably, in some embodiments, the third insulating layer 800 is wet-etched using a BOE etching solution. The BOE etching solution consists of 49% HF aqueous solution and 40% NH4F aqueous solution, with a volume ratio of NH4F aqueous solution to HF aqueous solution of 6:1 to 10:1. The etching temperature is 20°C to 30°C, and the etching time is 800s to 1100s. With the above etching process parameters, the etching ratio of the BOE etching solution to the third insulating layer 800 and the P-type metal interconnect layer 600 or the N-type metal interconnect layer 700 can be ≥100:1, thereby ensuring the integrity of the N-type metal interconnect layer 700 and the P-type metal interconnect layer 600 while effectively etching the third insulating layer 800.
[0058] More preferably, the etching time is 800s~1000s, and even more preferably 900s~1000s. Based on this etching time, it can be ensured that the third insulating layer 800 in the first contact hole 810 / second contact hole 820 is completely removed and a smooth slope of 12°~15° is formed, which greatly optimizes the coverage characteristics of the P-type pad layer 910 and the N-type pad layer 920 and improves reliability.
[0059] S3: A P-type pad layer is formed in the first contact hole; an N-type pad layer is formed in the second contact hole.
[0060] Specifically, metal layers can be formed through electron beam evaporation or PVD processes to obtain P-type pad layer 910 and N-type pad layer 920, but are not limited to these.
[0061] Preferably, in some embodiments, a photoresist layer is first formed in the third insulating layer 800, the first contact hole 810 and the second contact hole 820, then the photoresist layer in the preset area is removed by exposure and development, then a metal stack is deposited by electron beam evaporation to form a P-type pad layer 910 and an N-type pad layer 920, then the metal on the photoresist layer is removed by blue film stripping process, and finally the photoresist is removed.
[0062] Preferably, in some embodiments, the method for preparing flip-chip LEDs further includes: splitting the wafer obtained in step S3 along the isolation trench 250, and then testing and sorting it to obtain flip-chip LEDs.
[0063] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a flip-chip LED, the structure of which includes a substrate, an epitaxial layer, a current diffusion layer, a first insulating layer, a reflective layer, a passivation layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer and an N-type pad layer stacked on the substrate.
[0064] The third insulating layer is a SiO2 layer with a thickness of 850 nm. This third insulating layer covers both the P-type and N-type metal interconnect layers and forms a first contact hole exposing the P-type metal interconnect layer and a second contact hole exposing the N-type metal interconnect layer. The P-type pad layer is connected to the P-type metal interconnect layer through the first contact hole, and the N-type pad layer is connected to the N-type metal interconnect layer through the second contact hole. Both the first and second contact holes are formed using a wet etching process; specifically, a BOE etching solution (NH4F:HF = 6:1) is used with an etching temperature of 25°C and an etching time of 950 s.
[0065] The P-type metal interconnect layer comprises a first bottom layer and a first etch-resistant layer stacked sequentially. The first bottom layer has a Cr / AlCu / Ti / AlCu / Ti / AlCu structure, with thicknesses of 3.5nm / 500nm / 100nm / 500nm / 100nm / 500nm for each layer, and a Cu content of 10wt% in AlCu. The first etch-resistant layer has a Cr / Pt / Ti structure, with thicknesses of 50nm / 150nm / 5nm for each layer.
[0066] The N-type metal interconnect layer comprises a second bottom layer and a second etch-resistant layer stacked sequentially. The second bottom layer has a Cr / AlCu / Ti / AlCu / Ti / AlCu structure with thicknesses of 3.5 nm / 500 nm / 100 nm / 500 nm / 100 nm / 500 nm, respectively, and the Cu content in AlCu is 10 wt%. The second etch-resistant layer has a Cr / Pt / Ti structure with thicknesses of 50 nm / 150 nm / 5 nm, respectively.
[0067] The inclination angle of the sidewall of the third insulating layer near the P-type pad layer / N-type pad layer is 12.5°~13.3°; the minimum spacing between the third insulating layer and the P-type pad layer / pad layer is 1.24μm~1.3μm.
[0068] The P-type and N-type pad layers are both Ti / Al / Ti / Pt / Ti / Ni / Au stacked structures, with thicknesses of 0.5nm, 1600nm, 100nm, 200nm, 50nm, 1000nm, and 50nm, respectively. The sidewall tilt angles of the P-type and N-type pad layers are 55.4° to 56.6°.
[0069] Example 2 This embodiment provides a flip-chip LED, which differs from Embodiment 1 in that the wet etching time for forming the first and second contact holes is 800 seconds. All other aspects are the same as in Embodiment 1.
[0070] Through the above process, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer / N-type pad layer is 14.5°~16°; the minimum spacing between the third insulating layer and the P-type pad layer / pad layer is 0.8μm~1.1μm. The inclination angle of the sidewall of the P-type pad layer and the N-type pad layer is 58.5°~60°.
[0071] The SEM images of the flip-chip LEDs obtained in Examples 1 and 2 are shown below. Figure 7 As shown in (B) and (A) in the figures, it can be seen that both the third insulating layer and the pad layer form a smooth slope morphology, and the third insulating layer inside the contact hole is completely removed, resulting in good pad layer coverage. The pad layer coverage is particularly good in Example 1. It should be noted that in these two figures, the topmost layer is the metal layer formed by gold spraying during the SEM test.
[0072] Example 3 This embodiment provides a flip-chip LED, which differs from Embodiment 1 in that: Both the first and second anti-etching layers have a Ni / Cr / Ti structure, with thicknesses of 20 nm, 130 nm, and 5 nm, respectively. Everything else is the same as in Example 1.
[0073] In this embodiment, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer / N-type pad layer is 12.6°~13.1°; the minimum spacing between the third insulating layer and the P-type pad layer / pad layer is 0.75μm~0.98μm. The inclination angle of the sidewall of the P-type pad layer and the N-type pad layer is 60°~63°.
[0074] Example 4 This embodiment provides a flip-chip LED, which differs from Embodiment 3 in that: When wet etching is used to form the first and second contact holes, the etching time is 800 seconds. The rest is the same as in Example 3.
[0075] Through the above process, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer / N-type pad layer is 15.1°~16.2°; the minimum spacing between the third insulating layer and the P-type pad layer / pad layer is 0.5μm~0.77μm. The inclination angle of the sidewall of the P-type pad layer and the N-type pad layer is 62°~65°.
[0076] Example 5 This embodiment provides a flip-chip LED, which differs from Embodiment 3 in that: When wet etching is used to form the first and second contact holes, the etching time is 1050 s. The rest is the same as in Example 3.
[0077] Through the above process, the inclination angle of the sidewall of the third insulating layer near the P-type pad layer / N-type pad layer is 13.1°~14.5°; the minimum spacing between the third insulating layer and the P-type pad layer / pad layer is 1.3μm~1.5μm. The inclination angle of the sidewall of the P-type pad layer and the N-type pad layer is 58.3°~61.5°.
[0078] The SEM images of the flip-chip LEDs obtained in Examples 3, 4, and 5 are shown below. Figure 8 As shown in (B), (A), and (C) of the figure, it can be seen that the third insulating layer and pad layer of all three have formed a smooth slope morphology, and the third insulating layer inside the contact hole is completely removed, and the pad layer coverage is good. With an etching time of 950s (… Figure 8 Example 3 of (B) has the best morphology.
[0079] Comparative Example 1 This comparative example provides a flip-chip LED, which differs from Example 1 in that: Both the first and second anti-etching layers are Ti / Pt / Ti structures, with thicknesses of 100nm / 150nm / 5nm, respectively. Everything else is the same as in Example 1.
[0080] Furthermore, both the first and second contact holes were etched using ICP etching technology.
[0081] The flip-chip LEDs (50mil × 50mil) obtained in Examples 1, 3, and Comparative Example 1 were tested at 700mA. The specific results are shown in the table below:
[0082] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.
Claims
1. A flip-chip LED, characterized in that, include: A substrate, with an epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, a third insulating layer, a P-type pad layer, and an N-type pad layer stacked on the substrate; The third insulating layer covers the P-type metal interconnect layer and the N-type metal interconnect layer, and forms a first contact hole exposing the P-type metal interconnect layer and a second contact hole exposing the N-type metal interconnect layer. The P-type pad layer is connected to the P-type metal interconnect layer through the first contact hole, and the N-type pad layer is connected to the N-type metal interconnect layer through the second contact hole. Both the first contact hole and the second contact hole are formed by a wet etching process. The P-type metal interconnect layer includes a first bottom layer and a first etch-resistant layer sequentially stacked on the second insulating layer; the N-type metal interconnect layer includes a second bottom layer and a second etch-resistant layer sequentially stacked on the second insulating layer. Both the first anti-etching layer and the second anti-etching layer are made of one or more of Cr, Ni, Pt, Au, and Ti.
2. The flip-chip LED as described in claim 1, characterized in that, Both the first etch-resistant layer and the second etch-resistant layer comprise a first Cr layer, a first Pt layer, and a first Ti layer stacked sequentially. The thickness of the first Cr layer is 20nm~100nm, the thickness of the first Pt layer is 100nm~200nm, and the thickness of the first Ti layer is 4nm~15nm.
3. The flip-chip LED as described in claim 1, characterized in that, Both the first etch-resistant layer and the second etch-resistant layer comprise a first Ni layer, a second Cr layer, and a second Ti layer stacked sequentially. The thickness of the first Ni layer is 10nm~50nm, the thickness of the second Cr layer is 100nm~200nm, and the thickness of the second Ti layer is 4nm~15nm.
4. The flip-chip LED as described in claim 1, characterized in that, The inclination angle of the sidewall of the third insulating layer near the P-type pad layer is ≥10°; The inclination angle of the sidewall of the third insulating layer near the N-type pad layer is ≥10°; The minimum distance between the sidewall of the third insulating layer near the P-type pad layer and the sidewall of the P-type pad layer is ≥500nm. The minimum spacing between the sidewall of the third insulating layer near the N-type pad layer and the sidewall of the N-type pad layer is ≥500nm.
5. The flip-chip LED as described in claim 1, characterized in that, The inclination angle of the sidewall of the third insulating layer near the P-type pad layer is 10°~20°; The inclination angle of the sidewall of the third insulating layer near the N-type pad layer is 10°~20°; The minimum distance between the sidewall of the third insulating layer near the P-type pad layer and the sidewall of the P-type pad layer is 500nm~2000nm. The minimum spacing between the sidewall of the third insulating layer near the N-type pad layer and the sidewall of the N-type pad layer is 500nm~2000nm.
6. The flip-chip LED as described in claim 1, characterized in that, Both the first bottom layer and the second bottom layer are made of one or more of Cr, Al, Cu, Ti, Ni, Pt, Au, and Ag; and / or The first insulating layer is a SiO2 layer and / or SiN. x Layers with a thickness of 400nm~600nm; and / or The second insulating layer is a SiO2 layer and / or SiN. x Layers with a thickness of 600nm~1000nm; and / or The third insulating layer is a SiO2 layer and / or SiN. x The layer has a thickness of 600nm~1000nm.
7. The flip-chip LED as described in claim 1, characterized in that, Both the first bottom layer and the second bottom layer comprise a third Cr layer, a first AlCu layer, a third Ti layer, a second AlCu layer, a fourth Ti layer, and a third AlCu layer stacked sequentially. The thickness of the third Cr layer is 2 nm to 8 nm; the thickness of the first AlCu layer is 300 nm to 800 nm, and its Cu content is 5 wt% to 20 wt%; the thickness of the third Ti layer is 50 nm to 200 nm; the thickness of the second AlCu layer is 300 nm to 800 nm, and its Cu content is 5 wt% to 20 wt%; the thickness of the fourth Ti layer is 50 nm to 200 nm; and the thickness of the third AlCu layer is 300 nm to 800 nm, and its Cu content is 5 wt% to 20 wt%.
8. The flip-chip LED as described in claim 1, characterized in that, The flip-chip LED further includes a current diffusion layer disposed between the epitaxial layer and the first insulating layer; the current diffusion layer is an ITO layer, an IZO layer, an IGO layer, or an IGZO layer, with a thickness of 100nm~300nm; and / or The flip-chip LED further includes a passivation layer disposed below the second insulating layer. The passivation layer is an Al2O3 layer with a thickness of 100nm~150nm; and / or The reflective layer comprises a DBR reflective layer, a metal reflective layer, and a conductive anti-diffusion layer sequentially stacked on the first insulating layer; the DBR reflective layer is a SiO2 / TiO2 type DBR layer, a MgF2 / TiO2 type DBR layer, or a SiO2 / Ti2O5 type DBR layer; the thickness of the DBR reflective layer is 0.5μm~5μm; The metal reflective layer is made of one or more of Ag, Al or Au, and its thickness is 100nm~300nm; the conductive anti-diffusion layer is made of one or more of Ti, Ni, Cr, Au, TiW, PtPd, and its thickness is 200nm~500nm.
9. A method for fabricating a flip-chip LED, used to fabricate the flip-chip LED as described in any one of claims 1 to 8, characterized in that, include: An epitaxial layer, a first insulating layer, a reflective layer, a second insulating layer, a P-type metal interconnect layer, an N-type metal interconnect layer, and a third insulating layer are formed on a substrate. The first and second contact holes are formed on the third insulating layer using a wet etching process. A P-type pad layer is formed in the first contact hole; an N-type pad layer is formed in the second contact hole.
10. The method for fabricating a flip-chip LED as described in claim 9, characterized in that, The third insulating layer is wet-etched using BOE etching solution to form the first contact hole and the second contact hole; The volume ratio of NH4F aqueous solution to HF aqueous solution in the BOE etching solution is 6:1 to 10:1, the etching temperature is 20℃ to 30℃, and the etching time is 800s to 1000s. The etching ratio of the BOE etching solution to the third insulating layer and the P-type or N-type metal interconnect layer is ≥100:1.