3D circuit on RF bulk substrate

Abstract

Integrated circuit on a solid semiconductor substrate (10) comprising: - a solid semiconductor substrate (10), in particular highly resistive, - opposite a first region (R1) of said substrate (10), at least one transistor (T11) of a lower transistor level, formed in a first semiconductor layer (12) belonging to the solid semiconductor substrate or disposed on and in contact with said substrate (10), - at least one transistor (T21) of a higher transistor level having a channel region in a second semiconductor layer (112) arranged in a stack of layers resting on the substrate (11), the higher-level transistor being disposed opposite a second region (R2), - one or more metallic interconnect levels (M1,…,Mk) and at least one RF component (Ck) such as an antenna formed in a given level among said metallic interconnect levels,said RF component (Ck) being arranged opposite a localized structure (50) for charge trapping and / or blocking parasitic currents. Figure for the abbreviation: figure 1.

Description

Title of the invention: 3D circuit on a bulk RF substrate TECHNICAL FIELD AND PREVIOUS ART

[0001] The field of the invention is that of microelectronic devices formed on substrates adapted to radio frequency (RF) applications.

[0002] The invention relates more particularly to a 3D microelectronic device formed on a bulk substrate ("bulk" according to Anglo-Saxon terminology) having a heterogeneous surface area to make it suitable for both RF applications and the integration of particular transistors and optimized performance, in particular bipolar transistors.

[0003] For RF applications, and in particular those operating at high frequencies typically above 700 MHz, the substrates must support the circuits without disrupting their operation. In particular, propagation losses, crosstalk, and parasitic harmonics must be eliminated.

[0004] There are suitable semiconductor-on-insulator substrates for these RF applications, in particular those of the RF-SOI type (SOI for "Silicon On Insulator" or "Silicon on Insulator").

[0005] A semiconductor-on-insulator substrate is commonly formed of a semiconductor support layer covered by, and in contact with, an insulating layer, itself covered by, and in contact with, a surface semiconductor layer generally intended to serve as an active layer, that is to say, in which active components, such as transistors or passive components, in particular of an RF circuit, are intended to be formed.

[0006] For RF applications, known adaptations of these substrates consist of:

[0007] - providing a support layer made of a low resistive semiconductor material doped, and forming, beneath and against the insulating layer commonly called the "BOX," a charge-trapping layer commonly called a "trap rich." This layer is made of a semiconductor material rich in crystal defects and / or grain boundaries, which allows it to trap charges. Without this trapping layer, fixed (positive) charges in the BOX would induce the presence of mobile charges (electrons) in the support layer near the BOX, locally negating the benefit of the low doping of the support layer. The trapping layer is usually made of a polycrystalline silicon layer.

[0008] For certain specific applications where it is also necessary to have transistors capable of handling high current levels, in particular Bipolar transistors, RF-SOI substrates may have limitations in terms of density and performance.

[0009] RF-SOI substrates also prove to be particularly expensive.

[0010] Other types of substrates are now used for RF applications, including glass, quartz, and ceramic substrates.

[0011] Bulk substrates known as high resistivity (HR) substrates can also be used for RF applications.

[0012] Such substrates are not always suitable for high-density component integration.

[0013] Furthermore, the presence of unintentional impurities can have an important effect on the electrical properties of the HR semiconductor material, potentially becoming sources of disturbance.

[0014] The problem arises of realizing a microelectronic device on such a type of substrate which has an improved integration density while maintaining good performance with respect to possible disturbances related to an RF circuit and / or component(s). Description of the invention

[0015] It is therefore an object of the present invention to provide an integrated circuit on a bulk semiconductor substrate comprising:

[0016] - a bulk semiconductor substrate, in particular a highly resistive one,

[0017] - a lower level of transistors comprising, opposite a first region of the substrate, at least one lower-level transistor, the lower-level transistor being formed at least partly in a first semiconductor layer, the first semiconductor layer belonging to the bulk semiconductor substrate and / or being disposed on and in contact with the substrate,

[0018] - a higher level of transistors having at least one higher level transistor having a channel region in a second semiconductor layer arranged in a stack of layers resting on the substrate, said higher-level transistor being disposed opposite a second region of the bulk substrate,

[0019] - a localized structure for trapping charges and / or blocking currents parasitic, formed on or in the second region of the substrate and configured to limit parasitic conduction in the second region of the substrate, the localized structure being located below at least one upper-level transistor,

[0020] - one or more metallic interconnection levels, and

[0021] - at least one RF component such as an antenna or an inductor formed in a a given level among the metallic interconnection levels, the RF component being arranged in relation to the localized structure for trapping charges and / or blocking stray currents.

[0022] By providing such an arrangement, it is possible both to integrate transistors into the bulk substrate, to maintain a good integration density of transistors while protecting against losses related to substrates and undesirable effects such as parasitic capacitance, harmonic distortions and crosstalk.

[0023] The localized structure configured to limit parasitic conduction in the second region may comprise at least one element from among:

[0024] - a layer of semiconductor material having implantation defects;

[0025] - a layer of amorphous or polycrystalline semiconductor material;

[0026] - a set of junctions formed by an alternation of doped zones according to a first type of doping, N or P and doped areas according to a second type of doping, P or N, different from the first type of doping;

[0027] - a heterogeneous dielectric region formed by alternating blocks of material dielectric with fixed positive charges and blocks of dielectric material with fixed negative charges.

[0028] Advantageously, the lower level transistor is a transistor of a first type, while the upper level transistor is a transistor of a second type.

[0029] The lower level transistor opposite the first region may in particular be a bipolar transistor or HEMT.

[0030] The higher level transistor opposite the second region may in particular be a MOS transistor, advantageously a partially or fully channeled MOS transistor.

[0031] Advantageously, the higher-level transistor is a transistor of a switching circuit, the switching circuit being arranged opposite the second region and preferably not extending opposite the first region.

[0032] According to one embodiment, the integrated circuit includes at least one second higher-level transistor having a channel in the second semiconductor layer, this second higher-level transistor being at least partially arranged opposite the first region of the substrate.

[0033] According to a particular embodiment, the higher-level transistor may be provided with a back electrode, in particular a ground plane, the back electrode being arranged in said stack between the first region and said second higher-level transistor.

[0034] According to another aspect, the present invention relates to a method for manufacturing an integrated circuit as defined above.

[0035] One embodiment of the present invention relates to a method for manufacturing an integrated circuit comprising steps consisting of:

[0036] - provide a massive substrate, in particular highly resistive (HR), and form with respect to a first region of said bulk substrate, at least one lower-level transistor, the lower-level transistor having a channel in a semiconductor layer of the substrate and / or disposed in contact with said substrate,

[0037] - form opposite a second region of said substrate distinct from the first a localized charge trapping and / or parasitic current blocking structure in the region to limit parasitic conduction in the second region,

[0038] - to coat said lower level and said localized structure with at least one layer so-called "inter-level" insulation

[0039] - to assemble, in particular by molecular adhesion bonding, a support on said inter-level insulating layer, said support being provided with a semiconducting layer called the "second semiconducting layer",

[0040] - to form at least one higher-level transistor from said second semiconductor layer, said higher-level transistor having a channel region in the second semiconductor layer and being disposed opposite the second region of said substrate.

[0041] Advantageously, the formation of said at least one lower-level transistor comprises one or more steps carried out before the realization of said localized structure.

[0042] According to one possible implementation, the method may include carrying out a masking on the second region to protect the second region, this masking being carried out so as to retain an opening opposite the first region, the transistor being at least partially formed in the opening.

[0043] According to a particular embodiment, the method may include the formation of at least one layer covering the lower-level transistor and a passage through said at least one layer covering the lower-level transistor, so as to reveal said second region, the localized structure then being formed through the passage on or in at least a portion of the second region revealed by the passage.

[0044] According to one embodiment, the formation of the localized structure may include the following steps:

[0045] - deposition of a layer of amorphous or polycrystalline semiconductor material in the hole or passage and so as to cover at least a portion of the second region, then

[0046] - etching of the layer of amorphous or polycrystalline semiconductor material of way to retain at least a portion of amorphous or polycrystalline semiconductor material opposite the second region.

[0047] According to one possible embodiment of the process in which the localized structure comprises a heterogeneous dielectric region formed by alternating blocks of a dielectric material with positive fixed charges and blocks of a second dielectric material with negative fixed charges, the formation of the localized structure may include the following steps:

[0048] - deposit in the hole or passage of a first dielectric material, with fixed charges positive or fixed negative charges, then

[0049] - etching the first dielectric material so as to form blocks based on the first dielectric material, then

[0050] - deposition of a second dielectric material to form blocks based on the second dielectric material, the second dielectric material being positively fixed when the first dielectric material is negatively fixed, or being negatively fixed when the first dielectric material is positively fixed.

[0051] According to one possible embodiment of the method in which the localized structure comprises a plurality of juxtaposed junctions and formed of an alternation of areas doped according to a doping of a first type, in particular P or N and areas doped according to a doping of a second type, in particular N or P and different from the first type, the method comprising a plurality of doping implantations of the second region through the hole or a plurality of successive doping implantations of the second region through the passage.

[0052] According to a particular embodiment, the localized structure can be formed of a charge trapping layer the realization of which includes at least one amorphization implantation of a region of the substrate arranged under the masking, the amorphization implantation being advantageously carried out after formation of the lower level transistor.

[0053] According to another particular embodiment, the formation of the localized structure includes an implantation leading to the formation of a layer rich in crystalline defects of an area of ​​the substrate arranged under the masking.

[0054] According to one embodiment, prior to assembly between the substrate and the support, and after coating the lower level and the localized structure with at least one insulating layer called an "inter-level" layer, the process may comprise the following steps:

[0055] - form one or more ground plane zones on said inter-insulating layer levels, then,

[0056] - to coat said one or more ground plane areas with at least one layer insulating bonding agent, the assembly of the substrate and the support then being carried out by bonding by molecular adhesion of the insulating bonding layer with the support assembled on said inter-level insulating layer. Brief description of the drawings

[0057] The present invention will be better understood on the basis of the following description and the accompanying drawings in which:

[0058] [Fig. 1] serves to illustrate an example of a multi-level transistor integrated circuit formed on a solid substrate having a modified region, suitable for RF applications by allowing the blocking of parasitic currents and another region of different composition and preferably unmodified suitable for other applications in particular those using bipolar transistors.

[0059] [Fig.2] serves to illustrate an embodiment of the circuit in which the adapted region for RF applications is formed of a charge trapping layer.

[0060] [Fig.3] serves to illustrate a particular embodiment of the circuit in which the charge trapping layer is formed by an area implanted in the substrate and opposite which at least one RF component is placed.

[0061] [Fig.4] serves to illustrate a particular embodiment of the circuit in which the charge trapping layer is formed by a layer deposited on the substrate and opposite which at least one RF component is placed.

[0062] [Fig.5] serves to illustrate a particular embodiment of the circuit in which the modified region of the substrate comprises an alternation of P-doped regions and N-doped regions and opposite which at least one RF component is disposed.

[0063] [Fig.6] serves to illustrate a particular embodiment of the circuit in which the modified region of the substrate comprises an alternation of blocks of positively charged dielectric material and blocks of negatively charged dielectric material and opposite which at least one RF component is placed.

[0064] [Fig.7A] [Fig.7B] serve to illustrate different examples of transistor structures that can be integrated into the other region of the substrate adjacent to the one modified to limit the flow of parasitic currents.

[0065] [Fig.8A] [Fig.8B] [Fig.8C] [Fig.8D] [Fig.8E] [Fig.8F] [Fig.8G] [Fig.8H] [Fig.9] [Fig. 10] serve to illustrate an example of a process for realizing a multi-level circuit of superimposed transistors formed on a locally modified solid substrate for RF applications.

[0066] [Fig. 11 A] [Fig. 1 IB] [Fig. 1 IC] serve to illustrate different stages of realization of a trapping layer localized on a bulk substrate and juxtaposed to a region of the bulk substrate in which transistors of a first level of transistors are formed.

[0067] [Fig. 12] serves to illustrate an implementation of contacts by silicification of lower level transistors.

[0068] [Fig. 13] serves to illustrate an example of an embodiment of a parasitic current blocking structure formed of an alternation of blocks of positively charged dielectric material and blocks of negatively charged dielectric material.

[0069] [Fig.l4A] [Fig.l4B] serve to illustrate different stages of a parasitic current blocking structure formed by an alternation of N-doped and P-doped zones.

[0070] [Fig. 15] serves to illustrate an assembly step between a structure comprising a first level of transistors made on a solid substrate and above which one or more ground plane areas for higher level transistors are formed and a support having a semiconducting layer in which these higher level transistors are suitable for being formed.

[0071] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0072] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0073] In addition, in the description below, terms which depend on the orientation of a structure such as "front", "back", "upper", "lower", "on", "under", "above", "below" apply considering that the structure is oriented in the manner illustrated in the figures.

[0074] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0075] Reference is now made to [Fig. 1] on which an example of an integrated circuit is shown, called a “3D” » a multi-stage or superimposed level Nb N2 of transistors is represented.

[0076] The circuit is here formed from a bulk semiconductor substrate, for example silicon, in particular an HR substrate (HR for "Highly Resistant"), having at least one semiconductor layer with a high resistivity, i.e. greater than 100 Q.cm and preferably greater than 1 kQ.cm.

[0077] The circuit comprises a lower level Ni with at least one transistor Tu, in particular a transistor of a first type, for example of the bipolar type, advantageously of the heterojunction bipolar (HBT) type. This transistor may be at least partially formed in a surface semiconductor layer 12 of the substrate 10, for example of silicon, and / or at least partially formed in a semiconductor layer disposed on and in contact with the surface semiconductor layer 12 of the substrate 10. In the particular case where the transistor Tu is a heterojunction bipolar (HBT) transistor, a SiGe layer having a germanium concentration gradient may be formed to create the base region of the transistor.

[0078] According to another embodiment, the transistor Tu can be a HEMT (for "high-electron-mobility transistor"), formed in particular on the basis of at least one Gallium nitride (GaN) layer arranged on a silicon substrate.

[0079] The first type Tu transistor is here located in a first RI region distinct from a second R2 region of the substrate 10 by its composition.

[0080] It is also possible to form CMOS transistors in the first region Rb.

[0081] The integrated circuit here has at least one RF circuit or RF module, and the substrate 10 has a particular structure 50 located in the second region R2. This structure 50 is configured to limit parasitic surface conduction phenomena that may be generated by the RF circuit, in particular when it carries high-frequency signals, for example above 2 GHz.

[0082] The localized structure 50 may include a charge-trapping layer 23, commonly called a "trap-rich" layer, formed of a semiconductor material rich in crystal defects and / or grain boundaries. In this case, the charge-trapping layer 23 is typically a layer of polycrystalline semiconductor material, for example, polycrystalline silicon (polySi). A polySi layer 23 with a thickness, for example, between 10 nm and 3 pm, advantageously between 50 nm and 300 nm, may be provided. The charge-trapping layer 23 may advantageously be formed of a semiconductor material rich in implantation defects.

[0083] For example, the trapping layer 23 can be formed using steps of a process as described in the Applicant's EP3840033A1 document or in the document "Defect Engineering for Enhanced Silicon Radiofrequency Substrates", Perrosé et al., physica status solidi (a)Volume 221, Issue 17: Special Issue: Getting and Defect Engineering in Semiconductor Technology, 2024.

[0084] The structure 50 extends over a part of the substrate 10 opposite which the RF circuit is provided, such a circuit typically having at least one RF component of the antenna or inductor type and a switching circuit ("Switch circuit" according to Anglo-Saxon terminology) typically made from MOS type transistors.

[0085] This heterogeneous arrangement of the bulk substrate 10 with RI, R2 regions of different compositions makes it possible in particular to integrate certain types of transistors particularly suited to bulk substrates while optimizing performance with respect to the RF circuit.

[0086] The integrated circuit also has at least one second level N2 of transistors arranged on the first level Ni and whose respective channel regions extend into a second semiconductor layer 112, for example in silicon. The second semiconductor layer 112 is advantageously a thin layer, typically less than 500 nm and, for example, between 10 nm and 500 nm, preferably between 100 nm and 100 nm. Such a layer is particularly well-suited for the implementation of partially or fully stacked transistors. The second semiconductor layer 112 can be formed by transferring, and in particular by molecular adhesion, a support onto a stack of layers covering the substrate 10. The second semiconductor layer 112 can, for example, be a semiconductor-on-insulator support layer. Such a support typically consists of a semiconductor support layer coated with an insulating layer, typically made of silicon oxide and commonly called a "BOX," the insulating layer itself being coated with the semiconductor layer 112.According to a particular embodiment, the second semiconductor layer 112 can be based on a semiconductor material different from that of the substrate 10.

[0087] The first level N1 transistor(s) Tu and the second level N2 transistor(s) are separated by a stack or at least an insulating layer 35 ILD (acronym for "Inter-Layer Dielectric") "inter-levels" for example based on silicon oxide (SiO2).

[0088] An insulating thickness H1 between the second semiconducting layer 112 and the charge trapping layer 23 preferably of at least 5nm, in particular between 5nm and Ipm for example of the order of 200 nm, can be provided.

[0089] An insulating thickness H2 between the first Ni level of transistors and the semiconductor layer 112, for example between 5nm and Ipm, for example on the order of 100 nm, can also be provided.

[0090] The second level N2 of transistors comprises at least one transistor T2hdc of a different type than that of the lower level transistor Tnde, for example a MOS transistor.

[0091] Due to its thickness and the way in which it is made, the semiconductor layer 112 for the upper N2 stage is particularly suitable for the realization of CMOS or MOS transistors, in particular MOS with partially or totally stripped channel.

[0092] Thus, it is possible for example to form MOS or CMOS transistors in a semiconductor layer 112 of the upper level N2 while bipolar transistors are formed in the bulk substrate 10 of the lower level Ni.

[0093] Providing transistors of a given type and according to a given technology in one stage and transistors of a different type and according to a different technology in another stage can also simplify the circuit manufacturing process and reduce manufacturing costs. However, it It is possible to co-integrate transistors of different types and / or having different structures, within the same NbN2 level.

[0094] In the particular embodiment illustrated in [Fig. 1], a higher-level N2 transistor T2i is, for example, a switching transistor of the RF circuit located opposite the R2 region and the charge-trapping layer 23. Providing transistors of the RF circuit opposite the structure 50, and in particular the charge-trapping layer 23, improves the performance of this circuit.

[0095] Advantageously, the T2i transistor can be partially depleted channel, for example a switching MOS transistor made in PDSOI technology (acronym for "Partially Depleted Silicon-On-Insulator").

[0096] The transistors Tn,T2i are provided with conductive pads 148a and 149a, 149b, 149c respectively.

[0097] As in the particular embodiment illustrated in [Fig.1], the transistors Tn,T2ide at different levels Ni, N2 can be connected to each other via a conductive line 151 of a first metallic level Mi connecting pads 148a and 149a respectively of the transistors Tu T2i.

[0098] The second level N2 of transistor(s) T21 is covered with k (with k an integer greater than 1) stages of metallic interconnections Mi,...,Mk, each stage having one or more metallic lines and via(s) formed in one or more insulating layers 175 for example in SiO2.

[0099] In the particular embodiment example of [Fig.1], a component Ck of the RF circuit, in the form of an antenna, is made in a stage called BEOL (acronym for "Back-End Of Line") here at the same time as a metallic line of a metallic interconnection level Mk, with k being able for example to be equal to 10.

[0100] The component Ck is arranged opposite the localized structure 50 to limit parasitic conduction and in particular eddy currents that may be generated by RF signals carried by the antenna.

[0101] In another embodiment illustrated in [Fig.2], the second level N2 of transistors comprises transistors T22, T23 whose channel region is formed in the upper semiconductor layer 112, but which are located opposite this time the first region RI of the substrate 10 which is devoid of a charge trapping layer and in which the transistors of the lower level NI are provided.

[0102] It is also possible to co-integrate transistors having different dielectric thicknesses. Thus, transistors T22, T23 have, in this particular embodiment, a thick gate dielectric 124, for example twice as thick, as the dielectric of other transistors or than the standard thickness. As an alternative to the illustrated example, it is also possible to provide such transistors with a thicker dielectric above the second region R2.

[0103] In an embodiment of an integrated circuit as described above, one or more so-called "back" electrodes can be provided arranged between the substrate 10 and the semiconductor layer 112 in which the respective channel regions of the transistors of the upper N2 level extend.

[0104] A particular embodiment, illustrated in [Fig.3], provides as a back electrode a conductive zone 99 forming a ground plane, for example based on a doped semiconductor material such as doped silicon or on a metallic material such as TiN.

[0105] According to one embodiment illustrated in [Fig. 4], instead of being entirely formed within the thickness of a bulk substrate 10, for example by amorphization implantation followed by annealing, the charge-trapping layer 23 can be formed by depositing a layer of amorphous or polycrystalline semiconductor material onto the R2 region of the substrate 10, and then possibly undergoing further processing, for example with a laser, so as to create and / or enrich it with crystal defects or grain boundaries. The charge-trapping layer 23 can then form an overthickness, for example, of between 10 nm and 1 pm, on the substrate 10, and in particular on a highly resistive surface layer of this substrate 10.

[0106] The localized structure 50 allowing the limitation of parasitic surface conduction can, as an alternative to a charge trapping layer, be formed of a succession of junctions made in the R2 region of the substrate 10.

[0107] Thus, in the embodiment illustrated in [Fig.5], the localized structure 50 is formed of an alternation of doped regions 51 doped according to a doping of a first type, in particular N or P, and doped regions 53 doped according to a doping of a second type opposite to the first type, in particular P when the doping of the regions 51 is of type N, or in particular N when the doping of the regions 51 is of type P. An example of the implementation of such a structure is given in document EP3882971A1 from the applicant.

[0108] According to another embodiment illustrated in [Fig. 6], the localized structure 50, configured to limit parasitic surface conduction phenomena in the substrate 10, can be formed of alternating dielectric blocks made of a dielectric material 56 with positive fixed charges and dielectric blocks made of a second dielectric material 58 with negative fixed charges. By "dielectric material with positive fixed charges" is meant here a material capable of carrying positive fixed charges without the need for external polarization. Similarly, by "dielectric material with fixed negative charges" we mean here a material capable of carrying fixed negative charges without requiring external polarization. This alternation of dielectric materials creates an alternation of charge polarity in order to block the flow of parasitic current in the R2 region of the substrate 10. The dielectric material with fixed positive charges can, for example, be advantageously chosen from the following materials: silicon oxide, in particular SiO2, silicon nitride, silicon oxycarbide. The dielectric material with fixed negative charges can perhaps be, for example, based on alumina, in particular Al2O3, or hafnium oxide, in particular HfO2.Such dielectric blocks 56, 58 can be formed, for example, by deposition and etching so as to form an overthickness on a substrate area 10 which is juxtaposed to an RI region of the substrate 10 in which first-level transistors are arranged. An example of an embodiment of such a structure is given in document EP4297074A1 from the applicant.

[0109] Figures 7A-7B show various examples of transistor structures that can be formed in the RI region of the bulk substrate 10 for the lower NI level of the integrated circuit.

[0110] In the embodiment example of [Fig.7A], a transistor is made in the solid substrate 10 whose collector, base and emitter regions of the bipolar transistor are this time formed respectively by superimposed regions 719, 717, 715 doped respectively according to a doping of a first type, for example N-doped, according to a doping of a second type, for example P-doped, and according to a doping of the first type for example N-doped, so as to form here an NPN arrangement.

[0111] Advantageously, the collector and emitter regions can be formed from silicon, while the base region is made of SiGe with a germanium concentration gradient from the collector to the emitter. A germanium concentration gradient in the base region can be specifically provided to make the band gap narrower at the collector than at the emitter. Such a narrowing of the band gap accelerates transport through the base and results in an improved frequency response.

[0112] A particular example of an embodiment of a heterojunction bipolar transistor is given in the document "SiGe HBTs Featuring fT >400GHz at Room Temperature" by Geynet et al., 2008 IEEE Bipolar / BiCMOS Circuits and Technology Meeting.

[0113] In another embodiment illustrated in [Fig. 7B], an NMOS transistor formed of source- and drain-doped regions 721, 722 is constructed in the substrate 10 within a more lightly doped cavity 726 with an opposite type of doping, for example P-, and a PMOS transistor is formed of doped regions 723, 725 source and drain in a 728 low-doped chamber and according to an opposite type of doping, for example N-.

[0114] An example of a method for realizing an integrated circuit with superimposed transistor levels on a solid substrate and having a localized charge trapping and / or parasitic current blocking structure will now be described in connection with Figures 8A-8H.

[0115] A possible starting structure for the implementation of such a process is given in [Fig.8A], in the form of a massive substrate 10, for example a silicon substrate and highly resistive (HR) or having at least one semiconductor layer of high resistivity, i.e. greater than 500 Q.cm.

[0116] A localized masking 13 is then carried out in relation to a region R2 of the substrate 10, while preserving an opening 14 revealing another region RI of the substrate 10.

[0117] According to a particular embodiment shown in Figures 8A-8B, the masking 13 can be formed from a layer deposited "full plate", that is, over the entire extent of the substrate 10, and then locally etched so as to reveal the RI region. For example, the masking 13 can be made of silicon oxide. In this case, such masking 13 can be produced, for example, by thermal oxidation of the substrate 10. An oxide thickness of, for example, between 20 nm and 500 nm, for example, on the order of 150 nm, can be provided.

[0118] Next, the masking layer 13 is etched. Typically, this is done by coating it with a layer of resin in which patterns are formed by photolithography. Then, the pattern(s) are transferred by etching into the masking layer. This etching can, for example, be a dry etching using a plasma, such as a fluorocarbon gas-based plasma, for example, based on CF4, C2H6, CHF3, which may possibly be combined with CH4.

[0119] The masking 13 (and, where applicable, the resin layer not shown) covering it) is / are dimensioned, particularly in terms of thickness, to prevent diffusion of dopants into the substrate 10 during subsequent doping steps carried out to form transistors in the RI region of the substrate 10 exposed by the opening 14. The thickness of the masking 13 depends in particular on the thermal budget for manufacturing this or these transistors. By way of example, 150 nm of thermal oxide can be used.

[0120] One or more transistors are then formed, in particular transistors of a first type in the RI region of the substrate 10. The RI region can for example be dedicated to bipolar transistors and these transistors are produced in particular by means of implantation doping steps or in situ doped epitaxies to form doped regions and in particular PN junctions of the bipolar transistor.

[0121] Thus, in the particular embodiment example given in [Fig.8C], a Ti 10 transistor made in the substrate 10 has a structure of the type of that described previously in relation to [Fig.7A].

[0122] The masking 13 then makes it possible to protect the R2 region of the substrate 10 from these implantation steps and to keep it without dopant or at least to preserve it as a region of high resistivity.

[0123] Next, opposite region R2 of substrate 10, a structure 50 is made to limit parasitic conduction.

[0124] Such a structure 50 can be, as in the embodiment example of [Fig.8D], in the form of a charge-trapping layer 23 arranged under the masking 13.

[0125] Such a charge-trapping layer 23 rich in crystal defects and / or grain boundaries can in this case be formed for example using at least one implantation and / or amorphization step of the substrate 10. When an amorphization implantation is carried out, the dose and implantation energy can be determined using tools such as SRIM (acronym for "Stopping and Range of Ions in Matter") or TRIM ("Transport of Ions in Matter") which allow modeling of the ion implantation interaction with different materials.

[0126] An amorphization implantation is carried out under the masking 13, for example, using heavy ions formed from Si or Ge, or F, at a dose, for example, of the order of 1015 at / cm2. The thickness of the amorphous material, in particular of silicon rendered amorphous, can be, for example, between 5 nm and 500 nm, preferably between 5 nm and 50 nm.

[0127] A recrystallization anneal is then carried out, with a duration and temperature designed to transform the amorphous semiconductor material into a material rich in crystalline defects and / or grain boundaries. The annealing can advantageously be designed in terms of duration and temperature to allow the transformation of the amorphous semiconductor material into a polycrystalline material. For example, a rapid anneal, i.e., with a duration of less than 10 seconds and advantageously less than 2 seconds at a high temperature, preferably above 800°C but below 1400°C, can be carried out to transform amorphous Si into polycrystalline Si.

[0128] The formation of a polycrystalline semiconductor can also be achieved using laser processing. In particular, a laser with a wavelength between 20 nm and 400 nm with pulse durations typically less than one microsecond and, for example, on the order of one to several hundred nanoseconds can be used.

[0129] Another example involves a layer of crystalline defects created by implantation, for example using He as in the document: “Defect engineering for enhanced Silicon radiofrequency substrates” by M. Perose in Phys. Status Solidi A 2024, 221, 2400215 or by creating deep defects with, for example, metallic species as in the document “Deep Level Impurity Engineered Semi-Insulating Cz-Silicon as Microwave Substrates” by K. Mallik in Proceedings of the 6th European Micro wave Integrated Circuits Conference 2011.

[0130] Then ([Fig.8E]), the assembly is covered with at least one insulating layer and typically with an "inter-level" insulating stack 35. Such an insulating stack 35 may include an etching stop insulating layer 31 for contacts (CESL), for example made of silicon nitride, and with a thickness that may be, for example, between 10 nm and 60 nm.

[0131] This insulating layer 31 is then coated with another insulating layer 33, of the PMD type (for "Pre-Metal Dielectric") typically made of a different insulating material than that of the CESL layer 31. The other insulating layer 33 is, for example, made of silicon oxide and can be provided with a thickness, for example, between 100 nm and 1 pm

[0132] Next, the substrate 10 coated with the insulating stack 35 is assembled with another support having at least one semiconducting layer, preferably made of single-crystal semiconductor material, for example single-crystal silicon.

[0133] The assembly can be carried out by molecular adhesion bonding, also called "direct bonding," where a free face of a surface layer of the support 100 is transferred directly onto a free face of the insulating stack 35. In particular, an oxide-on-oxide type molecular bonding can be provided, the surface layer 114 then being made of silicon oxide, while the insulating stack 35 is also coated with a layer 34 of silicon oxide.

[0134] In the embodiment illustrated in [Fig. 8F], the support 100 attached to the substrate 10 is of the semiconductor-on-insulator type. Such a support 100 is typically formed of a semiconductor support layer 110, for example of silicon, coated with an insulating layer 111 typically of silicon oxide and commonly called a "BOX", the insulating layer 111 being itself coated with a semiconductor layer 112, for example of silicon, in which components and in particular transistors are intended to be at least partially formed.

[0135] The support layer 110 and the insulating layer 111 are then removed. This removal can be carried out in a conventional manner.

[0136] Following such a step, the semiconductor layer 112 is revealed, as in [Fig.8G], in which a second level N2 of components, in particular transistors, is planned.

[0137] According to one possible embodiment, the fabrication of higher-level transistors can be preceded by a step of slicing the semiconductor layer 112 into several distinct portions in which isolated active transistor areas are provided. Such a step is typically carried out by photolithography, followed by etching.

[0138] Thus, in the embodiment shown in [Fig. 8H], transistors T22b and T222 are formed in portions 112a and 112b of the semiconductor layer 112 opposite the RI region of the substrate 10, in which first-level Ni transistors are arranged. A transistor T210 is formed in another portion 112c of the semiconductor layer 112. This other portion 112c is located opposite the R2 region of the substrate 10, in which the localized structure 50 is formed. The transistors T221 and T222 can be, for example, CMOS transistors, while opposite the localized structure 50, transistors of an RF circuit are typically formed, in particular switching transistors, for example, partially split-channel MOS transistors.The fabrication of T221, T222, and T210 transistors typically includes steps such as deposition of a gate dielectric material, etching of these materials, and doping to form source and drain regions.

[0139] The second level N2 of transistors is then covered with one or more insulating layers, for example with an insulating stack 145 comprising an insulating layer 141 for etching stop for contacts (CESL), for example in silicon nitride and a thicker insulating layer 143 and for example in silicon oxide.

[0140] Conductive pads 248a, 248b, 247a, 247b, 249a, 249b are then formed on transistors T221, T222, T210.

[0141] To make such pads, one or more holes are typically formed through the insulating layers 141, 145, 33, 31 and revealing at least one lower level transistor Tno Ni and one or more holes through the insulating layers 141, 145 and revealing at least one higher level transistor T221, T222.

[0142] The filling of holes with a conductive material is typically preceded by at least one silicification step of semiconductor regions exposed by the bottom of the holes or of some of the holes to form contacts 238a, 238b, 237a, 237b, 239a, 239b. Such silicification typically comprises a deposition of metallic material, for example Ni, followed by heat treatment to form silicified areas based on a metal-semiconductor alloy. For example, silicification can be carried out by deposition of Nickel followed by heat treatment, for example, at a temperature of around 400°C.

[0143] To improve the performance of the lower-level transistor(s), the contacts 238a, 238b of the transistor(s) can be advantageously implemented as an alternative. of lower level Nor before the transfer of the semiconductor layer 112 and before the complete formation of the stack 35 on which this semiconductor layer is transferred.

[0144] One or more metallic interconnection levels Mb..., Mk are then formed in a new stack of insulating layers.

[0145] The second N2 transistor level(s) is thus covered with k levels of metallic interconnections, each stage being formed in one or more insulating layers, for example in SiO2, and having one or more metallic lines. Concurrently with the formation of at least one metallic interconnection level, passive components can be produced, and in particular passive components for RF circuits, also called RF components.

[0146] Thus, in the example illustrated in [Fig. 10], a metallic line 1200, for example made of copper and dedicated to an interconnection, and an antenna 1202, also made of copper, are implemented in the same layer. The antenna 1202 is positioned opposite the localized structure 50 to limit parasitic conduction and, in particular, eddy currents that may be generated when this antenna carries an alternating RF signal, for example, with a frequency above 2 GHz. The RF component(s), here for example the antenna 1202, can be provided in a so-called "thick" metallic layer, with a thickness typically of at least 1 µm and, for example, between 0.5 µm and 5 µm.

[0147] An alternative embodiment of the structure 50 localized and in the form of a load-trapping layer is illustrated in Figures 11A-1 IC.

[0148] For this variant, after forming the first Ni level of transistor(s) T110 and covering the whole with at least one insulating layer 31, such as a contact etch stop insulating layer 31 (CESL), for example in silicon nitride, a pass through this insulating layer 31 and the masking is made, so as to reveal the R2 region of the substrate 10 arranged under this masking 13 ([Fig. 11 A]).

[0149] Next, a layer 1123 of amorphous or polycrystalline semiconductor material, for example amorphous silicon or polycrystalline silicon, is deposited ([Fig. 1 IB]) in the passage 32 and so as to cover at least a portion of the R2 region of the substrate 10.

[0150] Next, an etching is carried out ([Fig.l IC]), for example, using SF6, of the layer 1123 of amorphous or polycrystalline semiconductor material so as to retain a portion of the layer 1123 in the passage 32 and opposite the region R2 of the substrate 10. Thus, rather than carrying out the charge trapping layer by means of an implantation to form a polycrystalline material, this layer can be formed by deposition.

[0151] According to another embodiment, the charge-trapping layer can be formed after partially forming the first Ni level of transistor(s) T110 but before forming contacts 238c, 238b, 238a for the first Ni level transistor(s). Thus, in the embodiment shown in [Fig. 12], after forming the collector, emitter, and base regions of transistor(s) T110, a charge-trapping layer 1123 is formed, for example, by polysilicon deposition. Then, after forming, for example, a protective insulating layer 131 on the charge-trapping layer 1123, silicification is carried out on the contacts 238c, 238b, 238a.

[0152] Another variant embodiment of the localized structure 50 is illustrated in [Fig.13].

[0153] For this variant, after forming the first level Ni of transistor(s) Tno and covering the whole with at least one insulating layer 31, such as a contact etch stop insulating layer 31 (CESL), for example in silicon nitride, a passage 32 is made through this insulating layer 31 and the masking, so as to reveal the region R2 of the substrate 10 arranged under this masking 13.

[0154] According to one embodiment, a layer of a dielectric 56 with positive fixed charges or a dielectric 58 with negative fixed charges is first deposited in the passage 32. The dielectric material with positive fixed charges may, for example, be advantageously chosen from the following materials: silicon oxide, in particular SiO2, silicon nitride, silicon oxycarbide. The dielectric material with negative fixed charges may, for example, be based on alumina, in particular Al2O3, or hafnium oxide, in particular HfO2. Separate blocks are then formed in this material 56 or 58.

[0155] Then, another layer of dielectric 58 with negative fixed charges is deposited (in the case where blocks of dielectric material 56 with positive fixed charges have just been formed) or of dielectric 56 with positive fixed charges (in the case where blocks of dielectric material 58 with negative fixed charges have just been formed) and this other layer is etched so as to form other blocks and in this way an alternation of blocks of dielectric 56 with positive fixed charges and blocks of dielectric 58 with negative fixed charges.

[0156] According to another embodiment illustrated in Figures 14A-14B, after forming the transistors in the RI region of the substrate 10, a set of doped areas 51 is formed according to a first type of doping, for example P, using one or more implantations of a region R2 of the substrate 10. Then, another set of doped areas 53 is formed according to a second type of doping different from the first type of doping, for example by implantation of the R2 region of the substrate, the doped areas 51, 53 being distributed so as to make a plurality of juxtaposed PN junctions.

[0157] As previously stated, a particular embodiment of the integrated circuit fabricated on a solid substrate 10 and with Ni, N2 levels of stacked transistors provides one or more back electrodes for controlling transistors of the higher level. In the illustrated embodiment, a back electrode is, for example, formed from a metallic region 99, for example, made of TiN or a doped semiconductor material. It can be fabricated before assembly of the substrate 10 coated with the first Ni level of transistors with a support 100 as described previously and comprising a semiconductor layer 112 for the transistors of the higher N2 level.

[0158] Thus, in the embodiment illustrated in [Fig. 15], the area 99, of the ground plane is formed in the inter-level insulating stack 35, and can be coated with an additional insulating layer 36, for example of silicon oxide, to allow bonding by molecular adhesion with an insulating layer 114 for example of silicon oxide of the support 100, and achieve dielectric separation with the higher level semiconductor layer 112.

Claims

Demands

1. Integrated circuit on a solid semiconductor substrate (10) comprising: - a solid semiconductor substrate (10), in particular a highly resistive substrate, - a lower level (Ni) of transistors comprising, opposite a first region (RJ) of said substrate (10), at least one lower-level transistor (Tu), said at least one lower-level transistor being formed at least partly in a first semiconductor layer (12), the first semiconductor layer (12) belonging to the solid semiconductor substrate and / or being disposed on and in contact with said substrate (10), - an upper level (N2) of transistors having at least one higher-level transistor (T2i) having a channel region in a second semiconductor layer (112) arranged in a stack of layers resting on said substrate (10), said higher-level transistor being disposed opposite a second region (R2) of said solid substrate (10), - a localized structure (50),charge trapping and / or parasitic current blocking structure, formed on or in said second region (R2) of the substrate and configured to limit parasitic conduction in the second region (R2) of the substrate, the localized structure (50) being located below at least one transistor (T21) of said upper level, - one or more metallic interconnection levels (Mi,...,Mk), and - at least one RF component (Ck) such as an antenna or an inductor formed in a given level among said metallic interconnection levels, said RF component (Ck) being arranged opposite the localized charge trapping and / or parasitic current blocking structure (50).

2. Integrated circuit according to claim 1, wherein said at least one lower-level transistor (Tu) is a transistor of a first type, among a bipolar or HEMT type, said higher-level transistor (T2i) being a MOS type transistor, in particular a partially stripped-channel or fully stripped-channel MOS transistor.

3. Integrated circuit according to any one of claims 1 or 2, wherein said higher level transistor (T2i) is a transistor of a switching circuit, the switching circuit being arranged opposite the second region (R2) and preferably not extending opposite the first region.

4. Integrated circuit according to any one of the preceding claims, wherein the localized structure (50) comprises at least one element among: - a layer of semiconductor material having implant defects; - a layer (23) of amorphous or polycrystalline semiconductor material; - a set of junctions formed of an alternation of doped areas (51) according to a first type of doping, N or P and doped areas (53) according to a second type of doping, P or N, different from the first type of doping; - a heterogeneous dielectric region formed of an alternation of blocks of dielectric material (56) with fixed positive charges and blocks of dielectric material (58) with fixed negative charges.

5. Integrated circuit according to any one of claims 1 to 4, wherein at least one second higher-level transistor (T24) (N2) is arranged opposite the first region (Ri) and includes a back electrode, in particular a ground plane (99), the back electrode being arranged in said stack between the first region (Ri) and said second higher-level transistor (T24) (N2).

6. A method for manufacturing an integrated circuit according to any one of the preceding claims comprising steps consisting of: - providing a solid substrate (10), in particular a highly resistive (HR) substrate, and forming opposite a first region (RJ) of said solid substrate, at least one lower-level transistor (Tu), the lower-level transistor having a channel in a semiconductor layer (12) of the substrate and / or disposed in contact with said substrate (10), - forming opposite a second region (R2) of said substrate (10) distinct from the first region (Ri) a localized charge-trapping and / or parasitic current-blocking structure (50) to limit parasitic conduction in the second region (R2), - to coat said lower level (Ni) and said localized structure (50) with at least one insulating layer (31, 33; 35) called "inter-levels", - to assemble, in particular by molecular adhesion bonding, a support (100) on said inter-level insulating layer (31, 33; 35), said support (100) having a semiconducting layer (112) called "second semiconducting layer", - to form at least one higher-level transistor (T2i T22T23T24, T210.T222.T221) from said second semiconducting layer (112), said higher-level transistor having a channel region in the second semiconducting layer (112) and being arranged opposite the second region (R2) of said substrate (10).

7. Method according to claim 6, wherein the formation of said at least one lower-level transistor (Tu) comprises one or more steps carried out before the realization of said localized structure (50).

8. Method according to any one of claims 6 or 7, the method comprises making a masking (13) on the second region (12) to protect the second region (R2), said masking (13) being made so as to retain an opening (14) opposite the first region (Ri), the transistor (Tu) being at least partially formed in said opening (14).

9. A method according to any one of claims 6 to 8, comprising the formation of at least one layer (31) covering the lower-level transistor (Tu) and a passage (32) through said at least one layer (31) covering the lower-level transistor (Tu), so as to expose said second region (R2), the localized structure (50) then being formed through the passage (32) on or in at least a portion of the second region (R2) exposed by the passage (32).

10. A method according to claim 9, wherein the formation of the localized structure (50) comprises the steps of: - depositing a layer (1123) of amorphous or polycrystalline semiconductor material in said passage (32) so as to cover said at least a portion of said second region (R2), and then - etching the layer (1123) of amorphous or polycrystalline semiconductor material so as to retain at least a portion of amorphous or polycrystalline semiconductor material opposite the second region (R2).

11. A method according to claim 9, wherein the localized structure (50) comprises a heterogeneous dielectric region formed of an alternation of blocks of a dielectric material (56) with positive fixed charges and blocks of a second dielectric material (58) with negative fixed charges, the formation of the localized structure (50) comprising the steps of: - deposition in said passage (32) of a first dielectric material, with positive fixed charges or with negative fixed charges, then - etching said first dielectric material so as to form blocks based on the first dielectric material, then - deposition of a second dielectric material to form blocks based on the second dielectric material, the second dielectric material being with positive fixed charges when the first dielectric material is with negative fixed charges or being with negative fixed charges when the first dielectric material is with positive fixed charges.

12. A method according to claim 9, wherein the formation of the localized structure (50) comprises the realization of a plurality of juxtaposed junctions, formed of an alternation of areas doped according to a doping of a first type, in particular P or N and areas doped according to a doping of a second type, in particular N or P and different from the first type, the localized structure being formed by successive implantations of the second region through said passage (32).

13. A method according to claim 8, wherein the formation of the localized structure (50) comprises an implantation leading to the formation of a layer rich in crystalline defects of an area of ​​the substrate arranged under said masking (13).

14. A method according to any one of claims 6 to 13, comprising prior to the assembly between the substrate (10) and the support (100), and after coating said lower level (Ni) and said localized structure (50) with at least one insulating layer (31, 33; 35) referred to as "inter-level", - forming one or more ground plane zones (99A) on said inter-level insulating layer, then, - to coat said one or more zones (99A) of ground plane with at least one insulating bonding layer (36), the assembly of the substrate and the support being then carried out by molecular adhesion bonding of the insulating bonding layer (36) with the support (100) assembled on said inter-level insulating layer (31, 33; 35).

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