Patterning method and patterning system for semiconductor processes

Abstract

This application discloses a patterning method and a patterning system for semiconductor processes. A patterning method for semiconductor processes includes: forming a first differential pattern on a target area using a double-layer photoresist photolithography process; etching a second hard mask layer using the first differential pattern as a mask to obtain the first pattern; forming a second differential pattern on the target area where the first pattern is formed using a double-layer photoresist photolithography process; etching the first pattern using the second differential pattern as a mask to obtain the second pattern; depositing a low-temperature oxide layer at a predetermined location in the target area where the second pattern is formed using photolithography and etching processes; etching the first hard mask layer using the second pattern and the low-temperature oxide layer as masks to form a hard mask pattern; etching a low-k dielectric layer using the hard mask pattern as a mask; and depositing a metal material on the etched low-k dielectric layer and performing chemical mechanical polishing to form a metal interconnect layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor microstructure fabrication technology, and more specifically to a patterning method and patterning system for semiconductor processes. Background Technology

[0002] The rapid development of integrated circuits relies on the development of related manufacturing processes—photolithography technology, which is the highest precision processing technology achievable to date.

[0003] In principle, photolithography refers to the technique of transferring a pattern from a photomask to a substrate using a photoresist (also known as a photoresist film) under illumination. The main process is as follows: First, ultraviolet light passes through the photomask and irradiates the surface of the substrate coated with a thin film of photoresist, causing a chemical reaction in the exposed areas of the photoresist. Then, development technology dissolves and removes the photoresist in the exposed or unexposed areas, allowing the pattern on the photomask to be copied onto the photoresist film. Finally, etching or deposition techniques are used to transfer the pattern onto the substrate. Photoresists can be mainly divided into positive and negative photoresists. Positive photoresists have the following characteristics: their exposed areas undergo a photochemical reaction and dissolve in the developer, while the unexposed areas are insoluble in the developer. Negative photoresists have the following characteristics: their exposed areas are insoluble in the developer due to cross-linking curing or a photochemical reaction, while the unexposed areas are soluble in the developer.

[0004] Photolithography technology is mainly divided into optical lithography based on the exposure source. Common light sources include ultraviolet (UV), deep ultraviolet (DUV), extreme ultraviolet (EUV) light sources, and particle beam lithography. Common particle beam lithography mainly includes X-ray, electron beam, and ion beam lithography.

[0005] Typically, in optical lithography, UV lithography can only achieve a pattern resolution of about one micrometer. While DUV and EUV lithography can achieve higher resolutions, they are expensive. In addition, in particle beam lithography, electron beam lithography and focused ion beam lithography can also improve the resolution to some extent, but they require time-consuming and multi-cycle writing processes, which greatly reduces work efficiency. Summary of the Invention

[0006] It should be understood that the above general description and the following detailed description of the invention are exemplary and illustrative, and are intended to provide further explanation of the invention as described in the claims.

[0007] According to a first aspect of the present invention, a patterning method for semiconductor processes is provided, the method comprising the following steps: (1) forming a first differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a substrate target layer and a low-k dielectric layer, a first hard mask layer, and a second hard mask layer located on the substrate target layer; (2) etching the second hard mask layer using the first differential pattern as a mask to obtain a first pattern; (3) forming a second differential pattern on the target region having the first pattern using a double-layer photoresist photolithography process; (4) etching the second hard mask layer using the second differential pattern as a mask to obtain a first pattern; (5) Using photolithography and etching processes, a low-temperature oxide layer is deposited at a predetermined location in the target area where the second pattern is formed, the predetermined location corresponding to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect; (6) Using the second pattern and the low-temperature oxide layer as a mask, the first hard mask layer is etched to form a hard mask pattern; (7) Using the hard mask pattern as a mask, the low-k dielectric layer is etched; and (8) A metal material is deposited on the etched low-k dielectric layer and chemically mechanically polished to form a metal interconnect layer.

[0008] Further, step (5) includes performing the following steps multiple times: applying a coating on the second pattern using photolithography and etching processes and etching the coating at a predetermined location; depositing a low-temperature oxide material on the coating; and etching back the low-temperature oxide material and removing the coating.

[0009] According to a second aspect of the present invention, a patterning method for semiconductor processes is provided, the method comprising the following steps: (1) using photolithography and etching processes to implant boron ions into a predetermined location of an amorphous silicon layer in a target region to form implanted amorphous silicon portions, the predetermined location corresponding to the two ends of the extension direction of a metal interconnect in a metal interconnect layer and the break point of the metal interconnect, the target region comprising a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer and the amorphous silicon layer located on the substrate target layer; (2) removing the unimplanted amorphous silicon portions in the amorphous silicon layer, retaining the implanted amorphous silicon portions; (3) using a double-layer photoresist photolithography process to form a first differential pattern on the target region where the implanted amorphous silicon portions are formed; (4) using the first differential pattern as a mask. (5) Etching the second hard mask layer to obtain a first pattern, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is exempt from etching; (6) Forming a second differential pattern on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (7) Etching the first pattern using the second differential pattern as a mask to obtain a second pattern, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempt from etching; (8) Etching the first hard mask layer using the second pattern and the implanted amorphous silicon portion as masks to form a hard mask pattern; (9) Etching the low-k dielectric layer using the hard mask pattern as a mask; and (10) Depositing a metal material on the etched low-k dielectric layer and performing chemical mechanical polishing to form a metal interconnect layer.

[0010] Further, step (1) includes performing the following steps multiple times: applying a coating on the amorphous silicon layer using photolithography and etching processes and etching the coating at a predetermined location; performing boron ion implantation on the target area where the coating is formed to form an implanted amorphous silicon portion; and removing the coating.

[0011] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (A1) forming a negative photoresist layer on the target area using negative photoresist, and forming a positive photoresist layer on the negative photoresist layer using positive photoresist; (A2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (A3) developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (A4) developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0012] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (B1) forming a positive photoresist layer on the target area using positive photoresist, and forming a negative photoresist layer on the positive photoresist layer using negative photoresist; (B2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (B3) developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist outside the negative pattern area; (B4) developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0013] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (C1) forming a negative photoresist layer on the target area using negative photoresist, forming a spacer layer on the negative photoresist layer, and forming a positive photoresist layer on the spacer layer using positive photoresist; (C2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer respectively, wherein the positive pattern area is larger than the negative pattern area; (C3) developing the positive photoresist layer with a positive photoresist developer to remove... (C4) Develop the spacer layer with a spacer developer, or etch the spacer layer using the pattern of the developed positive resist layer as an etch resist mask, so that the pattern of the spacer layer is consistent with the pattern of the developed positive resist layer; (C5) Develop the negative resist layer with a negative resist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0014] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (D1) forming a positive photoresist layer on the target area using a positive photoresist, forming a spacer layer on the positive photoresist layer, and forming a negative photoresist layer on the spacer layer using a negative photoresist; (D2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (D3) developing the negative photoresist layer with a negative photoresist developer to remove... (D4) The negative photoresist outside the negative pattern area; (D5) The spacer layer is developed with a spacer developer, or the spacer layer is etched using the pattern of the developed negative photoresist layer as an etch resist mask, so that the pattern of the spacer layer is consistent with the pattern of the developed negative photoresist layer; (D6) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0015] Further, patterning the negative resist layer and the positive resist layer to form positive and negative pattern areas on the positive and negative resist layers respectively includes: exposing the positive and negative resist layers under an exposure source using a photomask carrying a template pattern or by focused direct writing, thereby forming positive and negative pattern areas on the positive and negative resist layers respectively.

[0016] Furthermore, using projection exposure, the positive resist layer and the negative resist layer are exposed under an exposure source through a photomask carrying the template pattern; or using masking exposure, the positive resist layer and the negative resist layer are exposed under an exposure source through a photomask carrying the template pattern; or using reflective exposure, the positive resist layer and the negative resist layer are exposed under an exposure source by reflection from a photomask carrying the template pattern.

[0017] Furthermore, the focused direct writing includes ultraviolet light direct writing, deep ultraviolet light direct writing, extreme ultraviolet light direct writing, ion beam direct writing, electron beam direct writing, or X-ray direct writing.

[0018] According to a third aspect of the present invention, a patterning system for semiconductor processes is provided, comprising a first differential pattern forming section, a first pattern forming section, a second differential pattern forming section, a second pattern forming section, a low-temperature oxide layer deposition section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section. The patterning system is used to perform the following steps: (1) using the first differential pattern forming section, forming a first differential pattern on a target region using a double-layer photoresist photolithography process, wherein the target region is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer, and a second hard mask layer located on the substrate target layer; (2) using the first pattern forming section, using the first differential pattern as a mask, etching the second hard mask layer to obtain a first pattern; (3) using the second differential pattern forming section, forming a pattern on the target region where the first pattern is formed using a double-layer photoresist photolithography process. (4) Using the second pattern forming section, the first pattern is etched using the second difference pattern as a mask to obtain the second pattern; (5) Using the low-temperature oxide layer deposition section, a low-temperature oxide layer is deposited at a predetermined position in the target area where the second pattern is formed using photolithography and etching processes, the predetermined position corresponding to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect; (6) Using the first hard mask layer etching section, the first hard mask layer is etched using the second pattern and the low-temperature oxide layer as masks to form a hard mask pattern; (7) Using the low-k dielectric layer etching section, the low-k dielectric layer is etched using the hard mask pattern as a mask; and (8) Using the metal material deposition section, a metal material is deposited on the etched low-k dielectric layer and chemically mechanically polished to form a metal interconnect layer.

[0019] According to a fourth aspect of the present invention, a patterning system for semiconductor processing is provided, comprising a dicing and implantation section, an amorphous silicon portion removal section, a first differential pattern forming section, a first pattern forming section, a second differential pattern forming section, a second pattern forming section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section, wherein the patterning system is used to perform the following steps:

[0020] (1) Using the cutting and implantation unit, boron ions are implanted into the amorphous silicon layer at a predetermined location in the target region using photolithography and etching processes to form implanted amorphous silicon portions. The predetermined locations correspond to the two ends of the extension direction of the metal interconnects in the metal interconnect layer and the breakpoint of the metal interconnects. The target region consists of a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer, and the amorphous silicon layer located on the substrate target layer. (2) Using the amorphous silicon portion removal unit, the unimplanted amorphous silicon portions in the amorphous silicon layer are removed, while the implanted amorphous silicon portions are retained. (3) Using the first differential pattern forming unit, a first differential pattern is formed on the target region where the implanted amorphous silicon portions are formed using a double-layer photoresist photolithography process. (4) Using the first pattern forming unit, the second hard mask layer is etched using the first differential pattern as a mask to obtain a first pattern, wherein the first differential pattern is used as a mask. (5) Using the second differential patterning unit, a second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (6) Using the second patterning unit, the first pattern is etched using the second differential pattern as a mask to obtain the second pattern, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempted from etching; (7) Using the first hard mask layer etching unit, the first hard mask layer is etched using the second pattern and the implanted amorphous silicon portion as masks to form a hard mask pattern; (8) Using the low-k dielectric layer etching unit, the low-k dielectric layer is etched using the hard mask pattern as a mask; and (9) Using the metal material deposition unit, a metal material is deposited on the etched low-k dielectric layer and chemically mechanically polished to form a metal interconnect layer.

[0021] According to a fifth aspect of the present invention, a control method for a patterning system for semiconductor processes is provided, for controlling the aforementioned patterning system for semiconductor processes to perform various steps.

[0022] According to a sixth aspect of the present invention, a computer device is provided, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the control method described above for a patterning system for semiconductor processes. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of the invention; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the invention and, together with this specification, serve to explain the principles of the invention. In the drawings:

[0024] Figure 1 This is a schematic diagram of the SAQP process in the prior art.

[0025] Figure 2 This is a schematic flowchart illustrating a patterning method for manufacturing metal interconnect layers for semiconductor processes, which utilizes a double-layer photoresist photolithography process combined with a dicing process utilizing a low-temperature oxide deposition process, according to an embodiment of the present disclosure.

[0026] Figures 3A-3D This is a schematic flowchart illustrating the formation of a differential pattern on a target area using a double-layer photoresist photolithography process according to an embodiment of the present disclosure.

[0027] Figure 4 This is a schematic flowchart illustrating a patterning method for manufacturing metal interconnect layers for semiconductor processes, which utilizes a double-layer photoresist photolithography process combined with a dicing process utilizing boron ion implantation, according to an embodiment of the present disclosure. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0029] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatial relative terms are intended to include different orientations of the device used or operated in addition to those shown in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features.

[0030] Unless otherwise specified, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms should be understood to have the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formalized manner, unless explicitly stated otherwise herein.

[0031] In the semiconductor field, FinFET (Fin Field-Effect Transistor) is a novel type of complementary metal-oxide-semiconductor transistor. After semiconductor components are formed, metal wiring is required to create connections between them. As component sizes continue to shrink, the size of these metal interconnects needs to be reduced to further increase device density.

[0032] In the formation of FinFETs at 7nm and below, without the support of EUV lithography, existing solutions typically use SAQP (Self-Aligned Quadruple Patterning) combined with dicing to form the metal interconnect layer.

[0033] Figure 1 This is a schematic diagram of the SAQP process in the prior art. First, in step 1A, a first hard mask layer 120, a first spindle layer 130, a second hard mask layer 140, a second spindle layer 150, a SOC (Spin-On Carbon) layer 160, and an anti-reflective coating 170 are sequentially coated on the substrate material 110. Photoresist is then patterned on the anti-reflective coating 170 to form a first pattern 182. Next, in step 2A, using the first pattern 182 as a mask, the anti-reflective coating 170, the SOC layer 160, and the second spindle layer 150 are etched to form the second spindle 152. Then, in step 3A, a spacer layer 190 is deposited on the second spindle 152. In step 4A, the horizontal portion of the spacer layer 190 is etched, retaining the vertical portion 192 of the spacer layer 190 near the sidewall of the second spindle 152. In step 5A, the second spindle 152 is removed, retaining the vertical portion 192 of the spacer layer 190. Next, in step 6A, using the vertical portion 192 as a mask, the second hard mask layer 140 and the first mandrel layer 130 are etched to form the second hard mask pattern 142 and the first mandrel 132. In step 7A, the vertical portion 192 and the second hard mask pattern 142 are removed, leaving the first mandrel 132. Then, in step 8A, the deposition of the second spacer layer 194 is performed. Finally, in step 9A, the horizontal portion of the second spacer layer 194 is etched, the second vertical portion 196 of the second spacer layer 194 near the sidewall of the first mandrel 132 is retained, and the first mandrel 132 is removed to form a mask for the metal interconnect layer.

[0034] However, SAQP technology involves multiple thin film deposition and etching processes, especially the ALD (Atomic Layer Deposition) process involved in the deposition of the spacer layer, which leads to high costs. Furthermore, the multiple etching steps require precise control, making the process quite complex.

[0035] In addition, existing solutions also use DUV combined with LELE (LITHO-ETCH-LITHO-ETCH; photolithography-etching-photolithography-etching) technology. However, this technology requires more than four LE (photolithography-etching) processes, which makes it difficult to control the overlay error. At the same time, the required key dimensions are also difficult to achieve through etching miniaturization.

[0036] Therefore, this disclosure provides a patterning method for semiconductor processes to form a metal interconnect layer.

[0037] <First double-layer photoresist lithography process + first etching process + second double-layer photoresist lithography process + second etching process + dicing process using low-temperature oxide deposition>

[0038] The patterning method for semiconductor processes disclosed herein includes the following steps:

[0039] (1) A first differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer and a second hard mask layer located on the substrate target layer.

[0040] (2) Using the first difference pattern as a mask, the second hard mask layer is etched to obtain the first pattern;

[0041] (3) A second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process;

[0042] (4) Using the second difference pattern as a mask, the first pattern is etched to obtain the second pattern;

[0043] (5) Using photolithography and etching processes, a low-temperature oxide layer is deposited at a predetermined location in the target area where the second pattern is formed, the predetermined location corresponding to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect.

[0044] (6) Using the second pattern and the low-temperature oxide layer as a mask, the first hard mask layer is etched to form a hard mask pattern;

[0045] (7) Using the hard mask pattern as a mask, the low-k dielectric layer is etched; and

[0046] (8) Deposit a metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

[0047] In some embodiments, step (5) includes performing the following steps multiple times:

[0048] Using photolithography and etching processes, a coating is applied to the second pattern and the coating is etched at the intended location;

[0049] Depositing a low-temperature oxide material on the coating; and

[0050] The low-temperature oxide material is etched back and the coating is removed.

[0051] Figure 2 This is a schematic flowchart illustrating a patterning method for manufacturing metal interconnect layers for semiconductor processes, which utilizes a double-layer photoresist photolithography process combined with a dicing process utilizing a low-temperature oxide deposition process, according to an embodiment of the present disclosure.

[0052] <First Double-Layer Photoresist Lithography Process>

[0053] In step 1B, a target region is prepared. The target region may consist of a substrate target layer 210 and a low-k dielectric layer 220, a first hard mask layer 230, and a second hard mask layer 240 located on the substrate target layer 210. In some embodiments, the target region may further include a first coating layer 250 and a second coating layer 260 located on the second hard mask layer 240. Then, a first differential pattern consisting of a first photoresist layer 272 and a second photoresist layer 274 is formed on the target region using a double-layer photoresist photolithography process (corresponding to the formation of a first differential pattern on the target region using a double-layer photoresist photolithography process, wherein the target region consists of a substrate target layer and a low-k dielectric layer, a first hard mask layer, and a second hard mask layer located on the substrate target layer). See below. Figures 3A-3D The process of forming a differential pattern using a double-layer photoresist photolithography process is further described. Although a first differential pattern consisting of a first photoresist layer 272 and a second photoresist layer 274 is used as an example here, other differential patterns can be formed in other embodiments.

[0054] As an example, the substrate target layer 210 may be a front layer, the first coating 250 may be a SOC layer, and the second coating 260 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the present invention is not limited thereto. Alternatively, the target area may not include the first coating 250 and the second coating 260 described above, and is not limited to the above example.

[0055] <First Etching Process>

[0056] In step 2B, the target area is etched using the first differential pattern as a mask until the etching stops at the first hard mask layer 230, so as to form the first pattern 242 in the second hard mask layer 240 (corresponding to etching the second hard mask layer using the first differential pattern as a mask to obtain the first pattern). The top of the figure is a top view of the formed structure, and the bottom of the figure is a cross-sectional view along the dashed line.

[0057] <Second Double-Layer Photoresist Lithography Process>

[0058] In step 3B, a third coating layer 252 and a fourth coating layer 262 are applied to the first pattern 242. Then, a second differential pattern consisting of a third photoresist layer 276 and a fourth photoresist layer 278 is formed on the target area using a double-layer photoresist photolithography process (corresponding to the formation of a second differential pattern on the target area where the first pattern is formed using a double-layer photoresist photolithography process). See below. Figures 3A-3D The process of forming a differential pattern using a double-layer photoresist photolithography process is further described. Although a second differential pattern consisting of a third photoresist layer 276 and a fourth photoresist layer 278 is used as an example here, other differential patterns can be formed in other embodiments.

[0059] As an example, the third coating 252 may be a SOC layer, and the fourth coating 262 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the invention is not limited thereto. Alternatively, the steps of applying the third and fourth coatings on the first pattern may be omitted, and the invention is not limited to the above example.

[0060] <Second Etching Process>

[0061] In step 4B, the target area is etched using the second differential pattern as a mask until the etching stops at the first hard mask layer 230, to form the second pattern 244 in the first pattern 242 (corresponding to etching the first pattern using the second differential pattern as a mask to obtain the second pattern). The top of the figure is a top view of the formed structure, and the bottom of the figure is a cross-sectional view along the dashed line.

[0062] Cutting process using low-temperature oxide deposition technology

[0063] In step 5B, LTO (Low Temperature Oxide) is deposited within a portion of the gaps in the second pattern 244 using photolithography and etching processes to form island-like structures. LTO is also deposited at both ends of the extension direction of the second pattern 244 (corresponding to the deposition of low temperature oxide layers at predetermined locations in the target area where the second pattern is formed using photolithography and etching processes, the predetermined locations corresponding to the ends of the extension direction of the metal interconnects in the metal interconnect layer and the breakpoints of the metal interconnects). Each island-like structure extends in a direction perpendicular to the extension direction of the second pattern 244, connecting at least two adjacent protrusion patterns in the second pattern 244, thereby enabling the final metal interconnect layer to produce breakpoints in the extension direction of the second pattern 244 as needed.

[0064] In some embodiments, step 5B includes steps 5B-1 to 5B-3.

[0065] In step 5B-1, a fifth coating 280, an anti-reflective coating, and photoresist are coated on the second pattern 244. The photoresist is then exposed and developed according to wiring requirements to form a photolithographic pattern. The photolithographic pattern is then used as a mask to etch the anti-reflective coating and the fifth coating 280 to transfer the pattern to the fifth coating 280 (corresponding to coating the second pattern and etching the coating at the intended location using photolithography and etching processes). As an example, the fifth coating 280 may be a SOC layer, but the invention is not limited thereto. Alternatively, the step of coating the anti-reflective coating on the second pattern may be omitted, and the invention is not limited to the above example.

[0066] In step 5B-2, LTO material 290 is deposited on the fifth coating 280 (corresponding to the deposition of low-temperature oxide material on the coating).

[0067] In step 5B-3, the LTO material 290 is etched back and the fifth coating 280 is removed to form the LTO layer 292 (corresponding to etching back and removing the coating on the low-temperature oxide material). Although the island structures shown in the figure are located in the center and there are three in number, it should be understood that the location of the island structures is not limited to the center, and the location and number of island structures can be set as needed.

[0068] Then, steps 5B-1 to 5B-3 are repeated multiple times until an island-like structure is formed at the desired location and LTO material is deposited at both ends of the extension direction of the second pattern. It should be understood that the LTO layer formed by performing step 5B once corresponds only to a portion of the desired location, and the LTO layers formed by performing step 5B multiple times collectively correspond to the desired location.

[0069] Next, in step 6B, the first hard mask layer 230 is etched using the second pattern 244 and the LTO layer 292 as masks to form the first hard mask pattern 232 (corresponding to etching the first hard mask layer using the second pattern and the low-temperature oxide layer as masks to form the hard mask pattern). In step 7B, the low-k dielectric layer 220 is etched using the first hard mask pattern 232 as a mask to obtain the etched low-k dielectric layer 222 (corresponding to etching the low-k dielectric layer using the hard mask pattern as a mask).

[0070] Finally, in step 8B, a metal material is deposited on the etched low-k dielectric layer 222 and chemically mechanically polished to form a metal interconnect layer (corresponding to depositing a metal material on the etched low-k dielectric layer and chemically mechanically polishing to form a metal interconnect layer).

[0071] Figures 3A-3DThis is a schematic flowchart illustrating the formation of a differential pattern on a target area using a double-layer photoresist photolithography process according to an embodiment of the present disclosure.

[0072]

[0073] Figure 3A This is a schematic diagram of a two-layer photoresist photolithography process, where the negative resist is applied first, followed by the positive resist. In the accompanying figures, identical or equivalent parts are labeled with the same symbols for explanation.

[0074] First, in step 1C, a layer of negative photoresist 340A (i.e., negative resist layer) is spin-coated onto the target area and dried. Then, a layer of positive photoresist 350A (i.e., positive resist layer) is spin-coated onto the negative photoresist 340A and dried (corresponding to forming a negative resist layer on the target area using negative photoresist and forming a positive resist layer on the negative resist layer using positive photoresist).

[0075] The target area is composed of a substrate target layer 310A and a substrate coating (first coating 320A and second coating 330A) located on the substrate target layer 310A. However, the present invention is not limited to this, and the first coating 320A and the second coating 330A may be omitted depending on the circumstances. Furthermore, as the first coating 320A, a hard mask SOC may be used, and as the second coating 330A, an anti-reflective coating SiARC may be used. However, the present invention is not limited to this.

[0076] Following step 1C, in step 2C, under an exposure source, two layers of photoresist 340A and 350A are exposed using a photomask carrying a template pattern or by focused direct writing (an example of photomask 360A is shown in the figure). After exposure, exposure patterns 342A and 352A (i.e., negative pattern area and positive pattern area) of different sizes are formed on the negative photoresist 340A and positive photoresist 350A, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area).

[0077] The exposure source includes ultraviolet light, deep ultraviolet light, extreme ultraviolet light, ion beam, electron beam, or X-rays. As an example, the wavelength of the exposure source can be 1-500 nm, and the drying temperature after exposure can be 30-300 °C. Further, the wavelength of the exposure source can be 350-400 nm, and the drying temperature after exposure can be 95-105 °C.

[0078] Focused direct writing includes ultraviolet light direct writing, deep ultraviolet light direct writing, extreme ultraviolet light direct writing, ion beam direct writing, electron beam direct writing, or X-ray direct writing. As an example, the feature linewidth or feature size of the template pattern can be 2 nm to 1000 μm. Further, the feature linewidth or feature size of the template pattern can be 2 nm to 1 μm.

[0079] After step 2C, in step 3C, the positive photoresist is developed with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern area); then, in step 4C, the negative photoresist is controlled to develop with a negative photoresist developer, washing away only the edge portion of the exposure pattern 342A on the negative photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern). Therefore, the embodiments of this disclosure utilize positive and negative photoresists to produce different development results under the same illumination conditions. The positive photoresist exposure area is removed after development to form a groove of size CD1, while the negative photoresist exposure area is retained after development to form a protrusion of size CD2. By utilizing the difference between CD1 and CD2, a narrow groove with a size of (CD1-CD2) / 2 can be formed in a self-aligned manner, thus exceeding the original photolithography resolution and achieving pattern multiplication.

[0080] Therefore, the previously described method can be used in steps 1B and 3B to Figure 3A The resulting differential pattern is used as a mask for etching, thereby forming grooves on the coating in the target area for forming a metal interconnect layer.

[0081]

[0082] Figure 3B This is a schematic diagram of the double-layer photoresist photolithography process, which involves applying positive resist first and then negative resist.

[0083] The above description illustrates an example of using a double-layer photoresist lithography process (negative resist followed by positive resist) to form bumps, thereby doubling the line density; however, the present invention is not limited thereto. The present invention can also employ a double-layer photoresist lithography process (positive resist followed by negative resist) to form grooves on the coating in the target area.

[0084] Figure 3B In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0085] First, in step 1D, a layer of positive photoresist 350B (i.e., positive photoresist layer) is spin-coated onto the target area and dried. Then, a layer of negative photoresist 340B (i.e., negative photoresist layer) that matches the positive photoresist 350B is spin-coated onto the positive photoresist 350B and dried (corresponding to forming a positive photoresist layer on the target area using positive photoresist and forming a negative photoresist layer on the positive photoresist layer using negative photoresist).

[0086] The target area is composed of a substrate target layer 310B and a substrate coating (first coating 320B and second coating 330B) located on the substrate target layer 310B. However, the present invention is not limited to this, and the first coating 320B and the second coating 330B may be omitted depending on the circumstances. Furthermore, as the first coating 320B, a hard mask SOC may be used, and as the second coating 330B, an anti-reflective coating SiARC may be used, but the present invention is not limited to this.

[0087] Following step 1D, in step 2D, under an exposure source, two layers of photoresist 340B and 350B are exposed using a photomask carrying a template pattern or by focused direct writing (an example of photomask 360B is shown in the figure). After exposure, exposure patterns 342B and 352B of different sizes (i.e., negative pattern area and positive pattern area) are formed on the negative photoresist 340B and positive photoresist 350B, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area).

[0088] Following step 2D, in step 3D, the negative photoresist is developed using a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist outside the negative pattern area); then, in step 4D, the positive photoresist is controlled to develop using a positive photoresist developer, washing away only the edge portion of the exposed pattern 352B on the positive photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist at the edge portion of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern). Therefore, the embodiments of this disclosure utilize positive and negative photoresists to produce different development results under the same illumination conditions. The negative photoresist exposure area is retained after development, forming a groove of size CD1. The positive photoresist exposure area is removed only at the edge after development, forming a protrusion of size CD2. By utilizing the difference between CD1 and CD2, a narrow groove can be formed in self-alignment with a size of (CD1-CD2) / 2. Therefore, it can exceed the original photolithography resolution and achieve pattern multiplication.

[0089] Therefore, the previously described method can be used in steps 1B and 3B to Figure 3B The resulting differential pattern is used as a mask for etching, thereby forming grooves on the coating in the target area for forming a metal interconnect layer.

[0090] <A two-layer photoresist lithography process consisting of a negative resist layer, a spacer layer, and a positive resist layer>

[0091] Figure 3C This is a schematic diagram of a two-layer photoresist photolithography process consisting of a negative resist layer, a spacer layer, and a positive resist layer.

[0092] The above description illustrates examples of using a double-layer photoresist lithography process with a negative resist followed by a positive resist, and a double-layer photoresist lithography process with a positive resist followed by a negative resist, to form bumps and thus double the line density. However, the present invention is not limited to these examples. The present invention can also use a double-layer photoresist lithography process with a negative resist followed by a spacer and then a positive resist to form grooves on the coating in the target area.

[0093] Figure 3C In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0094] First, in step 1E, a layer of negative photoresist 340C (i.e., negative resist layer) is spin-coated onto the target area and dried; then, a spacer film 370C is coated onto the negative photoresist 340C; then, a layer of positive photoresist 350C (i.e., positive resist layer) that matches the negative photoresist 340C is spin-coated onto the spacer film 370C and dried (corresponding to forming a negative resist layer on the target area using negative photoresist, forming a spacer layer on the negative resist layer, and forming a positive resist layer on the spacer layer using positive photoresist).

[0095] The target area is composed of a substrate target layer 310C and a substrate coating (first coating 320C and second coating 330C) located on the substrate target layer 310C. However, the present invention is not limited to this, and the first coating 320C and the second coating 330C may be omitted depending on the circumstances. Furthermore, as the first coating 320C, a hard mask SOC may be used, and as the second coating 330C, an anti-reflective coating SiARC may be used, but the present invention is not limited to this.

[0096] Following step 1E, under an exposure source, two layers of photoresist 340C and 350C are exposed using a photomask carrying a template pattern or by focused direct writing. After exposure, exposure patterns (i.e., negative pattern areas and positive pattern areas) of different sizes are formed on the negative photoresist 340C and the positive photoresist 350C, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area). This exposure process is similar to... Figure 3A Step 2C is similar, so repeated explanations are omitted here.

[0097] After exposure, in step 2E, the positive photoresist is developed using a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist from the positive pattern area); then, in step 3E, the interlayer film is developed using a spacer film developer, or the interlayer film is etched using the pattern of the developed positive photoresist as an etch resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with an interlayer developer, or etching the interlayer using the pattern of the developed positive photoresist layer as an etch resist mask). Etching is performed to make the pattern of the spacer layer consistent with the pattern of the developed positive photoresist layer; then, in step 4E, the negative photoresist is controlled to develop with negative photoresist developer, washing away only the edge portion of the exposed pattern on the negative photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the negative photoresist layer with negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern).

[0098] By coating a separator film between two layers of photoresist, the dissolution of the two layers of photoresist during the coating process can be avoided or reduced.

[0099] Therefore, the previously described method can be used in steps 1B and 3B to Figure 3C The resulting differential pattern is used as a mask for etching, thereby forming grooves on the coating in the target area for forming a metal interconnect layer.

[0100] <A two-layer photoresist lithography process consisting of a positive resist layer, a spacer layer, and a negative resist layer>

[0101] Figure 3D This is a schematic diagram of a two-layer photoresist photolithography process consisting of a positive resist layer, a spacer layer, and a negative resist layer.

[0102] The above description illustrates examples of using a double-layer photoresist lithography process (negative resist followed by positive resist), a double-layer photoresist lithography process (positive resist followed by negative resist), and a double-layer photoresist lithography process (negative resist + spacer + positive resist) to form bumps and thus double the line density. However, the present invention is not limited to these methods. The present invention can also use a double-layer photoresist lithography process (positive resist + spacer + negative resist) to form grooves on the coating in the target area.

[0103] Figure 3D In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0104] First, in step 1F, a layer of positive photoresist 350D (i.e., positive resist layer) is spin-coated onto the target area and dried; then, a spacer film 370D is coated onto the positive photoresist 350D; then, a layer of negative photoresist 340D (i.e., negative resist layer) that matches the positive photoresist 350D is spin-coated onto the spacer film 370D and dried (corresponding to forming a positive resist layer on the target area using positive photoresist, forming a spacer layer on the positive resist layer, and forming a negative resist layer on the spacer layer using negative photoresist).

[0105] The target area is composed of a substrate target layer 310D and a substrate coating layer (first coating layer 320D and second coating layer 330D) located on the substrate target layer 310D. However, the present invention is not limited to this, and the first coating layer 320D and the second coating layer 330D may be omitted depending on the circumstances. Furthermore, a hard mask SOC may be used as the first coating layer 320D, and an anti-reflective coating SiARC may be used as the second coating layer 330D, but the present invention is not limited to this.

[0106] Following step 1F, under an exposure source, two layers of photoresist 340D and 350D are exposed using a photomask carrying a template pattern or by focused direct writing. After exposure, exposure patterns (i.e., negative pattern areas and positive pattern areas) of different sizes are formed on the negative photoresist 340D and the positive photoresist 350D, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area). This exposure process is similar to... Figure 3B Step 2D is similar, so repeated explanations are omitted here.

[0107] After exposure, in step 2F, the negative photoresist is developed using a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist outside the negative pattern area); then, in step 3F, the interlayer film is developed using a spacer film developer, or the interlayer film is etched using the pattern of the developed negative photoresist as an etch resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed negative photoresist (corresponding to developing the interlayer with an interlayer developer, or etching the interlayer using the pattern of the developed negative photoresist layer as an etch resist mask). Etching is performed to make the pattern of the spacer layer consistent with the pattern of the developed negative photoresist layer; then, in step 4F, the positive photoresist is controlled to develop with positive photoresist developer, washing away only the edge portions of the exposed pattern on the positive photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the positive photoresist layer with positive photoresist developer to remove the positive photoresist at the edge portions of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern).

[0108] By coating a separator film between two layers of photoresist, the dissolution of the two layers of photoresist during the coating process can be avoided or reduced.

[0109] Therefore, the previously described method can be used in steps 1B and 3B to Figure 3D The resulting differential pattern is used as a mask for etching, thereby forming grooves on the coating in the target area for forming a metal interconnect layer.

[0110] By using the above-described metal interconnect layer formation process, this disclosure enables the formation of the lower metal interconnect layer for FinFETs of 7nm and below. Although the above process is described with respect to the lower metal layer (M1 layer), embodiments of this disclosure are also applicable to other metal layers.

[0111] Therefore, this disclosure organically combines the double-layer photoresist photolithography process, which utilizes double-layer photoresist to achieve a doubling of line density, with etching and cutting processes, thereby achieving a further increase in pattern density and a further reduction in pattern size.

[0112] This disclosure reduces the size of metal interconnects by performing only two double-layer photoresist lithography processes and two etching processes, without using EUV, while meeting the pitch and critical dimension requirements of the metal interconnects and greatly simplifying the process flow. Compared with the existing SAQP process, this disclosure reduces steps such as mandrel deposition, spacer layer deposition using ALD, spacer layer etch-back, and mandrel removal, greatly simplifying the process flow and saving costs. This allows for the formation of higher-density metal interconnect layers with higher efficiency, lower cost, and simpler operation. Compared with the existing DUV combined with LELE process, this disclosure significantly reduces the difficulty of controlling overlay errors, and the very small linewidth that the double-layer photoresist lithography process can form itself greatly reduces the etching difficulty, which is beneficial for the transfer of patterns between different layers.

[0113]

[0114] Each step in the patterning method for semiconductor processes of the present invention can be implemented by each component in the patterning system for semiconductor processes.

[0115] This invention provides a patterning system for semiconductor processes, comprising a first differential pattern forming section, a second differential pattern forming section, a second pattern forming section, a low-temperature oxide layer deposition section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section. The patterning system is used to perform the following steps:

[0116] (1) Using a first differential pattern forming unit, a first differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer and a second hard mask layer located on the substrate target layer.

[0117] (2) Using the first pattern forming unit, the second hard mask layer is etched to obtain the first pattern, with the first differential pattern as a mask;

[0118] (3) Using the second differential pattern forming unit, a second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process;

[0119] (4) Using the second pattern forming unit, the first pattern is etched using the second differential pattern as a mask to obtain the second pattern;

[0120] (5) Using a low-temperature oxide layer deposition section, a low-temperature oxide layer is deposited at a predetermined location in the target area where the second pattern is formed by photolithography and etching processes. The predetermined location corresponds to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect.

[0121] (6) Using the first hard mask layer etching section, the first hard mask layer is etched to form a hard mask pattern by using the second pattern and the low-temperature oxide layer as masks;

[0122] (7) Using the low-k dielectric layer etching section, and with the hard mask pattern as a mask, the low-k dielectric layer is etched; and

[0123] (8) Using a metal material deposition section, deposit metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

[0124] In addition, this disclosure provides another patterning method for semiconductor processes to form metal interconnect layers.

[0125] <First double-layer photoresist lithography process + first etching process + second double-layer photoresist lithography process + second etching process + dicing process using boron ion implantation>

[0126] The patterning method for semiconductor processes disclosed herein includes the following steps:

[0127] (1) Using photolithography and etching processes, boron ions are implanted into the expected positions of the amorphous silicon layer in the target area to form implanted amorphous silicon portions. The expected positions correspond to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect. The target area consists of a substrate target layer, a low-k dielectric layer located on the substrate target layer, a first hard mask layer, a second hard mask layer and the amorphous silicon layer.

[0128] (2) Remove the unimplanted amorphous silicon portion from the amorphous silicon layer, and retain the implanted amorphous silicon portion;

[0129] (3) A first differential pattern is formed on the target region on which the implanted amorphous silicon portion is formed using a double-layer photoresist photolithography process;

[0130] (4) Using the first differential pattern as a mask, the second hard mask layer is etched to obtain the first pattern, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is exempted from etching.

[0131] (5) A second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process;

[0132] (6) Using the second differential pattern as a mask, the first pattern is etched to obtain the second pattern, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempted from etching.

[0133] (7) Using the second pattern and the implanted amorphous silicon portion as masks, the first hard mask layer is etched to form a hard mask pattern;

[0134] (8) Using the hard mask pattern as a mask, the low-k dielectric layer is etched; and

[0135] (9) Deposit a metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

[0136] In some embodiments, step (1) includes performing the following steps multiple times:

[0137] Using photolithography and etching processes, a coating is applied to the amorphous silicon layer and the coating is etched at the intended location;

[0138] Boron ion implantation is performed on the target region where the coating is formed to form implanted amorphous silicon portions; and

[0139] Remove the coating.

[0140] Figure 4 This is a schematic flowchart illustrating a patterning method for manufacturing metal interconnect layers for semiconductor processes, which utilizes a double-layer photoresist photolithography process combined with a dicing process utilizing boron ion implantation, according to an embodiment of the present disclosure.

[0141] Cutting process using boron ion implantation

[0142] In step 1G, a target region is prepared. The target region may consist of a substrate target layer 410 and a low-k dielectric layer 420, a first hard mask layer 430, a second hard mask layer 440, and an amorphous silicon layer 450 located on the substrate target layer 410. Then, using photolithography and etching processes, boron ion implantation is performed at the expected locations of the amorphous silicon layer 450 to form implanted amorphous silicon portions 452. The expected locations correspond to the two ends of the extension direction of the metal interconnects in the metal interconnect layer and the breakpoint of the metal interconnects (corresponding to the expected locations of the amorphous silicon layer in the target region being implanted with boron ions using photolithography and etching processes to form implanted amorphous silicon portions, the expected locations corresponding to the two ends of the extension direction of the metal interconnects in the metal interconnect layer and the breakpoint of the metal interconnects, the target region consisting of a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer, and the amorphous silicon layer located on the substrate target layer).

[0143] In some embodiments, step 1G may include the following steps.

[0144] First, a first coating 460 is applied. As an example, the first coating 460 can be a SOC layer, but the invention is not limited thereto. Using a photolithography process, an anti-reflective coating and photoresist are applied to the first coating 460. The photoresist is exposed and developed according to wiring requirements to form a photolithographic pattern. Then, using the photolithographic pattern as a mask, the anti-reflective coating and the first coating 460 are etched to transfer the pattern to the first coating 460 (corresponding to applying a coating on the amorphous silicon layer and etching the coating at the intended location using photolithography and etching processes). Next, boron ion implantation is performed on the target area where the first coating 460 is formed to change the properties of the exposed portion of the amorphous silicon layer 450, thereby forming an implanted amorphous silicon portion 452 (corresponding to boron ion implantation on the target area where the coating is formed to form an implanted amorphous silicon portion). Finally, the remaining first coating 460 is removed (corresponding to removing the coating).

[0145] Step 1G can be repeated multiple times until an implanted amorphous silicon portion 452 is formed at the desired location. The two island structures in the figure represent only one island structure formed in this step. It should be understood that the implanted amorphous silicon portion formed by performing step 1G once corresponds only to a portion of the desired location, and the implanted amorphous silicon portions formed by performing step 1G multiple times collectively correspond to the desired location.

[0146] In step 2G, the unimplanted portion of the amorphous silicon layer 450 is removed, retaining the implanted amorphous silicon portion 452 (corresponding to removing the unimplanted amorphous silicon portion from the amorphous silicon layer and retaining the implanted amorphous silicon portion). The upper part of the figure is a top view of the formed structure, and the lower part is a cross-sectional view along the dashed line. The three island structures in the figure represent island structures formed by performing step 1G multiple times. Although the island structures shown in the figure are located in the center and there are three of them, it should be understood that the location of the island structures is not limited to the center, and the location and number of island structures can be set as needed.

[0147] <First Double-Layer Photoresist Lithography Process>

[0148] In step 3G, a second coating 470 and a third coating 480 are applied to the implanted amorphous silicon portion 452. Then, a first differential pattern consisting of a first photoresist layer 492 and a second photoresist layer 494 is formed on the target area using a double-layer photoresist lithography process (corresponding to forming a first differential pattern on the target area where the implanted amorphous silicon portion is formed using a double-layer photoresist lithography process). Although a first differential pattern consisting of a first photoresist layer 492 and a second photoresist layer 494 is used as an example here, other differential patterns can be formed in other embodiments. (Referring to the above...) Figures 3A-3DThe process of forming differential patterns using a double-layer photoresist photolithography process is described in detail, so repeated explanations are omitted here.

[0149] As an example, the second coating 470 may be a SOC layer, and the third coating 480 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the invention is not limited thereto. Alternatively, the steps of applying the second and third coatings to the implanted amorphous silicon portion may be omitted, and the invention is not limited to the above example.

[0150] <First Etching Process>

[0151] In step 4G, the target area is etched using the first differential pattern as a mask until etching stops at the first hard mask layer 430, forming the first pattern 442 in the second hard mask layer 440. The portion of the second hard mask layer 440 located below the implanted amorphous silicon portion 452 is spared etching (corresponding to etching the second hard mask layer using the first differential pattern as a mask to obtain the first pattern, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is spared etching). The top of the figure is a top view of the formed structure.

[0152] <Second Double-Layer Photoresist Lithography Process>

[0153] In step 5G, a fourth coating layer 472 and a fifth coating layer 482 are applied to the first pattern 442. Then, a second differential pattern consisting of a third photoresist layer 496 and a fourth photoresist layer 498 is formed on the target area using a double-layer photoresist photolithography process (corresponding to forming a second differential pattern on the target area where the first pattern is formed using a double-layer photoresist photolithography process). Although a second differential pattern consisting of a third photoresist layer 496 and a fourth photoresist layer 498 is used as an example here, other differential patterns can be formed in other embodiments. (Referring to the above...) Figures 3A-3D The process of forming differential patterns using a double-layer photoresist photolithography process is described in detail, so repeated explanations are omitted here.

[0154] As an example, the fourth coating 472 may be a SOC layer, and the fifth coating 482 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the invention is not limited thereto. Alternatively, the steps of applying the fourth and fifth coatings on the first pattern may be omitted, and the invention is not limited to the above example.

[0155] <Second Etching Process>

[0156] In step 6G, the target area is etched using the second differential pattern as a mask until it stops at the first hard mask layer 430, forming the second pattern 444 in the first pattern 442. The portion of the first pattern 442 located below the implanted amorphous silicon portion 452 is spared from etching (corresponding to etching the first pattern using the second differential pattern as a mask to obtain the second pattern, wherein the portion of the first pattern located below the implanted amorphous silicon portion is spared from etching). The top of the figure is a top view of the formed structure. Individual island structures extend in a direction perpendicular to the extension direction of the second pattern 444, such that at least two adjacent protrusion patterns in the second pattern 444 are connected, thereby allowing the final metal interconnect layer to produce breaks in the extension direction of the second pattern 444 as needed.

[0157] Next, in step 7G, the first hard mask layer 430 is etched using the second pattern 444 and the implanted amorphous silicon portion 452 as a mask to form the first hard mask pattern 432 (corresponding to etching the first hard mask layer using the second pattern and the implanted amorphous silicon portion as a mask to form the hard mask pattern). Then, in step 8G, the low-k dielectric layer 420 is etched using the first hard mask pattern 432 as a mask to obtain the etched low-k dielectric layer 422 (corresponding to etching the low-k dielectric layer using the hard mask pattern as a mask).

[0158] Finally, in step 9G, a metal material is deposited on the etched low-k dielectric layer 422 and chemically mechanically polished to form a metal interconnect layer (corresponding to depositing a metal material on the etched low-k dielectric layer and chemically mechanically polishing to form a metal interconnect layer).

[0159] By using the above-described metal interconnect layer formation process, this disclosure enables the formation of the lower metal interconnect layer for FinFETs of 7nm and below. Although the above process is described with respect to the lower metal layer (M1 layer), embodiments of this disclosure are also applicable to other metal layers.

[0160] Therefore, this disclosure organically combines the double-layer photoresist photolithography process, which utilizes double-layer photoresist to achieve a doubling of line density, with etching and cutting processes, thereby achieving a further increase in pattern density and a further reduction in pattern size.

[0161] This disclosure reduces the size of metal interconnects by performing only two double-layer photoresist lithography processes and two etching processes, without using EUV, while meeting the pitch and critical dimension requirements of the metal interconnects and greatly simplifying the process flow. Compared with the existing SAQP process, this disclosure reduces steps such as mandrel deposition, spacer layer deposition using ALD, spacer layer etch-back, and mandrel removal, greatly simplifying the process flow and saving costs. This allows for the formation of higher-density metal interconnect layers with higher efficiency, lower cost, and simpler operation. Compared with the existing DUV combined with LELE process, this disclosure significantly reduces the difficulty of controlling overlay errors, and the very small linewidth that the double-layer photoresist lithography process can form itself greatly reduces the etching difficulty, which is beneficial for the transfer of patterns between different layers.

[0162]

[0163] Each step in the patterning method for semiconductor processes of the present invention can be implemented by each component in the patterning system for semiconductor processes.

[0164] This invention provides a patterning system for semiconductor processes, comprising a dicing and implantation section, an amorphous silicon portion removal section, a first differential pattern forming section, a first pattern forming section, a second differential pattern forming section, a second pattern forming section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section. The patterning system is used to perform the following steps:

[0165] (1) Using a cutting and implantation section, using photolithography and etching processes, boron ions are implanted at the expected positions of the amorphous silicon layer in the target area to form implanted amorphous silicon portions, the expected positions corresponding to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect, the target area being composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer and the amorphous silicon layer located on the substrate target layer;

[0166] (2) Using an amorphous silicon portion removal unit, remove the unimplanted amorphous silicon portion in the amorphous silicon layer, while retaining the implanted amorphous silicon portion;

[0167] (3) Using the first differential pattern forming unit, a first differential pattern is formed on the target area where the implanted amorphous silicon portion is formed using a double-layer photoresist photolithography process;

[0168] (4) Using a first pattern forming unit, the second hard mask layer is etched to obtain a first pattern using the first differential pattern as a mask, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is exempted from etching.

[0169] (5) Using the second differential pattern forming unit, a second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process;

[0170] (6) Using a second patterning unit, the first pattern is etched to obtain a second pattern using the second differential pattern as a mask, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempted from etching.

[0171] (7) Using the first hard mask layer etching section, the first hard mask layer is etched to form a hard mask pattern, with the second pattern and the implanted amorphous silicon portion as masks.

[0172] (8) Using the low-k dielectric layer etching section, and with the hard mask pattern as a mask, the low-k dielectric layer is etched; and

[0173] (9) Using a metal material deposition section, a metal material is deposited on the etched low-k dielectric layer and chemically mechanically polished to form a metal interconnect layer.

[0174] Furthermore, this disclosure also provides a control method for a patterning system for semiconductor processes, used to control the aforementioned patterning system for semiconductor processes to perform various steps.

[0175] Furthermore, this disclosure also provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described control method for a patterning system for semiconductor processes.

[0176] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A patterning method for semiconductor processes, characterized in that, The method includes the following steps: (1) A first differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer and a second hard mask layer located on the substrate target layer. (2) Using the first difference pattern as a mask, the second hard mask layer is etched to obtain the first pattern; (3) A second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (4) Using the second difference pattern as a mask, the first pattern is etched to obtain the second pattern; (5) Using photolithography and etching processes, a low-temperature oxide layer is deposited at a predetermined location in the target area where the second pattern is formed, the predetermined location corresponding to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect. (6) Using the second pattern and the low-temperature oxide layer as a mask, the first hard mask layer is etched to form a hard mask pattern; (7) Using the hard mask pattern as a mask, the low-k dielectric layer is etched; and (8) Deposit a metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

2. The patterning method for semiconductor processes according to claim 1, characterized in that, Step (5) involves performing the following steps multiple times: Using photolithography and etching processes, a coating is applied to the second pattern and the coating is etched at the intended location; A low-temperature oxide material is deposited on the coating; as well as The low-temperature oxide material is etched back and the coating is removed.

3. A patterning method for semiconductor processes, characterized in that, The method includes the following steps: (1) Using photolithography and etching processes, boron ions are implanted into the expected positions of the amorphous silicon layer in the target area to form implanted amorphous silicon portions. The expected positions correspond to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer and the amorphous silicon layer located on the substrate target layer. (2) Remove the unimplanted amorphous silicon portion from the amorphous silicon layer, and retain the implanted amorphous silicon portion; (3) A first differential pattern is formed on the target region on which the implanted amorphous silicon portion is formed using a double-layer photoresist photolithography process; (4) Using the first differential pattern as a mask, the second hard mask layer is etched to obtain the first pattern, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is exempted from etching. (5) A second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (6) Using the second differential pattern as a mask, the first pattern is etched to obtain the second pattern, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempted from etching. (7) Using the second pattern and the implanted amorphous silicon portion as masks, the first hard mask layer is etched to form a hard mask pattern; (8) Using the hard mask pattern as a mask, the low-k dielectric layer is etched; and (9) Deposit a metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

4. The patterning method for semiconductor processes according to claim 3, characterized in that, Step (1) involves performing the following steps multiple times: Using photolithography and etching processes, a coating is applied to the amorphous silicon layer and the coating is etched at the intended location; Boron ion implantation is performed on the target region where the coating is formed to form an implanted amorphous silicon portion; as well as Remove the coating.

5. The patterning method for semiconductor processes according to any one of claims 1 to 4, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (A1) A negative photoresist layer is formed on the target area using negative photoresist, and a positive photoresist layer is formed on the negative photoresist layer using positive photoresist; (A2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (A3) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (A4) The negative photoresist layer is developed with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

6. The patterning method for semiconductor processes according to any one of claims 1 to 4, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (B1) A positive photoresist layer is formed on the target area using a positive photoresist, and a negative photoresist layer is formed on the positive photoresist layer using a negative photoresist; (B2) The negative adhesive layer and the positive adhesive layer are patterned to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (B3) The negative photoresist layer is developed with a negative photoresist developer to remove negative photoresist outside the negative pattern area; (B4) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

7. The patterning method for semiconductor processes according to any one of claims 1 to 4, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (C1) A negative photoresist layer is formed on the target area using negative photoresist, a spacer layer is formed on the negative photoresist layer, and a positive photoresist layer is formed on the spacer layer using positive photoresist. (C2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (C3) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (C4) Develop the separator with a separator developer, or etch the separator using the pattern of the developed positive resist layer as an etch mask, so that the pattern of the separator is consistent with the pattern of the developed positive resist layer. (C5) The negative photoresist layer is developed with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

8. The patterning method for semiconductor processes according to any one of claims 1 to 4, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (D1) A positive photoresist layer is formed on the target area using a positive photoresist, a spacer layer is formed on the positive photoresist layer, and a negative photoresist layer is formed on the spacer layer using a negative photoresist. (D2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (D3) The negative photoresist layer is developed with a negative photoresist developer to remove negative photoresist outside the negative pattern area; (D4) Develop the separator with a separator developer, or etch the separator using the pattern of the developed negative adhesive layer as an anti-etching mask, so that the pattern of the separator is consistent with the pattern of the developed negative adhesive layer. (D5) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

9. The patterning method for semiconductor processes according to any one of claims 5 to 8, characterized in that, Patterning the negative adhesive layer and the positive adhesive layer to form positive and negative patterned areas on the positive and negative adhesive layers respectively includes: Under exposure source, the positive resist layer and the negative resist layer are exposed using a photomask carrying a template pattern or by focused direct writing, thereby forming positive pattern areas and negative pattern areas on the positive resist layer and the negative resist layer, respectively.

10. The patterning method for semiconductor processes according to claim 9, characterized in that, Using projection exposure, the positive resist layer and the negative resist layer are exposed under the exposure source through a photomask carrying the template pattern; or Using a masking exposure method, the positive resist layer and the negative resist layer are exposed under the exposure source through a photomask carrying the template pattern; or By using reflective exposure, the positive resist layer and the negative resist layer are exposed by reflection on a photomask carrying the template pattern under an exposure source.

11. The patterning method for semiconductor processes according to claim 9, characterized in that, The focused direct writing includes ultraviolet light direct writing, deep ultraviolet light direct writing, extreme ultraviolet light direct writing, ion beam direct writing, electron beam direct writing, or X-ray direct writing.

12. A patterning system for semiconductor processes, comprising a first differential patterning section, a first patterning section, a second differential patterning section, a second patterning section, a low-temperature oxide layer deposition section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section, wherein the patterning system is used to perform the following steps: (1) Using the first differential pattern forming unit, a first differential pattern is formed on the target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer and a second hard mask layer located on the substrate target layer. (2) Using the first pattern forming unit, the second hard mask layer is etched to obtain the first pattern, with the first differential pattern as a mask. (3) Using the second differential pattern forming unit, a second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (4) Using the second pattern forming unit, the first pattern is etched using the second difference pattern as a mask to obtain the second pattern; (5) Using the low-temperature oxide layer deposition section, a low-temperature oxide layer is deposited at a predetermined position in the target area where the second pattern is formed by photolithography and etching processes. The predetermined position corresponds to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect. (6) Using the first hard mask layer etching section, the first hard mask layer is etched to form a hard mask pattern by using the second pattern and the low-temperature oxide layer as masks; (7) Using the low-k dielectric layer etching section, with the hard mask pattern as a mask, the low-k dielectric layer is etched; as well as (8) Using the metal material deposition section, deposit metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

13. A patterning system for semiconductor processes, comprising a dicing and implantation section, an amorphous silicon portion removal section, a first differential pattern forming section, a first pattern forming section, a second differential pattern forming section, a second pattern forming section, a first hard mask layer etching section, a low-k dielectric layer etching section, and a metal material deposition section, wherein the patterning system is used to perform the following steps: (1) Using the cutting and implantation section, boron ions are implanted into the expected position of the amorphous silicon layer in the target area using photolithography and etching processes to form the implanted amorphous silicon portion. The expected position corresponds to the two ends of the extension direction of the metal interconnect in the metal interconnect layer and the break point of the metal interconnect. The target area is composed of a substrate target layer and a low-k dielectric layer, a first hard mask layer, a second hard mask layer and the amorphous silicon layer located on the substrate target layer. (2) Using the amorphous silicon portion removal unit, remove the unimplanted amorphous silicon portion in the amorphous silicon layer, and retain the implanted amorphous silicon portion; (3) Using the first differential pattern forming unit, a first differential pattern is formed on the target area where the implanted amorphous silicon portion is formed using a double-layer photoresist photolithography process; (4) Using the first pattern forming unit, the second hard mask layer is etched to obtain the first pattern using the first differential pattern as a mask, wherein the portion of the second hard mask layer located below the implanted amorphous silicon portion is exempted from etching. (5) Using the second differential pattern forming unit, a second differential pattern is formed on the target area where the first pattern is formed using a double-layer photoresist photolithography process; (6) Using the second pattern forming unit, the first pattern is etched to obtain the second pattern using the second differential pattern as a mask, wherein the portion of the first pattern located below the implanted amorphous silicon portion is exempted from etching. (7) Using the first hard mask layer etching section, the first hard mask layer is etched to form a hard mask pattern by using the second pattern and the implanted amorphous silicon portion as masks. (8) Using the low-k dielectric layer etching section, with the hard mask pattern as a mask, the low-k dielectric layer is etched; as well as (9) Using the metal material deposition section, deposit metal material on the etched low-k dielectric layer and perform chemical mechanical polishing to form a metal interconnect layer.

14. A control method for a patterning system for semiconductor processes, used to control the patterning system for semiconductor processes according to claim 12 or 13 to perform various steps.

15. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the control method for a patterning system for semiconductor processes as described in claim 14.

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