Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a substrate comprising a plurality of discrete device cell regions, each device cell region being used to form a standard cell, each device cell region including a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first and second device regions being arranged along a first direction; and embedded metal lines located in the substrate between the first and second device regions, the embedded metal lines extending along a second direction perpendicular to the first direction. This invention improves the wiring freedom of the device, facilitates the release of winding space for subsequent metal interconnects, thereby reducing the height of the standard cell and improving the device integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To meet the ever-growing needs of logic chip miniaturization, and to optimize power supply capabilities when metal spacing is very tight, one approach is to move the power rails down into the substrate to form buried power rails (BPR).

[0003] In the embedded power rail structure, the power rails are buried in the substrate and deep into the shallow trench isolation (STI) module, which helps to free up interconnect wiring resources. Moreover, the embedded power rail provides a lower resistive local current distribution for the technique of increasing BEOL resistance by miniaturizing the pitch. In addition, the embedded power rail also helps to reduce the effects of wiring congestion and resistance degradation on the grid distribution of VDD, VSS, word lines and bit lines, improving write margin and read speed.

[0004] However, the integration level of the devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the degree of freedom and integration of device interconnects.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a plurality of discrete device cell regions, the device cell regions being used to form standard cells, each device cell region including a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first device region and the second device region being arranged along a first direction; and a buried metal line located in the substrate between the first device region and the second device region, the buried metal line extending along a second direction, the second direction being perpendicular to the first direction.

[0007] Optionally, the semiconductor structure further includes: a buried power rail located in a substrate between adjacent device cell regions, the buried power rail extending along the second direction.

[0008] Optionally, the semiconductor structure further includes: a protrusion, disposed on the substrate of the first device region and the second device region; a channel structure, located above the protrusion, the channel structure and the protrusion extending along the second direction; an isolation layer, located on the substrate and surrounding the protrusion; a gate structure, located on the isolation layer and spanning the channel structure, the gate structure extending along the first direction; and source / drain doped regions, located within the channel structures on both sides of the gate structure.

[0009] Optionally, the embedded power rail is made of the same material as the embedded metal wire.

[0010] Optionally, the top surface of the embedded power rail is flush with the top surface of the embedded metal wire, and the bottom surface of the embedded power rail is flush with the bottom surface of the embedded metal wire.

[0011] Optionally, the gate structure is electrically connected to the buried metal line; or, the semiconductor structure further includes: a source-drain interconnect layer located above and in contact with the source-drain doped region, the source-drain interconnect layer being electrically connected to the buried metal line.

[0012] Optionally, the top surface of the embedded metal line is higher than the top surface of the substrate and lower than the top surface of the isolation layer; the semiconductor structure further includes: a covering dielectric layer located in the isolation layer on top of the embedded metal line.

[0013] Optionally, the semiconductor structure further includes a gate dielectric layer located between the gate structure and the channel structure.

[0014] Optionally, the material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0015] Optionally, the substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; the embedded metal wire material includes one or more of the following: Co, W, Ni, and Ru.

[0016] Optionally, the materials of the protrusion and the channel structure include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; the materials of the gate structure include any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0017] Optionally, the material of the source-drain interconnect layer includes one or more of W, Co, Cu, Ru, and Ni.

[0018] Optionally, the channel structure is a fin; the gate structure spans the fin and covers a portion of the top and a portion of the sidewalls of the fin; or, the channel structure is a channel structure layer, with the channel structure layer and the protrusion spaced apart, the channel structure layer including one or more channel layers spaced apart in sequence; the gate structure spans the channel structure layer and surrounds the channel layer.

[0019] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a plurality of discrete device cell regions, the device cell regions being used to form standard cells, each of the device cell regions including a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first device region and the second device region being arranged along a first direction; forming a buried metal line in the substrate between the first device region and the second device region, the buried metal line extending along a second direction, the second direction being perpendicular to the first direction.

[0020] Optionally, the method for forming the semiconductor structure further includes: during the formation of the buried metal line, forming a buried power rail in the substrate between adjacent device unit regions, the buried power rail extending along the second direction.

[0021] Optionally, in the step of providing a substrate, discrete protrusions are further formed on the substrates of the first device region and the second device region, and a channel structure is further formed on the protrusions. The channel structure and the protrusions extend along a second direction, which is perpendicular to the first direction. The method of forming the semiconductor structure further includes: forming an isolation material layer covering the protrusions and the channel structure on the substrate; removing the isolation material layer above the protrusions, and using the remaining isolation material layer surrounding the protrusions as an isolation layer; the step of forming the embedded metal line includes: after forming the isolation material layer and before removing the isolation material layer above the protrusions, forming an opening in the isolation material layer between the first device region and the second device region; and forming the embedded metal line in the opening.

[0022] Optionally, after forming the isolation layer, the method for forming the semiconductor structure further includes: forming a gate structure spanning the channel structure and source / drain doped regions within the channel structures located on both sides of the gate structure on the isolation layer; the gate structure is electrically connected to the buried metal line; or, the method for forming the semiconductor structure further includes: forming a source / drain interconnect layer above the source / drain doped regions and in contact with the source / drain doped regions, the source / drain interconnect layer being electrically connected to the buried metal line.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0024] The semiconductor structure provided in this embodiment of the invention has a buried metal line located in the substrate between the first device region and the second device region. That is, a buried metal line is also provided in the NMOS device region and PMOS device region of the standard cell. This allows the buried metal line to be set in the gap between the NMOS device region and the PMOS device region inside the standard cell, so as to provide power to different components of the device or to realize electrical connection between components in the NMOS device region and the PMOS device region. This improves the degree of freedom of device wiring and also utilizes the gap between the NMOS device region and the PMOS device region, which helps to release the winding space of the subsequent metal interconnect, thereby helping to compress the height of the standard cell and improve the integration of the device. Attached Figure Description

[0025] Figures 1 to 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0026] Figures 3 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0027] As can be seen from the background technology, the integration level of current devices still needs to be improved.

[0028] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a plurality of discrete device cell regions, the device cell regions being used to form standard cells, each device cell region including a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first device region and the second device region being arranged along a first direction; and a buried metal line located in the substrate between the first device region and the second device region, the buried metal line extending along a second direction, the second direction being perpendicular to the first direction.

[0029] The semiconductor structure provided in this embodiment of the invention has a buried metal line located in the substrate between the first device region and the second device region. That is, a buried metal line is also provided in the NMOS device region and PMOS device region of the standard cell. This allows the buried metal line to be set in the gap between the NMOS device region and the PMOS device region inside the standard cell, so as to provide power to different components of the device or to realize electrical connection between components in the NMOS device region and the PMOS device region. This improves the degree of freedom of device wiring and also utilizes the gap between the NMOS device region and the PMOS device region, which helps to release the winding space of the subsequent metal interconnect, thereby helping to compress the height of the standard cell and improve the integration of the device.

[0030] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 1 to 2 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention. Figure 1 This is a top view. Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the 1-1' direction.

[0031] like Figure 1 As shown, in this embodiment, the semiconductor structure includes: a substrate 100, comprising a plurality of discrete device cell regions 100S, wherein the device cell regions 100S are used to form standard cells, and each device cell region 100S includes a first device region 100N for forming an NMOS device and a second device region 100P for forming a PMOS device, the first device region 100N and the second device region 100P being aligned along a first direction (e.g., ...). Figure 1 Arranged in the second direction (as shown in the D1 direction); embedded metal lines 120 are located in the substrate 100 between the first device region 100N and the second device region 100P, the embedded metal lines 120 being arranged along the second direction (as shown in the D1 direction); Figure 1 Extending in the direction shown in D2, the second direction is perpendicular to the first direction.

[0032] Substrate 100 provides a process platform for the formation of semiconductor structures. The material of substrate 100 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, substrate 100 is a silicon substrate.

[0033] The device cell region 100S is used to form a standard cell. Specifically, the first device region 100N is used to form an NMOS device, and the second device region 100P is used to form a PMOS device.

[0034] In this embodiment, the semiconductor structure further includes: a protrusion 105, which is disposed on the substrate 100 of the first device region 100N and the second device region 100P; and a channel structure 110, which is located above the protrusion 105, and the channel structure 110 and the protrusion 105 extend along the second direction.

[0035] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure, and the material of the protrusion 105 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0036] The channel structure 110 is used to provide a conductive channel for the field-effect transistor. As an example, the first and second devices are fin field-effect transistors (FinFETs). Accordingly, the channel structure 110 is a fin. The fin is connected to the protrusion 105. In this embodiment, the fin and the protrusion 105 are an integral structure.

[0037] In this embodiment, the material of the fin is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the fin may be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other semiconductor materials suitable for forming fins. The material of the fin may also be different from that of the substrate.

[0038] In other embodiments, when the first device and the second device are Gate-All Around (GAA) transistors or Forksheet transistors, the channel structure can also be a channel structure layer, with the channel structure layer and the protrusions spaced apart, and the channel structure layer including one or more channel layers spaced apart in sequence.

[0039] In this embodiment, both the channel structure 110 and the protrusion 105 extend along the second direction, and the plurality of protrusions 105 and the plurality of channel structures 110 are arranged at intervals along the first direction.

[0040] In this embodiment, the semiconductor structure further includes an isolation layer 115, located on the substrate 100 and surrounding the protrusion 105.

[0041] The isolation layer 115 is used to isolate adjacent protrusions 105, and the isolation layer 115 is also used to isolate the substrate 100 from the gate structure 130. The isolation layer 115 exposes the channel structure 110.

[0042] The material of the insulating layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the material of the insulating layer 115 is silicon oxide.

[0043] The embedded metal line 120 is located in the substrate 100 between the first device region 100N and the second device region 100P. That is, the embedded metal line 120 is also provided in the NMOS device region and PMOS device region of the standard cell. This allows the embedded metal line 120 to be set in the gap between the NMOS device region and the PMOS device region inside the standard cell, so as to provide power to different components of the device or realize electrical connection between components in the NMOS device region and the PMOS device region. This improves the wiring freedom of the device. It also utilizes the gap between the NMOS device region and the PMOS device region, which helps to release the winding space of the subsequent metal interconnect, thereby helping to compress the height of the standard cell and improve the integration of the device.

[0044] The embedded metal line 120 is made of a conductive material. Specifically, the embedded metal line 120 is made of a metallic material. As an example, the material of the embedded metal line 120 includes one or more of Co, W, Ni, and Ru. By selecting these materials, the embedded metal line 120 has low resistivity, which is beneficial for improving RC delay, increasing chip processing speed, and reducing IR drop and improving power supply efficiency when using the embedded metal line 120 for power supply.

[0045] In this embodiment, the top surface of the embedded metal wire 120 is higher than the top surface of the substrate 100 and lower than the top surface of the isolation layer 115. That is, the embedded metal wire 120 is embedded in the substrate 100 and the isolation layer 115.

[0046] In this embodiment, the semiconductor structure further includes a covering dielectric layer 160 located in an isolation layer 115 on top of the embedded metal line 120.

[0047] The dielectric layer 160 is used to isolate the buried metal line 120 from the gate structure, or to isolate the buried metal line 120 from other conductive structures located on the isolation layer 115. The dielectric layer 160 is made of a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the dielectric layer 160 and the isolation layer 115 are made of the same material, which is beneficial for improving process compatibility.

[0048] In this embodiment, the top surface of the covering medium layer 160 is flush with the top surface of the isolation layer 115.

[0049] In this embodiment, the semiconductor structure further includes: an insulating layer 125 located between the buried metal line 120 and the substrate 100, between the buried metal line 120 and the isolation layer 115, and between the covering dielectric layer 160 and the isolation layer 115. The insulating layer 125 is used to achieve isolation between the buried metal line 120 and the substrate 100. The material of the insulating layer 125 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0050] In this embodiment, the semiconductor structure further includes: a buried power rail 130 located in the substrate 100 between adjacent device unit regions 100S, the buried power rail 130 extending along a second direction.

[0051] In this embodiment, the buried power rails (BPRs) 130 are used to provide power to different components of the chip. In this embodiment, the buried power rails 130 are located in the substrate 100 of the power rail region 100b, which helps to free up wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. Furthermore, the buried power rails employ a technique of increasing back-end (BEOL) resistance through pitch miniaturization, which also helps to provide a lower resistance-based local current distribution.

[0052] The embedded power rail 130 is made of a conductive material. In this embodiment, the embedded power rail 130 is made of a metallic material, such as one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the embedded power rail 130 is low, which is beneficial for improving RC delay, increasing chip processing speed, and power supply efficiency.

[0053] Specifically, in this embodiment, the embedded power rail 130 and the embedded metal wire 120 are made of the same material. The fact that the embedded power rail 130 and the embedded metal wire 120 are made of the same material is because they are formed in the same step, which improves the compatibility of the forming process of the embedded metal wire 120.

[0054] More specifically, the top surface of the embedded power rail 130 is flush with the top surface of the embedded metal line 120, and the bottom surface of the embedded power rail 130 is flush with the bottom surface of the embedded metal line 120. That is, the depth and top surface height of the embedded power rail 130 are the same as those of the embedded metal line 120. During the semiconductor structure formation process, the embedded metal line 130 can be formed using the same process steps as those for forming the embedded power rail 130. This improves process integration and compatibility, and eliminates the need for additional process steps, thus reducing process costs.

[0055] Accordingly, in this embodiment, the embedded power rail 130 is also located in the isolation layer 115 and the substrate 100 of a certain thickness, and a covering dielectric layer 160 is also formed on the top of the embedded power rail 130, and an insulating layer 125 is also formed between the embedded power rail 130 and the substrate 100, and between the embedded power rail 130 and the substrate 100.

[0056] The semiconductor structure further includes a gate structure 135 located on the isolation layer 115 and spanning the channel structure 110, the gate structure 135 extending along a first direction.

[0057] When the device is in operation, the gate structure 135 is used to control the opening or closing of the conductive channel.

[0058] Specifically, in this embodiment, the gate structure 135 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure spans the channel structure layer and surrounds the channel layer.

[0059] In this embodiment, the gate structure 135 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0060] The material of the gate structure 135 includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. Specifically, the gate structure 135 may include a work function layer (not shown) and a metal electrode layer located on the work function layer, or the gate structure 135 may be a work function layer or a metal electrode layer.

[0061] In this embodiment, the semiconductor structure further includes a gate dielectric layer (not shown) located between the gate structure 135 and the channel structure 110. In this embodiment, the gate dielectric layer is also located between the gate structure 135 and the top surface of the isolation layer 115. The gate dielectric layer serves to achieve insulation between the gate structure 135 and the conductive channel.

[0062] The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

[0063] In this embodiment, the semiconductor structure further includes a sidewall (not shown) located on the sidewall of the gate structure 130. The sidewall is used to protect the sidewall of the gate structure 130 and also to define the formation location of the source / drain doped regions 140.

[0064] In this embodiment, the semiconductor structure further includes: source / drain doped regions 140 located within the channel structures 110 on both sides of the gate structure 135.

[0065] The source / drain doped region 140 serves as the source or drain of the field-effect transistor (FET). When the FET is operating, the source / drain doped region 140 provides a carrier source. Specifically, the source / drain doped region 140 is located within the channel structure 110 on both sides of the gate structure 130 and the sidewalls. In this embodiment, the source / drain doped region 140 is located within the fins on both sides of the gate structure 130 and the sidewalls.

[0066] In this embodiment, the source / drain doped region 140 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. When forming a PMOS transistor, the source / drain doped region 140 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped region 140 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC.

[0067] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 150, located on the exposed isolation layer 115 of the gate structure 135 and covering the source / drain doped regions 140. Specifically, the interlayer dielectric layer 150 covers the sidewall of the sidewall.

[0068] The interlayer dielectric layer 150 is used to isolate adjacent devices and also to electrically isolate adjacent conductive structures.

[0069] In this embodiment, the interlayer dielectric layer 150 also covers the covering dielectric layer 160.

[0070] The interlayer dielectric layer 150 is made of an insulating material. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. It should be noted that, for ease of illustration and explanation, only the isolation layer 115, the cover dielectric layer 160, and the interlayer dielectric layer 150 are shown in the cross-sectional view.

[0071] In this embodiment, the semiconductor structure further includes a source-drain interconnect layer 180, which is located above and in contact with the source-drain doped region 140, and the source-drain interconnect layer 180 is electrically connected to the buried metal line 120.

[0072] The source / drain interconnect layer 180 is in contact with the source / drain doped region 140 to enable electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0073] The source / drain interconnect layer 180 is electrically connected to the embedded metal wire 120, thereby enabling power to be supplied to the source / drain doped region 140 through the embedded metal wire 120. Specifically, the source / drain interconnect layer 180 penetrates the interlayer dielectric layer 150 on top of the source / drain doped region 140.

[0074] Specifically, any one or both of the source-drain interconnect layer 180 of the first device region and the source-drain interconnect layer 180 of the second device region are electrically connected to the embedded metal wire 120.

[0075] The source-drain interconnect layer 180 is made of a conductive material, including one or more of W, Co, Cu, Ru, and Ni.

[0076] In this embodiment, the source-drain interconnect layer 180 extends longitudinally, and the extension direction of the source-drain interconnect layer 180 is perpendicular to the extension direction of the embedded metal wire 120.

[0077] Specifically, as one embodiment, the semiconductor structure may include a contact plug 190 located on the top surface of the buried metal line 120 and in contact with the source-drain interconnect layer 180. The contact plug 190 is used to achieve an electrical connection between the source-drain interconnect layer 180 and the buried metal line 120. More specifically, the contact plug 190 penetrates the overlay dielectric layer 160 and the interlayer dielectric layer 150 on the top surface of the buried metal line 120.

[0078] As an example, the contact plug 190 and the source-drain interconnect layer 180 are integrally formed, and the contact plug 190 and the source-drain interconnect layer 180 are made of the same material. In other embodiments, the material of the contact plug may be different from the material of the source-drain interconnect layer.

[0079] It should be noted that the above-described electrical connection between the embedded metal wire 120 and the source-drain interconnect layer 180 via the contact plug 190 is only an example, and the electrical connection between the embedded metal wire 120 and the source-drain interconnect layer 180 is not limited to this.

[0080] It should also be noted that in other embodiments, the gate structure may be electrically connected to the embedded metal line. Specifically, it may be any one or both of the gate structure of the first device region and the gate structure of the second device region that are electrically connected to the embedded metal line.

[0081] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. The semiconductor structure formation method of this embodiment will be described in detail below with reference to the accompanying drawings.

[0082] refer to Figure 3 and Figure 4 , Figure 3 This is a top view. Figure 4 for Figure 3 A cross-sectional view along the 1-1' direction shows a substrate 100 including multiple discrete device cell regions 100S. Each device cell region 100S includes a first device region 100N for forming an NMOS device and a second device region 100P for forming a PMOS device. The first device region 100N and the second device region 100P are aligned along a first direction (e.g., along the 1-1' direction). Figure 3 Arranged as shown in the D1 direction.

[0083] Substrate 100 serves as a process platform for subsequent process fabrication. The material of substrate 100 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, substrate 100 is a silicon substrate.

[0084] The device cell region 100s is used to form a standard cell. Specifically, the first device region 100N is used to form an NMOS device, and the second device region 100P is used to form a PMOS device.

[0085] In this embodiment, discrete protrusions 105 are further formed on the substrates 100 of the first device region 100N and the second device region 100P. A channel structure 110 is also formed on the protrusions 105. The channel structure 110 and the protrusions 105 are aligned along the second direction (e.g., ...). Figure 3 Extending in the direction shown in D2, the second direction is perpendicular to the first direction.

[0086] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure, and the material of the protrusion 105 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0087] The channel structure 110 is used to provide a conductive channel for the field-effect transistor. As an example, the first and second devices are fin field-effect transistors (FinFETs). Accordingly, the channel structure 110 is a fin. The fin is connected to the protrusion 105. In this embodiment, the fin and the protrusion 105 are an integral structure.

[0088] In this embodiment, the material of the fin is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the fin may be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other semiconductor materials suitable for forming fins. The material of the fin may also be different from that of the substrate.

[0089] In other embodiments, when the first device and the second device are Gate-All Around (GAA) transistors or Forksheet transistors, the channel structure can also be a channel structure layer, with the channel structure layer and the protrusions spaced apart, and the channel structure layer including one or more channel layers spaced apart in sequence.

[0090] In this embodiment, both the channel structure 110 and the protrusion 105 extend along the second direction, and the plurality of protrusions 105 and the plurality of channel structures 110 are arranged at intervals along the first direction.

[0091] refer to Figures 5 to 8 An embedded metal line 120 is formed in a substrate 100 between the first device region 100N and the second device region 100P. The embedded metal line 120 extends along a second direction, which is perpendicular to the first direction.

[0092] The embedded metal line 120 is located in the substrate 100 between the first device region 100N and the second device region 100P. That is, the embedded metal line 120 is also provided in the NMOS device region and PMOS device region of the standard cell. This allows the embedded metal line 120 to be set in the gap between the NMOS device region and the PMOS device region inside the standard cell, so as to provide power to different components of the device or realize electrical connection between components in the NMOS device region and the PMOS device region. This improves the wiring freedom of the device. It also utilizes the gap between the NMOS device region and the PMOS device region, which helps to release the winding space of the subsequent metal interconnect, thereby helping to compress the height of the standard cell and improve the integration of the device.

[0093] The embedded metal line 120 is made of a conductive material. Specifically, the embedded metal line 120 is made of a metallic material. As an example, the material of the embedded metal line 120 includes one or more of Co, W, Ni, and Ru. By selecting these materials, the embedded metal line 120 has low resistivity, which is beneficial for improving RC delay, increasing chip processing speed, and reducing IR drop and improving power supply efficiency when using the embedded metal line 120 for power supply.

[0094] In this embodiment, the method for forming the semiconductor structure further includes: during the process of forming the buried metal line 120, a buried power rail 130 is also formed in the substrate 100 between adjacent device unit regions 100S, the buried power rail 130 extending along the second direction.

[0095] In this embodiment, the buried power rail 130 is used to provide power to different components of the chip. In this embodiment, the buried power rail 130 is located in the substrate 100 of the power rail region 100b. The buried power rail 130 is a buried power rail (BPR), which is beneficial for freeing up wiring resources for back-end interconnects and for reducing the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rail uses the technique of increasing back end of line (BEOL) resistance by reducing pitch, which is also beneficial for providing a lower resistance local current distribution.

[0096] The embedded power rail 130 is made of a conductive material. In this embodiment, the embedded power rail 130 is made of a metallic material, such as one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the embedded power rail 130 is low, which is beneficial for improving RC delay, increasing chip processing speed, and power supply efficiency.

[0097] Specifically, in this embodiment, the embedded power rail 130 and the embedded metal wire 120 are made of the same material. The fact that the embedded power rail 130 and the embedded metal wire 120 are made of the same material is because they are formed in the same step, which improves the compatibility of the forming process of the embedded metal wire 120.

[0098] More specifically, the top surface of the embedded power rail 130 is flush with the top surface of the embedded metal wire 120, and the bottom surface of the embedded power rail 130 is flush with the bottom surface of the embedded metal wire 120. In other words, the depth and top surface height of the embedded power rail 130 are the same as those of the embedded metal wire 120.

[0099] In this embodiment, during the formation of the semiconductor structure, the embedded metal line 130 can be formed by utilizing the process steps for forming the embedded power rail 130. This is beneficial for improving process integration and process compatibility, and eliminates the need for additional process steps, thus reducing process costs.

[0100] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: forming an isolation material layer 145 on the substrate 100 covering the protrusion 105 and the channel structure 110; removing the isolation material layer 145 above the protrusion 105, and using the remaining isolation material layer 145 surrounding the protrusion 105 as an isolation layer 115.

[0101] The insulating material layer 145 is used to form an insulating layer in the future, and also to protect the trench structure 110 and the protrusion 105 during the formation of the embedded metal wire.

[0102] As an example, the step of forming the isolation material layer 145 includes: forming an isolation film (not shown) on the substrate 100 that fills the spaces between adjacent protrusions 105 and between adjacent channel structures 110, the isolation film also covering the top of the channel structures 110; and planarizing the isolation film.

[0103] As an example, the use of flowable chemical vapor deposition (FCVD) to form the isolation membrane is beneficial to improving the gap-filling ability of the isolation membrane, thereby reducing the probability of defects such as voids in the isolation membrane; the use of chemical mechanical planarization to planarize the isolation membrane is beneficial to improving the flatness of the top surface of the isolation material layer 145.

[0104] The isolation layer 115 is used to isolate adjacent protrusions 105, and the isolation layer 115 is also used to isolate the substrate 100 from the gate structure 130. The isolation layer 115 exposes the channel structure 110.

[0105] The material of the insulating layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the material of the insulating layer 115 is silicon oxide.

[0106] Accordingly, in this embodiment, the step of forming the embedded metal wire 120 includes: after forming the insulating material layer 145 and before removing the insulating material layer 145 that is higher than the protrusion 105, forming an opening 155 through the insulating material layer 145 between the first device region 100N and the second device region 100P; and forming the embedded metal wire 120 in the opening 155.

[0107] Specifically, in this embodiment, the opening 155 through the isolation material layer 145 between the first device region 100N and the second device region 100P is used as the first opening 155.

[0108] The first opening 155 is used to provide space for forming the embedded metal wire 120.

[0109] In this embodiment, the method for forming the semiconductor structure further includes forming a second opening 165 through an isolation material layer 145 between adjacent device cell regions 100S, during the step of forming the first opening 155. The second opening 165 provides space for forming a buried power rail.

[0110] In this embodiment, after forming the first opening 155 and the second opening 165, the forming method further includes: forming an insulating film 101 on the bottom and sidewalls of the first opening 155 and the second opening 165, and on the top surface of the insulating material layer 145. The insulating film 101 is used to form an insulating layer to isolate the buried metal wire from the substrate 100, and to isolate the buried power rail from the substrate 100.

[0111] In this embodiment, the insulating film 101 is made of silicon oxide.

[0112] In this embodiment, the step of forming the embedded metal wire 120 in the first opening 155 includes: forming a conductive material layer (not shown) in the first opening 155, the conductive material layer also being located on top of the insulating material layer 145; removing a portion of the thickness of the conductive material layer, the remaining conductive material layer located in the first opening 155 being used as the embedded metal wire 120.

[0113] In this embodiment, during the step of forming a conductive material layer in the first opening 155, the conductive material layer is also formed in the second opening 165; during the step of removing a portion of the conductive material layer, a portion of the conductive material layer located in the second opening 165 is also removed, and the remaining conductive material layer located in the second opening 165 is used as the embedded power rail 130.

[0114] In this embodiment, in the step of removing the insulating material layer 145 above the protrusion 105, the insulating film 101 above the protrusion 105 is also removed. The remaining insulating film 101 is used as an insulating layer 125 to isolate the buried metal wire 120 from the substrate 100, and to isolate the buried power rail 130 from the substrate 100.

[0115] It should be noted that, after removing a portion of the conductive material layer and before removing the isolation material layer 145 above the protrusion 105, the method for forming the semiconductor structure further includes filling the first opening 155 and the second opening 165 with a dielectric material layer 103. In the step of removing the isolation material layer 145 above the protrusion 105, the dielectric material layer 103 above the protrusion 105 is also removed, leaving the dielectric material layer 103 remaining on top of the embedded metal line 120 and the embedded power rail 130, which serves as a cover dielectric layer 160.

[0116] The covering dielectric layer 160 is used to isolate the buried metal line 120 from the gate structure, or to isolate the buried metal line 120 from other conductive structures located on the isolation layer 115. In this embodiment, the covering dielectric layer 160 is also used to isolate the buried power rail 130 from the gate structure, or to isolate the buried power rail 130 from other conductive structures located on the isolation layer 115.

[0117] The material of the covering dielectric layer 160 is a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the covering dielectric layer 160 and the isolation layer 115 are made of the same material, which is beneficial for improving process compatibility.

[0118] In this embodiment, the top surface of the covering medium layer 160 is flush with the top surface of the isolation layer 115.

[0119] refer to Figures 10 to 11 , Figure 10 This is a top view. Figure 11 for Figure 10 In a cross-sectional view along the 1-1' direction, after forming the isolation layer 115, the method of forming the semiconductor structure further includes: forming a gate structure 135 spanning the channel structure 110 on the isolation layer 115, and source / drain doped regions 140 located on both sides of the gate structure 135 within the channel structure 110. The gate structure 135 extends along a first direction.

[0120] When the device is in operation, the gate structure 135 is used to control the opening or closing of the conductive channel.

[0121] Specifically, in this embodiment, the gate structure 135 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure spans the channel structure layer and surrounds the channel layer.

[0122] In this embodiment, the gate structure 135 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0123] The material of the gate structure 135 includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. Specifically, the gate structure 135 may include a work function layer (not shown) and a metal electrode layer located on the work function layer, or the gate structure 135 may be a work function layer or a metal electrode layer.

[0124] In this embodiment, a gate dielectric layer (not shown) is further formed between the gate structure 135 and the channel structure 110. In this embodiment, the gate dielectric layer is also located between the gate structure 135 and the top surface of the isolation layer 115. The gate dielectric layer is used to achieve insulation between the gate structure 135 and the conductive channel.

[0125] The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

[0126] In this embodiment, a sidewall (not shown) is also formed on the sidewall of the gate structure 130. The sidewall is used to protect the sidewall of the gate structure 130 and also to define the formation location of the source / drain doped region 140.

[0127] The source / drain doped region 140 serves as the source or drain of the field-effect transistor (FET). When the FET is operating, the source / drain doped region 140 provides a carrier source. Specifically, the source / drain doped region 140 is located within the channel structure 110 on both sides of the gate structure 130 and the sidewalls. In this embodiment, the source / drain doped region 140 is located within the fins on both sides of the gate structure 130 and the sidewalls.

[0128] In this embodiment, the source / drain doped region 140 includes an ion-doped stress layer, which provides stress to the channel region to improve carrier mobility. When forming a PMOS transistor, the source / drain doped region 140 includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped region 140 includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC.

[0129] In this embodiment, an interlayer dielectric layer 150 is also formed on the exposed isolation layer 115 of the gate structure 135, covering the source / drain doped regions 140. Specifically, the interlayer dielectric layer 150 covers the sidewalls of the sidewalls.

[0130] The interlayer dielectric layer 150 is used to isolate adjacent devices and also to electrically isolate adjacent conductive structures.

[0131] In this embodiment, the interlayer dielectric layer 150 also covers the covering dielectric layer 160.

[0132] The interlayer dielectric layer 150 is made of an insulating material. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide. It should be noted that, for ease of illustration and explanation, only the isolation layer 115, the cover dielectric layer 160, and the interlayer dielectric layer 150 are shown in the cross-sectional view.

[0133] refer to Figures 12 to 13 , Figure 12 This is a top view. Figure 13 yes Figure 12 In the cross-sectional view along the 1-1' direction, in this embodiment, the method for forming the semiconductor structure further includes: forming a source-drain interconnect layer 180 above the source-drain doped region 140 and in contact with the source-drain doped region 140, wherein the source-drain interconnect layer 180 is electrically connected to the buried metal line 20.

[0134] The source / drain interconnect layer 180 is in contact with the source / drain doped region 140 to enable electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0135] The source / drain interconnect layer 180 is electrically connected to the embedded metal wire 120, thereby enabling power to be supplied to the source / drain doped region 140 through the embedded metal wire 120. Specifically, the source / drain interconnect layer 180 penetrates the interlayer dielectric layer 150 on top of the source / drain doped region 140.

[0136] Specifically, any one or both of the source-drain interconnect layer 180 of the first device region and the source-drain interconnect layer 180 of the second device region are electrically connected to the embedded metal wire 120.

[0137] The source-drain interconnect layer 180 is made of a conductive material, including one or more of W, Co, Cu, Ru, and Ni.

[0138] In this embodiment, the source-drain interconnect layer 180 extends longitudinally, and the extension direction of the source-drain interconnect layer 180 is perpendicular to the extension direction of the embedded metal wire 120.

[0139] Specifically, as one embodiment, a contact plug 190 may be formed on the top surface of the embedded metal wire 120, which contacts the source-drain interconnect layer 180. The contact plug 190 is used to realize the electrical connection between the source-drain interconnect layer 180 and the embedded metal wire 120. More specifically, the contact plug 190 penetrates the cover dielectric layer 160 and the interlayer dielectric layer 150 on the top surface of the embedded metal wire 120.

[0140] As an example, the contact plug 190 and the source-drain interconnect layer 180 are integrally formed, and the contact plug 190 and the source-drain interconnect layer 180 are made of the same material. In other embodiments, the material of the contact plug may be different from the material of the source-drain interconnect layer.

[0141] It should be noted that the above-described electrical connection between the embedded metal wire 120 and the source-drain interconnect layer 180 via the contact plug 190 is only an example, and the electrical connection between the embedded metal wire 120 and the source-drain interconnect layer 180 is not limited to this.

[0142] It should also be noted that in other embodiments, the gate structure may be electrically connected to the embedded metal line. Specifically, either the gate structure in the first device region or the second device region may be electrically connected to the embedded metal line.

[0143] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: The substrate includes a plurality of discrete device cell regions for forming standard cells. Each device cell region includes a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first device region and the second device region being arranged along a first direction. An embedded metal line is located in a substrate between the first device region and the second device region, and the embedded metal line extends along a second direction, which is perpendicular to the first direction; An embedded power rail is located in a substrate between adjacent device cell regions, and the embedded power rail extends along the second direction.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further includes: protrusions, which are disposed on the substrates of the first device region and the second device region; A channel structure is located above the protrusion, and the channel structure and the protrusion extend along the second direction; An isolation layer is located on the substrate and surrounds the protrusion; A gate structure is located on the isolation layer and spans the channel structure, the gate structure extending along a first direction; The source and drain doped regions are located within the channel structures on both sides of the gate structure.

3. The semiconductor structure of claim 1, wherein, The embedded power rail is made of the same material as the embedded metal wire.

4. The semiconductor structure of claim 1, wherein, The top surface of the embedded power rail is flush with the top surface of the embedded metal wire, and the bottom surface of the embedded power rail is flush with the bottom surface of the embedded metal wire.

5. The semiconductor structure of claim 2, wherein, The gate structure is electrically connected to the embedded metal wire. Alternatively, the semiconductor structure may further include: a source-drain interconnect layer located above and in contact with the source-drain doped region, the source-drain interconnect layer being electrically connected to the embedded metal line.

6. The semiconductor structure as described in claim 2, characterized in that, The top surface of the embedded metal wire is higher than the top surface of the substrate and lower than the top surface of the isolation layer; The semiconductor structure further includes a covering dielectric layer located in an isolation layer on top of the embedded metal wire.

7. The semiconductor structure of claim 2, wherein, The semiconductor structure further includes a gate dielectric layer located between the gate structure and the channel structure.

8. The semiconductor structure of claim 7, wherein, The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

9. The semiconductor structure of claim 1, wherein, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the embedded metal wire includes one or more of Co, W, Ni and Ru.

10. The semiconductor structure of claim 2, wherein, The materials of the protrusions and channel structures include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the gate structure includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

11. The semiconductor structure of claim 5, wherein, The material of the source-drain interconnect layer includes one or more of W, Co, Cu, Ru, and Ni.

12. The semiconductor structure of claim 2, wherein, The channel structure is a fin; the gate structure spans the fin and covers part of the top and part of the sidewalls of the fin; Alternatively, the channel structure is a channel structure layer, with the channel structure layer and the protrusion spaced apart, and the channel structure layer includes one or more channel layers spaced apart in sequence; the gate structure spans the channel structure layer and surrounds the channel layer.

13. A method of forming a semiconductor structure, comprising: include: A substrate is provided, comprising a plurality of discrete device cell regions for forming standard cells, each of the device cell regions including a first device region for forming an NMOS device and a second device region for forming a PMOS device, the first device region and the second device region being arranged along a first direction; An embedded metal line is formed in a substrate between the first device region and the second device region, the embedded metal line extending along a second direction perpendicular to the first direction; The method for forming the semiconductor structure further includes: during the process of forming the embedded metal line, an embedded power rail is also formed in the substrate between adjacent device unit regions, the embedded power rail extending along the second direction.

14. The method of forming a semiconductor structure of claim 13, wherein, In the step of providing a substrate, discrete protrusions are further formed on the substrates of the first device region and the second device region, and channel structures are further formed on the protrusions. The channel structures and the protrusions extend along the second direction, which is perpendicular to the first direction. The method for forming the semiconductor structure further includes: forming an isolation material layer covering the protrusion and the channel structure on the substrate; removing the isolation material layer above the protrusion, and using the remaining isolation material layer surrounding the protrusion as an isolation layer; The step of forming the embedded metal wire includes: after forming the insulating material layer and before removing the insulating material layer above the protrusion, forming an opening in the insulating material layer between the first device region and the second device region; and forming the embedded metal wire in the opening.

15. The method of forming a semiconductor structure of claim 14, wherein, After forming the isolation layer, the method for forming the semiconductor structure further includes: forming a gate structure spanning the channel structure and source / drain doped regions located on both sides of the gate structure on the isolation layer; The gate structure is electrically connected to the embedded metal wire; or... The method for forming the semiconductor structure further includes: forming a source-drain interconnect layer above the source-drain doped region and in contact with the source-drain doped region, wherein the source-drain interconnect layer is electrically connected to the embedded metal line.

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