Ashing method and preparation method of semiconductor device

Abstract

The invention provides an ashing method and a preparation method of a semiconductor device, in the ashing method, side walls are formed on a semiconductor substrate after a double patterning process and an etching process, and organic film layers are formed in gaps between the adjacent side walls; the circulating treatment processes are executed, each circulating treatment process comprises a physical bombardment step and a chemical ashing step which are carried out in sequence, bombardment gas is introduced into the reaction cavity in the physical bombardment step so as to remove by-products in the gaps, and ashing gas is introduced into the reaction cavity in the chemical ashing step so as to remove a part of thickness of the organic matter film layer; by-products which cannot be subjected to ashing reaction in the gaps are removed through bombardment gas, the exposed area of the organic matter film layer is enlarged, and the sufficient ashing reaction of the organic matter film layer is promoted so as to improve the product yield.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to an ashing method and a method for preparing semiconductor devices. Background Technology

[0002] In advanced manufacturing processes, double patterning (DP) is often used to form the gaps in semiconductor devices. With the increasing aspect ratio of these gaps resulting from 3D integrated circuit processes, removing residues within the gaps presents a challenge. Due to the unique characteristics of the sidewall films produced by double patterning, highly etchable gases cannot be used in the ashing process. Therefore, oxygen is typically used for ashing to remove residual sidewall films. However, the adsorption and masking of newly formed byproducts during ashing can lead to new residues, ultimately causing defects and affecting product yield. Summary of the Invention

[0003] This application provides an ashing method and a semiconductor device fabrication method to solve the product yield problem caused by surface residues in the gaps of semiconductor devices.

[0004] One aspect of this application provides an ashing method, which includes: placing a semiconductor substrate in the reaction chamber of a plasma stripper, wherein the semiconductor substrate has sidewalls formed after undergoing a dual patterning process and an etching process, and an organic film layer is formed in the gap between adjacent sidewalls; performing a cyclic processing process, each cyclic processing process including a physical bombardment step and a chemical ashing step performed sequentially, wherein in the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps, and in the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer.

[0005] Alternatively, in the ashing method, the bombardment gas may be at least one of nitrogen and argon.

[0006] Optionally, nitrogen or argon gas is used in the ashing method, with a gas flow rate of 100 sccm to 500 sccm.

[0007] Optionally, in the ashing method, a mixture of nitrogen and argon is used, with the nitrogen flow rate being less than 100 sccm and the argon flow rate being 100 sccm to 500 sccm.

[0008] Optionally, in the ashing method, the bombardment pressure is 5 mtorr to 20 mtorr, the TCP RF power is 600W to 1200W, and the bias RF power is selected from 0V to 120V.

[0009] Alternatively, in the ashing method, oxygen is used as the ashing gas in the chemical ashing step.

[0010] Alternatively, in the ashing method, the sidewall material is silicon nitride or silicon oxide, and the organic film layer includes an organic carbon layer.

[0011] Optionally, the ashing method may perform at least two loop processing steps.

[0012] In another aspect, this application provides a method for fabricating a semiconductor device, comprising: providing a semiconductor substrate, wherein sidewalls are formed on the semiconductor substrate after a dual patterning process and an etching process, and an organic film layer is formed in the gap between adjacent sidewalls; and employing a cyclic processing step in any of the above-mentioned ashing methods to remove byproducts in the gaps and a portion of the organic film layer.

[0013] Optionally, in the method for fabricating a semiconductor device, the semiconductor substrate includes a first region and a second region. Sidewalls are formed on the first region, and an organic film is formed in the gap between adjacent sidewalls. A patterned amorphous silicon layer is formed on the second region, and an organic film is formed on the patterned amorphous silicon layer.

[0014] The technical solution provided in this application has at least the following advantages: It performs a cyclic processing step, each cycle including a physical bombardment step and a chemical ashing step performed sequentially. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps, and in the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer. Because the physical bombardment and chemical ashing steps are performed cyclically, byproducts that cannot be ashing on the gap surface are first physically removed, increasing the exposed area of ​​the organic film layer, thereby promoting the ashing reaction of the organic film layer and improving product yield. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic cross-sectional view of a semiconductor substrate used in an advanced manufacturing process.

[0017] Figures 2A-2C A cross-sectional schematic diagram of each step in the formation of a patterned amorphous silicon layer in an advanced manufacturing process;

[0018] Figure 3A This is a cross-sectional schematic diagram of the process before ashing in advanced manufacturing processes.

[0019] Figure 3B This is a schematic cross-sectional view after the ashing process in an advanced manufacturing process.

[0020] Figure 4 This is a schematic flowchart of an ashing method provided in this embodiment;

[0021] Figure 5 This is a schematic cross-sectional view of the semiconductor substrate in the ashing method of this embodiment;

[0022] Figure 6A This is a schematic cross-sectional view of the adjacent sidewalls in the ashing method of this embodiment;

[0023] Figure 6B This is a cross-sectional view after the physical bombardment step in the cyclic processing of this embodiment;

[0024] Figure 6C This is a schematic cross-sectional view after the chemical ashing step in the cyclic processing of this embodiment;

[0025] Figures 7A-7J This is a cross-sectional schematic diagram of each step in the semiconductor device fabrication method in this embodiment.

[0026] In the attached image:

[0027] exist Figures 1 to 3B In the diagram, 110 is a semiconductor substrate, 120 is an amorphous silicon layer, 130 is an advanced patterned thin film, 131 is a spin-coated carbon layer, 132 is an anti-reflective coating, 133 is a patterned photoresist layer, 140 is a sidewall, A is a gap, B is a byproduct, 101 is a first region, and 102 is a second region.

[0028] exist Figures 5 to 7J In the diagram, 210 is a semiconductor substrate, 220 is an amorphous silicon layer, 230 is an advanced patterned thin film, 231 is a spin-coated carbon layer, 232 is an anti-reflective coating, 233 is a patterned photoresist layer, 240 is a sidewall material layer, 241 is a sidewall, A is a gap, B is a byproduct, 201 is a first region, and 202 is a second region. Detailed Implementation

[0029] In related technologies, there are gaps between adjacent sidewalls, and after the etching process, some residues usually remain in the gaps.

[0030] like Figure 1As shown, the semiconductor substrate 110 includes a first region 101 and a second region 102. An amorphous silicon layer 120 is formed on the first region 101 and the second region 102. Sidewalls 140 are also formed on the first region 101, typically made of materials such as silicon nitride or silicon oxide. A gap A is provided between adjacent sidewalls 140. An advanced patterning film (APF) 130 is also formed on the first region 101 and the second region 102. The advanced patterning film 130 includes a spin-on carbon layer 131 (SOC) and an anti-reflective coating 132 formed sequentially, with the spin-on carbon layer 131 filling the gap A of the sidewalls 140. The advanced patterning film 130 also includes a patterned photoresist layer 133, which is located above the anti-reflective coating 132 on the second region 102.

[0031] Using a patterned photoresist layer 133 as a mask, an anti-reflective coating 132 is etched to form a patterned anti-reflective coating 132 on the second region 102. Next, as... Figure 2A As shown, using a patterned anti-reflective coating 132 as a mask, spin-coated carbon layers 131 are etched on the first region 101 and the second region 102. Since the spin-coated carbon layer 131 and the patterned photoresist layer 133 are both carbon-based organic materials, during the etching of the spin-coated carbon layer 131, the patterned photoresist layer 133 is consumed, and a patterned spin-coated carbon layer 131 is formed on the second region 102, while a certain thickness of spin-coated carbon layer 131 is retained in the gap A between the adjacent sidewalls 140 of the first region 101.

[0032] like Figure 2B As shown, the graphicized anti-reflective coating 132 is removed.

[0033] like Figure 2C As shown, using a patterned spin-coated carbon layer 131 as a mask, an amorphous silicon layer 120 is etched to remove the amorphous silicon layer 120 in the first region 101 and to form a patterned amorphous silicon layer in the second region 102.

[0034] Next, the spin-coated carbon layer 131 on the first region 101 and the second region 102 is removed, typically by an ashing process.

[0035] As shown in 3A, during the removal of the spin-coated carbon layer 131, the residue of the organic film, including the spin-coated carbon layer 131, will be adsorbed or diffused at the bottom and inner wall of the sidewall gap A. If an etching gas containing fluorine (F) or chlorine (Cl) is used for removal, not only will the residual organic film be etched away, but also part of the sidewall 140 will be etched. If a pure oxygen ashing process is used, the organic film is converted into volatile gaseous byproducts (such as CO, CO2, and H2O), but some non-volatile byproducts B will be generated during the reaction, such as... Figure 3B As shown, byproduct B diffuses and deposits on the sidewalls or outlet of the gap, preventing the organic film layer inside the gap A from reacting fully, resulting in incomplete removal of organic matter and premature termination of the ashing step. The residual organic film layer and byproduct B will become masks in subsequent processes, causing uneven doping or short circuits in the product, affecting the product yield.

[0036] Based on this, this application provides an ashing method and a method for fabricating a semiconductor device. In the ashing method, a semiconductor substrate is placed in the reaction chamber of a plasma stripper. Since the semiconductor substrate has sidewalls formed after a dual patterning and etching process, an organic film is formed in the gap between adjacent sidewalls. A cyclic processing process is performed, each cycle including a physical bombardment step and a chemical ashing step. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film. By employing a cyclical physical bombardment and chemical ashing process, the physical bombardment step introduces bombardment gas into the reaction chamber to remove byproducts that cannot be ashed in the gaps, while the chemical ashing step introduces ashing gas into the reaction chamber to remove a portion of the organic film layer. This allows byproducts that cannot be ashed on the gap surface to be physically removed first, increasing the exposed area of ​​the organic film layer and promoting a thorough ashing reaction. In turn, this divide-and-conquer approach solves the problem of residue removal being limited by the gap aspect ratio, fully removing byproducts in the gaps, promoting the ashing reaction of the organic film layer, and improving product yield.

[0037] In the description of the embodiments of this application, if the technical terms include "first" or "second," these terms are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0038] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0039] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0040] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. The formation or provision of a second component above or on a first component, or on the surface of a first component, or on one side of a first component, may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be present between the first and second components, thereby preventing direct contact between the first and second components. For simplicity and clarity, various components may be drawn at different scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, the formation or provision of a second component on the surface of a first component refers to direct contact between the first and second components. The term "component" may refer to a layer, film, region, portion, structure, etc.

[0041] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0042] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] Figure 4 This is a schematic flowchart of an ashing method provided in this embodiment. The ashing method provided in this application embodiment includes:

[0044] S11: The semiconductor substrate is placed in the reaction chamber of the plasma stripper. After the semiconductor substrate undergoes a dual patterning process and an etching process, sidewalls are formed. An organic film is formed in the gap between adjacent sidewalls.

[0045] S12: Perform a cyclic processing procedure. Each cyclic processing procedure includes a physical bombardment step and a chemical ashing step performed sequentially. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer.

[0046] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0047] In one embodiment, in step S11, the semiconductor substrate 210 is placed inside the reaction chamber of the plasma stripper. For example... Figure 5 As shown, the semiconductor substrate 210 forms sidewalls 241 after undergoing a dual patterning and etching process, and an organic film layer is formed in the gap A between adjacent sidewalls 241.

[0048] Optionally, the sidewall 241 is made of silicon nitride or silicon oxide, and the organic film layer includes an organic carbon layer. The semiconductor substrate 210 can be used to form semiconductor devices with fin structures or wiring channels. Gaps exist between the fin structures or wiring channels, and these gaps have a certain aspect ratio; for example, the aspect ratio of the gaps between the fin structures in a fin field-effect transistor may exceed 10:1, making it difficult to remove residual organic film layers. Figure 6A As shown, an organic film layer is formed in the gap A between adjacent sidewalls 241, and there are also byproducts left over from the removal of the organic film layer in the previous process.

[0049] In one embodiment, such as Figure 6B As shown, the physical bombardment step is used to introduce bombardment gas into the reaction chamber to remove byproduct B that cannot be ashed in gap A. The byproducts in gap A are non-volatile and deposit on the sidewalls and bottom of the gap, affecting the complete ashing reaction in the chemical ashing step. In this embodiment, a physical bombardment step is performed before the chemical ashing step to remove the byproducts on the gap surface, thereby increasing the exposed area of ​​the organic film layer to facilitate a complete ashing reaction.

[0050] The plasma descaling machine has a lower electrode at the bottom of the reaction chamber and an upper electrode at the top, positioned opposite each other. In the physical bombardment step, after the bombardment gas forms a first plasma, it accelerates and bombards the semiconductor substrate to remove byproducts from the gaps. The upper electrode can be designed like a ceiling or shower head, delivering the bombardment gas and serving as an antenna for exciting the first plasma. The upper electrode body can be hollow, with internal gas channels to uniformly spray the bombardment gas into the reaction chamber. The lower electrode can be a tray design to hold the semiconductor substrate. Optionally, the semiconductor substrate can be fixed by electrostatic adsorption or mechanical means. Further, in the physical bombardment step, TCP (Transformer Coupled Plasma) RF power is applied to the upper electrode, and bias RF power is applied to the lower electrode. The upper electrode is connected to a TCP RF power supply outside the reaction chamber, generating the main energy for forming the first plasma. The TCP RF power supply can be a power system that excites and maintains a capacitively coupled plasma within a vacuum chamber. The lower electrode is connected to a bias radio frequency power supply outside the reaction chamber, generating a DC self-bias voltage on the surface of the semiconductor substrate to control the energy of ion bombardment.

[0051] In the physical bombardment step, at least one of nitrogen and argon is used as the bombardment gas. If nitrogen or argon is used, the gas flow rate is preferably 100 sccm to 500 sccm. Alternatively, a mixture of nitrogen and argon is used, with the nitrogen flow rate preferably less than 100 sccm and the argon flow rate preferably 100 sccm to 500 sccm. For example, if the nitrogen flow rate is set to 100 sccm and the argon flow rate is set to 200 sccm, and the byproducts are very stubborn or have an extremely high aspect ratio, pure argon (200 sccm) is used for physical bombardment. The Ar... +Ions possess high physical momentum, effectively removing the non-volatile byproduct layer covering the organic film surface. Considering that pure argon gas might damage the underlying sensitive material, a mixture of nitrogen (100 sccm) and argon (200 sccm) is used. The addition of nitrogen introduces a weak chemical reaction, which helps passivate the surface, reducing physical damage to the underlying sensitive material and facilitating the removal of the organic film during the chemical ashing step. Alternatively, pure nitrogen (100 sccm) can also be used, reducing physical damage to the underlying sensitive material, although its removal capability is weaker than that of argon. Optionally, TCP RF power is applied to the upper electrode to form a first plasma from the bombarding gas; a bias RF power, lower than the TCP RF power, is applied to the lower electrode, causing the first plasma to accelerate and bombard the semiconductor substrate. Further, in the physical bombardment step, the bombardment pressure is 5 mtorr to 20 mtorr, the TCP RF power is 600 W to 1200 W, and the bias RF power is selected from 0 V to 120 V. A bombardment pressure of 5 mtorr to 20 mtorr is selected to allow ions and atoms to bombard the interstitial surface of the semiconductor substrate at a more perpendicular and directional angle. A TCP RF power of 600 W to 1200 W is used to generate a high-density first plasma, ensuring a sufficient number of bombarding particles (Ar). + N2 + By selecting a bias RF power of 0V~120V, the bias RF power at different stages can be dynamically adjusted to avoid damaging the underlying material of the organic film.

[0052] In this embodiment, the upper electrode generates and maintains a high-density first plasma based on TCP radio frequency power through a physical bombardment step, and the lower electrode controls the positive ions in the first plasma to bombard the semiconductor substrate placed on the lower electrode with a predetermined energy through the generated DC self-bias voltage based on the bias radio frequency power, thereby realizing physical etching of the device gap surface.

[0053] In one embodiment, such as Figure 6C As shown, the chemical ashing step is used to introduce ashing gas into the reaction chamber to remove a portion of the organic film layer, thereby physically removing the byproducts that cannot be ashed on the surface of gap A, increasing the exposed area of ​​the organic film layer, promoting the full ashing reaction of the organic film layer, and fully removing the byproducts in the gap, thus promoting the ashing reaction of the organic film layer.

[0054] In step S12, the application of the first radio frequency power combination and the introduction of the bombardment gas are first stopped. Then, an ashing gas is introduced into the reaction chamber, and a second radio frequency power is applied to form a second plasma from the ashing gas. The second plasma chemically reacts with the organic film layer to remove a portion of the organic film layer within the gap. The organic film layer is an organic carbon layer in an advanced patterned thin film with a high aspect ratio structure formed by a dual patterning process. Optionally, oxygen is used as the ashing gas. Further, oxygen or an oxygen-containing mixed gas is used. Preferably, an oxygen-dominant mixed gas is used.

[0055] Optionally, a coil antenna is installed inside the reaction chamber of the plasma degumming machine, and the coil antenna is connected to an antenna radio frequency power supply outside the reaction chamber. A second radio frequency power is applied to the ashing gas to form a second plasma. Specifically, the second radio frequency power is applied to the coil antenna to form the second plasma from the ashing gas. Optionally, the ashing process pressure is selected in the range of 50 mtorr to 200 mtorr to promote isotropic chemical reactions, ensuring that oxygen diffuses uniformly and covers all newly exposed surfaces; the second radio frequency power is selected in the range of 300 W to 600 W to dissociate oxygen and generate a large number of reactive oxygen free radicals; the bias radio frequency power is selected in the range of 0 V to 50 V to suppress physical bombardment, purely utilizing the isotropic nature of the chemical reaction to avoid physical damage to the underlying material of the organic film.

[0056] The physical bombardment step and the chemical ashing step are completed in the same reaction chamber to reduce process costs, simplify the preparation process, and improve processing efficiency.

[0057] In a preferred embodiment, at least two cycles of processing are performed, namely two rounds of physical bombardment and chemical ashing, namely, a first physical bombardment step, a first chemical ashing step, a second physical bombardment step, and a second chemical ashing step.

[0058] While the organic film layer is not completely removed, the physical bombardment and chemical ashing steps are repeated until the gap surface meets the preset requirements. The preset requirements can be one of the following: the processing time reaches a preset time limit, the gap surface reaches its damage resistance limit, or the organic film layer thickness is below a preset range. For example, the time limit for each cycle is less than 120 seconds to avoid unnecessary physical damage and temperature rise during the process. For instance, each round lasts 30 seconds, with 10 seconds for physical bombardment and 20 seconds for chemical ashing. If the gap surface meets the preset requirements after the first round, the cycle ends; otherwise, the cycle continues until the processing time reaches the preset time limit, at which point the cycle ends. The luminescence intensity of the semiconductor substrate can be detected by optical emission spectroscopy to determine whether the gap surface meets the preset requirements. If it does, the semiconductor substrate is removed from the reaction chamber; otherwise, the cycle continues. Regions with byproducts in the gaps will undergo a specific chemical reaction with the second plasma, generating a large number of excited-state particles, thus emitting strong light at their characteristic wavelengths. Regions without residue / clean substrates either do not emit light or emit weaker light at a different wavelength than the residue. Based on this, by using optical emission spectra in conjunction with filters of specific wavelengths to capture the emission images on the surface of the device, the distribution of residues can be directly visualized. On the image, areas of strong emission correspond to areas where residues are concentrated, and the contrast between bright and dark emission directly outlines the extent of byproducts.

[0059] Because the ashing method employs a cyclical processing procedure, each cycle includes a sequential physical bombardment step and a chemical ashing step. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts that cannot be ashed in the gaps. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer. This cyclical, sequential physical bombardment and chemical ashing process, with the physical bombardment step introducing bombardment gas to remove byproducts that cannot be ashed in the gaps and the chemical ashing step introducing ashing gas to remove a portion of the organic film layer, allows for the physical removal of byproducts that cannot be ashed on the gap surface. This increases the exposed area of ​​the organic film layer, promotes a thorough ashing reaction, and effectively addresses the problem of residual removal being limited by the gap aspect ratio in a divide-and-conquer manner. This ensures the complete removal of byproducts in the gaps, promotes the ashing reaction of the organic film layer, and improves product yield.

[0060] This application also provides a method for fabricating a semiconductor device, comprising:

[0061] A semiconductor substrate is provided, wherein sidewalls are formed after a dual patterning and etching process, and an organic film layer is formed in the gap between adjacent sidewalls; and,

[0062] An ashing process is performed, which is a cyclic process. Each cyclic process includes a physical bombardment step and a chemical ashing step performed sequentially. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gap. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer.

[0063] Specifically, such as Figures 7A-7B As shown, the semiconductor substrate 210 includes a first region 201 and a second region 202. The first region 201 is, for example, a dual patterned area (DPT area), and the second region 202 is, for example, a photolithography-etched area (LEArea). A sidewall material layer 240 is formed on the semiconductor substrate 210, and a dual patterning process and an etching process are performed to form a sidewall 241 on the first region 201 of the semiconductor substrate.

[0064] Optionally, an oxide layer 250 is also formed on the semiconductor substrate 210, and a sidewall material layer 240 is formed above the oxide layer 250, such that sidewalls 241 are formed above the oxide layer 250.

[0065] like Figure 7C As shown, an amorphous silicon layer 220 is formed on a semiconductor substrate 210. The amorphous silicon layer 220 covers a first region 201 and a second region 202. The amorphous silicon layer 220 fills the space between the sidewalls 241 on the first region 201.

[0066] like Figure 7D As shown, the amorphous silicon layer 220 in the sidewall gap A in the first region 201 is etched away.

[0067] like Figure 7E As shown, an advanced patterned thin film 230 is formed on a semiconductor substrate 210. The advanced patterned thin film 230 is used as a hard mask to form a patterned amorphous silicon layer. The advanced patterned thin film 230 includes a spin-on carbon (SOC) layer 231 and an anti-reflective coating 232 formed sequentially. The advanced patterned thin film 230 also includes a patterned photoresist layer 233, which is located above the anti-reflective coating 232 in the second region 202. The spin-on carbon layer 231 fills the gaps A of the sidewalls 241 in the first region 201 and covers the amorphous silicon layer 220 in the second region 202.

[0068] Next, a dual patterning and etching process is performed. For example... Figure 7F As shown, using a patterned photoresist layer 233 as a mask, an anti-reflective coating 232 is etched to form a patterned anti-reflective coating 232 in the second region 202. Figure 7GAs shown, using the patterned anti-reflective coating 232 as a mask, the spin-coated carbon layer 231 is then etched to form the patterned spin-coated carbon layer 231 in the second region 202, and a portion of the thickness of the spin-coated carbon layer 231 is removed in the first region 201. Since both the patterned photoresist layer 233 and the spin-coated carbon layer 231 are composed of carbon-based organic materials, the patterned photoresist layer 233 is consumed during the etching of the spin-coated carbon layer 231. Figure 7H As shown, the patterned anti-reflective coating 232 is then removed. (As shown...) Figure 7I As shown, using a patterned spin-coated carbon layer 231 as a mask, an amorphous silicon layer 220 is etched to form a patterned amorphous silicon layer in the second region 202. Figure 7J As shown, the spin-coated carbon layer 231 in the first region 201 and the second region 202 is then etched away to form the final patterned amorphous silicon layer.

[0069] In the step of etching away the spin-coated carbon layer 231 in the first region 201 and the second region 202 to form the final patterned amorphous silicon layer, an organic film layer, including the spin-coated carbon layer 231, is formed in the gap between adjacent sidewalls. During the ashing reaction, this organic film layer produces non-volatile byproducts, which act as a mask and affect the effective ashing reaction of the organic film layer. Therefore, a cyclic processing procedure is performed. Each cyclic processing procedure includes a sequential physical bombardment step and a chemical ashing step. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer.

[0070] In the cyclic processing of the ashing method, byproduct C and a portion of the organic film layer in gap A are removed. Specifically, the semiconductor substrate 210 is placed in the reaction chamber of a plasma resist remover. The semiconductor substrate 210 has sidewalls 241 formed after a dual patterning and etching process, and an organic film layer is formed in the gap between adjacent sidewalls 241. The cyclic processing is performed, each cycle including a physical bombardment step and a chemical ashing step. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps, and in the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer.

[0071] Because the semiconductor device fabrication method provided in this embodiment employs a cyclic processing procedure, each cycle includes a physical bombardment step and a chemical ashing step performed sequentially. In the physical bombardment step, bombardment gas is introduced into the reaction chamber to remove byproducts in the gaps. In the chemical ashing step, ashing gas is introduced into the reaction chamber to remove a portion of the organic film layer. This allows the organic film layer formed in the gaps between adjacent sidewalls to undergo a complete ashing reaction in the chemical ashing step, provided that the physical bombardment step is followed by the chemical ashing step. The physical bombardment step removes byproducts that cannot be ashing in the gaps, increases the exposed area of ​​the organic film layer, and promotes a complete ashing reaction of the organic film layer. This divide-and-conquer approach solves the problem of residue removal being limited by the gap aspect ratio, effectively removing byproducts in the gaps, promoting the ashing reaction of the organic film layer, and improving product yield.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An ashing method, characterized by, The application relates to a method for removing by-products and organic film layers in the gaps between adjacent sidewalls of a semiconductor substrate. The semiconductor substrate is placed in a reaction cavity of a plasma stripping machine, the semiconductor substrate is formed with sidewalls after a double patterning process and an etching process, and an organic film layer is formed in the gaps between adjacent sidewalls; A cycle process is performed, each cycle process comprises a physical bombardment step and a chemical ashing step, the physical bombardment step is to introduce a bombardment gas into the reaction cavity to remove by-products in the gaps, and the chemical ashing step is to introduce an ashing gas into the reaction cavity to remove part of the thickness of the organic film layer.

2. The ashing method according to claim 1, wherein, In the physical bombardment step, the bombardment gas is at least one of nitrogen and argon.

3. The ashing method according to claim 2, wherein, In the physical bombardment step, nitrogen or argon is used, and the gas flow is 100sccm-500sccm.

4. The ashing method of claim 2, wherein, In the physical bombardment step, a mixed gas of nitrogen and argon is used, the nitrogen flow is less than 100sccm, and the argon flow is 100sccm-500sccm.

5. The ashing method of claim 2, wherein, In the physical bombardment step, the bombardment pressure is 5mtorr-20mtorr, the TCP radio frequency power is 600W-1200W, and the bias radio frequency power is selected from the range of 0V-120V.

6. The ashing method of claim 1, wherein, In the chemical ashing step, the ashing gas is oxygen.

7. The ashing method of claim 1, wherein, The material of the sidewall is silicon nitride or silicon oxide, and the organic film layer comprises an organic carbon layer.

8. The ashing method according to any one of claims 1 to 7, characterized by, The cycle process is performed at least twice.

9. A method of manufacturing a semiconductor device, characterized by, The application relates to a method for removing by-products and organic film layers in the gaps between adjacent sidewalls of a semiconductor substrate. The application relates to a method for removing by-products and organic film layers in the gaps between adjacent sidewalls of a semiconductor substrate. The semiconductor substrate comprises a first region and a second region, the first region is formed with the sidewalls, the gaps between adjacent sidewalls are formed with the organic film layer, the second region is formed with a patterned amorphous silicon layer, and the patterned amorphous silicon layer is formed with the organic film layer. ​ 10. The method of producing a semiconductor device according to Claim 9, wherein ​

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